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Searched refs:vlv_dpio_read (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
H A Dintel_dpio_phy.c731 val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW10(ch)); in chv_set_phy_signal_level()
738 val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW10(ch)); in chv_set_phy_signal_level()
745 val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW9(ch)); in chv_set_phy_signal_level()
751 val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW9(ch)); in chv_set_phy_signal_level()
759 val = vlv_dpio_read(dev_priv, phy, CHV_TX_DW4(ch, i)); in chv_set_phy_signal_level()
767 val = vlv_dpio_read(dev_priv, phy, CHV_TX_DW2(ch, i)); in chv_set_phy_signal_level()
790 val = vlv_dpio_read(dev_priv, phy, CHV_TX_DW3(ch, i)); in chv_set_phy_signal_level()
799 val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW10(ch)); in chv_set_phy_signal_level()
804 val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW10(ch)); in chv_set_phy_signal_level()
822 val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW0(ch)); in chv_data_lane_soft_reset()
[all …]
H A Dintel_dpll.c529 tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW3(ch)); in vlv_crtc_clock_get()
557 cmn_dw13 = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW13(ch)); in chv_crtc_clock_get()
558 pll_dw0 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW0(ch)); in chv_crtc_clock_get()
559 pll_dw1 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW1(ch)); in chv_crtc_clock_get()
560 pll_dw2 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW2(ch)); in chv_crtc_clock_get()
561 pll_dw3 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(ch)); in chv_crtc_clock_get()
1884 tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(ch)); in vlv_pllb_recal_opamp()
1889 tmp = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11); in vlv_pllb_recal_opamp()
1894 tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(ch)); in vlv_pllb_recal_opamp()
1898 tmp = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11); in vlv_pllb_recal_opamp()
[all …]
H A Dintel_display_power_well.c1447 tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW28); in chv_dpio_cmn_power_well_enable()
1453 tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW6_CH1); in chv_dpio_cmn_power_well_enable()
1462 tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW30); in chv_dpio_cmn_power_well_enable()
1536 val = vlv_dpio_read(dev_priv, phy, reg); in assert_chv_phy_powergate()
/linux/drivers/gpu/drm/xe/compat-i915-headers/
H A Dvlv_sideband.h83 static inline u32 vlv_dpio_read(struct drm_i915_private *i915, int pipe, int reg) in vlv_dpio_read() function
/linux/drivers/gpu/drm/i915/
H A Dvlv_sideband.h75 u32 vlv_dpio_read(struct drm_i915_private *i915, enum dpio_phy phy, int reg);
H A Dvlv_sideband.c212 u32 vlv_dpio_read(struct drm_i915_private *i915, enum dpio_phy phy, int reg) in vlv_dpio_read() function