| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 282 int vlevel) in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
287 enum clock_change_support temp_clock_change_support = vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
293 vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_support; in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
296 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, DC_VALIDATE_MODE_AND_PROGRAMMING); in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
299 if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported && in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
301 vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_support; in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
303 if (vlevel < (int)context->bw_ctx.dml.vba.soc.num_states && in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
304 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported) in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
481 unsigned int vlevel = context->bw_ctx.dml.vba.VoltageLevel; in dcn32_set_phantom_stream_timing()
482 unsigned int dcfclk = (unsigned int)context->bw_ctx.dml.vba.DCFCLKState[vlevel][contex in dcn32_set_phantom_stream_timing()
279 dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt,int vlevel) dcn32_find_dummy_latency_index_for_fw_based_mclk_switch() argument
478 unsigned int vlevel = context->bw_ctx.dml.vba.VoltageLevel; dcn32_set_phantom_stream_timing() local
1039 subvp_validate_static_schedulability(struct dc * dc,struct dc_state * context,int vlevel) subvp_validate_static_schedulability() argument
1399 try_odm_power_optimization_and_revalidate(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int * split,bool * merge,unsigned int * vlevel,int pipe_cnt) try_odm_power_optimization_and_revalidate() argument
1440 dcn32_full_validate_bw_helper(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int * vlevel,int * split,bool * merge,int * pipe_cnt,bool * repopulate_pipes) dcn32_full_validate_bw_helper() argument
1615 dcn32_calculate_dlg_params(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt,int vlevel) dcn32_calculate_dlg_params() argument
2113 int vlevel = context->bw_ctx.dml.soc.num_states; dcn32_internal_validate_bw() local
2268 dcn32_calculate_wm_and_dlg_fpu(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt,int vlevel) dcn32_calculate_wm_and_dlg_fpu() argument
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.h | 43 int vlevel);
53 int vlevel,
70 int vlevel,
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| H A D | dcn20_fpu.c | 1147 int vlevel) in dcn20_calculate_dlg_params()
1168 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] in dcn20_calculate_dlg_params()
1222 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = (int)(context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000.0); in dcn20_calculate_dlg_params()
1223 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = (int)(context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000.0); in dcn20_calculate_dlg_params()
1229 bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2; in dcn20_calculate_dlg_params()
1744 int vlevel, in dcn20_calculate_wm()
1757 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn20_calculate_wm()
1761 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; in dcn20_calculate_wm()
1770 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]]; in dcn20_calculate_wm()
1801 pipes[0].clks_cfg.voltage = vlevel; in dcn20_calculate_wm()
1144 dcn20_calculate_dlg_params(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt,int vlevel) dcn20_calculate_dlg_params() argument
1735 dcn20_calculate_wm(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int * out_pipe_cnt,int * pipe_split_from,int vlevel,enum dc_validate_mode validate_mode) dcn20_calculate_wm() argument
2036 int vlevel = 0; dcn20_validate_bandwidth_internal() local
2142 dcn20_fpu_adjust_dppclk(struct vba_vars_st * v,int vlevel,int max_mpc_comb,int pipe_idx,bool is_validating_bw) dcn20_fpu_adjust_dppclk() argument
2206 calculate_wm_set_for_vlevel(int vlevel,struct wm_range_table_entry * table_entry,struct dcn_watermarks * wm_set,struct display_mode_lib * dml,display_e2e_pipe_params_st * pipes,int pipe_cnt) calculate_wm_set_for_vlevel() argument
2244 int vlevel, vlevel_max; dcn21_calculate_wm() local
2327 int vlevel = 0; dcn21_validate_bandwidth_fp() local
[all...] |
| /linux/drivers/soc/qcom/ |
| H A D | spm.c | 333 unsigned int vlevel, volt_sel; in smp_set_vdd_v1_1() local
337 vlevel = volt_sel | 0x80; /* band */ in smp_set_vdd_v1_1()
355 vctl = FIELD_SET(vctl, SPM_VCTL_VLVL, vlevel); in smp_set_vdd_v1_1()
356 data0 = FIELD_SET(data0, SPM_PMIC_DATA_0_VLVL, vlevel); in smp_set_vdd_v1_1()
365 sts, sts == vlevel, in smp_set_vdd_v1_1()
368 dev_err_ratelimited(drv->dev, "timeout setting the voltage (%x %x)!\n", sts, vlevel); in smp_set_vdd_v1_1()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| H A D | dcn20_resource.c | 1864 int vlevel, in dcn20_validate_apply_pipe_split_flags()
1928 for (vlevel_split = vlevel; (unsigned int)vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) in dcn20_validate_apply_pipe_split_flags()
1929 if (v->NoOfDPP[vlevel][0][pipe_idx] == 1 && in dcn20_validate_apply_pipe_split_flags()
1930 v->ModeSupport[vlevel][0]) in dcn20_validate_apply_pipe_split_flags()
1933 if ((unsigned int)vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_validate_apply_pipe_split_flags()
1934 vlevel = vlevel_split; in dcn20_validate_apply_pipe_split_flags()
1959 if (split4mpc || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 4) in dcn20_validate_apply_pipe_split_flags()
1961 else if (force_split || v->NoOfDPP[vlevel][max_mpc_com in dcn20_validate_apply_pipe_split_flags()
1863 dcn20_validate_apply_pipe_split_flags(struct dc * dc,struct dc_state * context,int vlevel,int * split,bool * merge) dcn20_validate_apply_pipe_split_flags() argument
2067 int pipe_cnt, i, pipe_idx, vlevel; dcn20_fast_validate_bw() local
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 1798 int pipe_cnt, pipe_idx, vlevel = 0; in dcn30_internal_validate_bw()
1828 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn30_internal_validate_bw()
1829 /* This may adjust vlevel and maxMpcComb */ in dcn30_internal_validate_bw()
1830 if ((unsigned int)vlevel < context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1831 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); in dcn30_internal_validate_bw()
1834 (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING || vlevel == context->bw_ctx.dml.soc.num_states || in dcn30_internal_validate_bw()
1835 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported)) { in dcn30_internal_validate_bw()
1847 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn30_internal_validate_bw()
1848 if ((unsigned int)vlevel < contex in dcn30_internal_validate_bw()
1672 int pipe_cnt, i, pipe_idx, vlevel = 0; dcn30_internal_validate_bw() local
2067 dcn30_calculate_wm_and_dlg(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt,int vlevel) dcn30_calculate_wm_and_dlg() argument
2082 int vlevel = 0; dcn30_validate_bandwidth() local
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 486 int vlevel) in dcn31_calculate_wm_and_dlg_fp() argument
490 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn31_calculate_wm_and_dlg_fp()
505 context->bw_ctx.bw.dcn.clk.dcfclk_khz = (int)dcfclk; // always should be vlevel 0 in dcn31_calculate_wm_and_dlg_fp()
509 pipes[0].clks_cfg.voltage = vlevel; in dcn31_calculate_wm_and_dlg_fp()
511 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
562 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); in dcn31_calculate_wm_and_dlg_fp()
565 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_dram_clock_change_vactive; in dcn31_calculate_wm_and_dlg_fp()
|
| H A D | dcn31_fpu.h | 45 int vlevel);
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| H A D | dcn21_resource.c | 807 int pipe_cnt, pipe_idx, vlevel; in dcn21_fast_validate_bw() local
831 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
833 if ((unsigned int)vlevel > context->bw_ctx.dml.soc.num_states) { in dcn21_fast_validate_bw()
845 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
846 if ((unsigned int)vlevel > context->bw_ctx.dml.soc.num_states) in dcn21_fast_validate_bw()
853 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); in dcn21_fast_validate_bw()
912 dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe_idx, true); in dcn21_fast_validate_bw()
943 *vlevel_out = vlevel; in dcn21_fast_validate_bw()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| H A D | dcn31_resource.c | 1886 int vlevel)
1889 dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);
1922 int vlevel = 0; in dcn31_resource_construct()
1934 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode, true); in dcn31_resource_construct()
1951 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); in dcn31_resource_construct()
1762 dcn31_calculate_wm_and_dlg(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt,int vlevel) dcn31_calculate_wm_and_dlg() argument
1798 int vlevel = 0; dcn31_validate_bandwidth() local
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.c | 1920 int vlevel = 0; in dcn32_populate_dml_pipes_from_context()
1939 out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode); in dcn32_populate_dml_pipes_from_context()
1955 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); in dcn32_populate_dml_pipes_from_context()
2228 int vlevel) in dcn32_resource_construct()
2231 dcn32_calculate_wm_and_dlg_fpu(dc, context, pipes, pipe_cnt, vlevel); in dcn32_resource_construct()
1792 int vlevel = 0; dml1_validate() local
2099 dcn32_calculate_wm_and_dlg(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt,int vlevel) dcn32_calculate_wm_and_dlg() argument
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| H A D | dcn314_resource.c | 1864 int vlevel = 0; in dcn314_resource_construct()
1877 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode, false); in dcn314_resource_construct()
1894 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); in dcn314_resource_construct()
1739 int vlevel = 0; dcn314_validate_bandwidth() local
|