| /linux/drivers/soc/qcom/ |
| H A D | spm.c | 333 unsigned int vlevel, volt_sel; in smp_set_vdd_v1_1() local
337 vlevel = volt_sel | 0x80; /* band */ in smp_set_vdd_v1_1()
355 vctl = FIELD_SET(vctl, SPM_VCTL_VLVL, vlevel); in smp_set_vdd_v1_1()
356 data0 = FIELD_SET(data0, SPM_PMIC_DATA_0_VLVL, vlevel); in smp_set_vdd_v1_1()
365 sts, sts == vlevel, in smp_set_vdd_v1_1()
368 dev_err_ratelimited(drv->dev, "timeout setting the voltage (%x %x)!\n", sts, vlevel); in smp_set_vdd_v1_1()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| H A D | dcn20_resource.c | 1820 int vlevel, in dcn20_validate_apply_pipe_split_flags() argument
1883 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) in dcn20_validate_apply_pipe_split_flags()
1884 if (v->NoOfDPP[vlevel][0][pipe_idx] == 1 && in dcn20_validate_apply_pipe_split_flags()
1885 v->ModeSupport[vlevel][0]) in dcn20_validate_apply_pipe_split_flags()
1888 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_validate_apply_pipe_split_flags()
1889 vlevel = vlevel_split; in dcn20_validate_apply_pipe_split_flags()
1907 if (split4mpc || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 4) in dcn20_validate_apply_pipe_split_flags()
1909 else if (force_split || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 2) in dcn20_validate_apply_pipe_split_flags()
1923 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_2to1; in dcn20_validate_apply_pipe_split_flags()
1927 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_4to1; in dcn20_validate_apply_pipe_split_flags()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 1637 int pipe_cnt, i, pipe_idx, vlevel = 0; in dcn30_internal_validate_bw() local
1665 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn30_internal_validate_bw()
1667 if (vlevel < context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1668 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); in dcn30_internal_validate_bw()
1671 …(validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING || vlevel == context->bw_ctx.dml.soc.num_states… in dcn30_internal_validate_bw()
1672 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported)) { in dcn30_internal_validate_bw()
1684 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn30_internal_validate_bw()
1685 if (vlevel < context->bw_ctx.dml.soc.num_states) { in dcn30_internal_validate_bw()
1688 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); in dcn30_internal_validate_bw()
1695 if (vlevel == context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 486 int vlevel) in dcn31_calculate_wm_and_dlg_fp() argument
489 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn31_calculate_wm_and_dlg_fp()
506 pipes[0].clks_cfg.voltage = vlevel; in dcn31_calculate_wm_and_dlg_fp()
508 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
559 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); in dcn31_calculate_wm_and_dlg_fp()
562 …context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_d… in dcn31_calculate_wm_and_dlg_fp()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| H A D | dcn21_resource.c | 780 int pipe_cnt, i, pipe_idx, vlevel; in dcn21_fast_validate_bw() local
803 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
805 if (vlevel > context->bw_ctx.dml.soc.num_states) { in dcn21_fast_validate_bw()
815 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
816 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn21_fast_validate_bw()
820 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); in dcn21_fast_validate_bw()
879 …dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe… in dcn21_fast_validate_bw()
910 *vlevel_out = vlevel; in dcn21_fast_validate_bw()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| H A D | dcn31_resource.c | 1732 int vlevel) in dcn31_calculate_wm_and_dlg() argument
1735 dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel); in dcn31_calculate_wm_and_dlg()
1768 int vlevel = 0; in dcn31_validate_bandwidth() local
1780 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode, true); in dcn31_validate_bandwidth()
1797 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); in dcn31_validate_bandwidth()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource_helpers.c | 704 bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int vlevel) in dcn32_subvp_vblank_admissable() argument
744 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vblank_w_mall_sub_vp) in dcn32_subvp_vblank_admissable()
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| H A D | dcn32_resource.c | 1751 int vlevel = 0; in dml1_validate() local
1770 out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode); in dml1_validate()
1786 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); in dml1_validate()
2055 int vlevel) in dcn32_calculate_wm_and_dlg() argument
2058 dcn32_calculate_wm_and_dlg_fpu(dc, context, pipes, pipe_cnt, vlevel); in dcn32_calculate_wm_and_dlg()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| H A D | core_types.h | 93 int vlevel);
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| H A D | dcn314_resource.c | 1706 int vlevel = 0; in dcn314_validate_bandwidth() local
1719 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode, false); in dcn314_validate_bandwidth()
1736 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); in dcn314_validate_bandwidth()
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