| /linux/drivers/clk/meson/ |
| H A D | vclk.c | 20 struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk); in meson_vclk_gate_enable() local
22 meson_parm_write(clk->map, &vclk->enable, 1); in meson_vclk_gate_enable()
25 meson_parm_write(clk->map, &vclk->reset, 1); in meson_vclk_gate_enable()
26 meson_parm_write(clk->map, &vclk->reset, 0); in meson_vclk_gate_enable()
34 struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk); in meson_vclk_gate_disable() local
36 meson_parm_write(clk->map, &vclk->enable, 0); in meson_vclk_gate_disable()
42 struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk); in meson_vclk_gate_is_enabled() local
44 return meson_parm_read(clk->map, &vclk->enable); in meson_vclk_gate_is_enabled()
66 struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk); in meson_vclk_div_recalc_rate() local
68 return divider_recalc_rate(hw, prate, meson_parm_read(clk->map, &vclk->div), in meson_vclk_div_recalc_rate()
[all …]
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| H A D | Makefile | 15 obj-$(CONFIG_COMMON_CLK_MESON_VCLK) += vclk.o
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| /linux/drivers/video/fbdev/via/ |
| H A D | vt1636.c | 186 index = get_clk_range_index(plvds_setting_info->vclk); in viafb_vt1636_patch_skew_on_vt3324()
210 index = get_clk_range_index(plvds_setting_info->vclk); in viafb_vt1636_patch_skew_on_vt3327()
227 index = get_clk_range_index(plvds_setting_info->vclk); in viafb_vt1636_patch_skew_on_vt3364()
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| H A D | chip.h | 141 u32 vclk; /*panel mode clock value */ member
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| /linux/drivers/gpu/drm/radeon/ |
| H A D | rs780_dpm.c | 570 if ((new_ps->vclk == old_ps->vclk) && in rs780_set_uvd_clock_before_set_eng_clock()
577 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_before_set_eng_clock()
587 if ((new_ps->vclk == old_ps->vclk) && in rs780_set_uvd_clock_after_set_eng_clock()
594 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_after_set_eng_clock()
727 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in rs780_parse_pplib_non_clock_info()
730 rps->vclk = 0; in rs780_parse_pplib_non_clock_info()
735 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rs780_parse_pplib_non_clock_info()
736 rps->vclk = RS780_DEFAULT_VCLK_FREQ; in rs780_parse_pplib_non_clock_info()
945 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_print_power_state()
994 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_debugfs_print_current_performance_level()
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| H A D | trinity_dpm.c | 850 if ((rps->vclk == 0) && (rps->dclk == 0)) in trinity_uvd_clocks_zero()
862 if ((rps1->vclk == rps2->vclk) && in trinity_uvd_clocks_equal()
895 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
906 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
1410 if ((rps->vclk == pi->sys_info.uvd_clock_table_entries[i].vclk) && in trinity_get_uvd_clock_index()
1644 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in trinity_parse_pplib_non_clock_info()
1647 rps->vclk = 0; in trinity_parse_pplib_non_clock_info()
1887 pi->sys_info.uvd_clock_table_entries[i].vclk = in trinity_parse_sys_info_table()
1973 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_print_power_state()
1998 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_debugfs_print_current_performance_level()
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| H A D | sumo_dpm.c | 822 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in sumo_setup_uvd_clocks()
838 if ((new_rps->vclk == old_rps->vclk) && in sumo_set_uvd_clock_before_set_eng_clock()
856 if ((new_rps->vclk == old_rps->vclk) && in sumo_set_uvd_clock_after_set_eng_clock()
1412 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in sumo_parse_pplib_non_clock_info()
1415 rps->vclk = 0; in sumo_parse_pplib_non_clock_info()
1804 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_print_power_state()
1827 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
1835 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
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| H A D | rv770_dpm.c | 1440 if ((new_ps->vclk == old_ps->vclk) && in rv770_set_uvd_clock_before_set_eng_clock()
1447 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_before_set_eng_clock()
1457 if ((new_ps->vclk == old_ps->vclk) && in rv770_set_uvd_clock_after_set_eng_clock()
1464 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_after_set_eng_clock()
2155 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in rv7xx_parse_pplib_non_clock_info()
2158 rps->vclk = 0; in rv7xx_parse_pplib_non_clock_info()
2163 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rv7xx_parse_pplib_non_clock_info()
2164 rps->vclk = RV770_DEFAULT_VCLK_FREQ; in rv7xx_parse_pplib_non_clock_info()
2442 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_print_power_state()
2486 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_debugfs_print_current_performance_level()
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| H A D | rv6xx_dpm.c | 1518 if ((new_ps->vclk == old_ps->vclk) && in rv6xx_set_uvd_clock_before_set_eng_clock()
1525 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_before_set_eng_clock()
1535 if ((new_ps->vclk == old_ps->vclk) && in rv6xx_set_uvd_clock_after_set_eng_clock()
1542 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_after_set_eng_clock()
1803 rps->vclk = RV6XX_DEFAULT_VCLK_FREQ; in rv6xx_parse_pplib_non_clock_info()
1806 rps->vclk = 0; in rv6xx_parse_pplib_non_clock_info()
2015 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_print_power_state()
2047 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_debugfs_print_current_performance_level()
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| H A D | radeon_uvd.c | 949 unsigned vclk, unsigned dclk, in radeon_uvd_calc_upll_dividers() argument
964 vco_min = max(max(vco_min, vclk), dclk); in radeon_uvd_calc_upll_dividers()
979 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk, in radeon_uvd_calc_upll_dividers()
991 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); in radeon_uvd_calc_upll_dividers()
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| H A D | trinity_dpm.h | 68 u32 vclk; member
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| H A D | radeon_asic.h | 410 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
477 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
534 int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
535 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
749 int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
787 int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
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| /linux/Documentation/devicetree/bindings/media/ |
| H A D | aspeed-video.txt | 13 - clock-names: "vclk" and "eclk"
29 clock-names = "vclk", "eclk";
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| /linux/drivers/tty/serial/8250/ |
| H A D | 8250_aspeed_vuart.c | 424 struct clk *vclk; in aspeed_vuart_probe() local
464 vclk = devm_clk_get_enabled(dev, NULL); in aspeed_vuart_probe()
465 if (IS_ERR(vclk)) { in aspeed_vuart_probe()
466 rc = dev_err_probe(dev, PTR_ERR(vclk), "clk or clock-frequency not defined\n"); in aspeed_vuart_probe()
470 port.port.uartclk = clk_get_rate(vclk); in aspeed_vuart_probe()
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| /linux/drivers/media/platform/renesas/rzg2l-cru/ |
| H A D | rzg2l-csi2.c | 111 struct clk *vclk; member
393 clk_disable_unprepare(csi2->vclk); in rzg2l_csi2_mipi_link_enable()
398 return clk_prepare_enable(csi2->vclk); in rzg2l_csi2_mipi_link_enable()
793 csi2->vclk = devm_clk_get(&pdev->dev, "video"); in rzg2l_csi2_probe()
794 if (IS_ERR(csi2->vclk)) in rzg2l_csi2_probe()
795 return dev_err_probe(&pdev->dev, PTR_ERR(csi2->vclk), in rzg2l_csi2_probe()
797 csi2->vclk_rate = clk_get_rate(csi2->vclk); in rzg2l_csi2_probe()
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| /linux/drivers/gpu/drm/exynos/ |
| H A D | exynos7_drm_decon.c | 68 struct clk *vclk; member
202 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk); in decon_calc_clkdiv()
759 ctx->vclk = devm_clk_get(dev, "decon0_vclk"); in decon_probe()
760 if (IS_ERR(ctx->vclk)) { in decon_probe()
762 ret = PTR_ERR(ctx->vclk); in decon_probe()
819 clk_disable_unprepare(ctx->vclk); in exynos7_decon_suspend()
853 ret = clk_prepare_enable(ctx->vclk); in exynos7_decon_resume()
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| /linux/drivers/gpu/drm/renesas/rz-du/ |
| H A D | rzg2l_mipi_dsi.c | 41 struct clk *vclk; member
289 clk_set_rate(dsi->vclk, mode->clock * 1000); in rzg2l_mipi_dsi_startup()
722 dsi->vclk = devm_clk_get(dsi->dev, "vclk"); in rzg2l_mipi_dsi_probe()
723 if (IS_ERR(dsi->vclk)) in rzg2l_mipi_dsi_probe()
724 return PTR_ERR(dsi->vclk); in rzg2l_mipi_dsi_probe()
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| /linux/arch/arm64/boot/dts/renesas/ |
| H A D | r9a07g043u.dtsi | 139 clock-names = "aclk", "pclk", "vclk";
151 clock-names = "aclk", "pclk", "vclk";
163 clock-names = "aclk", "pclk", "vclk";
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| /linux/drivers/gpu/drm/nouveau/dispnv04/ |
| H A D | arb.c | 252 nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int *lwm) in nouveau_calc_arb() argument
258 nv04_update_arb(dev, vclk, bpp, burst, lwm); in nouveau_calc_arb()
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| /linux/drivers/gpu/drm/logicvc/ |
| H A D | logicvc_drm.h | 57 struct clk *vclk; member
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| H A D | logicvc_drm.c | 158 .clk = &logicvc->vclk, in logicvc_clocks_prepare()
224 &logicvc->vclk, in logicvc_clocks_unprepare()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | smu8_hwmgr.c | 140 if (clock <= ptable->entries[i].vclk) in smu8_get_uvd_level()
148 if (clock >= ptable->entries[i].vclk) in smu8_get_uvd_level()
513 (i < uvd_table->count) ? uvd_table->entries[i].vclk : 0; in smu8_upload_pptable_to_smu()
600 clock = table->entries[level].vclk; in smu8_init_uvd_limit()
602 clock = table->entries[table->count - 1].vclk; in smu8_init_uvd_limit()
1438 smu8_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK; in smu8_dpm_get_pp_table_entry()
1746 uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent; in smu8_read_sensor() local
1780 vclk = uvd_table->entries[uvd_index].vclk; in smu8_read_sensor()
1781 *((uint32_t *)value) = vclk; in smu8_read_sensor()
1916 ptable->entries[ptable->count - 1].vclk; in smu8_dpm_update_uvd_dpm()
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| H A D | hwmgr_ppt.h | 60 uint32_t vclk; /* UVD V-clock */ member
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| /linux/drivers/gpu/drm/amd/pm/powerplay/inc/ |
| H A D | power_state.h | 184 unsigned long vclk; member
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | dcn301_smu.h | 38 uint32_t vclk; member
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