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Searched refs:vclk (Results 1 – 25 of 60) sorted by relevance

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/linux/drivers/video/fbdev/via/
H A Dvt1636.c186 index = get_clk_range_index(plvds_setting_info->vclk); in viafb_vt1636_patch_skew_on_vt3324()
210 index = get_clk_range_index(plvds_setting_info->vclk); in viafb_vt1636_patch_skew_on_vt3327()
227 index = get_clk_range_index(plvds_setting_info->vclk); in viafb_vt1636_patch_skew_on_vt3364()
H A Dchip.h141 u32 vclk; /*panel mode clock value */ member
/linux/drivers/gpu/drm/radeon/
H A Drs780_dpm.c570 if ((new_ps->vclk == old_ps->vclk) && in rs780_set_uvd_clock_before_set_eng_clock()
577 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_before_set_eng_clock()
587 if ((new_ps->vclk == old_ps->vclk) && in rs780_set_uvd_clock_after_set_eng_clock()
594 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_after_set_eng_clock()
727 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in rs780_parse_pplib_non_clock_info()
730 rps->vclk = 0; in rs780_parse_pplib_non_clock_info()
735 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rs780_parse_pplib_non_clock_info()
736 rps->vclk = RS780_DEFAULT_VCLK_FREQ; in rs780_parse_pplib_non_clock_info()
945 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_print_power_state()
994 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_debugfs_print_current_performance_level()
H A Dtrinity_dpm.c850 if ((rps->vclk == 0) && (rps->dclk == 0)) in trinity_uvd_clocks_zero()
862 if ((rps1->vclk == rps2->vclk) && in trinity_uvd_clocks_equal()
895 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
906 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
1410 if ((rps->vclk == pi->sys_info.uvd_clock_table_entries[i].vclk) && in trinity_get_uvd_clock_index()
1644 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in trinity_parse_pplib_non_clock_info()
1647 rps->vclk = 0; in trinity_parse_pplib_non_clock_info()
1887 pi->sys_info.uvd_clock_table_entries[i].vclk = in trinity_parse_sys_info_table()
1973 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_print_power_state()
1998 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_debugfs_print_current_performance_level()
H A Dsumo_dpm.c822 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in sumo_setup_uvd_clocks()
838 if ((new_rps->vclk == old_rps->vclk) && in sumo_set_uvd_clock_before_set_eng_clock()
856 if ((new_rps->vclk == old_rps->vclk) && in sumo_set_uvd_clock_after_set_eng_clock()
1412 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in sumo_parse_pplib_non_clock_info()
1415 rps->vclk = 0; in sumo_parse_pplib_non_clock_info()
1804 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_print_power_state()
1827 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
1835 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
H A Drv770_dpm.c1440 if ((new_ps->vclk == old_ps->vclk) && in rv770_set_uvd_clock_before_set_eng_clock()
1447 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_before_set_eng_clock()
1457 if ((new_ps->vclk == old_ps->vclk) && in rv770_set_uvd_clock_after_set_eng_clock()
1464 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_after_set_eng_clock()
2155 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in rv7xx_parse_pplib_non_clock_info()
2158 rps->vclk = 0; in rv7xx_parse_pplib_non_clock_info()
2163 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rv7xx_parse_pplib_non_clock_info()
2164 rps->vclk = RV770_DEFAULT_VCLK_FREQ; in rv7xx_parse_pplib_non_clock_info()
2442 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_print_power_state()
2486 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_debugfs_print_current_performance_level()
H A Drv6xx_dpm.c1518 if ((new_ps->vclk == old_ps->vclk) && in rv6xx_set_uvd_clock_before_set_eng_clock()
1525 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_before_set_eng_clock()
1535 if ((new_ps->vclk == old_ps->vclk) && in rv6xx_set_uvd_clock_after_set_eng_clock()
1542 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_after_set_eng_clock()
1803 rps->vclk = RV6XX_DEFAULT_VCLK_FREQ; in rv6xx_parse_pplib_non_clock_info()
1806 rps->vclk = 0; in rv6xx_parse_pplib_non_clock_info()
2015 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_print_power_state()
2047 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_debugfs_print_current_performance_level()
H A Dtrinity_dpm.h68 u32 vclk; member
H A Drv770.c52 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
54 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) in rv770_set_uvd_clocks() argument
61 return evergreen_set_uvd_clocks(rdev, vclk, dclk); in rv770_set_uvd_clocks()
68 if (!vclk || !dclk) { in rv770_set_uvd_clocks()
74 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, in rv770_set_uvd_clocks()
H A Dkv_dpm.c677 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk); in kv_populate_uvd_table()
682 (u8)kv_get_clk_bypass(rdev, table->entries[i].vclk); in kv_populate_uvd_table()
687 table->entries[i].vclk, false, &dividers); in kv_populate_uvd_table()
2018 pi->video_start = new_rps->dclk || new_rps->vclk || in kv_apply_state_adjust_rules()
2391 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in kv_parse_pplib_non_clock_info()
2394 rps->vclk = 0; in kv_parse_pplib_non_clock_info()
2652 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in kv_dpm_print_power_state()
/linux/drivers/tty/serial/8250/
H A D8250_aspeed_vuart.c425 struct clk *vclk; in aspeed_vuart_probe() local
465 vclk = devm_clk_get_enabled(dev, NULL); in aspeed_vuart_probe()
466 if (IS_ERR(vclk)) { in aspeed_vuart_probe()
467 rc = dev_err_probe(dev, PTR_ERR(vclk), "clk or clock-frequency not defined\n"); in aspeed_vuart_probe()
471 port.port.uartclk = clk_get_rate(vclk); in aspeed_vuart_probe()
/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g043u.dtsi139 clock-names = "aclk", "pclk", "vclk";
151 clock-names = "aclk", "pclk", "vclk";
163 clock-names = "aclk", "pclk", "vclk";
/linux/drivers/gpu/drm/nouveau/dispnv04/
H A Darb.c252 nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int *lwm) in nouveau_calc_arb() argument
258 nv04_update_arb(dev, vclk, bpp, burst, lwm); in nouveau_calc_arb()
/linux/drivers/gpu/drm/logicvc/
H A Dlogicvc_drm.h57 struct clk *vclk; member
H A Dlogicvc_drm.c158 .clk = &logicvc->vclk, in logicvc_clocks_prepare()
224 &logicvc->vclk, in logicvc_clocks_unprepare()
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu8_hwmgr.c140 if (clock <= ptable->entries[i].vclk) in smu8_get_uvd_level()
148 if (clock >= ptable->entries[i].vclk) in smu8_get_uvd_level()
513 (i < uvd_table->count) ? uvd_table->entries[i].vclk : 0; in smu8_upload_pptable_to_smu()
600 clock = table->entries[level].vclk; in smu8_init_uvd_limit()
602 clock = table->entries[table->count - 1].vclk; in smu8_init_uvd_limit()
1438 smu8_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK; in smu8_dpm_get_pp_table_entry()
1746 uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent; in smu8_read_sensor() local
1780 vclk = uvd_table->entries[uvd_index].vclk; in smu8_read_sensor()
1781 *((uint32_t *)value) = vclk; in smu8_read_sensor()
1916 ptable->entries[ptable->count - 1].vclk; in smu8_dpm_update_uvd_dpm()
H A Dhwmgr_ppt.h60 uint32_t vclk; /* UVD V-clock */ member
H A Dsmu10_hwmgr.h97 uint32_t vclk; member
H A Dsmu8_hwmgr.h114 uint32_t vclk; member
H A Dsmu7_hwmgr.h68 uint32_t vclk; member
H A Dvega10_hwmgr.h96 uint32_t vclk; member
/linux/drivers/clk/meson/
H A DMakefile14 obj-$(CONFIG_COMMON_CLK_MESON_VCLK) += vclk.o
/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dpower_state.h184 unsigned long vclk; member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Ddcn301_smu.h38 uint32_t vclk; member
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_vangogh.h120 uint32_t vclk; member

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