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Searched refs:vba (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_mode_vba_32.c41 dml32_CalculateMaxDETAndMinCompressedBufferSize(mode_lib->vba.ConfigReturnBufferSizeInKByte, in dml32_recalculate()
42 mode_lib->vba.ROBBufferSizeInKByte, in dml32_recalculate()
48 &mode_lib->vba.MaxTotalDETInKByte, &mode_lib->vba.nomDETInKByte, in dml32_recalculate()
49 &mode_lib->vba.MinCompressedBufferSizeInKByte); in dml32_recalculate()
61 struct vba_vars_st *v = &mode_lib->vba; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
76 dml_print("DML::%s: mode_lib->vba.PrefetchMode = %d\n", __func__, mode_lib->vba.PrefetchMode); in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
77 …dml_print("DML::%s: mode_lib->vba.ImmediateFlipSupport = %d\n", __func__, mode_lib->vba.ImmediateF… in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
78 dml_print("DML::%s: mode_lib->vba.VoltageLevel = %d\n", __func__, mode_lib->vba.VoltageLevel); in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
85 for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) { in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
86 if (mode_lib->vba.WritebackEnable[k]) { in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
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H A Ddcn32_fpu.c282 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch() local
284 …ock_change_support temp_clock_change_support = vba->DRAMClockChangeSupport[vlevel][context->bw_ctx… in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
290 …vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_suppor… in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
296 if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported && in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
298 …vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_suppor… in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
300 if (vlevel < context->bw_ctx.dml.vba.soc.num_states && in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
301 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported) in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
478 unsigned int vlevel = context->bw_ctx.dml.vba.VoltageLevel; in dcn32_set_phantom_stream_timing()
479 …unsigned int dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcCo… in dcn32_set_phantom_stream_timing()
480 unsigned int socclk = context->bw_ctx.dml.vba.SOCCLKPerState[vlevel]; in dcn32_set_phantom_stream_timing()
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/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_vba.c57 bool need_recalculate = memcmp(&mode_lib->soc, &mode_lib->vba.soc, sizeof(mode_lib->vba.soc)) != 0 in dml_get_voltage_level()
58 || memcmp(&mode_lib->ip, &mode_lib->vba.ip, sizeof(mode_lib->vba.ip)) != 0 in dml_get_voltage_level()
59 || num_pipes != mode_lib->vba.cache_num_pipes in dml_get_voltage_level()
60 || memcmp(pipes, mode_lib->vba.cache_pipes, in dml_get_voltage_level()
63 mode_lib->vba.soc = mode_lib->soc; in dml_get_voltage_level()
64 mode_lib->vba.ip = mode_lib->ip; in dml_get_voltage_level()
65 memcpy(mode_lib->vba.cache_pipes, pipes, sizeof(*pipes) * num_pipes); in dml_get_voltage_level()
66 mode_lib->vba.cache_num_pipes = num_pipes; in dml_get_voltage_level()
79 return mode_lib->vba.VoltageLevel; in dml_get_voltage_level()
88 dml_get_attr_func(clk_dcf_deepsleep, mode_lib->vba.DCFCLKDeepSleep);
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H A Ddisplay_mode_lib.h89 struct vba_vars_st vba; member
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c1085 bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency; in decide_zstate_support()
1095 if (is_pwrseq0 && context->bw_ctx.dml.vba.StutterPeriod > 5000.0) in decide_zstate_support()
1153 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; in dcn20_calculate_dlg_params()
1154 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; in dcn20_calculate_dlg_params()
1155 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; in dcn20_calculate_dlg_params()
1156 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; in dcn20_calculate_dlg_params()
1161 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; in dcn20_calculate_dlg_params()
1162 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; in dcn20_calculate_dlg_params()
1164 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] in dcn20_calculate_dlg_params()
1225 …bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] … in dcn20_calculate_dlg_params()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c471 …if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[context->bw_ctx.dml.vba.VoltageLevel][context->… in dcn315_update_soc_for_wm_a()
489 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn31_calculate_wm_and_dlg_fp()
562 …context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_d… in dcn31_calculate_wm_and_dlg_fp()
/linux/mm/
H A Dpagewalk.c805 pgoff_t vba, vea, cba, cea; in walk_page_mapping() local
816 vba = vma->vm_pgoff; in walk_page_mapping()
817 vea = vba + vma_pages(vma); in walk_page_mapping()
819 cba = max(cba, vba); in walk_page_mapping()
823 start_addr = ((cba - vba) << PAGE_SHIFT) + vma->vm_start; in walk_page_mapping()
824 end_addr = ((cea - vba) << PAGE_SHIFT) + vma->vm_start; in walk_page_mapping()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c1673 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn30_internal_validate_bw() local
1681 context->bw_ctx.dml.vba.maxMpcComb = 0; in dcn30_internal_validate_bw()
1682 context->bw_ctx.dml.vba.VoltageLevel = 0; in dcn30_internal_validate_bw()
1683 context->bw_ctx.dml.vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive; in dcn30_internal_validate_bw()
1709 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported)) { in dcn30_internal_validate_bw()
1744 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled in dcn30_internal_validate_bw()
1813 odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled; in dcn30_internal_validate_bw()
1899 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; in dcn30_internal_validate_bw()
1905 context->bw_ctx.dml.vba.VoltageLevel = vlevel; in dcn30_internal_validate_bw()
2121 …dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_st… in dcn30_validate_bandwidth()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/
H A Ddcn21_resource.c857 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn21_fast_validate_bw() local
863 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled in dcn21_fast_validate_bw()
887 …if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn21_fast_validate_bw()
911 …dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe… in dcn21_fast_validate_bw()
915 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn21_fast_validate_bw()
937 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = in dcn21_fast_validate_bw()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c1871 struct vba_vars_st *v = &context->bw_ctx.dml.vba; in dcn20_validate_apply_pipe_split_flags()
2104 …if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn20_fast_validate_bw()
2123 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) in dcn20_fast_validate_bw()
2133 …dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe… in dcn20_fast_validate_bw()
2137 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn20_fast_validate_bw()
2160 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = in dcn20_fast_validate_bw()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddml2_wrapper_fpu.c497 context->bw_ctx.dml.vba.StutterPeriod = context->bw_ctx.dml2->v20.dml_core_ctx.mp.StutterPeriod; in dml2_validate_and_build_resource()
501 if (context->bw_ctx.dml.vba.StutterPeriod < in_dc->debug.minimum_z8_residency_time && in dml2_validate_and_build_resource()
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_hw_sequencer.c642 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in set_p_state_switch_method() local
645 if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !vba) in set_p_state_switch_method()
649 if (vba->DRAMClockChangeSupport[vba->VoltageLevel][vba->maxMpcComb] != in set_p_state_switch_method()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/
H A Ddcn314_resource.c1777 …dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_st… in dcn314_validate_bandwidth()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/
H A Ddcn31_resource.c1835 …dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_st… in dcn31_validate_bandwidth()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.c1835 …dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_st… in dml1_validate()