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Searched refs:vba (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_mode_vba_32.c43 dml32_CalculateMaxDETAndMinCompressedBufferSize(mode_lib->vba.ConfigReturnBufferSizeInKByte, in dml32_recalculate()
44 mode_lib->vba.ROBBufferSizeInKByte, in dml32_recalculate()
46 false, //mode_lib->vba.override_setting.nomDETInKByteOverrideEnable, in dml32_recalculate()
47 0, //mode_lib->vba.override_setting.nomDETInKByteOverrideValue, in dml32_recalculate()
50 &mode_lib->vba.MaxTotalDETInKByte, &mode_lib->vba.nomDETInKByte, in dml32_recalculate()
51 &mode_lib->vba.MinCompressedBufferSizeInKByte); in dml32_recalculate()
63 struct vba_vars_st *v = &mode_lib->vba; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
78 dml_print("DML::%s: mode_lib->vba.PrefetchMode = %d\n", __func__, mode_lib->vba in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
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H A Ddcn32_fpu.c285 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
287 enum clock_change_support temp_clock_change_support = vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
293 vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_support; in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
299 if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported && in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
301 vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
282 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; dcn32_find_dummy_latency_index_for_fw_based_mclk_switch() local
481 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; dcn32_set_phantom_stream_timing() local
607 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; dcn32_assign_subvp_pipe() local
1042 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; subvp_validate_static_schedulability() local
1202 update_pipe_slice_table_with_split_flags(struct pipe_slice_table * table,struct dc * dc,struct dc_state * context,struct vba_vars_st * vba,int split[MAX_PIPES],bool merge[MAX_PIPES]) update_pipe_slice_table_with_split_flags() argument
1286 update_pipes_with_split_flags(struct dc * dc,struct dc_state * context,struct vba_vars_st * vba,int split[MAX_PIPES],bool merge[MAX_PIPES]) update_pipes_with_split_flags() argument
1446 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; dcn32_full_validate_bw_helper() local
1620 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; dcn32_calculate_dlg_params() local
1909 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; dcn32_apply_merge_split_flags_helper() local
2114 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; dcn32_internal_validate_bw() local
3490 const struct vba_vars_st *vba = &context->bw_ctx.dml.vba; dcn32_assign_fpo_vactive_candidate() local
3527 const struct vba_vars_st *vba = &context->bw_ctx.dml.vba; dcn32_find_vactive_pipe() local
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/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_vba.c57 bool need_recalculate = memcmp(&mode_lib->soc, &mode_lib->vba.soc, sizeof(mode_lib->vba.soc)) != 0 in dml_get_voltage_level()
58 || memcmp(&mode_lib->ip, &mode_lib->vba.ip, sizeof(mode_lib->vba.ip)) != 0 in dml_get_voltage_level()
59 || num_pipes != mode_lib->vba.cache_num_pipes in dml_get_voltage_level()
60 || memcmp(pipes, mode_lib->vba.cache_pipes, in dml_get_voltage_level()
63 mode_lib->vba.soc = mode_lib->soc; in dml_get_voltage_level()
64 mode_lib->vba.ip = mode_lib->ip; in dml_get_voltage_level()
65 memcpy(mode_lib->vba.cache_pipes, pipes, sizeof(*pipes) * num_pipes); in dml_get_voltage_level()
66 mode_lib->vba in dml_get_voltage_level()
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H A Ddisplay_mode_lib.h89 struct vba_vars_st vba; member
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c1088 bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency; in decide_zstate_support()
1098 if (is_pwrseq0 && context->bw_ctx.dml.vba.StutterPeriod > 5000.0) in decide_zstate_support()
1157 context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(context->bw_ctx.dml.vba.DISPCLK * 1000.0); in dcn20_calculate_dlg_params()
1158 context->bw_ctx.bw.dcn.clk.dcfclk_khz = (int)(context->bw_ctx.dml.vba.DCFCLK * 1000.0); in dcn20_calculate_dlg_params()
1159 context->bw_ctx.bw.dcn.clk.socclk_khz = (int)(context->bw_ctx.dml.vba.SOCCLK * 1000.0); in dcn20_calculate_dlg_params()
1160 context->bw_ctx.bw.dcn.clk.dramclk_khz = (int)(context->bw_ctx.dml.vba.DRAMSpeed * 1000.0 / 16.0); in dcn20_calculate_dlg_params()
1165 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (int)(context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000.0); in dcn20_calculate_dlg_params()
1166 context->bw_ctx.bw.dcn.clk.fclk_khz = (int)(context->bw_ctx.dml.vba.FabricClock * 1000.0); in dcn20_calculate_dlg_params()
1168 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba in dcn20_calculate_dlg_params()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c471 if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[context->bw_ctx.dml.vba.VoltageLevel][context->bw_ctx.dml.vba.maxMpcComb] != dm_dram_clock_change_vactive) in dcn315_update_soc_for_wm_a()
490 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn31_calculate_wm_and_dlg_fp()
565 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_dram_clock_change_vactive; in dcn31_calculate_wm_and_dlg_fp()
/linux/mm/
H A Dpagewalk.c805 pgoff_t vba, vea, cba, cea; in walk_page_mapping() local
816 vba = vma->vm_pgoff; in walk_page_mapping()
817 vea = vba + vma_pages(vma); in walk_page_mapping()
819 cba = max(cba, vba); in walk_page_mapping()
823 start_addr = ((cba - vba) << PAGE_SHIFT) + vma->vm_start; in walk_page_mapping()
824 end_addr = ((cea - vba) << PAGE_SHIFT) + vma->vm_start; in walk_page_mapping()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c1799 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn30_internal_validate_bw()
1807 context->bw_ctx.dml.vba.maxMpcComb = 0; in dcn30_internal_validate_bw()
1808 context->bw_ctx.dml.vba.VoltageLevel = 0; in dcn30_internal_validate_bw()
1809 context->bw_ctx.dml.vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive; in dcn30_internal_validate_bw()
1835 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported)) { in dcn30_internal_validate_bw()
1870 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled in dcn30_internal_validate_bw()
1939 odm = vba
1673 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; dcn30_internal_validate_bw() local
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/
H A Ddcn21_resource.c858 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn21_fast_validate_bw()
864 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled in dcn21_fast_validate_bw()
888 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn21_fast_validate_bw()
912 dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe_idx, true); in dcn21_fast_validate_bw()
916 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn21_fast_validate_bw()
938 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba in dcn21_fast_validate_bw()
857 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; dcn21_fast_validate_bw() local
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c1873 struct vba_vars_st *v = &context->bw_ctx.dml.vba; in dcn20_validate_apply_pipe_split_flags()
2107 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn20_fast_validate_bw()
2126 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) in dcn20_fast_validate_bw()
2136 dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe_idx, true); in dcn20_fast_validate_bw()
2140 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn20_fast_validate_bw()
2163 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = in dcn20_fast_validate_bw()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddml2_wrapper_fpu.c497 context->bw_ctx.dml.vba.StutterPeriod = context->bw_ctx.dml2->v20.dml_core_ctx.mp.StutterPeriod; in dml2_validate_and_build_resource()
501 if (context->bw_ctx.dml.vba.StutterPeriod < in_dc->debug.minimum_z8_residency_time && in dml2_validate_and_build_resource()
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_hw_sequencer.c643 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in set_p_state_switch_method()
646 if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !vba) in set_p_state_switch_method()
650 if (vba->DRAMClockChangeSupport[vba->VoltageLevel][vba->maxMpcComb] != in set_p_state_switch_method()
642 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; set_p_state_switch_method() local
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/
H A Ddcn314_resource.c1902 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); in dcn314_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/
H A Ddcn31_resource.c1959 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); in dcn31_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.c1969 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); in dcn32_populate_dml_pipes_from_context()