1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2014-2018 Broadcom */
3
4 #include <linux/device.h>
5 #include <linux/dma-mapping.h>
6 #include <linux/io.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/reset.h>
10 #include <linux/sched/signal.h>
11 #include <linux/uaccess.h>
12
13 #include <drm/drm_managed.h>
14 #include <drm/drm_print.h>
15
16 #include "v3d_drv.h"
17 #include "v3d_regs.h"
18 #include "v3d_trace.h"
19
20 static void
v3d_init_core(struct v3d_dev * v3d,int core)21 v3d_init_core(struct v3d_dev *v3d, int core)
22 {
23 /* Set OVRTMUOUT, which means that the texture sampler uniform
24 * configuration's tmu output type field is used, instead of
25 * using the hardware default behavior based on the texture
26 * type. If you want the default behavior, you can still put
27 * "2" in the indirect texture state's output_type field.
28 */
29 if (v3d->ver < V3D_GEN_41)
30 V3D_CORE_WRITE(core, V3D_CTL_MISCCFG, V3D_MISCCFG_OVRTMUOUT);
31
32 /* Whenever we flush the L2T cache, we always want to flush
33 * the whole thing.
34 */
35 V3D_CORE_WRITE(core, V3D_CTL_L2TFLSTA, 0);
36 V3D_CORE_WRITE(core, V3D_CTL_L2TFLEND, ~0);
37 }
38
39 /* Sets invariant state for the HW. */
40 static void
v3d_init_hw_state(struct v3d_dev * v3d)41 v3d_init_hw_state(struct v3d_dev *v3d)
42 {
43 v3d_init_core(v3d, 0);
44 }
45
46 static void
v3d_idle_axi(struct v3d_dev * v3d,int core)47 v3d_idle_axi(struct v3d_dev *v3d, int core)
48 {
49 V3D_CORE_WRITE(core, V3D_GMP_CFG(v3d->ver), V3D_GMP_CFG_STOP_REQ);
50
51 if (wait_for((V3D_CORE_READ(core, V3D_GMP_STATUS(v3d->ver)) &
52 (V3D_GMP_STATUS_RD_COUNT_MASK |
53 V3D_GMP_STATUS_WR_COUNT_MASK |
54 V3D_GMP_STATUS_CFG_BUSY)) == 0, 100)) {
55 drm_err(&v3d->drm, "Failed to wait for safe GMP shutdown\n");
56 }
57 }
58
59 static void
v3d_idle_gca(struct v3d_dev * v3d)60 v3d_idle_gca(struct v3d_dev *v3d)
61 {
62 if (v3d->ver >= V3D_GEN_41)
63 return;
64
65 V3D_GCA_WRITE(V3D_GCA_SAFE_SHUTDOWN, V3D_GCA_SAFE_SHUTDOWN_EN);
66
67 if (wait_for((V3D_GCA_READ(V3D_GCA_SAFE_SHUTDOWN_ACK) &
68 V3D_GCA_SAFE_SHUTDOWN_ACK_ACKED) ==
69 V3D_GCA_SAFE_SHUTDOWN_ACK_ACKED, 100)) {
70 drm_err(&v3d->drm, "Failed to wait for safe GCA shutdown\n");
71 }
72 }
73
74 static void
v3d_reset_by_bridge(struct v3d_dev * v3d)75 v3d_reset_by_bridge(struct v3d_dev *v3d)
76 {
77 int version = V3D_BRIDGE_READ(V3D_TOP_GR_BRIDGE_REVISION);
78
79 if (V3D_GET_FIELD(version, V3D_TOP_GR_BRIDGE_MAJOR) == 2) {
80 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_0,
81 V3D_TOP_GR_BRIDGE_SW_INIT_0_V3D_CLK_108_SW_INIT);
82 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_0, 0);
83
84 /* GFXH-1383: The SW_INIT may cause a stray write to address 0
85 * of the unit, so reset it to its power-on value here.
86 */
87 V3D_WRITE(V3D_HUB_AXICFG, V3D_HUB_AXICFG_MAX_LEN_MASK);
88 } else {
89 WARN_ON_ONCE(V3D_GET_FIELD(version,
90 V3D_TOP_GR_BRIDGE_MAJOR) != 7);
91 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_1,
92 V3D_TOP_GR_BRIDGE_SW_INIT_1_V3D_CLK_108_SW_INIT);
93 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_1, 0);
94 }
95 }
96
97 static void
v3d_reset_v3d(struct v3d_dev * v3d)98 v3d_reset_v3d(struct v3d_dev *v3d)
99 {
100 if (v3d->reset)
101 reset_control_reset(v3d->reset);
102 else
103 v3d_reset_by_bridge(v3d);
104
105 v3d_init_hw_state(v3d);
106 }
107
108 void
v3d_reset_sms(struct v3d_dev * v3d)109 v3d_reset_sms(struct v3d_dev *v3d)
110 {
111 if (v3d->ver < V3D_GEN_71)
112 return;
113
114 V3D_SMS_WRITE(V3D_SMS_REE_CS, V3D_SET_FIELD(0x4, V3D_SMS_STATE));
115
116 if (wait_for(!(V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_REE_CS),
117 V3D_SMS_STATE) == V3D_SMS_ISOLATING_FOR_RESET) &&
118 !(V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_REE_CS),
119 V3D_SMS_STATE) == V3D_SMS_RESETTING), 100)) {
120 drm_err(&v3d->drm, "Failed to wait for SMS reset\n");
121 }
122 }
123
124 void
v3d_reset(struct v3d_dev * v3d)125 v3d_reset(struct v3d_dev *v3d)
126 {
127 struct drm_device *dev = &v3d->drm;
128
129 drm_err(dev, "Resetting GPU for hang.\n");
130 drm_err(dev, "V3D_ERR_STAT: 0x%08x\n", V3D_CORE_READ(0, V3D_ERR_STAT));
131
132 trace_v3d_reset_begin(dev);
133
134 /* XXX: only needed for safe powerdown, not reset. */
135 if (false)
136 v3d_idle_axi(v3d, 0);
137
138 v3d_irq_disable(v3d);
139
140 v3d_idle_gca(v3d);
141 v3d_reset_sms(v3d);
142 v3d_reset_v3d(v3d);
143
144 v3d_mmu_set_page_table(v3d);
145 v3d_irq_reset(v3d);
146
147 v3d_perfmon_stop(v3d, v3d->active_perfmon, false);
148
149 trace_v3d_reset_end(dev);
150 }
151
152 static void
v3d_flush_l3(struct v3d_dev * v3d)153 v3d_flush_l3(struct v3d_dev *v3d)
154 {
155 if (v3d->ver < V3D_GEN_41) {
156 u32 gca_ctrl = V3D_GCA_READ(V3D_GCA_CACHE_CTRL);
157
158 V3D_GCA_WRITE(V3D_GCA_CACHE_CTRL,
159 gca_ctrl | V3D_GCA_CACHE_CTRL_FLUSH);
160
161 if (v3d->ver < V3D_GEN_33) {
162 V3D_GCA_WRITE(V3D_GCA_CACHE_CTRL,
163 gca_ctrl & ~V3D_GCA_CACHE_CTRL_FLUSH);
164 }
165 }
166 }
167
168 /* Invalidates the (read-only) L2C cache. This was the L2 cache for
169 * uniforms and instructions on V3D 3.2.
170 */
171 static void
v3d_invalidate_l2c(struct v3d_dev * v3d,int core)172 v3d_invalidate_l2c(struct v3d_dev *v3d, int core)
173 {
174 if (v3d->ver >= V3D_GEN_33)
175 return;
176
177 V3D_CORE_WRITE(core, V3D_CTL_L2CACTL,
178 V3D_L2CACTL_L2CCLR |
179 V3D_L2CACTL_L2CENA);
180 }
181
182 /* Invalidates texture L2 cachelines */
183 static void
v3d_flush_l2t(struct v3d_dev * v3d,int core)184 v3d_flush_l2t(struct v3d_dev *v3d, int core)
185 {
186 /* While there is a busy bit (V3D_L2TCACTL_L2TFLS), we don't
187 * need to wait for completion before dispatching the job --
188 * L2T accesses will be stalled until the flush has completed.
189 * However, we do need to make sure we don't try to trigger a
190 * new flush while the L2_CLEAN queue is trying to
191 * synchronously clean after a job.
192 */
193 mutex_lock(&v3d->cache_clean_lock);
194 V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL,
195 V3D_L2TCACTL_L2TFLS |
196 V3D_SET_FIELD(V3D_L2TCACTL_FLM_FLUSH, V3D_L2TCACTL_FLM));
197 mutex_unlock(&v3d->cache_clean_lock);
198 }
199
200 /* Cleans texture L1 and L2 cachelines (writing back dirty data).
201 *
202 * For cleaning, which happens from the CACHE_CLEAN queue after CSD has
203 * executed, we need to make sure that the clean is done before
204 * signaling job completion. So, we synchronously wait before
205 * returning, and we make sure that L2 invalidates don't happen in the
206 * meantime to confuse our are-we-done checks.
207 */
208 void
v3d_clean_caches(struct v3d_dev * v3d)209 v3d_clean_caches(struct v3d_dev *v3d)
210 {
211 struct drm_device *dev = &v3d->drm;
212 int core = 0;
213
214 trace_v3d_cache_clean_begin(dev);
215
216 /* GFXH-1897: Ensure pending flushes complete before writing L2TCACTL */
217 if (v3d->ver < V3D_GEN_71) {
218 if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) &
219 V3D_L2TCACTL_L2TFLS), 100)) {
220 drm_err(dev, "Timeout waiting for L2T clean\n");
221 }
222 }
223
224 V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, V3D_L2TCACTL_TMUWCF);
225 if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) &
226 V3D_L2TCACTL_TMUWCF), 100)) {
227 drm_err(dev, "Timeout waiting for TMU write combiner flush\n");
228 }
229
230 mutex_lock(&v3d->cache_clean_lock);
231 V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL,
232 V3D_L2TCACTL_L2TFLS |
233 V3D_SET_FIELD(V3D_L2TCACTL_FLM_CLEAN, V3D_L2TCACTL_FLM));
234
235 if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) &
236 V3D_L2TCACTL_L2TFLS), 100)) {
237 drm_err(dev, "Timeout waiting for L2T clean\n");
238 }
239
240 mutex_unlock(&v3d->cache_clean_lock);
241
242 trace_v3d_cache_clean_end(dev);
243 }
244
245 /* Invalidates the slice caches. These are read-only caches. */
246 static void
v3d_invalidate_slices(struct v3d_dev * v3d,int core)247 v3d_invalidate_slices(struct v3d_dev *v3d, int core)
248 {
249 V3D_CORE_WRITE(core, V3D_CTL_SLCACTL,
250 V3D_SET_FIELD(0xf, V3D_SLCACTL_TVCCS) |
251 V3D_SET_FIELD(0xf, V3D_SLCACTL_TDCCS) |
252 V3D_SET_FIELD(0xf, V3D_SLCACTL_UCC) |
253 V3D_SET_FIELD(0xf, V3D_SLCACTL_ICC));
254 }
255
256 void
v3d_invalidate_caches(struct v3d_dev * v3d)257 v3d_invalidate_caches(struct v3d_dev *v3d)
258 {
259 /* Invalidate the caches from the outside in. That way if
260 * another CL's concurrent use of nearby memory were to pull
261 * an invalidated cacheline back in, we wouldn't leave stale
262 * data in the inner cache.
263 */
264 v3d_flush_l3(v3d);
265 v3d_invalidate_l2c(v3d, 0);
266 v3d_flush_l2t(v3d, 0);
267 v3d_invalidate_slices(v3d, 0);
268 }
269
270 static void
v3d_huge_mnt_init(struct v3d_dev * v3d)271 v3d_huge_mnt_init(struct v3d_dev *v3d)
272 {
273 int err = 0;
274
275 if (IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE) && super_pages)
276 err = drm_gem_huge_mnt_create(&v3d->drm, "within_size");
277
278 if (drm_gem_get_huge_mnt(&v3d->drm))
279 drm_info(&v3d->drm, "Using Transparent Hugepages\n");
280 else if (err)
281 drm_warn(&v3d->drm, "Can't use Transparent Hugepages (%d)\n",
282 err);
283 else
284 drm_notice(&v3d->drm,
285 "Transparent Hugepage support is recommended for optimal performance on this platform!\n");
286 }
287
288 int
v3d_gem_init(struct drm_device * dev)289 v3d_gem_init(struct drm_device *dev)
290 {
291 struct v3d_dev *v3d = to_v3d_dev(dev);
292 u32 pt_size = 4096 * 1024;
293 int ret, i;
294
295 for (i = 0; i < V3D_MAX_QUEUES; i++) {
296 struct v3d_queue_state *queue = &v3d->queue[i];
297
298 queue->stats = v3d_stats_alloc();
299 if (!queue->stats) {
300 ret = -ENOMEM;
301 goto err_stats;
302 }
303
304 queue->fence_context = dma_fence_context_alloc(1);
305
306 spin_lock_init(&queue->queue_lock);
307 }
308
309 spin_lock_init(&v3d->mm_lock);
310 ret = drmm_mutex_init(dev, &v3d->bo_lock);
311 if (ret)
312 goto err_stats;
313 ret = drmm_mutex_init(dev, &v3d->reset_lock);
314 if (ret)
315 goto err_stats;
316 ret = drmm_mutex_init(dev, &v3d->sched_lock);
317 if (ret)
318 goto err_stats;
319 ret = drmm_mutex_init(dev, &v3d->cache_clean_lock);
320 if (ret)
321 goto err_stats;
322
323 /* Note: We don't allocate address 0. Various bits of HW
324 * treat 0 as special, such as the occlusion query counters
325 * where 0 means "disabled".
326 */
327 drm_mm_init(&v3d->mm, 1, pt_size / sizeof(u32) - 1);
328
329 v3d->pt = dma_alloc_wc(v3d->drm.dev, pt_size,
330 &v3d->pt_paddr,
331 GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO);
332 if (!v3d->pt) {
333 dev_err(v3d->drm.dev,
334 "Failed to allocate page tables. Please ensure you have DMA enabled.\n");
335 ret = -ENOMEM;
336 goto err_dma_alloc;
337 }
338
339 v3d_init_hw_state(v3d);
340 v3d_mmu_set_page_table(v3d);
341
342 v3d_huge_mnt_init(v3d);
343
344 ret = v3d_sched_init(v3d);
345 if (ret)
346 goto err_sched;
347
348 return 0;
349
350 err_sched:
351 dma_free_coherent(v3d->drm.dev, pt_size, (void *)v3d->pt, v3d->pt_paddr);
352 err_dma_alloc:
353 drm_mm_takedown(&v3d->mm);
354 err_stats:
355 for (i--; i >= 0; i--)
356 v3d_stats_put(v3d->queue[i].stats);
357
358 return ret;
359 }
360
361 void
v3d_gem_destroy(struct drm_device * dev)362 v3d_gem_destroy(struct drm_device *dev)
363 {
364 struct v3d_dev *v3d = to_v3d_dev(dev);
365 enum v3d_queue q;
366
367 v3d_sched_fini(v3d);
368
369 /* Waiting for jobs to finish would need to be done before
370 * unregistering V3D.
371 */
372 for (q = 0; q < V3D_MAX_QUEUES; q++) {
373 WARN_ON(v3d->queue[q].active_job);
374 v3d_stats_put(v3d->queue[q].stats);
375 }
376
377 drm_mm_takedown(&v3d->mm);
378
379 dma_free_coherent(v3d->drm.dev, 4096 * 1024, (void *)v3d->pt,
380 v3d->pt_paddr);
381 }
382