1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 #ifndef __DML_TOP_DISPLAY_CFG_TYPES_H__ 6 #define __DML_TOP_DISPLAY_CFG_TYPES_H__ 7 8 #include "dml2_external_lib_deps.h" 9 10 #define DML2_MAX_PLANES 8 11 #define DML2_MAX_DCN_PIPES 8 12 #define DML2_MAX_MCACHES 8 // assume plane is going to be supported by a max of 8 mcaches 13 #define DML2_MAX_WRITEBACK 3 14 15 enum dml2_swizzle_mode { 16 dml2_sw_linear, // SW_LINEAR accepts 256 byte aligned pitch and also 128 byte aligned pitch if DCC is not enabled 17 dml2_sw_256b_2d, 18 dml2_sw_4kb_2d, 19 dml2_sw_64kb_2d, 20 dml2_sw_256kb_2d, 21 22 dml2_gfx11_sw_linear, 23 dml2_gfx11_sw_64kb_d, 24 dml2_gfx11_sw_64kb_d_t, 25 dml2_gfx11_sw_64kb_d_x, 26 dml2_gfx11_sw_64kb_r_x, 27 dml2_gfx11_sw_256kb_d_x, 28 dml2_gfx11_sw_256kb_r_x, 29 }; 30 31 enum dml2_source_format_class { 32 dml2_444_8 = 0, 33 dml2_444_16 = 1, 34 dml2_444_32 = 2, 35 dml2_444_64 = 3, 36 dml2_420_8 = 4, 37 dml2_420_10 = 5, 38 dml2_420_12 = 6, 39 dml2_rgbe_alpha = 9, 40 dml2_rgbe = 10, 41 dml2_mono_8 = 11, 42 dml2_mono_16 = 12, 43 dml2_422_planar_8 = 13, 44 dml2_422_planar_10 = 14, 45 dml2_422_planar_12 = 15, 46 dml2_422_packed_8 = 16, 47 dml2_422_packed_10 = 17, 48 dml2_422_packed_12 = 18 49 }; 50 51 enum dml2_sample_positioning { 52 dml2_interstitial = 0, 53 dml2_cosited = 1 54 }; 55 56 enum dml2_rotation_angle { 57 dml2_rotation_0 = 0, 58 dml2_rotation_90 = 1, 59 dml2_rotation_180 = 2, 60 dml2_rotation_270 = 3 61 }; 62 63 enum dml2_output_format_class { 64 dml2_444 = 0, 65 dml2_s422 = 1, 66 dml2_n422 = 2, 67 dml2_420 = 3 68 }; 69 70 enum dml2_output_encoder_class { 71 dml2_dp = 0, 72 dml2_edp = 1, 73 dml2_dp2p0 = 2, 74 dml2_hdmi = 3, 75 dml2_hdmifrl = 4, 76 dml2_none = 5 77 }; 78 79 enum dml2_output_link_dp_rate { 80 dml2_dp_rate_na = 0, 81 dml2_dp_rate_hbr = 1, 82 dml2_dp_rate_hbr2 = 2, 83 dml2_dp_rate_hbr3 = 3, 84 dml2_dp_rate_uhbr10 = 4, 85 dml2_dp_rate_uhbr13p5 = 5, 86 dml2_dp_rate_uhbr20 = 6 87 }; 88 89 enum dml2_pstate_type { 90 dml2_pstate_type_uclk = 0, 91 dml2_pstate_type_fclk = 1, 92 dml2_pstate_type_ppt = 2, 93 dml2_pstate_type_temp_read = 3, 94 dml2_pstate_type_dummy_pstate = 4, 95 dml2_pstate_type_count = 5 96 }; 97 98 enum dml2_uclk_pstate_change_strategy { 99 dml2_uclk_pstate_change_strategy_auto = 0, 100 dml2_uclk_pstate_change_strategy_force_vactive = 1, 101 dml2_uclk_pstate_change_strategy_force_vblank = 2, 102 dml2_uclk_pstate_change_strategy_force_drr = 3, 103 dml2_uclk_pstate_change_strategy_force_mall_svp = 4, 104 dml2_uclk_pstate_change_strategy_force_mall_full_frame = 5, 105 }; 106 107 enum dml2_svp_mode_override { 108 dml2_svp_mode_override_auto = 0, 109 dml2_svp_mode_override_main_pipe = 1, 110 dml2_svp_mode_override_phantom_pipe = 2, //does not need to be defined explicitly, main overrides result in implicit phantom additions 111 dml2_svp_mode_override_phantom_pipe_no_data_return = 3, 112 dml2_svp_mode_override_imall = 4 113 }; 114 115 enum dml2_refresh_from_mall_mode_override { 116 dml2_refresh_from_mall_mode_override_auto = 0, 117 dml2_refresh_from_mall_mode_override_force_disable = 1, 118 dml2_refresh_from_mall_mode_override_force_enable = 2 119 }; 120 121 enum dml2_odm_mode { 122 dml2_odm_mode_auto = 0, 123 dml2_odm_mode_bypass, 124 dml2_odm_mode_combine_2to1, 125 dml2_odm_mode_combine_3to1, 126 dml2_odm_mode_combine_4to1, 127 dml2_odm_mode_split_1to2, 128 dml2_odm_mode_mso_1to2, 129 dml2_odm_mode_mso_1to4 130 }; 131 132 enum dml2_scaling_transform { 133 dml2_scaling_transform_explicit = 0, 134 dml2_scaling_transform_fullscreen, 135 dml2_scaling_transform_aspect_ratio, 136 dml2_scaling_transform_centered 137 }; 138 139 enum dml2_dsc_enable_option { 140 dml2_dsc_disable = 0, 141 dml2_dsc_enable = 1, 142 dml2_dsc_enable_if_necessary = 2 143 }; 144 145 enum dml2_tdlut_addressing_mode { 146 dml2_tdlut_sw_linear = 0, 147 dml2_tdlut_simple_linear = 1 148 }; 149 150 enum dml2_tdlut_width_mode { 151 dml2_tdlut_width_17_cube = 0, 152 dml2_tdlut_width_33_cube = 1 153 }; 154 155 enum dml2_twait_budgeting_setting { 156 dml2_twait_budgeting_setting_ignore = 0,// Ignore this budget in twait 157 158 dml2_twait_budgeting_setting_if_needed, // Budget for it only if needed 159 //(i.e. UCLK/FCLK DPM cannot be supported in active) 160 161 dml2_twait_budgeting_setting_try, // Budget for it as long as there is an SoC state that 162 // can support it 163 }; 164 165 struct dml2_get_cursor_dlg_reg{ 166 unsigned int cursor_x_position; 167 unsigned int cursor_hotspot_x; 168 unsigned int cursor_primary_offset; 169 unsigned int cursor_secondary_offset; 170 bool cursor_stereo_en; 171 bool cursor_2x_magnify; 172 double hratio; 173 double pixel_rate_mhz; 174 double dlg_refclk_mhz; 175 }; 176 177 /// @brief Surface Parameters 178 struct dml2_surface_cfg { 179 enum dml2_swizzle_mode tiling; 180 181 struct { 182 unsigned long pitch; // In elements, two pixels per element in 422 packed format 183 unsigned long width; 184 unsigned long height; 185 } plane0; 186 187 188 struct { 189 unsigned long pitch; 190 unsigned long width; 191 unsigned long height; 192 } plane1; 193 194 struct { 195 bool enable; 196 struct { 197 unsigned long pitch; 198 } plane0; 199 struct { 200 unsigned long pitch; 201 } plane1; 202 203 struct { 204 double dcc_rate_plane0; 205 double dcc_rate_plane1; 206 double fraction_of_zero_size_request_plane0; 207 double fraction_of_zero_size_request_plane1; 208 } informative; 209 } dcc; 210 }; 211 212 213 struct dml2_composition_cfg { 214 enum dml2_rotation_angle rotation_angle; 215 bool mirrored; 216 enum dml2_scaling_transform scaling_transform; 217 bool rect_out_height_spans_vactive; 218 219 struct { 220 bool stationary; 221 struct { 222 unsigned long width; 223 unsigned long height; 224 unsigned long x_start; 225 unsigned long y_start; 226 } plane0; 227 228 struct { 229 unsigned long width; 230 unsigned long height; 231 unsigned long x_start; 232 unsigned long y_start; 233 } plane1; 234 } viewport; 235 236 struct { 237 bool enabled; 238 bool easf_enabled; 239 bool isharp_enabled; 240 bool upsp_enabled; 241 enum dml2_sample_positioning upsp_sample_positioning; 242 unsigned int upsp_vtaps; 243 struct { 244 double h_ratio; 245 double v_ratio; 246 unsigned int h_taps; 247 unsigned int v_taps; 248 } plane0; 249 250 struct { 251 double h_ratio; 252 double v_ratio; 253 unsigned int h_taps; 254 unsigned int v_taps; 255 } plane1; 256 257 unsigned long rect_out_width; 258 } scaler_info; 259 }; 260 261 struct dml2_timing_cfg { 262 unsigned long h_total; 263 unsigned long v_total; 264 unsigned long h_blank_end; 265 unsigned long v_blank_end; 266 unsigned long h_front_porch; 267 unsigned long v_front_porch; 268 unsigned long h_sync_width; 269 unsigned long pixel_clock_khz; 270 unsigned long h_active; 271 unsigned long v_active; 272 unsigned int bpc; //FIXME: review with Jun 273 struct { 274 enum dml2_dsc_enable_option enable; 275 unsigned int dsc_compressed_bpp_x16; 276 struct { 277 // for dv to specify num dsc slices to use 278 unsigned int num_slices; 279 } overrides; 280 } dsc; 281 bool interlaced; 282 struct { 283 /* static */ 284 bool enabled; 285 unsigned long min_refresh_uhz; 286 unsigned int max_instant_vtotal_delta; 287 /* dynamic */ 288 bool disallowed; 289 bool drr_active_variable; 290 bool drr_active_fixed; 291 } drr_config; 292 unsigned long vblank_nom; 293 }; 294 295 struct dml2_link_output_cfg { 296 enum dml2_output_format_class output_format; 297 enum dml2_output_encoder_class output_encoder; 298 unsigned int output_dp_lane_count; 299 enum dml2_output_link_dp_rate output_dp_link_rate; 300 unsigned long audio_sample_rate; 301 unsigned long audio_sample_layout; 302 bool output_disabled; // The stream does not go to a backend for output to a physical 303 //connector (e.g. writeback only, phantom pipe) goes to writeback 304 bool validate_output; // Do not validate the link configuration for this display stream. 305 }; 306 307 struct dml2_writeback_info { 308 enum dml2_source_format_class pixel_format; 309 unsigned long input_width; 310 unsigned long input_height; 311 unsigned long output_width; 312 unsigned long output_height; 313 unsigned long v_taps; 314 unsigned long h_taps; 315 unsigned long v_taps_chroma; 316 unsigned long h_taps_chroma; 317 double h_ratio; 318 double v_ratio; 319 }; 320 321 struct dml2_writeback_cfg { 322 unsigned int active_writebacks_per_stream; 323 struct dml2_writeback_info writeback_stream[DML2_MAX_WRITEBACK]; 324 }; 325 326 struct dml2_plane_parameters { 327 unsigned int stream_index; // Identifies which plane will be composed 328 329 enum dml2_source_format_class pixel_format; 330 /* 331 * The surface and composition structures use 332 * the terms plane0 and plane1. These planes 333 * are expected to hold the following data based 334 * on the pixel format. 335 * 336 * RGB or YUV Non-Planar Types: 337 * dml2_444_8 338 * dml2_444_16 339 * dml2_444_32 340 * dml2_444_64 341 * dml2_rgbe 342 * 343 * plane0 = argb or rgbe 344 * plane1 = not used 345 * 346 * YUV Planar-Types: 347 * dml2_420_8 348 * dml2_420_10 349 * dml2_420_12 350 * 351 * plane0 = luma 352 * plane1 = chroma 353 * 354 * RGB Planar Types: 355 * dml2_rgbe_alpha 356 * 357 * plane0 = rgbe 358 * plane1 = alpha 359 * 360 * Mono Non-Planar Types: 361 * dml2_mono_8 362 * dml2_mono_16 363 * 364 * plane0 = luma 365 * plane1 = not used 366 */ 367 368 struct dml2_surface_cfg surface; 369 struct dml2_composition_cfg composition; 370 371 struct { 372 bool enable; 373 unsigned long lines_before_active_required; 374 unsigned long transmitted_bytes; 375 } dynamic_meta_data; 376 377 struct { 378 unsigned int num_cursors; 379 unsigned long cursor_width; 380 unsigned long cursor_bpp; 381 } cursor; 382 383 // For TDLUT, SW would assume TDLUT is setup and enable all the time and 384 // budget for worst case addressing/width mode 385 struct { 386 bool setup_for_tdlut; 387 enum dml2_tdlut_addressing_mode tdlut_addressing_mode; 388 enum dml2_tdlut_width_mode tdlut_width_mode; 389 bool tdlut_mpc_width_flag; 390 } tdlut; 391 392 bool immediate_flip; 393 394 struct { 395 // Logical overrides to power management policies (usually) 396 enum dml2_uclk_pstate_change_strategy uclk_pstate_change_strategy; 397 enum dml2_refresh_from_mall_mode_override refresh_from_mall; 398 unsigned int det_size_override_kb; 399 unsigned int mpcc_combine_factor; 400 401 // reserved_vblank_time_ns is the minimum time to reserve in vblank for Twait 402 // The actual reserved vblank time used for the corresponding stream in mode_programming would be at least as much as this per-plane override. 403 long reserved_vblank_time_ns; 404 unsigned int max_vactive_det_fill_delay_us[dml2_pstate_type_count]; // 0 = no reserved time, +ve = explicit max delay 405 unsigned int gpuvm_min_page_size_kbytes; 406 unsigned int hostvm_min_page_size_kbytes; 407 408 enum dml2_svp_mode_override legacy_svp_config; //TODO remove in favor of svp_config 409 bool use_max_lsw; 410 411 struct { 412 // HW specific overrides, there's almost no reason to mess with these 413 // generally used for debugging or simulation 414 bool force_one_row_for_frame; 415 struct { 416 bool enable; 417 bool value; 418 } force_pte_buffer_mode; 419 double dppclk_mhz; 420 } hw; 421 } overrides; 422 }; 423 424 struct dml2_stream_parameters { 425 struct dml2_timing_cfg timing; 426 struct dml2_link_output_cfg output; 427 struct dml2_writeback_cfg writeback; 428 429 struct { 430 enum dml2_odm_mode odm_mode; 431 bool disable_dynamic_odm; 432 bool disable_subvp; 433 int minimum_vblank_idle_requirement_us; 434 435 struct { 436 struct { 437 enum dml2_twait_budgeting_setting uclk_pstate; 438 enum dml2_twait_budgeting_setting fclk_pstate; 439 enum dml2_twait_budgeting_setting stutter_enter_exit; 440 } twait_budgeting; 441 } hw; 442 } overrides; 443 }; 444 445 struct dml2_display_cfg { 446 bool gpuvm_enable; 447 bool ffbm_enable; 448 bool hostvm_enable; 449 450 // Allocate DET proportionally between streams based on pixel rate 451 // and then allocate proportionally between planes. 452 bool minimize_det_reallocation; 453 454 unsigned int gpuvm_max_page_table_levels; 455 unsigned int hostvm_max_non_cached_page_table_levels; 456 457 struct dml2_plane_parameters plane_descriptors[DML2_MAX_PLANES]; 458 struct dml2_stream_parameters stream_descriptors[DML2_MAX_PLANES]; 459 460 unsigned int num_planes; 461 unsigned int num_streams; 462 463 struct { 464 struct { 465 // HW specific overrides, there's almost no reason to mess with these 466 // generally used for debugging or simulation 467 struct { 468 bool enable; 469 bool value; 470 } force_unbounded_requesting; 471 472 struct { 473 bool enable; 474 bool value; 475 } force_nom_det_size_kbytes; 476 477 bool mode_support_check_disable; 478 bool mcache_admissibility_check_disable; 479 bool surface_viewport_size_check_disable; 480 double dlg_ref_clk_mhz; 481 double dispclk_mhz; 482 double dcfclk_mhz; 483 bool optimize_tdlut_scheduling; // TBD: for DV, will set this to 1, to ensure tdlut schedule is calculated based on address/width mode 484 } hw; 485 486 struct { 487 bool uclk_pstate_change_disable; 488 bool fclk_pstate_change_disable; 489 bool g6_temp_read_pstate_disable; 490 bool g7_ppt_pstate_disable; 491 } power_management; 492 493 bool enhanced_prefetch_schedule_acceleration; 494 bool dcc_programming_assumes_scan_direction_unknown; 495 bool synchronize_timings; 496 bool synchronize_ddr_displays_for_uclk_pstate_change; 497 bool max_outstanding_when_urgent_expected_disable; 498 bool enable_subvp_implicit_pmo; //enables PMO to switch pipe uclk strategy to subvp, and generate phantom programming 499 bool all_streams_blanked; 500 } overrides; 501 }; 502 503 struct dml2_pipe_configuration_descriptor { 504 struct { 505 unsigned int viewport_x_start; 506 unsigned int viewport_width; 507 } plane0; 508 509 struct { 510 unsigned int viewport_x_start; 511 unsigned int viewport_width; 512 } plane1; 513 514 bool plane1_enabled; 515 bool imall_enabled; 516 }; 517 518 struct dml2_plane_mcache_configuration_descriptor { 519 const struct dml2_plane_parameters *plane_descriptor; 520 const struct dml2_mcache_surface_allocation *mcache_allocation; 521 522 struct dml2_pipe_configuration_descriptor pipe_configurations[DML2_MAX_DCN_PIPES]; 523 char num_pipes; 524 }; 525 526 #endif 527