Searched refs:umc (Results 1 – 16 of 16) sorted by relevance
75 return adev->umc.channel_offs * ch_inst + UMC_8_INST_DIST * umc_inst + in get_umc_v8_10_reg_offset()216 adev->umc.channel_idx_tbl[node_inst * adev->umc.umc_inst_num * in umc_v8_10_convert_error_address()217 adev->umc.channel_inst_num + in umc_v8_10_convert_error_address()218 umc_inst * adev->umc.channel_inst_num + in umc_v8_10_convert_error_address()343 eccinfo_table_idx = node_inst * adev->umc.umc_inst_num * in umc_v8_10_ecc_info_query_correctable_error_count()344 adev->umc.channel_inst_num + in umc_v8_10_ecc_info_query_correctable_error_count()345 umc_inst * adev->umc.channel_inst_num + in umc_v8_10_ecc_info_query_correctable_error_count()362 eccinfo_table_idx = node_inst * adev->umc.umc_inst_num * in umc_v8_10_ecc_info_query_uncorrectable_error_count()363 adev->umc.channel_inst_num + in umc_v8_10_ecc_info_query_uncorrectable_error_count()364 umc_inst * adev->umc.channel_inst_num + in umc_v8_10_ecc_info_query_uncorrectable_error_count()[all …]
50 uint32_t index = umc_inst * adev->umc.channel_inst_num + ch_inst; in get_umc_v6_7_reg_offset()57 return adev->umc.channel_offs * ch_inst + UMC_V6_7_INST_DIST * umc_inst; in get_umc_v6_7_reg_offset()106 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst; in umc_v6_7_ecc_info_query_correctable_error_count()119 adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst]; in umc_v6_7_ecc_info_query_correctable_error_count()148 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst; in umc_v6_7_ecc_info_querry_uncorrectable_error_count()195 adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst]; in umc_v6_7_convert_error_address()231 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst; in umc_v6_7_ecc_info_query_error_address()319 adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst]; in umc_v6_7_query_correctable_error_count()
1412 adev->umc.funcs = &umc_v6_0_funcs; in gmc_v9_0_set_umc_funcs()1415 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; in gmc_v9_0_set_umc_funcs()1416 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; in gmc_v9_0_set_umc_funcs()1417 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; in gmc_v9_0_set_umc_funcs()1418 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20; in gmc_v9_0_set_umc_funcs()1419 adev->umc.retire_unit = 1; in gmc_v9_0_set_umc_funcs()1420 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; in gmc_v9_0_set_umc_funcs()1421 adev->umc.ras = &umc_v6_1_ras; in gmc_v9_0_set_umc_funcs()1424 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; in gmc_v9_0_set_umc_funcs()1425 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; in gmc_v9_0_set_umc_funcs()[all …]
573 adev->umc.channel_inst_num = UMC_V8_10_CHANNEL_INSTANCE_NUM; in gmc_v11_0_set_umc_funcs()574 adev->umc.umc_inst_num = UMC_V8_10_UMC_INSTANCE_NUM; in gmc_v11_0_set_umc_funcs()575 adev->umc.max_ras_err_cnt_per_query = UMC_V8_10_TOTAL_CHANNEL_NUM(adev); in gmc_v11_0_set_umc_funcs()576 adev->umc.channel_offs = UMC_V8_10_PER_CHANNEL_OFFSET; in gmc_v11_0_set_umc_funcs()577 adev->umc.retire_unit = UMC_V8_10_NA_COL_2BITS_POWER_OF_2_NUM; in gmc_v11_0_set_umc_funcs()578 if (adev->umc.node_inst_num == 4) in gmc_v11_0_set_umc_funcs()579 adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl_ext0[0][0][0]; in gmc_v11_0_set_umc_funcs()581 adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl[0][0][0]; in gmc_v11_0_set_umc_funcs()582 adev->umc.ras = &umc_v8_10_ras; in gmc_v11_0_set_umc_funcs()963 if (adev->umc.funcs && adev->umc.funcs->init_registers) in gmc_v11_0_hw_init()[all …]
47 return adev->umc.channel_offs*ch_inst + UMC_8_INST_DIST*umc_inst; in get_umc_v8_7_reg_offset()58 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst; in umc_v8_7_ecc_info_query_correctable_error_count()77 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst; in umc_v8_7_ecc_info_querry_uncorrectable_error_count()119 adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst]; in umc_v8_7_convert_error_address()139 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst; in umc_v8_7_ecc_info_query_error_address()
1103 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_ras_get_ecc_info()1104 adev->umc.ras->ras_block.hw_ops->query_ras_error_count) in amdgpu_ras_get_ecc_info()1105 adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data); in amdgpu_ras_get_ecc_info()1110 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_ras_get_ecc_info()1111 adev->umc.ras->ras_block.hw_ops->query_ras_error_address) in amdgpu_ras_get_ecc_info()1112 adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, err_data); in amdgpu_ras_get_ecc_info()1114 if (adev->umc.ras && in amdgpu_ras_get_ecc_info()1115 adev->umc.ras->ecc_info_query_ras_error_count) in amdgpu_ras_get_ecc_info()1116 adev->umc.ras->ecc_info_query_ras_error_count(adev, err_data); in amdgpu_ras_get_ecc_info()1118 if (adev->umc.ras && in amdgpu_ras_get_ecc_info()[all …]
583 adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM; in gmc_v10_0_set_umc_funcs()584 adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM; in gmc_v10_0_set_umc_funcs()585 adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM; in gmc_v10_0_set_umc_funcs()586 adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA; in gmc_v10_0_set_umc_funcs()587 adev->umc.retire_unit = 1; in gmc_v10_0_set_umc_funcs()588 adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0]; in gmc_v10_0_set_umc_funcs()589 adev->umc.ras = &umc_v8_7_ras; in gmc_v10_0_set_umc_funcs()1011 if (adev->umc.funcs && adev->umc.funcs->init_registers) in gmc_v10_0_hw_init()1012 adev->umc.funcs->init_registers(adev); in gmc_v10_0_hw_init()
607 adev->umc.channel_inst_num = UMC_V8_14_CHANNEL_INSTANCE_NUM; in gmc_v12_0_set_umc_funcs()608 adev->umc.umc_inst_num = UMC_V8_14_UMC_INSTANCE_NUM(adev); in gmc_v12_0_set_umc_funcs()609 adev->umc.node_inst_num = 0; in gmc_v12_0_set_umc_funcs()610 adev->umc.max_ras_err_cnt_per_query = UMC_V8_14_TOTAL_CHANNEL_NUM(adev); in gmc_v12_0_set_umc_funcs()611 adev->umc.channel_offs = UMC_V8_14_PER_CHANNEL_OFFSET; in gmc_v12_0_set_umc_funcs()612 adev->umc.ras = &umc_v8_14_ras; in gmc_v12_0_set_umc_funcs()948 if (adev->umc.funcs && adev->umc.funcs->init_registers) in gmc_v12_0_hw_init()949 adev->umc.funcs->init_registers(adev); in gmc_v12_0_hw_init()
32 #define UMC_V8_14_UMC_INSTANCE_NUM(adev) ((adev)->umc.node_inst_num)
91 return adev->umc.channel_offs*ch_inst + UMC_6_INST_DIST*umc_inst; in get_umc_6_reg_offset()303 …uint32_t channel_index = adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst… in umc_v6_1_query_error_address()
34 return adev->umc.channel_offs * ch_inst + UMC_V8_14_INST_DIST * umc_inst; in get_umc_v8_14_reg_offset()
33 if (adev->umc.ras->check_ecc_err_status) in amdgpu_mca_is_deferred_error()34 return adev->umc.ras->check_ecc_err_status(adev, in amdgpu_mca_is_deferred_error()
811 adev->umc.active_mask = ((1 << adev->umc.node_inst_num) - 1) & in amdgpu_discovery_read_from_harvest_table()1484 adev->umc.node_inst_num++; in amdgpu_discovery_reg_base_init()
1156 struct amdgpu_umc umc; member
16 amd_atl-y += umc.o
48 obj-$(CONFIG_CPU_SUP_UMC_32) += umc.o