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Searched refs:umc (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_umc.c62 adev->umc.max_ras_err_cnt_per_query); in amdgpu_umc_page_retirement_mca()
70 err_data.err_addr_len = adev->umc.max_ras_err_cnt_per_query; in amdgpu_umc_page_retirement_mca()
109 adev->umc.max_ras_err_cnt_per_query); in amdgpu_umc_handle_bad_pages()
118 err_data->err_addr_len = adev->umc.max_ras_err_cnt_per_query; in amdgpu_umc_handle_bad_pages()
125 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_handle_bad_pages()
126 adev->umc.ras->ras_block.hw_ops->query_ras_error_count) in amdgpu_umc_handle_bad_pages()
127 adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, in amdgpu_umc_handle_bad_pages()
130 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_handle_bad_pages()
131 adev->umc.ras->ras_block.hw_ops->query_ras_error_address && in amdgpu_umc_handle_bad_pages()
132 adev->umc.max_ras_err_cnt_per_query) { in amdgpu_umc_handle_bad_pages()
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H A Dumc_v8_10.c75 return adev->umc.channel_offs * ch_inst + UMC_8_INST_DIST * umc_inst + in get_umc_v8_10_reg_offset()
216 adev->umc.channel_idx_tbl[node_inst * adev->umc.umc_inst_num * in umc_v8_10_convert_error_address()
217 adev->umc.channel_inst_num + in umc_v8_10_convert_error_address()
218 umc_inst * adev->umc.channel_inst_num + in umc_v8_10_convert_error_address()
343 eccinfo_table_idx = node_inst * adev->umc.umc_inst_num * in umc_v8_10_ecc_info_query_correctable_error_count()
344 adev->umc.channel_inst_num + in umc_v8_10_ecc_info_query_correctable_error_count()
345 umc_inst * adev->umc.channel_inst_num + in umc_v8_10_ecc_info_query_correctable_error_count()
362 eccinfo_table_idx = node_inst * adev->umc.umc_inst_num * in umc_v8_10_ecc_info_query_uncorrectable_error_count()
363 adev->umc.channel_inst_num + in umc_v8_10_ecc_info_query_uncorrectable_error_count()
364 umc_inst * adev->umc.channel_inst_num + in umc_v8_10_ecc_info_query_uncorrectable_error_count()
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H A Dumc_v6_7.c50 uint32_t index = umc_inst * adev->umc.channel_inst_num + ch_inst; in get_umc_v6_7_reg_offset()
57 return adev->umc.channel_offs * ch_inst + UMC_V6_7_INST_DIST * umc_inst; in get_umc_v6_7_reg_offset()
106 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst; in umc_v6_7_ecc_info_query_correctable_error_count()
119 adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst]; in umc_v6_7_ecc_info_query_correctable_error_count()
148 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst; in umc_v6_7_ecc_info_querry_uncorrectable_error_count()
195 adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst]; in umc_v6_7_convert_error_address()
231 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst; in umc_v6_7_ecc_info_query_error_address()
319 adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst]; in umc_v6_7_query_correctable_error_count()
H A Dgmc_v9_0.c1381 adev->umc.funcs = &umc_v6_0_funcs; in gmc_v9_0_set_umc_funcs()
1384 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; in gmc_v9_0_set_umc_funcs()
1385 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; in gmc_v9_0_set_umc_funcs()
1386 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; in gmc_v9_0_set_umc_funcs()
1387 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20; in gmc_v9_0_set_umc_funcs()
1388 adev->umc.retire_unit = 1; in gmc_v9_0_set_umc_funcs()
1389 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; in gmc_v9_0_set_umc_funcs()
1390 adev->umc.ras = &umc_v6_1_ras; in gmc_v9_0_set_umc_funcs()
1393 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; in gmc_v9_0_set_umc_funcs()
1394 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; in gmc_v9_0_set_umc_funcs()
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H A Dumc_v12_0.c39 uint32_t index = umc_inst * adev->umc.channel_inst_num + ch_inst; in get_umc_v12_0_reg_offset()
45 return adev->umc.channel_offs * ch_inst + UMC_V12_0_INST_DIST * umc_inst + in get_umc_v12_0_reg_offset()
181 struct amdgpu_umc_flip_bits *flip_bits = &(adev->umc.flip_bits); in umc_v12_0_get_retire_flip_bits()
232 adev->umc.retire_unit = 0x1 << flip_bits->bit_num; in umc_v12_0_get_retire_flip_bits()
271 flip_bits = adev->umc.flip_bits.flip_bits_in_pa; in umc_v12_0_convert_error_address()
272 bit_num = adev->umc.flip_bits.bit_num; in umc_v12_0_convert_error_address()
273 retire_unit = adev->umc.retire_unit; in umc_v12_0_convert_error_address()
286 row_lower &= ~BIT_ULL(adev->umc.flip_bits.flip_row_bit); in umc_v12_0_convert_error_address()
289 row_high = (soc_pa >> adev->umc.flip_bits.r13_in_pa) & 0x3ULL; in umc_v12_0_convert_error_address()
309 row = ((column >> 3) << adev->umc.flip_bits.flip_row_bit) | in umc_v12_0_convert_error_address()
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H A Dumc_v8_7.c47 return adev->umc.channel_offs*ch_inst + UMC_8_INST_DIST*umc_inst; in get_umc_v8_7_reg_offset()
58 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst; in umc_v8_7_ecc_info_query_correctable_error_count()
77 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst; in umc_v8_7_ecc_info_querry_uncorrectable_error_count()
119 adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst]; in umc_v8_7_convert_error_address()
139 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst; in umc_v8_7_ecc_info_query_error_address()
H A Damdgpu_ras.c1108 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_ras_get_ecc_info()
1109 adev->umc.ras->ras_block.hw_ops->query_ras_error_count) in amdgpu_ras_get_ecc_info()
1110 adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data); in amdgpu_ras_get_ecc_info()
1115 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_ras_get_ecc_info()
1116 adev->umc.ras->ras_block.hw_ops->query_ras_error_address) in amdgpu_ras_get_ecc_info()
1117 adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, err_data); in amdgpu_ras_get_ecc_info()
1119 if (adev->umc.ras && in amdgpu_ras_get_ecc_info()
1120 adev->umc.ras->ecc_info_query_ras_error_count) in amdgpu_ras_get_ecc_info()
1121 adev->umc.ras->ecc_info_query_ras_error_count(adev, err_data); in amdgpu_ras_get_ecc_info()
1123 if (adev->umc.ras && in amdgpu_ras_get_ecc_info()
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H A Dumc_v8_14.h32 #define UMC_V8_14_UMC_INSTANCE_NUM(adev) ((adev)->umc.node_inst_num)
H A Dumc_v8_14.c34 return adev->umc.channel_offs * ch_inst + UMC_V8_14_INST_DIST * umc_inst; in get_umc_v8_14_reg_offset()
H A Damdgpu_mca.c33 if (adev->umc.ras->check_ecc_err_status) in amdgpu_mca_is_deferred_error()
34 return adev->umc.ras->check_ecc_err_status(adev, in amdgpu_mca_is_deferred_error()
H A Damdgpu_ras_eeprom.c1055 if (!adev->umc.ras || !adev->umc.ras->mca_ipid_parse) in amdgpu_ras_eeprom_read_idx()
1078 adev->umc.ras->mca_ipid_parse(adev, ipid, in amdgpu_ras_eeprom_read_idx()
H A Damdgpu_discovery.c833 adev->umc.active_mask = ((1 << adev->umc.node_inst_num) - 1) & in amdgpu_discovery_read_from_harvest_table()
1502 adev->umc.node_inst_num++; in amdgpu_discovery_reg_base_init()
H A Damdgpu.h1068 struct amdgpu_umc umc; member
H A Damdgpu_psp.c1997 ras_cmd->ras_in_message.init_flags.active_umc_mask = adev->umc.active_mask; in psp_ras_initialize()
/linux/drivers/edac/
H A Damd64_edac.c1085 if (!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT)) in umc_determine_edac_cap()
1091 if (pvt->umc[i].umc_cfg & BIT(12)) in umc_determine_edac_cap()
1283 static int umc_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc, in umc_addr_mask_to_cs_size() argument
1326 addr_mask = pvt->csels[umc].csmasks[cs_mask_nr]; in umc_addr_mask_to_cs_size()
1329 addr_mask_sec = pvt->csels[umc].csmasks_sec[cs_mask_nr]; in umc_addr_mask_to_cs_size()
1357 struct amd64_umc *umc; in umc_dump_misc_regs() local
1361 umc = &pvt->umc[i]; in umc_dump_misc_regs()
1363 edac_dbg(1, "UMC%d DIMM cfg: 0x%x\n", i, umc->dimm_cfg); in umc_dump_misc_regs()
1364 edac_dbg(1, "UMC%d UMC cfg: 0x%x\n", i, umc->umc_cfg); in umc_dump_misc_regs()
1365 edac_dbg(1, "UMC%d SDP ctrl: 0x%x\n", i, umc->sdp_ctrl); in umc_dump_misc_regs()
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/linux/drivers/ras/amd/atl/
H A DMakefile16 amd_atl-y += umc.o
/linux/arch/x86/kernel/cpu/
H A DMakefile48 obj-$(CONFIG_CPU_SUP_UMC_32) += umc.o
/linux/drivers/scsi/
H A Dmegaraid.c3501 megacmd_t __user *umc; in mega_n_to_m() local
3521 umc = MBOX_P(uiocp); in mega_n_to_m()
3523 if (get_user(upthru, (mega_passthru __user * __user *)&umc->xferaddr)) in mega_n_to_m()
3538 umc = (megacmd_t __user *)uioc_mimd->mbox; in mega_n_to_m()
3540 if (get_user(upthru, (mega_passthru __user * __user *)&umc->xferaddr)) in mega_n_to_m()
/linux/drivers/gpu/drm/amd/ras/ras_mgr/
H A Damdgpu_ras_mgr.c218 ras_ta_param->active_umc_mask = adev->umc.active_mask; in amdgpu_ras_mgr_get_ras_ta_init_param()