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Searched refs:umc (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_umc.c62 adev->umc.max_ras_err_cnt_per_query); in amdgpu_umc_page_retirement_mca()
70 err_data.err_addr_len = adev->umc.max_ras_err_cnt_per_query; in amdgpu_umc_page_retirement_mca()
108 adev->umc.max_ras_err_cnt_per_query); in amdgpu_umc_handle_bad_pages()
117 err_data->err_addr_len = adev->umc.max_ras_err_cnt_per_query; in amdgpu_umc_handle_bad_pages()
123 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_handle_bad_pages()
124 adev->umc.ras->ras_block.hw_ops->query_ras_error_count) in amdgpu_umc_handle_bad_pages()
125 adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, in amdgpu_umc_handle_bad_pages()
128 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_handle_bad_pages()
129 adev->umc.ras->ras_block.hw_ops->query_ras_error_address && in amdgpu_umc_handle_bad_pages()
130 adev->umc.max_ras_err_cnt_per_query) { in amdgpu_umc_handle_bad_pages()
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H A Dumc_v8_10.c75 return adev->umc.channel_offs * ch_inst + UMC_8_INST_DIST * umc_inst + in get_umc_v8_10_reg_offset()
216 adev->umc.channel_idx_tbl[node_inst * adev->umc.umc_inst_num * in umc_v8_10_convert_error_address()
217 adev->umc.channel_inst_num + in umc_v8_10_convert_error_address()
218 umc_inst * adev->umc.channel_inst_num + in umc_v8_10_convert_error_address()
343 eccinfo_table_idx = node_inst * adev->umc.umc_inst_num * in umc_v8_10_ecc_info_query_correctable_error_count()
344 adev->umc.channel_inst_num + in umc_v8_10_ecc_info_query_correctable_error_count()
345 umc_inst * adev->umc.channel_inst_num + in umc_v8_10_ecc_info_query_correctable_error_count()
362 eccinfo_table_idx = node_inst * adev->umc.umc_inst_num * in umc_v8_10_ecc_info_query_uncorrectable_error_count()
363 adev->umc.channel_inst_num + in umc_v8_10_ecc_info_query_uncorrectable_error_count()
364 umc_inst * adev->umc.channel_inst_num + in umc_v8_10_ecc_info_query_uncorrectable_error_count()
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H A Dumc_v6_7.c50 uint32_t index = umc_inst * adev->umc.channel_inst_num + ch_inst; in get_umc_v6_7_reg_offset()
57 return adev->umc.channel_offs * ch_inst + UMC_V6_7_INST_DIST * umc_inst; in get_umc_v6_7_reg_offset()
106 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst; in umc_v6_7_ecc_info_query_correctable_error_count()
119 adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst]; in umc_v6_7_ecc_info_query_correctable_error_count()
148 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst; in umc_v6_7_ecc_info_querry_uncorrectable_error_count()
195 adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst]; in umc_v6_7_convert_error_address()
231 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst; in umc_v6_7_ecc_info_query_error_address()
319 adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst]; in umc_v6_7_query_correctable_error_count()
H A Dgmc_v11_0.c556 adev->umc.channel_inst_num = UMC_V8_10_CHANNEL_INSTANCE_NUM; in gmc_v11_0_set_umc_funcs()
557 adev->umc.umc_inst_num = UMC_V8_10_UMC_INSTANCE_NUM; in gmc_v11_0_set_umc_funcs()
558 adev->umc.max_ras_err_cnt_per_query = UMC_V8_10_TOTAL_CHANNEL_NUM(adev); in gmc_v11_0_set_umc_funcs()
559 adev->umc.channel_offs = UMC_V8_10_PER_CHANNEL_OFFSET; in gmc_v11_0_set_umc_funcs()
560 adev->umc.retire_unit = UMC_V8_10_NA_COL_2BITS_POWER_OF_2_NUM; in gmc_v11_0_set_umc_funcs()
561 if (adev->umc.node_inst_num == 4) in gmc_v11_0_set_umc_funcs()
562 adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl_ext0[0][0][0]; in gmc_v11_0_set_umc_funcs()
564 adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl[0][0][0]; in gmc_v11_0_set_umc_funcs()
565 adev->umc.ras = &umc_v8_10_ras; in gmc_v11_0_set_umc_funcs()
948 if (adev->umc.funcs && adev->umc.funcs->init_registers) in gmc_v11_0_hw_init()
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H A Dumc_v8_7.c47 return adev->umc.channel_offs*ch_inst + UMC_8_INST_DIST*umc_inst; in get_umc_v8_7_reg_offset()
58 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst; in umc_v8_7_ecc_info_query_correctable_error_count()
77 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst; in umc_v8_7_ecc_info_querry_uncorrectable_error_count()
119 adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst]; in umc_v8_7_convert_error_address()
139 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst; in umc_v8_7_ecc_info_query_error_address()
H A Dumc_v8_14.h32 #define UMC_V8_14_UMC_INSTANCE_NUM(adev) ((adev)->umc.node_inst_num)
H A Dumc_v8_14.c34 return adev->umc.channel_offs * ch_inst + UMC_V8_14_INST_DIST * umc_inst; in get_umc_v8_14_reg_offset()
H A Damdgpu_discovery.c938 adev->umc.active_mask = ((1ULL << adev->umc.node_inst_num) - 1ULL) & in amdgpu_discovery_read_from_harvest_table()
1856 adev->umc.node_inst_num++; in amdgpu_discovery_reg_base_init()
H A Damdgpu.h797 struct amdgpu_umc umc; member
H A Damdgpu_psp.c2462 ras_cmd->ras_in_message.init_flags.active_umc_mask = adev->umc.active_mask; in psp_ras_initialize()
/linux/drivers/edac/
H A Damd64_edac.c1085 if (!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT)) in umc_determine_edac_cap()
1091 if (pvt->umc[i].umc_cfg & BIT(12)) in umc_determine_edac_cap()
1283 static int umc_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc, in umc_addr_mask_to_cs_size() argument
1326 addr_mask = pvt->csels[umc].csmasks[cs_mask_nr]; in umc_addr_mask_to_cs_size()
1329 addr_mask_sec = pvt->csels[umc].csmasks_sec[cs_mask_nr]; in umc_addr_mask_to_cs_size()
1357 struct amd64_umc *umc; in umc_dump_misc_regs() local
1361 umc = &pvt->umc[i]; in umc_dump_misc_regs()
1363 edac_dbg(1, "UMC%d DIMM cfg: 0x%x\n", i, umc->dimm_cfg); in umc_dump_misc_regs()
1364 edac_dbg(1, "UMC%d UMC cfg: 0x%x\n", i, umc in umc_dump_misc_regs()
1439 int umc; umc_prep_chip_selects() local
1455 int cs, umc; umc_read_base_mask() local
1555 struct amd64_umc *umc; umc_determine_memory_type() local
2920 struct amd64_umc *umc; umc_read_mc_regs() local
3089 u8 umc, cs; umc_init_csrows() local
3376 struct amd64_umc *umc; umc_ecc_enabled() local
3526 gpu_addr_mask_to_cs_size(struct amd64_pvt * pvt,u8 umc,unsigned int cs_mode,int csrow_nr) gpu_addr_mask_to_cs_size() argument
3551 struct amd64_umc *umc; gpu_dump_misc_regs() local
3584 u8 umc, cs; gpu_init_csrows() local
3627 gpu_get_umc_base(struct amd64_pvt * pvt,u8 umc,u8 channel) gpu_get_umc_base() argument
3655 struct amd64_umc *umc; gpu_read_mc_regs() local
3678 int umc, cs; gpu_read_base_mask() local
3703 int umc; gpu_prep_chip_selects() local
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/linux/drivers/ras/amd/atl/
H A DMakefile16 amd_atl-y += umc.o
/linux/drivers/scsi/
H A Dmegaraid.c3501 megacmd_t __user *umc; in mega_n_to_m() local
3521 umc = MBOX_P(uiocp); in mega_n_to_m()
3523 if (get_user(upthru, (mega_passthru __user * __user *)&umc->xferaddr)) in mega_n_to_m()
3538 umc = (megacmd_t __user *)uioc_mimd->mbox; in mega_n_to_m()
3540 if (get_user(upthru, (mega_passthru __user * __user *)&umc->xferaddr)) in mega_n_to_m()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu15/
H A Dsmu_v15_0_8_ppt.c434 if (adev->umc.active_mask) { in smu_v15_0_8_get_smu_metrics_data()
435 u64 mask = adev->umc.active_mask; in smu_v15_0_8_get_smu_metrics_data()
1708 if (adev->umc.active_mask) { in smu_v15_0_8_get_gpu_metrics()
1709 u64 mask = adev->umc.active_mask; in smu_v15_0_8_get_gpu_metrics()