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Searched refs:ufshcd_dme_set (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/ufs/host/
H A Dufs-hisi.c148 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), 0x1); in ufs_hisi_link_startup_pre_change()
150 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x156A, 0x0), 0x2); in ufs_hisi_link_startup_pre_change()
152 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8114, 0x0), 0x1); in ufs_hisi_link_startup_pre_change()
154 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8121, 0x0), 0x2D); in ufs_hisi_link_startup_pre_change()
156 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8122, 0x0), 0x1); in ufs_hisi_link_startup_pre_change()
160 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8127, 0x0), 0x98); in ufs_hisi_link_startup_pre_change()
162 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8128, 0x0), 0x1); in ufs_hisi_link_startup_pre_change()
166 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1); in ufs_hisi_link_startup_pre_change()
168 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800D, 0x4), 0x58); in ufs_hisi_link_startup_pre_change()
170 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800D, 0x5), 0x58); in ufs_hisi_link_startup_pre_change()
[all …]
H A Dufs-rockchip.c65 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(PA_LOCAL_TX_LCC_ENABLE, 0x0), 0x0); in ufs_rockchip_rk3576_phy_init()
67 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(MPHY_CFG, 0x0), MPHY_CFG_ENABLE); in ufs_rockchip_rk3576_phy_init()
70 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD, SEL_TX_LANE0 + i), 0x06); in ufs_rockchip_rk3576_phy_init()
71 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD_EN, SEL_TX_LANE0 + i), 0x02); in ufs_rockchip_rk3576_phy_init()
72 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_VALUE, SEL_TX_LANE0 + i), 0x44); in ufs_rockchip_rk3576_phy_init()
73 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE1, SEL_TX_LANE0 + i), 0xe6); in ufs_rockchip_rk3576_phy_init()
74 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE2, SEL_TX_LANE0 + i), 0x07); in ufs_rockchip_rk3576_phy_init()
75 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_TASE_VALUE, SEL_TX_LANE0 + i), 0x93); in ufs_rockchip_rk3576_phy_init()
76 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_BASE_NVALUE, SEL_TX_LANE0 + i), 0xc9); in ufs_rockchip_rk3576_phy_init()
77 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_POWER_SAVING_CTRL, SEL_TX_LANE0 + i), 0x00); in ufs_rockchip_rk3576_phy_init()
[all …]
H A Dcdns-pltfrm.c76 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), 0); in cdns_ufs_set_l4_attr()
77 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERDEVICEID), in cdns_ufs_set_l4_attr()
79 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERCPORTID), in cdns_ufs_set_l4_attr()
81 ufshcd_dme_set(hba, UIC_ARG_MIB(T_TRAFFICCLASS), in cdns_ufs_set_l4_attr()
83 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PROTOCOLID), in cdns_ufs_set_l4_attr()
85 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CPORTFLAGS), in cdns_ufs_set_l4_attr()
87 ufshcd_dme_set(hba, UIC_ARG_MIB(T_TXTOKENVALUE), in cdns_ufs_set_l4_attr()
89 ufshcd_dme_set(hba, UIC_ARG_MIB(T_RXTOKENVALUE), in cdns_ufs_set_l4_attr()
91 ufshcd_dme_set(hba, UIC_ARG_MIB(T_LOCALBUFFERSPACE), in cdns_ufs_set_l4_attr()
93 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERBUFFERSPACE), in cdns_ufs_set_l4_attr()
[all …]
H A Dufs-sprd.c280 ufshcd_dme_set(hba, UIC_ARG_MIB(CBREFCLKCTRL2), 0x90); in ufs_sprd_n6_phy_init()
281 ufshcd_dme_set(hba, UIC_ARG_MIB(CBCRCTRL), 0x01); in ufs_sprd_n6_phy_init()
282 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RXSQCONTROL, in ufs_sprd_n6_phy_init()
284 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RXSQCONTROL, in ufs_sprd_n6_phy_init()
286 ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 0x01); in ufs_sprd_n6_phy_init()
287 ufshcd_dme_set(hba, UIC_ARG_MIB(CBRATESEL), 0x01); in ufs_sprd_n6_phy_init()
295 ufshcd_dme_set(hba, UIC_ARG_MIB(CBCREGADDRLSB), 0x1c); in ufs_sprd_n6_phy_init()
296 ufshcd_dme_set(hba, UIC_ARG_MIB(CBCREGADDRMSB), offset); in ufs_sprd_n6_phy_init()
297 ufshcd_dme_set(hba, UIC_ARG_MIB(CBCREGWRLSB), 0x04); in ufs_sprd_n6_phy_init()
298 ufshcd_dme_set(hba, UIC_ARG_MIB(CBCREGWRMSB), 0x00); in ufs_sprd_n6_phy_init()
[all …]
H A Dufs-mediatek.c166 ufshcd_dme_set(hba, in ufs_mtk_cfg_unipro_cg()
172 ufshcd_dme_set(hba, in ufs_mtk_cfg_unipro_cg()
180 ufshcd_dme_set(hba, in ufs_mtk_cfg_unipro_cg()
186 ufshcd_dme_set(hba, in ufs_mtk_cfg_unipro_cg()
1366 ufshcd_dme_set(hba, UIC_ARG_MIB(att), min); in ufs_mtk_adjust_sync_length()
1399 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), true); in ufs_mtk_pre_pwr_change()
1400 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), UFS_HS_G1); in ufs_mtk_pre_pwr_change()
1402 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), true); in ufs_mtk_pre_pwr_change()
1403 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), UFS_HS_G1); in ufs_mtk_pre_pwr_change()
1405 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES), in ufs_mtk_pre_pwr_change()
[all …]
H A Dufs-exynos.h276 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OV_TM), true); in exynos_ufs_enable_ov_tm()
281 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OV_TM), false); in exynos_ufs_disable_ov_tm()
286 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), true); in exynos_ufs_enable_dbg_mode()
291 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), false); in exynos_ufs_disable_dbg_mode()
H A Dtc-dwc-g210.c267 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 0x01); in tc_dwc_g210_config_40_bit()
272 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_DEBUGOMC), 0x01); in tc_dwc_g210_config_40_bit()
297 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 0x01); in tc_dwc_g210_config_20_bit()
302 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_DEBUGOMC), 0x01); in tc_dwc_g210_config_20_bit()
H A Dufs-amd-versal2.c102 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYDISABLE), 0); in ufs_versal2_enable_phy()
106 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 1); in ufs_versal2_enable_phy()
471 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(CBRATESEL), rate); in ufs_versal2_pwr_change_notify()
475 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 1); in ufs_versal2_pwr_change_notify()
H A Dufs-qcom.c912 ret = ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HS_EQUALIZER, i), in ufs_qcom_set_tx_hs_equalizer()
1008 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), in ufs_qcom_quirk_host_pa_saveconfigtime()
1492 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), reg); in ufs_qcom_set_clk_40ns_cycles()
1557 err = ufshcd_dme_set(hba, in ufs_qcom_set_core_clk_ctrl()
1598 err = ufshcd_dme_set(hba, in ufs_qcom_clk_scale_down_pre_change()
/linux/drivers/ufs/core/
H A Dufshcd.c4096 ret = ufshcd_dme_set(hba, in ufshcd_dme_configure_adapt()
4300 return ufshcd_dme_set(hba, UIC_ARG_MIB(attr), cfg); in ufshcd_dme_rmw()
4442 ret = ufshcd_dme_set(hba, in ufshcd_uic_change_pwr_mode()
4686 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx); in ufshcd_change_power_mode()
4687 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES), in ufshcd_change_power_mode()
4691 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), true); in ufshcd_change_power_mode()
4693 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), false); in ufshcd_change_power_mode()
4695 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx); in ufshcd_change_power_mode()
4696 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES), in ufshcd_change_power_mode()
4700 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), true); in ufshcd_change_power_mode()
[all …]
/linux/include/ufs/
H A Dufshcd.h1376 static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel, in ufshcd_dme_set() function
1426 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0); in ufshcd_disable_host_tx_lcc()