xref: /linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_int.h (revision 79790b6818e96c58fe2bffee1b418c16e64e7b80)
1 // SPDX-License-Identifier: ISC
2 /*
3  * Copyright (c) 2010 Broadcom Corporation
4  */
5 
6 #ifndef _BRCM_PHY_INT_H_
7 #define _BRCM_PHY_INT_H_
8 
9 #include <types.h>
10 #include <brcmu_utils.h>
11 #include <brcmu_wifi.h>
12 
13 #define	PHY_VERSION			{ 1, 82, 8, 0 }
14 
15 #define LCNXN_BASEREV		16
16 
17 struct phy_shim_info;
18 
19 struct brcms_phy_srom_fem {
20 	/* TSSI positive slope, 1: positive, 0: negative */
21 	u8 tssipos;
22 	/* Ext PA gain-type: full-gain: 0, pa-lite: 1, no_pa: 2 */
23 	u8 extpagain;
24 	/* support 32 combinations of different Pdet dynamic ranges */
25 	u8 pdetrange;
26 	/* TR switch isolation */
27 	u8 triso;
28 	/* antswctrl lookup table configuration: 32 possible choices */
29 	u8 antswctrllut;
30 };
31 
32 #define ISNPHY(pi)	PHYTYPE_IS((pi)->pubpi.phy_type, PHY_TYPE_N)
33 #define ISLCNPHY(pi)	PHYTYPE_IS((pi)->pubpi.phy_type, PHY_TYPE_LCN)
34 
35 #define PHY_GET_RFATTN(rfgain)	((rfgain) & 0x0f)
36 #define PHY_GET_PADMIX(rfgain)	(((rfgain) & 0x10) >> 4)
37 #define PHY_GET_RFGAINID(rfattn, padmix, width)	((rfattn) + ((padmix)*(width)))
38 #define PHY_SAT(x, n)		((x) > ((1<<((n)-1))-1) ? ((1<<((n)-1))-1) : \
39 				((x) < -(1<<((n)-1)) ? -(1<<((n)-1)) : (x)))
40 #define PHY_SHIFT_ROUND(x, n)	((x) >= 0 ? ((x)+(1<<((n)-1)))>>(n) : (x)>>(n))
41 #define PHY_HW_ROUND(x, s)		((x >> s) + ((x >> (s-1)) & (s != 0)))
42 
43 #define CH_5G_GROUP	3
44 #define A_LOW_CHANS	0
45 #define A_MID_CHANS	1
46 #define A_HIGH_CHANS	2
47 #define CH_2G_GROUP	1
48 #define G_ALL_CHANS	0
49 
50 #define FIRST_REF5_CHANNUM	149
51 #define LAST_REF5_CHANNUM	165
52 #define	FIRST_5G_CHAN		14
53 #define	LAST_5G_CHAN		50
54 #define	FIRST_MID_5G_CHAN	14
55 #define	LAST_MID_5G_CHAN	35
56 #define	FIRST_HIGH_5G_CHAN	36
57 #define	LAST_HIGH_5G_CHAN	41
58 #define	FIRST_LOW_5G_CHAN	42
59 #define	LAST_LOW_5G_CHAN	50
60 
61 #define BASE_LOW_5G_CHAN	4900
62 #define BASE_MID_5G_CHAN	5100
63 #define BASE_HIGH_5G_CHAN	5500
64 
65 #define CHAN5G_FREQ(chan)  (5000 + chan*5)
66 #define CHAN2G_FREQ(chan)  (2407 + chan*5)
67 
68 #define TXP_FIRST_CCK		0
69 #define TXP_LAST_CCK		3
70 #define TXP_FIRST_OFDM		4
71 #define TXP_LAST_OFDM		11
72 #define TXP_FIRST_OFDM_20_CDD	12
73 #define TXP_LAST_OFDM_20_CDD	19
74 #define TXP_FIRST_MCS_20_SISO	20
75 #define TXP_LAST_MCS_20_SISO	27
76 #define TXP_FIRST_MCS_20_CDD	28
77 #define TXP_LAST_MCS_20_CDD	35
78 #define TXP_FIRST_MCS_20_STBC	36
79 #define TXP_LAST_MCS_20_STBC	43
80 #define TXP_FIRST_MCS_20_SDM	44
81 #define TXP_LAST_MCS_20_SDM	51
82 #define TXP_FIRST_OFDM_40_SISO	52
83 #define TXP_LAST_OFDM_40_SISO	59
84 #define TXP_FIRST_OFDM_40_CDD	60
85 #define TXP_LAST_OFDM_40_CDD	67
86 #define TXP_FIRST_MCS_40_SISO	68
87 #define TXP_LAST_MCS_40_SISO	75
88 #define TXP_FIRST_MCS_40_CDD	76
89 #define TXP_LAST_MCS_40_CDD	83
90 #define TXP_FIRST_MCS_40_STBC	84
91 #define TXP_LAST_MCS_40_STBC	91
92 #define TXP_FIRST_MCS_40_SDM	92
93 #define TXP_LAST_MCS_40_SDM	99
94 #define TXP_MCS_32	        100
95 #define TXP_NUM_RATES		101
96 #define ADJ_PWR_TBL_LEN		84
97 
98 #define TXP_FIRST_SISO_MCS_20	20
99 #define TXP_LAST_SISO_MCS_20	27
100 
101 #define PHY_CORE_NUM_1	1
102 #define PHY_CORE_NUM_2	2
103 #define PHY_CORE_NUM_3	3
104 #define PHY_CORE_NUM_4	4
105 #define PHY_CORE_MAX	PHY_CORE_NUM_4
106 #define PHY_CORE_0	0
107 #define PHY_CORE_1	1
108 #define PHY_CORE_2	2
109 #define PHY_CORE_3	3
110 
111 #define MA_WINDOW_SZ		8
112 
113 #define PHY_NOISE_SAMPLE_MON		1
114 #define PHY_NOISE_SAMPLE_EXTERNAL	2
115 #define PHY_NOISE_WINDOW_SZ	16
116 #define PHY_NOISE_GLITCH_INIT_MA 10
117 #define PHY_NOISE_GLITCH_INIT_MA_BADPlCP 10
118 #define PHY_NOISE_STATE_MON		0x1
119 #define PHY_NOISE_STATE_EXTERNAL	0x2
120 #define PHY_NOISE_SAMPLE_LOG_NUM_NPHY	10
121 #define PHY_NOISE_SAMPLE_LOG_NUM_UCODE	9
122 
123 #define PHY_NOISE_OFFSETFACT_4322  (-103)
124 #define PHY_NOISE_MA_WINDOW_SZ	2
125 
126 #define	PHY_RSSI_TABLE_SIZE	64
127 #define RSSI_ANT_MERGE_MAX	0
128 #define RSSI_ANT_MERGE_MIN	1
129 #define RSSI_ANT_MERGE_AVG	2
130 
131 #define	PHY_TSSI_TABLE_SIZE	64
132 #define	APHY_TSSI_TABLE_SIZE	256
133 #define	TX_GAIN_TABLE_LENGTH	64
134 #define	DEFAULT_11A_TXP_IDX	24
135 #define NUM_TSSI_FRAMES        4
136 #define	NULL_TSSI		0x7f
137 #define	NULL_TSSI_W		0x7f7f
138 
139 #define PHY_PAPD_EPS_TBL_SIZE_LCNPHY 64
140 
141 #define LCNPHY_PERICAL_TEMPBASED_TXPWRCTRL 9
142 
143 #define PHY_TXPWR_MIN		10
144 #define PHY_TXPWR_MIN_NPHY	8
145 #define RADIOPWR_OVERRIDE_DEF	(-1)
146 
147 #define PWRTBL_NUM_COEFF	3
148 
149 #define SPURAVOID_DISABLE	0
150 #define SPURAVOID_AUTO		1
151 #define SPURAVOID_FORCEON	2
152 #define SPURAVOID_FORCEON2	3
153 
154 #define PHY_SW_TIMER_FAST		15
155 #define PHY_SW_TIMER_SLOW		60
156 #define PHY_SW_TIMER_GLACIAL	120
157 
158 #define PHY_PERICAL_AUTO	0
159 #define PHY_PERICAL_FULL	1
160 #define PHY_PERICAL_PARTIAL	2
161 
162 #define PHY_PERICAL_NODELAY	0
163 #define PHY_PERICAL_INIT_DELAY	5
164 #define PHY_PERICAL_ASSOC_DELAY	5
165 #define PHY_PERICAL_WDOG_DELAY	5
166 
167 #define MPHASE_TXCAL_NUMCMDS	2
168 
169 #define PHY_PERICAL_MPHASE_PENDING(pi) \
170 	(pi->mphase_cal_phase_id > MPHASE_CAL_STATE_IDLE)
171 
172 enum {
173 	MPHASE_CAL_STATE_IDLE = 0,
174 	MPHASE_CAL_STATE_INIT = 1,
175 	MPHASE_CAL_STATE_TXPHASE0,
176 	MPHASE_CAL_STATE_TXPHASE1,
177 	MPHASE_CAL_STATE_TXPHASE2,
178 	MPHASE_CAL_STATE_TXPHASE3,
179 	MPHASE_CAL_STATE_TXPHASE4,
180 	MPHASE_CAL_STATE_TXPHASE5,
181 	MPHASE_CAL_STATE_PAPDCAL,
182 	MPHASE_CAL_STATE_RXCAL,
183 	MPHASE_CAL_STATE_RSSICAL,
184 	MPHASE_CAL_STATE_IDLETSSI
185 };
186 
187 enum phy_cal_mode {
188 	CAL_FULL,
189 	CAL_RECAL,
190 	CAL_CURRECAL,
191 	CAL_DIGCAL,
192 	CAL_GCTRL,
193 	CAL_SOFT,
194 	CAL_DIGLO
195 };
196 
197 #define RDR_NTIERS  1
198 #define RDR_TIER_SIZE 64
199 #define RDR_LIST_SIZE (512/3)
200 #define RDR_EPOCH_SIZE 40
201 #define RDR_NANTENNAS 2
202 #define RDR_NTIER_SIZE  RDR_LIST_SIZE
203 #define RDR_LP_BUFFER_SIZE 64
204 #define LP_LEN_HIS_SIZE 10
205 
206 #define STATIC_NUM_RF 32
207 #define STATIC_NUM_BB 9
208 
209 #define BB_MULT_MASK		0x0000ffff
210 #define BB_MULT_VALID_MASK	0x80000000
211 
212 #define PHY_CHAIN_TX_DISABLE_TEMP	115
213 #define PHY_HYSTERESIS_DELTATEMP	5
214 
215 #define SCAN_INPROG_PHY(pi) \
216 	(mboolisset(pi->measure_hold, PHY_HOLD_FOR_SCAN))
217 
218 #define PLT_INPROG_PHY(pi)      (mboolisset(pi->measure_hold, PHY_HOLD_FOR_PLT))
219 
220 #define ASSOC_INPROG_PHY(pi) \
221 	(mboolisset(pi->measure_hold, PHY_HOLD_FOR_ASSOC))
222 
223 #define SCAN_RM_IN_PROGRESS(pi) \
224 	(mboolisset(pi->measure_hold, PHY_HOLD_FOR_SCAN | PHY_HOLD_FOR_RM))
225 
226 #define PHY_MUTED(pi) \
227 	(mboolisset(pi->measure_hold, PHY_HOLD_FOR_MUTE))
228 
229 #define PUB_NOT_ASSOC(pi) \
230 	(mboolisset(pi->measure_hold, PHY_HOLD_FOR_NOT_ASSOC))
231 
232 struct phy_table_info {
233 	uint table;
234 	int q;
235 	uint max;
236 };
237 
238 struct phytbl_info {
239 	const void *tbl_ptr;
240 	u32 tbl_len;
241 	u32 tbl_id;
242 	u32 tbl_offset;
243 	u32 tbl_width;
244 };
245 
246 struct interference_info {
247 	u8 curr_home_channel;
248 	u16 crsminpwrthld_40_stored;
249 	u16 crsminpwrthld_20L_stored;
250 	u16 crsminpwrthld_20U_stored;
251 	u16 init_gain_code_core1_stored;
252 	u16 init_gain_code_core2_stored;
253 	u16 init_gain_codeb_core1_stored;
254 	u16 init_gain_codeb_core2_stored;
255 	u16 init_gain_table_stored[4];
256 
257 	u16 clip1_hi_gain_code_core1_stored;
258 	u16 clip1_hi_gain_code_core2_stored;
259 	u16 clip1_hi_gain_codeb_core1_stored;
260 	u16 clip1_hi_gain_codeb_core2_stored;
261 	u16 nb_clip_thresh_core1_stored;
262 	u16 nb_clip_thresh_core2_stored;
263 	u16 init_ofdmlna2gainchange_stored[4];
264 	u16 init_ccklna2gainchange_stored[4];
265 	u16 clip1_lo_gain_code_core1_stored;
266 	u16 clip1_lo_gain_code_core2_stored;
267 	u16 clip1_lo_gain_codeb_core1_stored;
268 	u16 clip1_lo_gain_codeb_core2_stored;
269 	u16 w1_clip_thresh_core1_stored;
270 	u16 w1_clip_thresh_core2_stored;
271 	u16 radio_2056_core1_rssi_gain_stored;
272 	u16 radio_2056_core2_rssi_gain_stored;
273 	u16 energy_drop_timeout_len_stored;
274 
275 	u16 ed_crs40_assertthld0_stored;
276 	u16 ed_crs40_assertthld1_stored;
277 	u16 ed_crs40_deassertthld0_stored;
278 	u16 ed_crs40_deassertthld1_stored;
279 	u16 ed_crs20L_assertthld0_stored;
280 	u16 ed_crs20L_assertthld1_stored;
281 	u16 ed_crs20L_deassertthld0_stored;
282 	u16 ed_crs20L_deassertthld1_stored;
283 	u16 ed_crs20U_assertthld0_stored;
284 	u16 ed_crs20U_assertthld1_stored;
285 	u16 ed_crs20U_deassertthld0_stored;
286 	u16 ed_crs20U_deassertthld1_stored;
287 
288 	u16 badplcp_ma;
289 	u16 badplcp_ma_previous;
290 	u16 badplcp_ma_total;
291 	u16 badplcp_ma_list[MA_WINDOW_SZ];
292 	int badplcp_ma_index;
293 	s16 pre_badplcp_cnt;
294 	s16 bphy_pre_badplcp_cnt;
295 
296 	u16 init_gain_core1;
297 	u16 init_gain_core2;
298 	u16 init_gainb_core1;
299 	u16 init_gainb_core2;
300 	u16 init_gain_rfseq[4];
301 
302 	u16 crsminpwr0;
303 	u16 crsminpwrl0;
304 	u16 crsminpwru0;
305 
306 	s16 crsminpwr_index;
307 
308 	u16 radio_2057_core1_rssi_wb1a_gc_stored;
309 	u16 radio_2057_core2_rssi_wb1a_gc_stored;
310 	u16 radio_2057_core1_rssi_wb1g_gc_stored;
311 	u16 radio_2057_core2_rssi_wb1g_gc_stored;
312 	u16 radio_2057_core1_rssi_wb2_gc_stored;
313 	u16 radio_2057_core2_rssi_wb2_gc_stored;
314 	u16 radio_2057_core1_rssi_nb_gc_stored;
315 	u16 radio_2057_core2_rssi_nb_gc_stored;
316 };
317 
318 struct aci_save_gphy {
319 	u16 rc_cal_ovr;
320 	u16 phycrsth1;
321 	u16 phycrsth2;
322 	u16 init_n1p1_gain;
323 	u16 p1_p2_gain;
324 	u16 n1_n2_gain;
325 	u16 n1_p1_gain;
326 	u16 div_search_gain;
327 	u16 div_p1_p2_gain;
328 	u16 div_search_gn_change;
329 	u16 table_7_2;
330 	u16 table_7_3;
331 	u16 cckshbits_gnref;
332 	u16 clip_thresh;
333 	u16 clip2_thresh;
334 	u16 clip3_thresh;
335 	u16 clip_p2_thresh;
336 	u16 clip_pwdn_thresh;
337 	u16 clip_n1p1_thresh;
338 	u16 clip_n1_pwdn_thresh;
339 	u16 bbconfig;
340 	u16 cthr_sthr_shdin;
341 	u16 energy;
342 	u16 clip_p1_p2_thresh;
343 	u16 threshold;
344 	u16 reg15;
345 	u16 reg16;
346 	u16 reg17;
347 	u16 div_srch_idx;
348 	u16 div_srch_p1_p2;
349 	u16 div_srch_gn_back;
350 	u16 ant_dwell;
351 	u16 ant_wr_settle;
352 };
353 
354 struct lo_complex_abgphy_info {
355 	s8 i;
356 	s8 q;
357 };
358 
359 struct nphy_iq_comp {
360 	s16 a0;
361 	s16 b0;
362 	s16 a1;
363 	s16 b1;
364 };
365 
366 struct nphy_txpwrindex {
367 	s8 index;
368 	s8 index_internal;
369 	s8 index_internal_save;
370 	u16 AfectrlOverride;
371 	u16 AfeCtrlDacGain;
372 	u16 rad_gain;
373 	u8 bbmult;
374 	u16 iqcomp_a;
375 	u16 iqcomp_b;
376 	u16 locomp;
377 };
378 
379 struct txiqcal_cache {
380 
381 	u16 txcal_coeffs_2G[8];
382 	u16 txcal_radio_regs_2G[8];
383 	struct nphy_iq_comp rxcal_coeffs_2G;
384 
385 	u16 txcal_coeffs_5G[8];
386 	u16 txcal_radio_regs_5G[8];
387 	struct nphy_iq_comp rxcal_coeffs_5G;
388 };
389 
390 struct nphy_pwrctrl {
391 	s8 max_pwr_2g;
392 	s8 idle_targ_2g;
393 	s16 pwrdet_2g_a1;
394 	s16 pwrdet_2g_b0;
395 	s16 pwrdet_2g_b1;
396 	s8 max_pwr_5gm;
397 	s8 idle_targ_5gm;
398 	s8 max_pwr_5gh;
399 	s8 max_pwr_5gl;
400 	s16 pwrdet_5gm_a1;
401 	s16 pwrdet_5gm_b0;
402 	s16 pwrdet_5gm_b1;
403 	s16 pwrdet_5gl_a1;
404 	s16 pwrdet_5gl_b0;
405 	s16 pwrdet_5gl_b1;
406 	s16 pwrdet_5gh_a1;
407 	s16 pwrdet_5gh_b0;
408 	s16 pwrdet_5gh_b1;
409 	s8 idle_targ_5gl;
410 	s8 idle_targ_5gh;
411 	s8 idle_tssi_2g;
412 	s8 idle_tssi_5g;
413 	s8 idle_tssi;
414 	s16 a1;
415 	s16 b0;
416 	s16 b1;
417 };
418 
419 struct nphy_txgains {
420 	u16 txlpf[2];
421 	u16 txgm[2];
422 	u16 pga[2];
423 	u16 pad[2];
424 	u16 ipa[2];
425 };
426 
427 #define PHY_NOISEVAR_BUFSIZE 10
428 
429 struct nphy_noisevar_buf {
430 	int bufcount;
431 	int tone_id[PHY_NOISEVAR_BUFSIZE];
432 	u32 noise_vars[PHY_NOISEVAR_BUFSIZE];
433 	u32 min_noise_vars[PHY_NOISEVAR_BUFSIZE];
434 };
435 
436 struct rssical_cache {
437 	u16 rssical_radio_regs_2G[2];
438 	u16 rssical_phyregs_2G[12];
439 
440 	u16 rssical_radio_regs_5G[2];
441 	u16 rssical_phyregs_5G[12];
442 };
443 
444 struct lcnphy_cal_results {
445 
446 	u16 txiqlocal_a;
447 	u16 txiqlocal_b;
448 	u16 txiqlocal_didq;
449 	u8 txiqlocal_ei0;
450 	u8 txiqlocal_eq0;
451 	u8 txiqlocal_fi0;
452 	u8 txiqlocal_fq0;
453 
454 	u16 txiqlocal_bestcoeffs[11];
455 	u16 txiqlocal_bestcoeffs_valid;
456 
457 	u32 papd_eps_tbl[PHY_PAPD_EPS_TBL_SIZE_LCNPHY];
458 	u16 analog_gain_ref;
459 	u16 lut_begin;
460 	u16 lut_end;
461 	u16 lut_step;
462 	u16 rxcompdbm;
463 	u16 papdctrl;
464 	u16 sslpnCalibClkEnCtrl;
465 
466 	u16 rxiqcal_coeff_a0;
467 	u16 rxiqcal_coeff_b0;
468 };
469 
470 struct shared_phy {
471 	struct brcms_phy *phy_head;
472 	uint unit;
473 	struct phy_shim_info *physhim;
474 	uint corerev;
475 	u32 machwcap;
476 	bool up;
477 	bool clk;
478 	uint now;
479 	u16 vid;
480 	u16 did;
481 	uint chip;
482 	uint chiprev;
483 	uint chippkg;
484 	uint sromrev;
485 	uint boardtype;
486 	uint boardrev;
487 	u32 boardflags;
488 	u32 boardflags2;
489 	uint fast_timer;
490 	uint slow_timer;
491 	uint glacial_timer;
492 	u8 rx_antdiv;
493 	s8 phy_noise_window[MA_WINDOW_SZ];
494 	uint phy_noise_index;
495 	u8 hw_phytxchain;
496 	u8 hw_phyrxchain;
497 	u8 phytxchain;
498 	u8 phyrxchain;
499 	u8 rssi_mode;
500 	bool _rifs_phy;
501 };
502 
503 struct brcms_phy_pub {
504 	uint phy_type;
505 	uint phy_rev;
506 	u8 phy_corenum;
507 	u16 radioid;
508 	u8 radiorev;
509 	u8 radiover;
510 
511 	uint coreflags;
512 	uint ana_rev;
513 	bool abgphy_encore;
514 };
515 
516 struct phy_func_ptr {
517 	void (*init)(struct brcms_phy *);
518 	void (*calinit)(struct brcms_phy *);
519 	void (*chanset)(struct brcms_phy *, u16 chanspec);
520 	void (*txpwrrecalc)(struct brcms_phy *);
521 	int (*longtrn)(struct brcms_phy *, int);
522 	void (*txiqccget)(struct brcms_phy *, u16 *, u16 *);
523 	void (*txiqccset)(struct brcms_phy *, u16, u16);
524 	u16 (*txloccget)(struct brcms_phy *);
525 	void (*radioloftget)(struct brcms_phy *, u8 *, u8 *, u8 *, u8 *);
526 	void (*carrsuppr)(struct brcms_phy *);
527 	s32 (*rxsigpwr)(struct brcms_phy *, s32);
528 	void (*detach)(struct brcms_phy *);
529 };
530 
531 struct brcms_phy {
532 	struct brcms_phy_pub pubpi_ro;
533 	struct shared_phy *sh;
534 	struct phy_func_ptr pi_fptr;
535 
536 	union {
537 		struct brcms_phy_lcnphy *pi_lcnphy;
538 	} u;
539 	bool user_txpwr_at_rfport;
540 
541 	struct bcma_device *d11core;
542 	struct brcms_phy *next;
543 	struct brcms_phy_pub pubpi;
544 
545 	bool do_initcal;
546 	bool phytest_on;
547 	bool ofdm_rateset_war;
548 	bool bf_preempt_4306;
549 	u16 radio_chanspec;
550 	u8 antsel_type;
551 	u16 bw;
552 	u8 txpwr_percent;
553 	bool phy_init_por;
554 
555 	bool init_in_progress;
556 	bool initialized;
557 	bool sbtml_gm;
558 	uint refcnt;
559 	bool watchdog_override;
560 	u8 phynoise_state;
561 	uint phynoise_now;
562 	int phynoise_chan_watchdog;
563 	bool phynoise_polling;
564 	bool disable_percal;
565 	u32 measure_hold;
566 
567 	s16 txpa_2g[PWRTBL_NUM_COEFF];
568 	s16 txpa_2g_low_temp[PWRTBL_NUM_COEFF];
569 	s16 txpa_2g_high_temp[PWRTBL_NUM_COEFF];
570 	s16 txpa_5g_low[PWRTBL_NUM_COEFF];
571 	s16 txpa_5g_mid[PWRTBL_NUM_COEFF];
572 	s16 txpa_5g_hi[PWRTBL_NUM_COEFF];
573 
574 	u8 tx_srom_max_2g;
575 	u8 tx_srom_max_5g_low;
576 	u8 tx_srom_max_5g_mid;
577 	u8 tx_srom_max_5g_hi;
578 	u8 tx_srom_max_rate_2g[TXP_NUM_RATES];
579 	u8 tx_srom_max_rate_5g_low[TXP_NUM_RATES];
580 	u8 tx_srom_max_rate_5g_mid[TXP_NUM_RATES];
581 	u8 tx_srom_max_rate_5g_hi[TXP_NUM_RATES];
582 	u8 tx_user_target[TXP_NUM_RATES];
583 	s8 tx_power_offset[TXP_NUM_RATES];
584 	u8 tx_power_target[TXP_NUM_RATES];
585 
586 	struct brcms_phy_srom_fem srom_fem2g;
587 	struct brcms_phy_srom_fem srom_fem5g;
588 
589 	u8 tx_power_max;
590 	u8 tx_power_max_rate_ind;
591 	bool hwpwrctrl;
592 	u8 nphy_txpwrctrl;
593 	s8 nphy_txrx_chain;
594 	bool phy_5g_pwrgain;
595 
596 	u16 phy_wreg;
597 	u16 phy_wreg_limit;
598 
599 	s8 n_preamble_override;
600 	u8 antswitch;
601 	u8 aa2g, aa5g;
602 
603 	s8 idle_tssi[CH_5G_GROUP];
604 	s8 target_idle_tssi;
605 	s8 txpwr_est_Pout;
606 	u8 tx_power_min;
607 	u8 txpwr_limit[TXP_NUM_RATES];
608 	u8 txpwr_env_limit[TXP_NUM_RATES];
609 	u8 adj_pwr_tbl_nphy[ADJ_PWR_TBL_LEN];
610 
611 	bool channel_14_wide_filter;
612 
613 	bool txpwroverride;
614 	bool txpwridx_override_aphy;
615 	s16 radiopwr_override;
616 	u16 hwpwr_txcur;
617 	u8 saved_txpwr_idx;
618 
619 	bool edcrs_threshold_lock;
620 
621 	u32 tr_R_gain_val;
622 	u32 tr_T_gain_val;
623 
624 	s16 ofdm_analog_filt_bw_override;
625 	s16 cck_analog_filt_bw_override;
626 	s16 ofdm_rccal_override;
627 	s16 cck_rccal_override;
628 	u16 extlna_type;
629 
630 	uint interference_mode_crs_time;
631 	u16 crsglitch_prev;
632 	bool interference_mode_crs;
633 
634 	u32 phy_tx_tone_freq;
635 	uint phy_lastcal;
636 	bool phy_forcecal;
637 	bool phy_fixed_noise;
638 	u32 xtalfreq;
639 	u8 pdiv;
640 	s8 carrier_suppr_disable;
641 
642 	bool phy_bphy_evm;
643 	bool phy_bphy_rfcs;
644 	s8 phy_scraminit;
645 	u8 phy_gpiosel;
646 
647 	s16 phy_txcore_disable_temp;
648 	s16 phy_txcore_enable_temp;
649 	s8 phy_tempsense_offset;
650 	bool phy_txcore_heatedup;
651 
652 	u16 radiopwr;
653 	u16 bb_atten;
654 	u16 txctl1;
655 
656 	u16 mintxbias;
657 	u16 mintxmag;
658 	struct lo_complex_abgphy_info gphy_locomp_iq
659 			[STATIC_NUM_RF][STATIC_NUM_BB];
660 	s8 stats_11b_txpower[STATIC_NUM_RF][STATIC_NUM_BB];
661 	u16 gain_table[TX_GAIN_TABLE_LENGTH];
662 	bool loopback_gain;
663 	s16 max_lpback_gain_hdB;
664 	s16 trsw_rx_gain_hdB;
665 	u8 power_vec[8];
666 
667 	u16 rc_cal;
668 	int nrssi_table_delta;
669 	int nrssi_slope_scale;
670 	int nrssi_slope_offset;
671 	int min_rssi;
672 	int max_rssi;
673 
674 	s8 txpwridx;
675 	u8 min_txpower;
676 
677 	u8 a_band_high_disable;
678 
679 	u16 tx_vos;
680 	u16 global_tx_bb_dc_bias_loft;
681 
682 	int rf_max;
683 	int bb_max;
684 	int rf_list_size;
685 	int bb_list_size;
686 	u16 *rf_attn_list;
687 	u16 *bb_attn_list;
688 	u16 padmix_mask;
689 	u16 padmix_reg;
690 	u16 *txmag_list;
691 	uint txmag_len;
692 	bool txmag_enable;
693 
694 	s8 *a_tssi_to_dbm;
695 	s8 *m_tssi_to_dbm;
696 	s8 *l_tssi_to_dbm;
697 	s8 *h_tssi_to_dbm;
698 	u8 *hwtxpwr;
699 
700 	u16 freqtrack_saved_regs[2];
701 	int cur_interference_mode;
702 	bool hwpwrctrl_capable;
703 	bool temppwrctrl_capable;
704 
705 	uint phycal_nslope;
706 	uint phycal_noffset;
707 	uint phycal_mlo;
708 	uint phycal_txpower;
709 
710 	u8 phy_aa2g;
711 
712 	bool nphy_tableloaded;
713 	s8 nphy_rssisel;
714 	u32 nphy_bb_mult_save;
715 	u16 nphy_txiqlocal_bestc[11];
716 	bool nphy_txiqlocal_coeffsvalid;
717 	struct nphy_txpwrindex nphy_txpwrindex[PHY_CORE_NUM_2];
718 	struct nphy_pwrctrl nphy_pwrctrl_info[PHY_CORE_NUM_2];
719 	u16 cck2gpo;
720 	u32 ofdm2gpo;
721 	u32 ofdm5gpo;
722 	u32 ofdm5glpo;
723 	u32 ofdm5ghpo;
724 	u8 bw402gpo;
725 	u8 bw405gpo;
726 	u8 bw405glpo;
727 	u8 bw405ghpo;
728 	u8 cdd2gpo;
729 	u8 cdd5gpo;
730 	u8 cdd5glpo;
731 	u8 cdd5ghpo;
732 	u8 stbc2gpo;
733 	u8 stbc5gpo;
734 	u8 stbc5glpo;
735 	u8 stbc5ghpo;
736 	u8 bwdup2gpo;
737 	u8 bwdup5gpo;
738 	u8 bwdup5glpo;
739 	u8 bwdup5ghpo;
740 	u16 mcs2gpo[8];
741 	u16 mcs5gpo[8];
742 	u16 mcs5glpo[8];
743 	u16 mcs5ghpo[8];
744 	u32 nphy_rxcalparams;
745 
746 	u8 phy_spuravoid;
747 	bool phy_isspuravoid;
748 
749 	u8 phy_pabias;
750 	u8 nphy_papd_skip;
751 	u8 nphy_tssi_slope;
752 
753 	s16 nphy_noise_win[PHY_CORE_MAX][PHY_NOISE_WINDOW_SZ];
754 	u8 nphy_noise_index;
755 
756 	bool nphy_gain_boost;
757 	bool nphy_elna_gain_config;
758 	u16 old_bphy_test;
759 	u16 old_bphy_testcontrol;
760 
761 	bool phyhang_avoid;
762 
763 	bool rssical_nphy;
764 	u8 nphy_perical;
765 	uint nphy_perical_last;
766 	u8 cal_type_override;
767 	u8 mphase_cal_phase_id;
768 	u8 mphase_txcal_cmdidx;
769 	u8 mphase_txcal_numcmds;
770 	u16 mphase_txcal_bestcoeffs[11];
771 	u16 nphy_txiqlocal_chanspec;
772 	u16 nphy_iqcal_chanspec_2G;
773 	u16 nphy_iqcal_chanspec_5G;
774 	u16 nphy_rssical_chanspec_2G;
775 	u16 nphy_rssical_chanspec_5G;
776 	struct wlapi_timer *phycal_timer;
777 	bool use_int_tx_iqlo_cal_nphy;
778 	bool internal_tx_iqlo_cal_tapoff_intpa_nphy;
779 	s16 nphy_lastcal_temp;
780 
781 	struct txiqcal_cache calibration_cache;
782 	struct rssical_cache rssical_cache;
783 
784 	u8 nphy_txpwr_idx[2];
785 	u8 nphy_papd_cal_type;
786 	uint nphy_papd_last_cal;
787 	u16 nphy_papd_tx_gain_at_last_cal[2];
788 	u8 nphy_papd_cal_gain_index[2];
789 	s16 nphy_papd_epsilon_offset[2];
790 	bool nphy_papd_recal_enable;
791 	u32 nphy_papd_recal_counter;
792 	bool nphy_force_papd_cal;
793 	bool nphy_papdcomp;
794 	bool ipa2g_on;
795 	bool ipa5g_on;
796 
797 	u16 classifier_state;
798 	u16 clip_state[2];
799 	uint nphy_deaf_count;
800 	u8 rxiq_samps;
801 	u8 rxiq_antsel;
802 
803 	u16 rfctrlIntc1_save;
804 	u16 rfctrlIntc2_save;
805 	bool first_cal_after_assoc;
806 	u16 tx_rx_cal_radio_saveregs[22];
807 	u16 tx_rx_cal_phy_saveregs[15];
808 
809 	u8 nphy_cal_orig_pwr_idx[2];
810 	u8 nphy_txcal_pwr_idx[2];
811 	u8 nphy_rxcal_pwr_idx[2];
812 	u16 nphy_cal_orig_tx_gain[2];
813 	struct nphy_txgains nphy_cal_target_gain;
814 	u16 nphy_txcal_bbmult;
815 	u16 nphy_gmval;
816 
817 	u16 nphy_saved_bbconf;
818 
819 	bool nphy_gband_spurwar_en;
820 	bool nphy_gband_spurwar2_en;
821 	bool nphy_aband_spurwar_en;
822 	u16 nphy_rccal_value;
823 	u16 nphy_crsminpwr[3];
824 	struct nphy_noisevar_buf nphy_saved_noisevars;
825 	bool nphy_anarxlpf_adjusted;
826 	bool nphy_crsminpwr_adjusted;
827 	bool nphy_noisevars_adjusted;
828 
829 	bool nphy_rxcal_active;
830 	u16 radar_percal_mask;
831 	bool dfs_lp_buffer_nphy;
832 
833 	u16 nphy_fineclockgatecontrol;
834 
835 	s8 rx2tx_biasentry;
836 
837 	u16 crsminpwr0;
838 	u16 crsminpwrl0;
839 	u16 crsminpwru0;
840 	s16 noise_crsminpwr_index;
841 	u16 init_gain_core1;
842 	u16 init_gain_core2;
843 	u16 init_gainb_core1;
844 	u16 init_gainb_core2;
845 	u8 aci_noise_curr_channel;
846 	u16 init_gain_rfseq[4];
847 
848 	bool radio_is_on;
849 
850 	bool nphy_sample_play_lpf_bw_ctl_ovr;
851 
852 	u16 tbl_data_hi;
853 	u16 tbl_data_lo;
854 	u16 tbl_addr;
855 
856 	uint tbl_save_id;
857 	uint tbl_save_offset;
858 
859 	u8 txpwrctrl;
860 	s8 txpwrindex[PHY_CORE_MAX];
861 
862 	u8 phycal_tempdelta;
863 	u32 mcs20_po;
864 	u32 mcs40_po;
865 	struct wiphy *wiphy;
866 };
867 
868 struct cs32 {
869 	s32 q;
870 	s32 i;
871 };
872 
873 struct radio_regs {
874 	u16 address;
875 	u32 init_a;
876 	u32 init_g;
877 	u8 do_init_a;
878 	u8 do_init_g;
879 };
880 
881 struct radio_20xx_regs {
882 	u16 address;
883 	u8 init;
884 	u8 do_init;
885 };
886 
887 struct lcnphy_radio_regs {
888 	u16 address;
889 	u8 init_a;
890 	u8 init_g;
891 	u8 do_init_a;
892 	u8 do_init_g;
893 };
894 
895 u16 read_phy_reg(struct brcms_phy *pi, u16 addr);
896 void write_phy_reg(struct brcms_phy *pi, u16 addr, u16 val);
897 void and_phy_reg(struct brcms_phy *pi, u16 addr, u16 val);
898 void or_phy_reg(struct brcms_phy *pi, u16 addr, u16 val);
899 void mod_phy_reg(struct brcms_phy *pi, u16 addr, u16 mask, u16 val);
900 
901 u16 read_radio_reg(struct brcms_phy *pi, u16 addr);
902 void or_radio_reg(struct brcms_phy *pi, u16 addr, u16 val);
903 void and_radio_reg(struct brcms_phy *pi, u16 addr, u16 val);
904 void mod_radio_reg(struct brcms_phy *pi, u16 addr, u16 mask, u16 val);
905 void xor_radio_reg(struct brcms_phy *pi, u16 addr, u16 mask);
906 
907 void write_radio_reg(struct brcms_phy *pi, u16 addr, u16 val);
908 
909 void wlc_phyreg_enter(struct brcms_phy_pub *pih);
910 void wlc_phyreg_exit(struct brcms_phy_pub *pih);
911 void wlc_radioreg_enter(struct brcms_phy_pub *pih);
912 void wlc_radioreg_exit(struct brcms_phy_pub *pih);
913 
914 void wlc_phy_read_table(struct brcms_phy *pi,
915 			const struct phytbl_info *ptbl_info,
916 			u16 tblAddr, u16 tblDataHi, u16 tblDatalo);
917 void wlc_phy_write_table(struct brcms_phy *pi,
918 			 const struct phytbl_info *ptbl_info,
919 			 u16 tblAddr, u16 tblDataHi, u16 tblDatalo);
920 void wlc_phy_table_addr(struct brcms_phy *pi, uint tbl_id, uint tbl_offset,
921 			u16 tblAddr, u16 tblDataHi, u16 tblDataLo);
922 void wlc_phy_table_data_write(struct brcms_phy *pi, uint width, u32 val);
923 
924 void write_phy_channel_reg(struct brcms_phy *pi, uint val);
925 void wlc_phy_txpower_update_shm(struct brcms_phy *pi);
926 
927 u8 wlc_phy_nbits(s32 value);
928 void wlc_phy_compute_dB(u32 *cmplx_pwr, s8 *p_dB, u8 core);
929 
930 uint wlc_phy_init_radio_regs_allbands(struct brcms_phy *pi,
931 				      struct radio_20xx_regs *radioregs);
932 uint wlc_phy_init_radio_regs(struct brcms_phy *pi,
933 			     const struct radio_regs *radioregs,
934 			     u16 core_offset);
935 
936 void wlc_phy_txpower_ipa_upd(struct brcms_phy *pi);
937 
938 void wlc_phy_do_dummy_tx(struct brcms_phy *pi, bool ofdm, bool pa_on);
939 void wlc_phy_papd_decode_epsilon(u32 epsilon, s32 *eps_real, s32 *eps_imag);
940 
941 void wlc_phy_cal_perical_mphase_reset(struct brcms_phy *pi);
942 void wlc_phy_cal_perical_mphase_restart(struct brcms_phy *pi);
943 
944 void wlc_phy_attach_nphy(struct brcms_phy *pi);
945 bool wlc_phy_attach_lcnphy(struct brcms_phy *pi);
946 
947 void wlc_phy_detach_lcnphy(struct brcms_phy *pi);
948 
949 void wlc_phy_init_nphy(struct brcms_phy *pi);
950 void wlc_phy_init_lcnphy(struct brcms_phy *pi);
951 
952 void wlc_phy_cal_init_nphy(struct brcms_phy *pi);
953 void wlc_phy_cal_init_lcnphy(struct brcms_phy *pi);
954 
955 void wlc_phy_chanspec_set_nphy(struct brcms_phy *pi, u16 chanspec);
956 void wlc_phy_chanspec_set_lcnphy(struct brcms_phy *pi, u16 chanspec);
957 void wlc_phy_chanspec_set_fixup_lcnphy(struct brcms_phy *pi, u16 chanspec);
958 int wlc_phy_channel2freq(uint channel);
959 int wlc_phy_chanspec_freq2bandrange_lpssn(uint);
960 int wlc_phy_chanspec_bandrange_get(struct brcms_phy *, u16 chanspec);
961 
962 void wlc_lcnphy_set_tx_pwr_ctrl(struct brcms_phy *pi, u16 mode);
963 s8 wlc_lcnphy_get_current_tx_pwr_idx(struct brcms_phy *pi);
964 
965 void wlc_phy_txpower_recalc_target_nphy(struct brcms_phy *pi);
966 void wlc_lcnphy_txpower_recalc_target(struct brcms_phy *pi);
967 void wlc_phy_txpower_recalc_target_lcnphy(struct brcms_phy *pi);
968 
969 void wlc_lcnphy_set_tx_pwr_by_index(struct brcms_phy *pi, int index);
970 void wlc_lcnphy_tx_pu(struct brcms_phy *pi, bool bEnable);
971 void wlc_lcnphy_stop_tx_tone(struct brcms_phy *pi);
972 void wlc_lcnphy_start_tx_tone(struct brcms_phy *pi, s32 f_kHz, u16 max_val,
973 			      bool iqcalmode);
974 
975 void wlc_phy_txpower_sromlimit_get_nphy(struct brcms_phy *pi, uint chan,
976 					u8 *max_pwr, u8 rate_id);
977 void wlc_phy_ofdm_to_mcs_powers_nphy(u8 *power, u8 rate_mcs_start,
978 				     u8 rate_mcs_end, u8 rate_ofdm_start);
979 void wlc_phy_mcs_to_ofdm_powers_nphy(u8 *power, u8 rate_ofdm_start,
980 				     u8 rate_ofdm_end, u8 rate_mcs_start);
981 
982 u16 wlc_lcnphy_tempsense(struct brcms_phy *pi, bool mode);
983 s16 wlc_lcnphy_tempsense_new(struct brcms_phy *pi, bool mode);
984 s8 wlc_lcnphy_tempsense_degree(struct brcms_phy *pi, bool mode);
985 s8 wlc_lcnphy_vbatsense(struct brcms_phy *pi, bool mode);
986 void wlc_phy_carrier_suppress_lcnphy(struct brcms_phy *pi);
987 void wlc_lcnphy_crsuprs(struct brcms_phy *pi, int channel);
988 void wlc_lcnphy_epa_switch(struct brcms_phy *pi, bool mode);
989 void wlc_2064_vco_cal(struct brcms_phy *pi);
990 
991 void wlc_phy_txpower_recalc_target(struct brcms_phy *pi);
992 
993 #define LCNPHY_TBL_ID_PAPDCOMPDELTATBL	0x18
994 #define LCNPHY_TX_POWER_TABLE_SIZE	128
995 #define LCNPHY_MAX_TX_POWER_INDEX	(LCNPHY_TX_POWER_TABLE_SIZE - 1)
996 #define LCNPHY_TBL_ID_TXPWRCTL	0x07
997 #define LCNPHY_TX_PWR_CTRL_OFF	0
998 #define LCNPHY_TX_PWR_CTRL_SW		(0x1 << 15)
999 #define LCNPHY_TX_PWR_CTRL_HW         ((0x1 << 15) | \
1000 					(0x1 << 14) | \
1001 					(0x1 << 13))
1002 
1003 #define LCNPHY_TX_PWR_CTRL_TEMPBASED	0xE001
1004 
1005 void wlc_lcnphy_write_table(struct brcms_phy *pi,
1006 			    const struct phytbl_info *pti);
1007 void wlc_lcnphy_read_table(struct brcms_phy *pi, struct phytbl_info *pti);
1008 void wlc_lcnphy_set_tx_iqcc(struct brcms_phy *pi, u16 a, u16 b);
1009 void wlc_lcnphy_set_tx_locc(struct brcms_phy *pi, u16 didq);
1010 void wlc_lcnphy_get_tx_iqcc(struct brcms_phy *pi, u16 *a, u16 *b);
1011 u16 wlc_lcnphy_get_tx_locc(struct brcms_phy *pi);
1012 void wlc_lcnphy_get_radio_loft(struct brcms_phy *pi, u8 *ei0, u8 *eq0, u8 *fi0,
1013 			       u8 *fq0);
1014 void wlc_lcnphy_calib_modes(struct brcms_phy *pi, uint mode);
1015 void wlc_lcnphy_deaf_mode(struct brcms_phy *pi, bool mode);
1016 bool wlc_phy_tpc_isenabled_lcnphy(struct brcms_phy *pi);
1017 void wlc_lcnphy_tx_pwr_update_npt(struct brcms_phy *pi);
1018 s32 wlc_lcnphy_tssi2dbm(s32 tssi, s32 a1, s32 b0, s32 b1);
1019 void wlc_lcnphy_get_tssi(struct brcms_phy *pi, s8 *ofdm_pwr, s8 *cck_pwr);
1020 void wlc_lcnphy_tx_power_adjustment(struct brcms_phy_pub *ppi);
1021 
1022 s32 wlc_lcnphy_rx_signal_power(struct brcms_phy *pi, s32 gain_index);
1023 
1024 #define NPHY_MAX_HPVGA1_INDEX		10
1025 #define NPHY_DEF_HPVGA1_INDEXLIMIT	7
1026 
1027 struct phy_iq_est {
1028 	s32 iq_prod;
1029 	u32 i_pwr;
1030 	u32 q_pwr;
1031 };
1032 
1033 void wlc_phy_stay_in_carriersearch_nphy(struct brcms_phy *pi, bool enable);
1034 void wlc_nphy_deaf_mode(struct brcms_phy *pi, bool mode);
1035 
1036 #define wlc_phy_write_table_nphy(pi, pti) \
1037 	wlc_phy_write_table(pi, pti, 0x72, 0x74, 0x73)
1038 
1039 #define wlc_phy_read_table_nphy(pi, pti) \
1040 	wlc_phy_read_table(pi, pti, 0x72, 0x74, 0x73)
1041 
1042 #define wlc_nphy_table_addr(pi, id, off) \
1043 	wlc_phy_table_addr((pi), (id), (off), 0x72, 0x74, 0x73)
1044 
1045 #define wlc_nphy_table_data_write(pi, w, v) \
1046 	wlc_phy_table_data_write((pi), (w), (v))
1047 
1048 void wlc_phy_table_read_nphy(struct brcms_phy *pi, u32, u32 l, u32 o, u32 w,
1049 			     void *d);
1050 void wlc_phy_table_write_nphy(struct brcms_phy *pi, u32, u32, u32, u32,
1051 			      const void *);
1052 
1053 #define	PHY_IPA(pi) \
1054 	((pi->ipa2g_on && CHSPEC_IS2G(pi->radio_chanspec)) || \
1055 	 (pi->ipa5g_on && CHSPEC_IS5G(pi->radio_chanspec)))
1056 
1057 #define BRCMS_PHY_WAR_PR51571(pi) \
1058 	if (NREV_LT((pi)->pubpi.phy_rev, 3)) \
1059 		(void)bcma_read32(pi->d11core, D11REGOFFS(maccontrol))
1060 
1061 void wlc_phy_cal_perical_nphy_run(struct brcms_phy *pi, u8 caltype);
1062 void wlc_phy_aci_reset_nphy(struct brcms_phy *pi);
1063 void wlc_phy_pa_override_nphy(struct brcms_phy *pi, bool en);
1064 
1065 u8 wlc_phy_get_chan_freq_range_nphy(struct brcms_phy *pi, uint chan);
1066 void wlc_phy_switch_radio_nphy(struct brcms_phy *pi, bool on);
1067 
1068 void wlc_phy_stf_chain_upd_nphy(struct brcms_phy *pi);
1069 
1070 void wlc_phy_force_rfseq_nphy(struct brcms_phy *pi, u8 cmd);
1071 s16 wlc_phy_tempsense_nphy(struct brcms_phy *pi);
1072 
1073 u16 wlc_phy_classifier_nphy(struct brcms_phy *pi, u16 mask, u16 val);
1074 
1075 void wlc_phy_rx_iq_est_nphy(struct brcms_phy *pi, struct phy_iq_est *est,
1076 			    u16 num_samps, u8 wait_time, u8 wait_for_crs);
1077 
1078 void wlc_phy_rx_iq_coeffs_nphy(struct brcms_phy *pi, u8 write,
1079 			       struct nphy_iq_comp *comp);
1080 void wlc_phy_aci_and_noise_reduction_nphy(struct brcms_phy *pi);
1081 
1082 void wlc_phy_rxcore_setstate_nphy(struct brcms_phy_pub *pih, u8 rxcore_bitmask);
1083 u8 wlc_phy_rxcore_getstate_nphy(struct brcms_phy_pub *pih);
1084 
1085 void wlc_phy_txpwrctrl_enable_nphy(struct brcms_phy *pi, u8 ctrl_type);
1086 void wlc_phy_txpwr_fixpower_nphy(struct brcms_phy *pi);
1087 void wlc_phy_txpwr_apply_nphy(struct brcms_phy *pi);
1088 void wlc_phy_txpwr_papd_cal_nphy(struct brcms_phy *pi);
1089 u16 wlc_phy_txpwr_idx_get_nphy(struct brcms_phy *pi);
1090 
1091 struct nphy_txgains wlc_phy_get_tx_gain_nphy(struct brcms_phy *pi);
1092 int wlc_phy_cal_txiqlo_nphy(struct brcms_phy *pi,
1093 			    struct nphy_txgains target_gain, bool full, bool m);
1094 int wlc_phy_cal_rxiq_nphy(struct brcms_phy *pi, struct nphy_txgains target_gain,
1095 			  u8 type, bool d);
1096 void wlc_phy_txpwr_index_nphy(struct brcms_phy *pi, u8 core_mask,
1097 			      s8 txpwrindex, bool res);
1098 void wlc_phy_rssisel_nphy(struct brcms_phy *pi, u8 core, u8 rssi_type);
1099 int wlc_phy_poll_rssi_nphy(struct brcms_phy *pi, u8 rssi_type,
1100 			   s32 *rssi_buf, u8 nsamps);
1101 void wlc_phy_rssi_cal_nphy(struct brcms_phy *pi);
1102 int wlc_phy_aci_scan_nphy(struct brcms_phy *pi);
1103 void wlc_phy_cal_txgainctrl_nphy(struct brcms_phy *pi, s32 dBm_targetpower,
1104 				 bool debug);
1105 int wlc_phy_tx_tone_nphy(struct brcms_phy *pi, u32 f_kHz, u16 max_val, u8 mode,
1106 			 u8, bool);
1107 void wlc_phy_stopplayback_nphy(struct brcms_phy *pi);
1108 void wlc_phy_est_tonepwr_nphy(struct brcms_phy *pi, s32 *qdBm_pwrbuf,
1109 			      u8 num_samps);
1110 void wlc_phy_radio205x_vcocal_nphy(struct brcms_phy *pi);
1111 
1112 int wlc_phy_rssi_compute_nphy(struct brcms_phy *pi, struct d11rxhdr *rxh);
1113 
1114 #define NPHY_TESTPATTERN_BPHY_EVM   0
1115 #define NPHY_TESTPATTERN_BPHY_RFCS  1
1116 
1117 void wlc_phy_nphy_tkip_rifs_war(struct brcms_phy *pi, u8 rifs);
1118 
1119 void wlc_phy_get_pwrdet_offsets(struct brcms_phy *pi, s8 *cckoffset,
1120 				s8 *ofdmoffset);
1121 s8 wlc_phy_upd_rssi_offset(struct brcms_phy *pi, s8 rssi, u16 chanspec);
1122 
1123 bool wlc_phy_n_txpower_ipa_ison(struct brcms_phy *pih);
1124 #endif				/* _BRCM_PHY_INT_H_ */
1125