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Searched refs:tx_reg (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/net/ethernet/intel/idpf/
H A Didpf_vf_dev.c18 struct libie_ctlq_reg *tx_reg = &cci[LIBIE_CTLQ_TYPE_TX].reg; in idpf_vf_ctlq_reg_init() local
21 tx_reg->head = libie_pci_get_mmio_addr(mmio, VF_ATQH); in idpf_vf_ctlq_reg_init()
22 tx_reg->tail = libie_pci_get_mmio_addr(mmio, VF_ATQT); in idpf_vf_ctlq_reg_init()
23 tx_reg->len = libie_pci_get_mmio_addr(mmio, VF_ATQLEN); in idpf_vf_ctlq_reg_init()
24 tx_reg->addr_high = libie_pci_get_mmio_addr(mmio, VF_ATQBAH); in idpf_vf_ctlq_reg_init()
25 tx_reg->addr_low = libie_pci_get_mmio_addr(mmio, VF_ATQBAL); in idpf_vf_ctlq_reg_init()
26 tx_reg->len_mask = VF_ATQLEN_ATQLEN_M; in idpf_vf_ctlq_reg_init()
27 tx_reg->len_ena_mask = VF_ATQLEN_ATQENABLE_M; in idpf_vf_ctlq_reg_init()
28 tx_reg->head_mask = VF_ATQH_ATQH_M; in idpf_vf_ctlq_reg_init()
H A Didpf_dev.c19 struct libie_ctlq_reg *tx_reg = &cci[LIBIE_CTLQ_TYPE_TX].reg; in idpf_ctlq_reg_init() local
22 tx_reg->head = libie_pci_get_mmio_addr(mmio, PF_FW_ATQH); in idpf_ctlq_reg_init()
23 tx_reg->tail = libie_pci_get_mmio_addr(mmio, PF_FW_ATQT); in idpf_ctlq_reg_init()
24 tx_reg->len = libie_pci_get_mmio_addr(mmio, PF_FW_ATQLEN); in idpf_ctlq_reg_init()
25 tx_reg->addr_high = libie_pci_get_mmio_addr(mmio, PF_FW_ATQBAH); in idpf_ctlq_reg_init()
26 tx_reg->addr_low = libie_pci_get_mmio_addr(mmio, PF_FW_ATQBAL); in idpf_ctlq_reg_init()
27 tx_reg->len_mask = PF_FW_ATQLEN_ATQLEN_M; in idpf_ctlq_reg_init()
28 tx_reg->len_ena_mask = PF_FW_ATQLEN_ATQENABLE_M; in idpf_ctlq_reg_init()
29 tx_reg->head_mask = PF_FW_ATQH_ATQH_M; in idpf_ctlq_reg_init()
/linux/drivers/mailbox/
H A Dplatform_mhu.c35 void __iomem *tx_reg; member
66 u32 val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS); in platform_mhu_last_tx_done()
76 writel_relaxed(*arg, mlink->tx_reg + INTR_SET_OFS); in platform_mhu_send_data()
87 val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS); in platform_mhu_startup()
88 writel_relaxed(val, mlink->tx_reg + INTR_CLR_OFS); in platform_mhu_startup()
141 mhu->mlink[i].tx_reg = mhu->mlink[i].rx_reg + TX_REG_OFFSET; in platform_mhu_probe()
H A Darm_mhu_db.c34 void __iomem *tx_reg; member
140 void __iomem *base = chan_info->mhu->mlink[chan_info->pchan].tx_reg; in mhu_db_last_tx_done()
151 void __iomem *base = chan_info->mhu->mlink[chan_info->pchan].tx_reg; in mhu_db_send_data()
315 mhu->mlink[i].tx_reg = mhu->mlink[i].rx_reg + TX_REG_OFFSET; in mhu_db_probe()
/linux/drivers/net/wireless/ath/ath5k/
H A Ddma.c355 u16 tx_reg; in ath5k_hw_get_txdp() local
366 tx_reg = AR5K_NOQCU_TXDP0; in ath5k_hw_get_txdp()
370 tx_reg = AR5K_NOQCU_TXDP1; in ath5k_hw_get_txdp()
376 tx_reg = AR5K_QUEUE_TXDP(queue); in ath5k_hw_get_txdp()
379 return ath5k_hw_reg_read(ah, tx_reg); in ath5k_hw_get_txdp()
398 u16 tx_reg; in ath5k_hw_set_txdp() local
409 tx_reg = AR5K_NOQCU_TXDP0; in ath5k_hw_set_txdp()
413 tx_reg = AR5K_NOQCU_TXDP1; in ath5k_hw_set_txdp()
427 tx_reg = AR5K_QUEUE_TXDP(queue); in ath5k_hw_set_txdp()
431 ath5k_hw_reg_write(ah, phys_addr, tx_reg); in ath5k_hw_set_txdp()
/linux/include/linux/
H A Dpch_dma.h20 dma_addr_t tx_reg; member
/linux/arch/mips/include/asm/txx9/
H A Ddmac.h40 u64 tx_reg; member
/linux/drivers/dma/
H A Dtxx9dmac.c351 if (ds->tx_reg) { in txx9dmac_dostart()
372 if (ds->tx_reg) { in txx9dmac_dostart()
818 if (ds->tx_reg) in txx9dmac_prep_slave_sg()
843 desc->hwdesc.DAR = ds->tx_reg; in txx9dmac_prep_slave_sg()
852 desc->hwdesc32.DAR = ds->tx_reg; in txx9dmac_prep_slave_sg()
1011 (ds->tx_reg && ds->rx_reg) || (!ds->tx_reg && !ds->rx_reg)) in txx9dmac_alloc_chan_resources()
/linux/drivers/media/rc/
H A Dene_ir.h209 int tx_reg; /* current reg used for TX */ member
/linux/drivers/net/phy/
H A Dmotorcomm.c895 u32 rx_reg, tx_reg; in ytphy_rgmii_clk_delay_config() local
903 tx_reg = ytphy_get_delay_reg_value(phydev, "tx-internal-delay-ps", in ytphy_rgmii_clk_delay_config()
916 val |= FIELD_PREP(YT8521_RC1R_GE_TX_DELAY_MASK, tx_reg); in ytphy_rgmii_clk_delay_config()
920 FIELD_PREP(YT8521_RC1R_GE_TX_DELAY_MASK, tx_reg); in ytphy_rgmii_clk_delay_config()
/linux/drivers/net/ethernet/intel/i40e/
H A Di40e_main.c4674 u32 tx_reg; in i40e_pf_txq_wait() local
4677 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q)); in i40e_pf_txq_wait()
4678 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK)) in i40e_pf_txq_wait()
4702 u32 tx_reg; in i40e_control_tx_q() local
4711 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q)); in i40e_control_tx_q()
4712 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) == in i40e_control_tx_q()
4713 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1)) in i40e_control_tx_q()
4719 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK)) in i40e_control_tx_q()
4725 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK; in i40e_control_tx_q()
4727 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK; in i40e_control_tx_q()
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