1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Per core/cpu state
4 *
5 * Used to coordinate shared registers between HT threads or
6 * among events on a single PMU.
7 */
8
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11 #include <linux/stddef.h>
12 #include <linux/types.h>
13 #include <linux/init.h>
14 #include <linux/slab.h>
15 #include <linux/export.h>
16 #include <linux/nmi.h>
17 #include <linux/kvm_host.h>
18
19 #include <asm/cpufeature.h>
20 #include <asm/debugreg.h>
21 #include <asm/hardirq.h>
22 #include <asm/intel-family.h>
23 #include <asm/intel_pt.h>
24 #include <asm/apic.h>
25 #include <asm/cpu_device_id.h>
26
27 #include "../perf_event.h"
28
29 /*
30 * Intel PerfMon, used on Core and later.
31 */
32 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
33 {
34 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
35 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
36 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
37 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
38 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
39 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
40 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
41 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
42 };
43
44 static struct event_constraint intel_core_event_constraints[] __read_mostly =
45 {
46 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
47 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
48 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
49 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
50 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
51 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
52 EVENT_CONSTRAINT_END
53 };
54
55 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
56 {
57 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
58 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
59 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
60 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
61 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
62 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
63 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
64 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
65 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
66 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
67 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
68 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
69 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
70 EVENT_CONSTRAINT_END
71 };
72
73 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
74 {
75 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
76 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
77 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
78 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
79 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
80 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
81 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
82 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
83 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
84 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
85 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
86 EVENT_CONSTRAINT_END
87 };
88
89 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
90 {
91 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
92 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
93 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
94 EVENT_EXTRA_END
95 };
96
97 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
98 {
99 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
100 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
101 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
102 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
103 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
104 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
105 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
106 EVENT_CONSTRAINT_END
107 };
108
109 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
110 {
111 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
112 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
113 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
114 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
115 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
116 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
117 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
118 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
119 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
120 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
121 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
122 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
123
124 /*
125 * When HT is off these events can only run on the bottom 4 counters
126 * When HT is on, they are impacted by the HT bug and require EXCL access
127 */
128 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
129 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
130 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
131 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
132
133 EVENT_CONSTRAINT_END
134 };
135
136 static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
137 {
138 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
139 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
140 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
141 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
142 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMPTY */
143 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
144 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
145 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
146 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
147 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
148 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
149 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
150 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
151
152 /*
153 * When HT is off these events can only run on the bottom 4 counters
154 * When HT is on, they are impacted by the HT bug and require EXCL access
155 */
156 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
157 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
158 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
159 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
160
161 EVENT_CONSTRAINT_END
162 };
163
164 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
165 {
166 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
167 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
168 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
169 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
170 EVENT_EXTRA_END
171 };
172
173 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
174 {
175 EVENT_CONSTRAINT_END
176 };
177
178 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
179 {
180 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
181 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
182 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
183 EVENT_CONSTRAINT_END
184 };
185
186 static struct event_constraint intel_v5_gen_event_constraints[] __read_mostly =
187 {
188 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
189 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
190 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
191 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
192 FIXED_EVENT_CONSTRAINT(0x0500, 4),
193 FIXED_EVENT_CONSTRAINT(0x0600, 5),
194 FIXED_EVENT_CONSTRAINT(0x0700, 6),
195 FIXED_EVENT_CONSTRAINT(0x0800, 7),
196 FIXED_EVENT_CONSTRAINT(0x0900, 8),
197 FIXED_EVENT_CONSTRAINT(0x0a00, 9),
198 FIXED_EVENT_CONSTRAINT(0x0b00, 10),
199 FIXED_EVENT_CONSTRAINT(0x0c00, 11),
200 FIXED_EVENT_CONSTRAINT(0x0d00, 12),
201 FIXED_EVENT_CONSTRAINT(0x0e00, 13),
202 FIXED_EVENT_CONSTRAINT(0x0f00, 14),
203 FIXED_EVENT_CONSTRAINT(0x1000, 15),
204 EVENT_CONSTRAINT_END
205 };
206
207 static struct event_constraint intel_slm_event_constraints[] __read_mostly =
208 {
209 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
210 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
211 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
212 EVENT_CONSTRAINT_END
213 };
214
215 static struct event_constraint intel_grt_event_constraints[] __read_mostly = {
216 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
217 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
218 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
219 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
220 EVENT_CONSTRAINT_END
221 };
222
223 static struct event_constraint intel_skt_event_constraints[] __read_mostly = {
224 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
225 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
226 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
227 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
228 FIXED_EVENT_CONSTRAINT(0x0073, 4), /* TOPDOWN_BAD_SPECULATION.ALL */
229 FIXED_EVENT_CONSTRAINT(0x019c, 5), /* TOPDOWN_FE_BOUND.ALL */
230 FIXED_EVENT_CONSTRAINT(0x02c2, 6), /* TOPDOWN_RETIRING.ALL */
231 EVENT_CONSTRAINT_END
232 };
233
234 static struct event_constraint intel_skl_event_constraints[] = {
235 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
236 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
237 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
238 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
239
240 /*
241 * when HT is off, these can only run on the bottom 4 counters
242 */
243 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
244 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
245 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
246 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
247 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */
248
249 EVENT_CONSTRAINT_END
250 };
251
252 static struct extra_reg intel_knl_extra_regs[] __read_mostly = {
253 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0),
254 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1),
255 EVENT_EXTRA_END
256 };
257
258 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
259 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
260 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
261 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
262 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
263 EVENT_EXTRA_END
264 };
265
266 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
267 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
268 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
269 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
270 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
271 EVENT_EXTRA_END
272 };
273
274 static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
275 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
276 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
277 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
278 /*
279 * Note the low 8 bits eventsel code is not a continuous field, containing
280 * some #GPing bits. These are masked out.
281 */
282 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
283 EVENT_EXTRA_END
284 };
285
286 static struct event_constraint intel_icl_event_constraints[] = {
287 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
288 FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* old INST_RETIRED.PREC_DIST */
289 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */
290 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
291 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
292 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
293 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
294 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
295 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
296 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
297 INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf),
298 INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf),
299 INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */
300 INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x56, 0xf),
301 INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf),
302 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */
303 INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */
304 INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */
305 INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */
306 INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf),
307 INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf),
308 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf),
309 INTEL_EVENT_CONSTRAINT(0xef, 0xf),
310 INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf),
311 EVENT_CONSTRAINT_END
312 };
313
314 static struct extra_reg intel_icl_extra_regs[] __read_mostly = {
315 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0),
316 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1),
317 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
318 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
319 EVENT_EXTRA_END
320 };
321
322 static struct extra_reg intel_glc_extra_regs[] __read_mostly = {
323 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
324 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
325 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
326 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
327 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE),
328 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
329 EVENT_EXTRA_END
330 };
331
332 static struct event_constraint intel_glc_event_constraints[] = {
333 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
334 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */
335 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
336 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
337 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
338 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
339 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
340 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
341 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
342 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
343 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4),
344 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5),
345 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6),
346 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7),
347
348 INTEL_EVENT_CONSTRAINT(0x2e, 0xff),
349 INTEL_EVENT_CONSTRAINT(0x3c, 0xff),
350 /*
351 * Generally event codes < 0x90 are restricted to counters 0-3.
352 * The 0x2E and 0x3C are exception, which has no restriction.
353 */
354 INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf),
355
356 INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf),
357 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf),
358 INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf),
359 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
360 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
361 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1),
362 INTEL_EVENT_CONSTRAINT(0xce, 0x1),
363 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf),
364 /*
365 * Generally event codes >= 0x90 are likely to have no restrictions.
366 * The exception are defined as above.
367 */
368 INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0xff),
369
370 EVENT_CONSTRAINT_END
371 };
372
373 static struct extra_reg intel_rwc_extra_regs[] __read_mostly = {
374 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
375 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
376 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
377 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE),
378 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
379 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE),
380 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
381 EVENT_EXTRA_END
382 };
383
384 static struct event_constraint intel_lnc_event_constraints[] = {
385 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
386 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */
387 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
388 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
389 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
390 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
391 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
392 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
393 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
394 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
395 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4),
396 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5),
397 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6),
398 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7),
399
400 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4),
401 INTEL_UEVENT_CONSTRAINT(0x0175, 0x4),
402
403 INTEL_EVENT_CONSTRAINT(0x2e, 0x3ff),
404 INTEL_EVENT_CONSTRAINT(0x3c, 0x3ff),
405 /*
406 * Generally event codes < 0x90 are restricted to counters 0-3.
407 * The 0x2E and 0x3C are exception, which has no restriction.
408 */
409 INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf),
410
411 INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf),
412 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf),
413 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
414 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
415 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
416 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
417 INTEL_UEVENT_CONSTRAINT(0x10a4, 0x1),
418 INTEL_UEVENT_CONSTRAINT(0x01b1, 0x8),
419 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x3),
420 INTEL_EVENT_CONSTRAINT(0xce, 0x1),
421
422 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf),
423 /*
424 * Generally event codes >= 0x90 are likely to have no restrictions.
425 * The exception are defined as above.
426 */
427 INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0x3ff),
428
429 EVENT_CONSTRAINT_END
430 };
431
432 static struct extra_reg intel_lnc_extra_regs[] __read_mostly = {
433 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0xfffffffffffull, RSP_0),
434 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0xfffffffffffull, RSP_1),
435 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
436 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE),
437 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
438 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0xf, FE),
439 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
440 EVENT_EXTRA_END
441 };
442
443 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
444 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
445 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
446
447 static struct attribute *nhm_mem_events_attrs[] = {
448 EVENT_PTR(mem_ld_nhm),
449 NULL,
450 };
451
452 /*
453 * topdown events for Intel Core CPUs.
454 *
455 * The events are all in slots, which is a free slot in a 4 wide
456 * pipeline. Some events are already reported in slots, for cycle
457 * events we multiply by the pipeline width (4).
458 *
459 * With Hyper Threading on, topdown metrics are either summed or averaged
460 * between the threads of a core: (count_t0 + count_t1).
461 *
462 * For the average case the metric is always scaled to pipeline width,
463 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4)
464 */
465
466 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots,
467 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */
468 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */
469 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2");
470 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued,
471 "event=0xe,umask=0x1"); /* uops_issued.any */
472 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired,
473 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */
474 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles,
475 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */
476 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles,
477 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */
478 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */
479 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale,
480 "4", "2");
481
482 EVENT_ATTR_STR(slots, slots, "event=0x00,umask=0x4");
483 EVENT_ATTR_STR(topdown-retiring, td_retiring, "event=0x00,umask=0x80");
484 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec, "event=0x00,umask=0x81");
485 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound, "event=0x00,umask=0x82");
486 EVENT_ATTR_STR(topdown-be-bound, td_be_bound, "event=0x00,umask=0x83");
487 EVENT_ATTR_STR(topdown-heavy-ops, td_heavy_ops, "event=0x00,umask=0x84");
488 EVENT_ATTR_STR(topdown-br-mispredict, td_br_mispredict, "event=0x00,umask=0x85");
489 EVENT_ATTR_STR(topdown-fetch-lat, td_fetch_lat, "event=0x00,umask=0x86");
490 EVENT_ATTR_STR(topdown-mem-bound, td_mem_bound, "event=0x00,umask=0x87");
491
492 static struct attribute *snb_events_attrs[] = {
493 EVENT_PTR(td_slots_issued),
494 EVENT_PTR(td_slots_retired),
495 EVENT_PTR(td_fetch_bubbles),
496 EVENT_PTR(td_total_slots),
497 EVENT_PTR(td_total_slots_scale),
498 EVENT_PTR(td_recovery_bubbles),
499 EVENT_PTR(td_recovery_bubbles_scale),
500 NULL,
501 };
502
503 static struct attribute *snb_mem_events_attrs[] = {
504 EVENT_PTR(mem_ld_snb),
505 EVENT_PTR(mem_st_snb),
506 NULL,
507 };
508
509 static struct event_constraint intel_hsw_event_constraints[] = {
510 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
511 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
512 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
513 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
514 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
515 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
516 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
517 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
518 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
519 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
520 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
521 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
522
523 /*
524 * When HT is off these events can only run on the bottom 4 counters
525 * When HT is on, they are impacted by the HT bug and require EXCL access
526 */
527 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
528 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
529 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
530 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
531
532 EVENT_CONSTRAINT_END
533 };
534
535 static struct event_constraint intel_bdw_event_constraints[] = {
536 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
537 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
538 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
539 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
540 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */
541 /*
542 * when HT is off, these can only run on the bottom 4 counters
543 */
544 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
545 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
546 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
547 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
548 EVENT_CONSTRAINT_END
549 };
550
intel_pmu_event_map(int hw_event)551 static u64 intel_pmu_event_map(int hw_event)
552 {
553 return intel_perfmon_event_map[hw_event];
554 }
555
556 static __initconst const u64 glc_hw_cache_event_ids
557 [PERF_COUNT_HW_CACHE_MAX]
558 [PERF_COUNT_HW_CACHE_OP_MAX]
559 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
560 {
561 [ C(L1D ) ] = {
562 [ C(OP_READ) ] = {
563 [ C(RESULT_ACCESS) ] = 0x81d0,
564 [ C(RESULT_MISS) ] = 0xe124,
565 },
566 [ C(OP_WRITE) ] = {
567 [ C(RESULT_ACCESS) ] = 0x82d0,
568 },
569 },
570 [ C(L1I ) ] = {
571 [ C(OP_READ) ] = {
572 [ C(RESULT_MISS) ] = 0xe424,
573 },
574 [ C(OP_WRITE) ] = {
575 [ C(RESULT_ACCESS) ] = -1,
576 [ C(RESULT_MISS) ] = -1,
577 },
578 },
579 [ C(LL ) ] = {
580 [ C(OP_READ) ] = {
581 [ C(RESULT_ACCESS) ] = 0x12a,
582 [ C(RESULT_MISS) ] = 0x12a,
583 },
584 [ C(OP_WRITE) ] = {
585 [ C(RESULT_ACCESS) ] = 0x12a,
586 [ C(RESULT_MISS) ] = 0x12a,
587 },
588 },
589 [ C(DTLB) ] = {
590 [ C(OP_READ) ] = {
591 [ C(RESULT_ACCESS) ] = 0x81d0,
592 [ C(RESULT_MISS) ] = 0xe12,
593 },
594 [ C(OP_WRITE) ] = {
595 [ C(RESULT_ACCESS) ] = 0x82d0,
596 [ C(RESULT_MISS) ] = 0xe13,
597 },
598 },
599 [ C(ITLB) ] = {
600 [ C(OP_READ) ] = {
601 [ C(RESULT_ACCESS) ] = -1,
602 [ C(RESULT_MISS) ] = 0xe11,
603 },
604 [ C(OP_WRITE) ] = {
605 [ C(RESULT_ACCESS) ] = -1,
606 [ C(RESULT_MISS) ] = -1,
607 },
608 [ C(OP_PREFETCH) ] = {
609 [ C(RESULT_ACCESS) ] = -1,
610 [ C(RESULT_MISS) ] = -1,
611 },
612 },
613 [ C(BPU ) ] = {
614 [ C(OP_READ) ] = {
615 [ C(RESULT_ACCESS) ] = 0x4c4,
616 [ C(RESULT_MISS) ] = 0x4c5,
617 },
618 [ C(OP_WRITE) ] = {
619 [ C(RESULT_ACCESS) ] = -1,
620 [ C(RESULT_MISS) ] = -1,
621 },
622 [ C(OP_PREFETCH) ] = {
623 [ C(RESULT_ACCESS) ] = -1,
624 [ C(RESULT_MISS) ] = -1,
625 },
626 },
627 [ C(NODE) ] = {
628 [ C(OP_READ) ] = {
629 [ C(RESULT_ACCESS) ] = 0x12a,
630 [ C(RESULT_MISS) ] = 0x12a,
631 },
632 },
633 };
634
635 static __initconst const u64 glc_hw_cache_extra_regs
636 [PERF_COUNT_HW_CACHE_MAX]
637 [PERF_COUNT_HW_CACHE_OP_MAX]
638 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
639 {
640 [ C(LL ) ] = {
641 [ C(OP_READ) ] = {
642 [ C(RESULT_ACCESS) ] = 0x10001,
643 [ C(RESULT_MISS) ] = 0x3fbfc00001,
644 },
645 [ C(OP_WRITE) ] = {
646 [ C(RESULT_ACCESS) ] = 0x3f3ffc0002,
647 [ C(RESULT_MISS) ] = 0x3f3fc00002,
648 },
649 },
650 [ C(NODE) ] = {
651 [ C(OP_READ) ] = {
652 [ C(RESULT_ACCESS) ] = 0x10c000001,
653 [ C(RESULT_MISS) ] = 0x3fb3000001,
654 },
655 },
656 };
657
658 /*
659 * Notes on the events:
660 * - data reads do not include code reads (comparable to earlier tables)
661 * - data counts include speculative execution (except L1 write, dtlb, bpu)
662 * - remote node access includes remote memory, remote cache, remote mmio.
663 * - prefetches are not included in the counts.
664 * - icache miss does not include decoded icache
665 */
666
667 #define SKL_DEMAND_DATA_RD BIT_ULL(0)
668 #define SKL_DEMAND_RFO BIT_ULL(1)
669 #define SKL_ANY_RESPONSE BIT_ULL(16)
670 #define SKL_SUPPLIER_NONE BIT_ULL(17)
671 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26)
672 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27)
673 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28)
674 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29)
675 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \
676 SKL_L3_MISS_REMOTE_HOP0_DRAM| \
677 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
678 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
679 #define SKL_SPL_HIT BIT_ULL(30)
680 #define SKL_SNOOP_NONE BIT_ULL(31)
681 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32)
682 #define SKL_SNOOP_MISS BIT_ULL(33)
683 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34)
684 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35)
685 #define SKL_SNOOP_HITM BIT_ULL(36)
686 #define SKL_SNOOP_NON_DRAM BIT_ULL(37)
687 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \
688 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
689 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
690 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM)
691 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD
692 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \
693 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
694 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
695 SKL_SNOOP_HITM|SKL_SPL_HIT)
696 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO
697 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE
698 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \
699 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
700 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
701
702 static __initconst const u64 skl_hw_cache_event_ids
703 [PERF_COUNT_HW_CACHE_MAX]
704 [PERF_COUNT_HW_CACHE_OP_MAX]
705 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
706 {
707 [ C(L1D ) ] = {
708 [ C(OP_READ) ] = {
709 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
710 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
711 },
712 [ C(OP_WRITE) ] = {
713 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
714 [ C(RESULT_MISS) ] = 0x0,
715 },
716 [ C(OP_PREFETCH) ] = {
717 [ C(RESULT_ACCESS) ] = 0x0,
718 [ C(RESULT_MISS) ] = 0x0,
719 },
720 },
721 [ C(L1I ) ] = {
722 [ C(OP_READ) ] = {
723 [ C(RESULT_ACCESS) ] = 0x0,
724 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */
725 },
726 [ C(OP_WRITE) ] = {
727 [ C(RESULT_ACCESS) ] = -1,
728 [ C(RESULT_MISS) ] = -1,
729 },
730 [ C(OP_PREFETCH) ] = {
731 [ C(RESULT_ACCESS) ] = 0x0,
732 [ C(RESULT_MISS) ] = 0x0,
733 },
734 },
735 [ C(LL ) ] = {
736 [ C(OP_READ) ] = {
737 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
738 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
739 },
740 [ C(OP_WRITE) ] = {
741 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
742 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
743 },
744 [ C(OP_PREFETCH) ] = {
745 [ C(RESULT_ACCESS) ] = 0x0,
746 [ C(RESULT_MISS) ] = 0x0,
747 },
748 },
749 [ C(DTLB) ] = {
750 [ C(OP_READ) ] = {
751 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
752 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
753 },
754 [ C(OP_WRITE) ] = {
755 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
756 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
757 },
758 [ C(OP_PREFETCH) ] = {
759 [ C(RESULT_ACCESS) ] = 0x0,
760 [ C(RESULT_MISS) ] = 0x0,
761 },
762 },
763 [ C(ITLB) ] = {
764 [ C(OP_READ) ] = {
765 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */
766 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */
767 },
768 [ C(OP_WRITE) ] = {
769 [ C(RESULT_ACCESS) ] = -1,
770 [ C(RESULT_MISS) ] = -1,
771 },
772 [ C(OP_PREFETCH) ] = {
773 [ C(RESULT_ACCESS) ] = -1,
774 [ C(RESULT_MISS) ] = -1,
775 },
776 },
777 [ C(BPU ) ] = {
778 [ C(OP_READ) ] = {
779 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
780 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
781 },
782 [ C(OP_WRITE) ] = {
783 [ C(RESULT_ACCESS) ] = -1,
784 [ C(RESULT_MISS) ] = -1,
785 },
786 [ C(OP_PREFETCH) ] = {
787 [ C(RESULT_ACCESS) ] = -1,
788 [ C(RESULT_MISS) ] = -1,
789 },
790 },
791 [ C(NODE) ] = {
792 [ C(OP_READ) ] = {
793 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
794 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
795 },
796 [ C(OP_WRITE) ] = {
797 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
798 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
799 },
800 [ C(OP_PREFETCH) ] = {
801 [ C(RESULT_ACCESS) ] = 0x0,
802 [ C(RESULT_MISS) ] = 0x0,
803 },
804 },
805 };
806
807 static __initconst const u64 skl_hw_cache_extra_regs
808 [PERF_COUNT_HW_CACHE_MAX]
809 [PERF_COUNT_HW_CACHE_OP_MAX]
810 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
811 {
812 [ C(LL ) ] = {
813 [ C(OP_READ) ] = {
814 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
815 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
816 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
817 SKL_L3_MISS|SKL_ANY_SNOOP|
818 SKL_SUPPLIER_NONE,
819 },
820 [ C(OP_WRITE) ] = {
821 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
822 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
823 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
824 SKL_L3_MISS|SKL_ANY_SNOOP|
825 SKL_SUPPLIER_NONE,
826 },
827 [ C(OP_PREFETCH) ] = {
828 [ C(RESULT_ACCESS) ] = 0x0,
829 [ C(RESULT_MISS) ] = 0x0,
830 },
831 },
832 [ C(NODE) ] = {
833 [ C(OP_READ) ] = {
834 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
835 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
836 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
837 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
838 },
839 [ C(OP_WRITE) ] = {
840 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
841 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
842 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
843 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
844 },
845 [ C(OP_PREFETCH) ] = {
846 [ C(RESULT_ACCESS) ] = 0x0,
847 [ C(RESULT_MISS) ] = 0x0,
848 },
849 },
850 };
851
852 #define SNB_DMND_DATA_RD (1ULL << 0)
853 #define SNB_DMND_RFO (1ULL << 1)
854 #define SNB_DMND_IFETCH (1ULL << 2)
855 #define SNB_DMND_WB (1ULL << 3)
856 #define SNB_PF_DATA_RD (1ULL << 4)
857 #define SNB_PF_RFO (1ULL << 5)
858 #define SNB_PF_IFETCH (1ULL << 6)
859 #define SNB_LLC_DATA_RD (1ULL << 7)
860 #define SNB_LLC_RFO (1ULL << 8)
861 #define SNB_LLC_IFETCH (1ULL << 9)
862 #define SNB_BUS_LOCKS (1ULL << 10)
863 #define SNB_STRM_ST (1ULL << 11)
864 #define SNB_OTHER (1ULL << 15)
865 #define SNB_RESP_ANY (1ULL << 16)
866 #define SNB_NO_SUPP (1ULL << 17)
867 #define SNB_LLC_HITM (1ULL << 18)
868 #define SNB_LLC_HITE (1ULL << 19)
869 #define SNB_LLC_HITS (1ULL << 20)
870 #define SNB_LLC_HITF (1ULL << 21)
871 #define SNB_LOCAL (1ULL << 22)
872 #define SNB_REMOTE (0xffULL << 23)
873 #define SNB_SNP_NONE (1ULL << 31)
874 #define SNB_SNP_NOT_NEEDED (1ULL << 32)
875 #define SNB_SNP_MISS (1ULL << 33)
876 #define SNB_NO_FWD (1ULL << 34)
877 #define SNB_SNP_FWD (1ULL << 35)
878 #define SNB_HITM (1ULL << 36)
879 #define SNB_NON_DRAM (1ULL << 37)
880
881 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
882 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
883 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
884
885 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
886 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
887 SNB_HITM)
888
889 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
890 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
891
892 #define SNB_L3_ACCESS SNB_RESP_ANY
893 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
894
895 static __initconst const u64 snb_hw_cache_extra_regs
896 [PERF_COUNT_HW_CACHE_MAX]
897 [PERF_COUNT_HW_CACHE_OP_MAX]
898 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
899 {
900 [ C(LL ) ] = {
901 [ C(OP_READ) ] = {
902 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
903 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
904 },
905 [ C(OP_WRITE) ] = {
906 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
907 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
908 },
909 [ C(OP_PREFETCH) ] = {
910 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
911 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
912 },
913 },
914 [ C(NODE) ] = {
915 [ C(OP_READ) ] = {
916 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
917 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
918 },
919 [ C(OP_WRITE) ] = {
920 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
921 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
922 },
923 [ C(OP_PREFETCH) ] = {
924 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
925 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
926 },
927 },
928 };
929
930 static __initconst const u64 snb_hw_cache_event_ids
931 [PERF_COUNT_HW_CACHE_MAX]
932 [PERF_COUNT_HW_CACHE_OP_MAX]
933 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
934 {
935 [ C(L1D) ] = {
936 [ C(OP_READ) ] = {
937 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
938 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
939 },
940 [ C(OP_WRITE) ] = {
941 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
942 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
943 },
944 [ C(OP_PREFETCH) ] = {
945 [ C(RESULT_ACCESS) ] = 0x0,
946 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
947 },
948 },
949 [ C(L1I ) ] = {
950 [ C(OP_READ) ] = {
951 [ C(RESULT_ACCESS) ] = 0x0,
952 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
953 },
954 [ C(OP_WRITE) ] = {
955 [ C(RESULT_ACCESS) ] = -1,
956 [ C(RESULT_MISS) ] = -1,
957 },
958 [ C(OP_PREFETCH) ] = {
959 [ C(RESULT_ACCESS) ] = 0x0,
960 [ C(RESULT_MISS) ] = 0x0,
961 },
962 },
963 [ C(LL ) ] = {
964 [ C(OP_READ) ] = {
965 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
966 [ C(RESULT_ACCESS) ] = 0x01b7,
967 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
968 [ C(RESULT_MISS) ] = 0x01b7,
969 },
970 [ C(OP_WRITE) ] = {
971 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
972 [ C(RESULT_ACCESS) ] = 0x01b7,
973 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
974 [ C(RESULT_MISS) ] = 0x01b7,
975 },
976 [ C(OP_PREFETCH) ] = {
977 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
978 [ C(RESULT_ACCESS) ] = 0x01b7,
979 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
980 [ C(RESULT_MISS) ] = 0x01b7,
981 },
982 },
983 [ C(DTLB) ] = {
984 [ C(OP_READ) ] = {
985 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
986 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
987 },
988 [ C(OP_WRITE) ] = {
989 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
990 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
991 },
992 [ C(OP_PREFETCH) ] = {
993 [ C(RESULT_ACCESS) ] = 0x0,
994 [ C(RESULT_MISS) ] = 0x0,
995 },
996 },
997 [ C(ITLB) ] = {
998 [ C(OP_READ) ] = {
999 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
1000 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
1001 },
1002 [ C(OP_WRITE) ] = {
1003 [ C(RESULT_ACCESS) ] = -1,
1004 [ C(RESULT_MISS) ] = -1,
1005 },
1006 [ C(OP_PREFETCH) ] = {
1007 [ C(RESULT_ACCESS) ] = -1,
1008 [ C(RESULT_MISS) ] = -1,
1009 },
1010 },
1011 [ C(BPU ) ] = {
1012 [ C(OP_READ) ] = {
1013 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1014 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1015 },
1016 [ C(OP_WRITE) ] = {
1017 [ C(RESULT_ACCESS) ] = -1,
1018 [ C(RESULT_MISS) ] = -1,
1019 },
1020 [ C(OP_PREFETCH) ] = {
1021 [ C(RESULT_ACCESS) ] = -1,
1022 [ C(RESULT_MISS) ] = -1,
1023 },
1024 },
1025 [ C(NODE) ] = {
1026 [ C(OP_READ) ] = {
1027 [ C(RESULT_ACCESS) ] = 0x01b7,
1028 [ C(RESULT_MISS) ] = 0x01b7,
1029 },
1030 [ C(OP_WRITE) ] = {
1031 [ C(RESULT_ACCESS) ] = 0x01b7,
1032 [ C(RESULT_MISS) ] = 0x01b7,
1033 },
1034 [ C(OP_PREFETCH) ] = {
1035 [ C(RESULT_ACCESS) ] = 0x01b7,
1036 [ C(RESULT_MISS) ] = 0x01b7,
1037 },
1038 },
1039
1040 };
1041
1042 /*
1043 * Notes on the events:
1044 * - data reads do not include code reads (comparable to earlier tables)
1045 * - data counts include speculative execution (except L1 write, dtlb, bpu)
1046 * - remote node access includes remote memory, remote cache, remote mmio.
1047 * - prefetches are not included in the counts because they are not
1048 * reliably counted.
1049 */
1050
1051 #define HSW_DEMAND_DATA_RD BIT_ULL(0)
1052 #define HSW_DEMAND_RFO BIT_ULL(1)
1053 #define HSW_ANY_RESPONSE BIT_ULL(16)
1054 #define HSW_SUPPLIER_NONE BIT_ULL(17)
1055 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)
1056 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)
1057 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)
1058 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)
1059 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \
1060 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
1061 HSW_L3_MISS_REMOTE_HOP2P)
1062 #define HSW_SNOOP_NONE BIT_ULL(31)
1063 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)
1064 #define HSW_SNOOP_MISS BIT_ULL(33)
1065 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)
1066 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)
1067 #define HSW_SNOOP_HITM BIT_ULL(36)
1068 #define HSW_SNOOP_NON_DRAM BIT_ULL(37)
1069 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \
1070 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
1071 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
1072 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
1073 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
1074 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD
1075 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO
1076 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\
1077 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
1078 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE
1079
1080 #define BDW_L3_MISS_LOCAL BIT(26)
1081 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \
1082 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
1083 HSW_L3_MISS_REMOTE_HOP2P)
1084
1085
1086 static __initconst const u64 hsw_hw_cache_event_ids
1087 [PERF_COUNT_HW_CACHE_MAX]
1088 [PERF_COUNT_HW_CACHE_OP_MAX]
1089 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1090 {
1091 [ C(L1D ) ] = {
1092 [ C(OP_READ) ] = {
1093 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1094 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
1095 },
1096 [ C(OP_WRITE) ] = {
1097 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1098 [ C(RESULT_MISS) ] = 0x0,
1099 },
1100 [ C(OP_PREFETCH) ] = {
1101 [ C(RESULT_ACCESS) ] = 0x0,
1102 [ C(RESULT_MISS) ] = 0x0,
1103 },
1104 },
1105 [ C(L1I ) ] = {
1106 [ C(OP_READ) ] = {
1107 [ C(RESULT_ACCESS) ] = 0x0,
1108 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
1109 },
1110 [ C(OP_WRITE) ] = {
1111 [ C(RESULT_ACCESS) ] = -1,
1112 [ C(RESULT_MISS) ] = -1,
1113 },
1114 [ C(OP_PREFETCH) ] = {
1115 [ C(RESULT_ACCESS) ] = 0x0,
1116 [ C(RESULT_MISS) ] = 0x0,
1117 },
1118 },
1119 [ C(LL ) ] = {
1120 [ C(OP_READ) ] = {
1121 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1122 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1123 },
1124 [ C(OP_WRITE) ] = {
1125 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1126 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1127 },
1128 [ C(OP_PREFETCH) ] = {
1129 [ C(RESULT_ACCESS) ] = 0x0,
1130 [ C(RESULT_MISS) ] = 0x0,
1131 },
1132 },
1133 [ C(DTLB) ] = {
1134 [ C(OP_READ) ] = {
1135 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1136 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
1137 },
1138 [ C(OP_WRITE) ] = {
1139 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1140 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
1141 },
1142 [ C(OP_PREFETCH) ] = {
1143 [ C(RESULT_ACCESS) ] = 0x0,
1144 [ C(RESULT_MISS) ] = 0x0,
1145 },
1146 },
1147 [ C(ITLB) ] = {
1148 [ C(OP_READ) ] = {
1149 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
1150 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
1151 },
1152 [ C(OP_WRITE) ] = {
1153 [ C(RESULT_ACCESS) ] = -1,
1154 [ C(RESULT_MISS) ] = -1,
1155 },
1156 [ C(OP_PREFETCH) ] = {
1157 [ C(RESULT_ACCESS) ] = -1,
1158 [ C(RESULT_MISS) ] = -1,
1159 },
1160 },
1161 [ C(BPU ) ] = {
1162 [ C(OP_READ) ] = {
1163 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
1164 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1165 },
1166 [ C(OP_WRITE) ] = {
1167 [ C(RESULT_ACCESS) ] = -1,
1168 [ C(RESULT_MISS) ] = -1,
1169 },
1170 [ C(OP_PREFETCH) ] = {
1171 [ C(RESULT_ACCESS) ] = -1,
1172 [ C(RESULT_MISS) ] = -1,
1173 },
1174 },
1175 [ C(NODE) ] = {
1176 [ C(OP_READ) ] = {
1177 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1178 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1179 },
1180 [ C(OP_WRITE) ] = {
1181 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1182 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1183 },
1184 [ C(OP_PREFETCH) ] = {
1185 [ C(RESULT_ACCESS) ] = 0x0,
1186 [ C(RESULT_MISS) ] = 0x0,
1187 },
1188 },
1189 };
1190
1191 static __initconst const u64 hsw_hw_cache_extra_regs
1192 [PERF_COUNT_HW_CACHE_MAX]
1193 [PERF_COUNT_HW_CACHE_OP_MAX]
1194 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1195 {
1196 [ C(LL ) ] = {
1197 [ C(OP_READ) ] = {
1198 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1199 HSW_LLC_ACCESS,
1200 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
1201 HSW_L3_MISS|HSW_ANY_SNOOP,
1202 },
1203 [ C(OP_WRITE) ] = {
1204 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1205 HSW_LLC_ACCESS,
1206 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
1207 HSW_L3_MISS|HSW_ANY_SNOOP,
1208 },
1209 [ C(OP_PREFETCH) ] = {
1210 [ C(RESULT_ACCESS) ] = 0x0,
1211 [ C(RESULT_MISS) ] = 0x0,
1212 },
1213 },
1214 [ C(NODE) ] = {
1215 [ C(OP_READ) ] = {
1216 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1217 HSW_L3_MISS_LOCAL_DRAM|
1218 HSW_SNOOP_DRAM,
1219 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
1220 HSW_L3_MISS_REMOTE|
1221 HSW_SNOOP_DRAM,
1222 },
1223 [ C(OP_WRITE) ] = {
1224 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1225 HSW_L3_MISS_LOCAL_DRAM|
1226 HSW_SNOOP_DRAM,
1227 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
1228 HSW_L3_MISS_REMOTE|
1229 HSW_SNOOP_DRAM,
1230 },
1231 [ C(OP_PREFETCH) ] = {
1232 [ C(RESULT_ACCESS) ] = 0x0,
1233 [ C(RESULT_MISS) ] = 0x0,
1234 },
1235 },
1236 };
1237
1238 static __initconst const u64 westmere_hw_cache_event_ids
1239 [PERF_COUNT_HW_CACHE_MAX]
1240 [PERF_COUNT_HW_CACHE_OP_MAX]
1241 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1242 {
1243 [ C(L1D) ] = {
1244 [ C(OP_READ) ] = {
1245 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1246 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1247 },
1248 [ C(OP_WRITE) ] = {
1249 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1250 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1251 },
1252 [ C(OP_PREFETCH) ] = {
1253 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1254 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1255 },
1256 },
1257 [ C(L1I ) ] = {
1258 [ C(OP_READ) ] = {
1259 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1260 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1261 },
1262 [ C(OP_WRITE) ] = {
1263 [ C(RESULT_ACCESS) ] = -1,
1264 [ C(RESULT_MISS) ] = -1,
1265 },
1266 [ C(OP_PREFETCH) ] = {
1267 [ C(RESULT_ACCESS) ] = 0x0,
1268 [ C(RESULT_MISS) ] = 0x0,
1269 },
1270 },
1271 [ C(LL ) ] = {
1272 [ C(OP_READ) ] = {
1273 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1274 [ C(RESULT_ACCESS) ] = 0x01b7,
1275 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1276 [ C(RESULT_MISS) ] = 0x01b7,
1277 },
1278 /*
1279 * Use RFO, not WRITEBACK, because a write miss would typically occur
1280 * on RFO.
1281 */
1282 [ C(OP_WRITE) ] = {
1283 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1284 [ C(RESULT_ACCESS) ] = 0x01b7,
1285 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1286 [ C(RESULT_MISS) ] = 0x01b7,
1287 },
1288 [ C(OP_PREFETCH) ] = {
1289 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1290 [ C(RESULT_ACCESS) ] = 0x01b7,
1291 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1292 [ C(RESULT_MISS) ] = 0x01b7,
1293 },
1294 },
1295 [ C(DTLB) ] = {
1296 [ C(OP_READ) ] = {
1297 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1298 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1299 },
1300 [ C(OP_WRITE) ] = {
1301 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1302 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1303 },
1304 [ C(OP_PREFETCH) ] = {
1305 [ C(RESULT_ACCESS) ] = 0x0,
1306 [ C(RESULT_MISS) ] = 0x0,
1307 },
1308 },
1309 [ C(ITLB) ] = {
1310 [ C(OP_READ) ] = {
1311 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1312 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
1313 },
1314 [ C(OP_WRITE) ] = {
1315 [ C(RESULT_ACCESS) ] = -1,
1316 [ C(RESULT_MISS) ] = -1,
1317 },
1318 [ C(OP_PREFETCH) ] = {
1319 [ C(RESULT_ACCESS) ] = -1,
1320 [ C(RESULT_MISS) ] = -1,
1321 },
1322 },
1323 [ C(BPU ) ] = {
1324 [ C(OP_READ) ] = {
1325 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1326 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1327 },
1328 [ C(OP_WRITE) ] = {
1329 [ C(RESULT_ACCESS) ] = -1,
1330 [ C(RESULT_MISS) ] = -1,
1331 },
1332 [ C(OP_PREFETCH) ] = {
1333 [ C(RESULT_ACCESS) ] = -1,
1334 [ C(RESULT_MISS) ] = -1,
1335 },
1336 },
1337 [ C(NODE) ] = {
1338 [ C(OP_READ) ] = {
1339 [ C(RESULT_ACCESS) ] = 0x01b7,
1340 [ C(RESULT_MISS) ] = 0x01b7,
1341 },
1342 [ C(OP_WRITE) ] = {
1343 [ C(RESULT_ACCESS) ] = 0x01b7,
1344 [ C(RESULT_MISS) ] = 0x01b7,
1345 },
1346 [ C(OP_PREFETCH) ] = {
1347 [ C(RESULT_ACCESS) ] = 0x01b7,
1348 [ C(RESULT_MISS) ] = 0x01b7,
1349 },
1350 },
1351 };
1352
1353 /*
1354 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
1355 * See IA32 SDM Vol 3B 30.6.1.3
1356 */
1357
1358 #define NHM_DMND_DATA_RD (1 << 0)
1359 #define NHM_DMND_RFO (1 << 1)
1360 #define NHM_DMND_IFETCH (1 << 2)
1361 #define NHM_DMND_WB (1 << 3)
1362 #define NHM_PF_DATA_RD (1 << 4)
1363 #define NHM_PF_DATA_RFO (1 << 5)
1364 #define NHM_PF_IFETCH (1 << 6)
1365 #define NHM_OFFCORE_OTHER (1 << 7)
1366 #define NHM_UNCORE_HIT (1 << 8)
1367 #define NHM_OTHER_CORE_HIT_SNP (1 << 9)
1368 #define NHM_OTHER_CORE_HITM (1 << 10)
1369 /* reserved */
1370 #define NHM_REMOTE_CACHE_FWD (1 << 12)
1371 #define NHM_REMOTE_DRAM (1 << 13)
1372 #define NHM_LOCAL_DRAM (1 << 14)
1373 #define NHM_NON_DRAM (1 << 15)
1374
1375 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
1376 #define NHM_REMOTE (NHM_REMOTE_DRAM)
1377
1378 #define NHM_DMND_READ (NHM_DMND_DATA_RD)
1379 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
1380 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
1381
1382 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
1383 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
1384 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
1385
1386 static __initconst const u64 nehalem_hw_cache_extra_regs
1387 [PERF_COUNT_HW_CACHE_MAX]
1388 [PERF_COUNT_HW_CACHE_OP_MAX]
1389 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1390 {
1391 [ C(LL ) ] = {
1392 [ C(OP_READ) ] = {
1393 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1394 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
1395 },
1396 [ C(OP_WRITE) ] = {
1397 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1398 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
1399 },
1400 [ C(OP_PREFETCH) ] = {
1401 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1402 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
1403 },
1404 },
1405 [ C(NODE) ] = {
1406 [ C(OP_READ) ] = {
1407 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1408 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
1409 },
1410 [ C(OP_WRITE) ] = {
1411 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1412 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
1413 },
1414 [ C(OP_PREFETCH) ] = {
1415 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1416 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
1417 },
1418 },
1419 };
1420
1421 static __initconst const u64 nehalem_hw_cache_event_ids
1422 [PERF_COUNT_HW_CACHE_MAX]
1423 [PERF_COUNT_HW_CACHE_OP_MAX]
1424 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1425 {
1426 [ C(L1D) ] = {
1427 [ C(OP_READ) ] = {
1428 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1429 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1430 },
1431 [ C(OP_WRITE) ] = {
1432 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1433 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1434 },
1435 [ C(OP_PREFETCH) ] = {
1436 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1437 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1438 },
1439 },
1440 [ C(L1I ) ] = {
1441 [ C(OP_READ) ] = {
1442 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1443 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1444 },
1445 [ C(OP_WRITE) ] = {
1446 [ C(RESULT_ACCESS) ] = -1,
1447 [ C(RESULT_MISS) ] = -1,
1448 },
1449 [ C(OP_PREFETCH) ] = {
1450 [ C(RESULT_ACCESS) ] = 0x0,
1451 [ C(RESULT_MISS) ] = 0x0,
1452 },
1453 },
1454 [ C(LL ) ] = {
1455 [ C(OP_READ) ] = {
1456 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1457 [ C(RESULT_ACCESS) ] = 0x01b7,
1458 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1459 [ C(RESULT_MISS) ] = 0x01b7,
1460 },
1461 /*
1462 * Use RFO, not WRITEBACK, because a write miss would typically occur
1463 * on RFO.
1464 */
1465 [ C(OP_WRITE) ] = {
1466 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1467 [ C(RESULT_ACCESS) ] = 0x01b7,
1468 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1469 [ C(RESULT_MISS) ] = 0x01b7,
1470 },
1471 [ C(OP_PREFETCH) ] = {
1472 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1473 [ C(RESULT_ACCESS) ] = 0x01b7,
1474 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1475 [ C(RESULT_MISS) ] = 0x01b7,
1476 },
1477 },
1478 [ C(DTLB) ] = {
1479 [ C(OP_READ) ] = {
1480 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1481 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1482 },
1483 [ C(OP_WRITE) ] = {
1484 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1485 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1486 },
1487 [ C(OP_PREFETCH) ] = {
1488 [ C(RESULT_ACCESS) ] = 0x0,
1489 [ C(RESULT_MISS) ] = 0x0,
1490 },
1491 },
1492 [ C(ITLB) ] = {
1493 [ C(OP_READ) ] = {
1494 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1495 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
1496 },
1497 [ C(OP_WRITE) ] = {
1498 [ C(RESULT_ACCESS) ] = -1,
1499 [ C(RESULT_MISS) ] = -1,
1500 },
1501 [ C(OP_PREFETCH) ] = {
1502 [ C(RESULT_ACCESS) ] = -1,
1503 [ C(RESULT_MISS) ] = -1,
1504 },
1505 },
1506 [ C(BPU ) ] = {
1507 [ C(OP_READ) ] = {
1508 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1509 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1510 },
1511 [ C(OP_WRITE) ] = {
1512 [ C(RESULT_ACCESS) ] = -1,
1513 [ C(RESULT_MISS) ] = -1,
1514 },
1515 [ C(OP_PREFETCH) ] = {
1516 [ C(RESULT_ACCESS) ] = -1,
1517 [ C(RESULT_MISS) ] = -1,
1518 },
1519 },
1520 [ C(NODE) ] = {
1521 [ C(OP_READ) ] = {
1522 [ C(RESULT_ACCESS) ] = 0x01b7,
1523 [ C(RESULT_MISS) ] = 0x01b7,
1524 },
1525 [ C(OP_WRITE) ] = {
1526 [ C(RESULT_ACCESS) ] = 0x01b7,
1527 [ C(RESULT_MISS) ] = 0x01b7,
1528 },
1529 [ C(OP_PREFETCH) ] = {
1530 [ C(RESULT_ACCESS) ] = 0x01b7,
1531 [ C(RESULT_MISS) ] = 0x01b7,
1532 },
1533 },
1534 };
1535
1536 static __initconst const u64 core2_hw_cache_event_ids
1537 [PERF_COUNT_HW_CACHE_MAX]
1538 [PERF_COUNT_HW_CACHE_OP_MAX]
1539 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1540 {
1541 [ C(L1D) ] = {
1542 [ C(OP_READ) ] = {
1543 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
1544 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
1545 },
1546 [ C(OP_WRITE) ] = {
1547 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
1548 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
1549 },
1550 [ C(OP_PREFETCH) ] = {
1551 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
1552 [ C(RESULT_MISS) ] = 0,
1553 },
1554 },
1555 [ C(L1I ) ] = {
1556 [ C(OP_READ) ] = {
1557 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
1558 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
1559 },
1560 [ C(OP_WRITE) ] = {
1561 [ C(RESULT_ACCESS) ] = -1,
1562 [ C(RESULT_MISS) ] = -1,
1563 },
1564 [ C(OP_PREFETCH) ] = {
1565 [ C(RESULT_ACCESS) ] = 0,
1566 [ C(RESULT_MISS) ] = 0,
1567 },
1568 },
1569 [ C(LL ) ] = {
1570 [ C(OP_READ) ] = {
1571 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1572 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1573 },
1574 [ C(OP_WRITE) ] = {
1575 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1576 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1577 },
1578 [ C(OP_PREFETCH) ] = {
1579 [ C(RESULT_ACCESS) ] = 0,
1580 [ C(RESULT_MISS) ] = 0,
1581 },
1582 },
1583 [ C(DTLB) ] = {
1584 [ C(OP_READ) ] = {
1585 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1586 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
1587 },
1588 [ C(OP_WRITE) ] = {
1589 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1590 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
1591 },
1592 [ C(OP_PREFETCH) ] = {
1593 [ C(RESULT_ACCESS) ] = 0,
1594 [ C(RESULT_MISS) ] = 0,
1595 },
1596 },
1597 [ C(ITLB) ] = {
1598 [ C(OP_READ) ] = {
1599 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1600 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
1601 },
1602 [ C(OP_WRITE) ] = {
1603 [ C(RESULT_ACCESS) ] = -1,
1604 [ C(RESULT_MISS) ] = -1,
1605 },
1606 [ C(OP_PREFETCH) ] = {
1607 [ C(RESULT_ACCESS) ] = -1,
1608 [ C(RESULT_MISS) ] = -1,
1609 },
1610 },
1611 [ C(BPU ) ] = {
1612 [ C(OP_READ) ] = {
1613 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1614 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1615 },
1616 [ C(OP_WRITE) ] = {
1617 [ C(RESULT_ACCESS) ] = -1,
1618 [ C(RESULT_MISS) ] = -1,
1619 },
1620 [ C(OP_PREFETCH) ] = {
1621 [ C(RESULT_ACCESS) ] = -1,
1622 [ C(RESULT_MISS) ] = -1,
1623 },
1624 },
1625 };
1626
1627 static __initconst const u64 atom_hw_cache_event_ids
1628 [PERF_COUNT_HW_CACHE_MAX]
1629 [PERF_COUNT_HW_CACHE_OP_MAX]
1630 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1631 {
1632 [ C(L1D) ] = {
1633 [ C(OP_READ) ] = {
1634 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
1635 [ C(RESULT_MISS) ] = 0,
1636 },
1637 [ C(OP_WRITE) ] = {
1638 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
1639 [ C(RESULT_MISS) ] = 0,
1640 },
1641 [ C(OP_PREFETCH) ] = {
1642 [ C(RESULT_ACCESS) ] = 0x0,
1643 [ C(RESULT_MISS) ] = 0,
1644 },
1645 },
1646 [ C(L1I ) ] = {
1647 [ C(OP_READ) ] = {
1648 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1649 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1650 },
1651 [ C(OP_WRITE) ] = {
1652 [ C(RESULT_ACCESS) ] = -1,
1653 [ C(RESULT_MISS) ] = -1,
1654 },
1655 [ C(OP_PREFETCH) ] = {
1656 [ C(RESULT_ACCESS) ] = 0,
1657 [ C(RESULT_MISS) ] = 0,
1658 },
1659 },
1660 [ C(LL ) ] = {
1661 [ C(OP_READ) ] = {
1662 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1663 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1664 },
1665 [ C(OP_WRITE) ] = {
1666 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1667 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1668 },
1669 [ C(OP_PREFETCH) ] = {
1670 [ C(RESULT_ACCESS) ] = 0,
1671 [ C(RESULT_MISS) ] = 0,
1672 },
1673 },
1674 [ C(DTLB) ] = {
1675 [ C(OP_READ) ] = {
1676 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
1677 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
1678 },
1679 [ C(OP_WRITE) ] = {
1680 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
1681 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
1682 },
1683 [ C(OP_PREFETCH) ] = {
1684 [ C(RESULT_ACCESS) ] = 0,
1685 [ C(RESULT_MISS) ] = 0,
1686 },
1687 },
1688 [ C(ITLB) ] = {
1689 [ C(OP_READ) ] = {
1690 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1691 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1692 },
1693 [ C(OP_WRITE) ] = {
1694 [ C(RESULT_ACCESS) ] = -1,
1695 [ C(RESULT_MISS) ] = -1,
1696 },
1697 [ C(OP_PREFETCH) ] = {
1698 [ C(RESULT_ACCESS) ] = -1,
1699 [ C(RESULT_MISS) ] = -1,
1700 },
1701 },
1702 [ C(BPU ) ] = {
1703 [ C(OP_READ) ] = {
1704 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1705 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1706 },
1707 [ C(OP_WRITE) ] = {
1708 [ C(RESULT_ACCESS) ] = -1,
1709 [ C(RESULT_MISS) ] = -1,
1710 },
1711 [ C(OP_PREFETCH) ] = {
1712 [ C(RESULT_ACCESS) ] = -1,
1713 [ C(RESULT_MISS) ] = -1,
1714 },
1715 },
1716 };
1717
1718 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c");
1719 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2");
1720 /* no_alloc_cycles.not_delivered */
1721 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm,
1722 "event=0xca,umask=0x50");
1723 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2");
1724 /* uops_retired.all */
1725 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm,
1726 "event=0xc2,umask=0x10");
1727 /* uops_retired.all */
1728 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm,
1729 "event=0xc2,umask=0x10");
1730
1731 static struct attribute *slm_events_attrs[] = {
1732 EVENT_PTR(td_total_slots_slm),
1733 EVENT_PTR(td_total_slots_scale_slm),
1734 EVENT_PTR(td_fetch_bubbles_slm),
1735 EVENT_PTR(td_fetch_bubbles_scale_slm),
1736 EVENT_PTR(td_slots_issued_slm),
1737 EVENT_PTR(td_slots_retired_slm),
1738 NULL
1739 };
1740
1741 static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1742 {
1743 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1744 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
1745 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
1746 EVENT_EXTRA_END
1747 };
1748
1749 #define SLM_DMND_READ SNB_DMND_DATA_RD
1750 #define SLM_DMND_WRITE SNB_DMND_RFO
1751 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1752
1753 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1754 #define SLM_LLC_ACCESS SNB_RESP_ANY
1755 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
1756
1757 static __initconst const u64 slm_hw_cache_extra_regs
1758 [PERF_COUNT_HW_CACHE_MAX]
1759 [PERF_COUNT_HW_CACHE_OP_MAX]
1760 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1761 {
1762 [ C(LL ) ] = {
1763 [ C(OP_READ) ] = {
1764 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
1765 [ C(RESULT_MISS) ] = 0,
1766 },
1767 [ C(OP_WRITE) ] = {
1768 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1769 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1770 },
1771 [ C(OP_PREFETCH) ] = {
1772 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1773 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1774 },
1775 },
1776 };
1777
1778 static __initconst const u64 slm_hw_cache_event_ids
1779 [PERF_COUNT_HW_CACHE_MAX]
1780 [PERF_COUNT_HW_CACHE_OP_MAX]
1781 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1782 {
1783 [ C(L1D) ] = {
1784 [ C(OP_READ) ] = {
1785 [ C(RESULT_ACCESS) ] = 0,
1786 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
1787 },
1788 [ C(OP_WRITE) ] = {
1789 [ C(RESULT_ACCESS) ] = 0,
1790 [ C(RESULT_MISS) ] = 0,
1791 },
1792 [ C(OP_PREFETCH) ] = {
1793 [ C(RESULT_ACCESS) ] = 0,
1794 [ C(RESULT_MISS) ] = 0,
1795 },
1796 },
1797 [ C(L1I ) ] = {
1798 [ C(OP_READ) ] = {
1799 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1800 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
1801 },
1802 [ C(OP_WRITE) ] = {
1803 [ C(RESULT_ACCESS) ] = -1,
1804 [ C(RESULT_MISS) ] = -1,
1805 },
1806 [ C(OP_PREFETCH) ] = {
1807 [ C(RESULT_ACCESS) ] = 0,
1808 [ C(RESULT_MISS) ] = 0,
1809 },
1810 },
1811 [ C(LL ) ] = {
1812 [ C(OP_READ) ] = {
1813 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1814 [ C(RESULT_ACCESS) ] = 0x01b7,
1815 [ C(RESULT_MISS) ] = 0,
1816 },
1817 [ C(OP_WRITE) ] = {
1818 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1819 [ C(RESULT_ACCESS) ] = 0x01b7,
1820 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1821 [ C(RESULT_MISS) ] = 0x01b7,
1822 },
1823 [ C(OP_PREFETCH) ] = {
1824 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1825 [ C(RESULT_ACCESS) ] = 0x01b7,
1826 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1827 [ C(RESULT_MISS) ] = 0x01b7,
1828 },
1829 },
1830 [ C(DTLB) ] = {
1831 [ C(OP_READ) ] = {
1832 [ C(RESULT_ACCESS) ] = 0,
1833 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
1834 },
1835 [ C(OP_WRITE) ] = {
1836 [ C(RESULT_ACCESS) ] = 0,
1837 [ C(RESULT_MISS) ] = 0,
1838 },
1839 [ C(OP_PREFETCH) ] = {
1840 [ C(RESULT_ACCESS) ] = 0,
1841 [ C(RESULT_MISS) ] = 0,
1842 },
1843 },
1844 [ C(ITLB) ] = {
1845 [ C(OP_READ) ] = {
1846 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1847 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1848 },
1849 [ C(OP_WRITE) ] = {
1850 [ C(RESULT_ACCESS) ] = -1,
1851 [ C(RESULT_MISS) ] = -1,
1852 },
1853 [ C(OP_PREFETCH) ] = {
1854 [ C(RESULT_ACCESS) ] = -1,
1855 [ C(RESULT_MISS) ] = -1,
1856 },
1857 },
1858 [ C(BPU ) ] = {
1859 [ C(OP_READ) ] = {
1860 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1861 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1862 },
1863 [ C(OP_WRITE) ] = {
1864 [ C(RESULT_ACCESS) ] = -1,
1865 [ C(RESULT_MISS) ] = -1,
1866 },
1867 [ C(OP_PREFETCH) ] = {
1868 [ C(RESULT_ACCESS) ] = -1,
1869 [ C(RESULT_MISS) ] = -1,
1870 },
1871 },
1872 };
1873
1874 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c");
1875 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3");
1876 /* UOPS_NOT_DELIVERED.ANY */
1877 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c");
1878 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */
1879 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02");
1880 /* UOPS_RETIRED.ANY */
1881 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2");
1882 /* UOPS_ISSUED.ANY */
1883 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e");
1884
1885 static struct attribute *glm_events_attrs[] = {
1886 EVENT_PTR(td_total_slots_glm),
1887 EVENT_PTR(td_total_slots_scale_glm),
1888 EVENT_PTR(td_fetch_bubbles_glm),
1889 EVENT_PTR(td_recovery_bubbles_glm),
1890 EVENT_PTR(td_slots_issued_glm),
1891 EVENT_PTR(td_slots_retired_glm),
1892 NULL
1893 };
1894
1895 static struct extra_reg intel_glm_extra_regs[] __read_mostly = {
1896 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1897 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0),
1898 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1),
1899 EVENT_EXTRA_END
1900 };
1901
1902 #define GLM_DEMAND_DATA_RD BIT_ULL(0)
1903 #define GLM_DEMAND_RFO BIT_ULL(1)
1904 #define GLM_ANY_RESPONSE BIT_ULL(16)
1905 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33)
1906 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD
1907 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO
1908 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1909 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE
1910 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM)
1911 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM)
1912
1913 static __initconst const u64 glm_hw_cache_event_ids
1914 [PERF_COUNT_HW_CACHE_MAX]
1915 [PERF_COUNT_HW_CACHE_OP_MAX]
1916 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1917 [C(L1D)] = {
1918 [C(OP_READ)] = {
1919 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1920 [C(RESULT_MISS)] = 0x0,
1921 },
1922 [C(OP_WRITE)] = {
1923 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1924 [C(RESULT_MISS)] = 0x0,
1925 },
1926 [C(OP_PREFETCH)] = {
1927 [C(RESULT_ACCESS)] = 0x0,
1928 [C(RESULT_MISS)] = 0x0,
1929 },
1930 },
1931 [C(L1I)] = {
1932 [C(OP_READ)] = {
1933 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1934 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1935 },
1936 [C(OP_WRITE)] = {
1937 [C(RESULT_ACCESS)] = -1,
1938 [C(RESULT_MISS)] = -1,
1939 },
1940 [C(OP_PREFETCH)] = {
1941 [C(RESULT_ACCESS)] = 0x0,
1942 [C(RESULT_MISS)] = 0x0,
1943 },
1944 },
1945 [C(LL)] = {
1946 [C(OP_READ)] = {
1947 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1948 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1949 },
1950 [C(OP_WRITE)] = {
1951 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1952 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1953 },
1954 [C(OP_PREFETCH)] = {
1955 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1956 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1957 },
1958 },
1959 [C(DTLB)] = {
1960 [C(OP_READ)] = {
1961 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1962 [C(RESULT_MISS)] = 0x0,
1963 },
1964 [C(OP_WRITE)] = {
1965 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1966 [C(RESULT_MISS)] = 0x0,
1967 },
1968 [C(OP_PREFETCH)] = {
1969 [C(RESULT_ACCESS)] = 0x0,
1970 [C(RESULT_MISS)] = 0x0,
1971 },
1972 },
1973 [C(ITLB)] = {
1974 [C(OP_READ)] = {
1975 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
1976 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
1977 },
1978 [C(OP_WRITE)] = {
1979 [C(RESULT_ACCESS)] = -1,
1980 [C(RESULT_MISS)] = -1,
1981 },
1982 [C(OP_PREFETCH)] = {
1983 [C(RESULT_ACCESS)] = -1,
1984 [C(RESULT_MISS)] = -1,
1985 },
1986 },
1987 [C(BPU)] = {
1988 [C(OP_READ)] = {
1989 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1990 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1991 },
1992 [C(OP_WRITE)] = {
1993 [C(RESULT_ACCESS)] = -1,
1994 [C(RESULT_MISS)] = -1,
1995 },
1996 [C(OP_PREFETCH)] = {
1997 [C(RESULT_ACCESS)] = -1,
1998 [C(RESULT_MISS)] = -1,
1999 },
2000 },
2001 };
2002
2003 static __initconst const u64 glm_hw_cache_extra_regs
2004 [PERF_COUNT_HW_CACHE_MAX]
2005 [PERF_COUNT_HW_CACHE_OP_MAX]
2006 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2007 [C(LL)] = {
2008 [C(OP_READ)] = {
2009 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
2010 GLM_LLC_ACCESS,
2011 [C(RESULT_MISS)] = GLM_DEMAND_READ|
2012 GLM_LLC_MISS,
2013 },
2014 [C(OP_WRITE)] = {
2015 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
2016 GLM_LLC_ACCESS,
2017 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
2018 GLM_LLC_MISS,
2019 },
2020 [C(OP_PREFETCH)] = {
2021 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH|
2022 GLM_LLC_ACCESS,
2023 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH|
2024 GLM_LLC_MISS,
2025 },
2026 },
2027 };
2028
2029 static __initconst const u64 glp_hw_cache_event_ids
2030 [PERF_COUNT_HW_CACHE_MAX]
2031 [PERF_COUNT_HW_CACHE_OP_MAX]
2032 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2033 [C(L1D)] = {
2034 [C(OP_READ)] = {
2035 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
2036 [C(RESULT_MISS)] = 0x0,
2037 },
2038 [C(OP_WRITE)] = {
2039 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
2040 [C(RESULT_MISS)] = 0x0,
2041 },
2042 [C(OP_PREFETCH)] = {
2043 [C(RESULT_ACCESS)] = 0x0,
2044 [C(RESULT_MISS)] = 0x0,
2045 },
2046 },
2047 [C(L1I)] = {
2048 [C(OP_READ)] = {
2049 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
2050 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
2051 },
2052 [C(OP_WRITE)] = {
2053 [C(RESULT_ACCESS)] = -1,
2054 [C(RESULT_MISS)] = -1,
2055 },
2056 [C(OP_PREFETCH)] = {
2057 [C(RESULT_ACCESS)] = 0x0,
2058 [C(RESULT_MISS)] = 0x0,
2059 },
2060 },
2061 [C(LL)] = {
2062 [C(OP_READ)] = {
2063 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
2064 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
2065 },
2066 [C(OP_WRITE)] = {
2067 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
2068 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
2069 },
2070 [C(OP_PREFETCH)] = {
2071 [C(RESULT_ACCESS)] = 0x0,
2072 [C(RESULT_MISS)] = 0x0,
2073 },
2074 },
2075 [C(DTLB)] = {
2076 [C(OP_READ)] = {
2077 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
2078 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
2079 },
2080 [C(OP_WRITE)] = {
2081 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
2082 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
2083 },
2084 [C(OP_PREFETCH)] = {
2085 [C(RESULT_ACCESS)] = 0x0,
2086 [C(RESULT_MISS)] = 0x0,
2087 },
2088 },
2089 [C(ITLB)] = {
2090 [C(OP_READ)] = {
2091 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
2092 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
2093 },
2094 [C(OP_WRITE)] = {
2095 [C(RESULT_ACCESS)] = -1,
2096 [C(RESULT_MISS)] = -1,
2097 },
2098 [C(OP_PREFETCH)] = {
2099 [C(RESULT_ACCESS)] = -1,
2100 [C(RESULT_MISS)] = -1,
2101 },
2102 },
2103 [C(BPU)] = {
2104 [C(OP_READ)] = {
2105 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
2106 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
2107 },
2108 [C(OP_WRITE)] = {
2109 [C(RESULT_ACCESS)] = -1,
2110 [C(RESULT_MISS)] = -1,
2111 },
2112 [C(OP_PREFETCH)] = {
2113 [C(RESULT_ACCESS)] = -1,
2114 [C(RESULT_MISS)] = -1,
2115 },
2116 },
2117 };
2118
2119 static __initconst const u64 glp_hw_cache_extra_regs
2120 [PERF_COUNT_HW_CACHE_MAX]
2121 [PERF_COUNT_HW_CACHE_OP_MAX]
2122 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2123 [C(LL)] = {
2124 [C(OP_READ)] = {
2125 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
2126 GLM_LLC_ACCESS,
2127 [C(RESULT_MISS)] = GLM_DEMAND_READ|
2128 GLM_LLC_MISS,
2129 },
2130 [C(OP_WRITE)] = {
2131 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
2132 GLM_LLC_ACCESS,
2133 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
2134 GLM_LLC_MISS,
2135 },
2136 [C(OP_PREFETCH)] = {
2137 [C(RESULT_ACCESS)] = 0x0,
2138 [C(RESULT_MISS)] = 0x0,
2139 },
2140 },
2141 };
2142
2143 #define TNT_LOCAL_DRAM BIT_ULL(26)
2144 #define TNT_DEMAND_READ GLM_DEMAND_DATA_RD
2145 #define TNT_DEMAND_WRITE GLM_DEMAND_RFO
2146 #define TNT_LLC_ACCESS GLM_ANY_RESPONSE
2147 #define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \
2148 SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM)
2149 #define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM)
2150
2151 static __initconst const u64 tnt_hw_cache_extra_regs
2152 [PERF_COUNT_HW_CACHE_MAX]
2153 [PERF_COUNT_HW_CACHE_OP_MAX]
2154 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2155 [C(LL)] = {
2156 [C(OP_READ)] = {
2157 [C(RESULT_ACCESS)] = TNT_DEMAND_READ|
2158 TNT_LLC_ACCESS,
2159 [C(RESULT_MISS)] = TNT_DEMAND_READ|
2160 TNT_LLC_MISS,
2161 },
2162 [C(OP_WRITE)] = {
2163 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE|
2164 TNT_LLC_ACCESS,
2165 [C(RESULT_MISS)] = TNT_DEMAND_WRITE|
2166 TNT_LLC_MISS,
2167 },
2168 [C(OP_PREFETCH)] = {
2169 [C(RESULT_ACCESS)] = 0x0,
2170 [C(RESULT_MISS)] = 0x0,
2171 },
2172 },
2173 };
2174
2175 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_tnt, "event=0x71,umask=0x0");
2176 EVENT_ATTR_STR(topdown-retiring, td_retiring_tnt, "event=0xc2,umask=0x0");
2177 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_tnt, "event=0x73,umask=0x6");
2178 EVENT_ATTR_STR(topdown-be-bound, td_be_bound_tnt, "event=0x74,umask=0x0");
2179
2180 static struct attribute *tnt_events_attrs[] = {
2181 EVENT_PTR(td_fe_bound_tnt),
2182 EVENT_PTR(td_retiring_tnt),
2183 EVENT_PTR(td_bad_spec_tnt),
2184 EVENT_PTR(td_be_bound_tnt),
2185 NULL,
2186 };
2187
2188 static struct extra_reg intel_tnt_extra_regs[] __read_mostly = {
2189 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2190 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0),
2191 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1),
2192 EVENT_EXTRA_END
2193 };
2194
2195 EVENT_ATTR_STR(mem-loads, mem_ld_grt, "event=0xd0,umask=0x5,ldlat=3");
2196 EVENT_ATTR_STR(mem-stores, mem_st_grt, "event=0xd0,umask=0x6");
2197
2198 static struct attribute *grt_mem_attrs[] = {
2199 EVENT_PTR(mem_ld_grt),
2200 EVENT_PTR(mem_st_grt),
2201 NULL
2202 };
2203
2204 static struct extra_reg intel_grt_extra_regs[] __read_mostly = {
2205 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2206 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
2207 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
2208 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0),
2209 EVENT_EXTRA_END
2210 };
2211
2212 EVENT_ATTR_STR(topdown-retiring, td_retiring_cmt, "event=0x72,umask=0x0");
2213 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_cmt, "event=0x73,umask=0x0");
2214
2215 static struct attribute *cmt_events_attrs[] = {
2216 EVENT_PTR(td_fe_bound_tnt),
2217 EVENT_PTR(td_retiring_cmt),
2218 EVENT_PTR(td_bad_spec_cmt),
2219 EVENT_PTR(td_be_bound_tnt),
2220 NULL
2221 };
2222
2223 static struct extra_reg intel_cmt_extra_regs[] __read_mostly = {
2224 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2225 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff3ffffffffffull, RSP_0),
2226 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff3ffffffffffull, RSP_1),
2227 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0),
2228 INTEL_UEVENT_EXTRA_REG(0x0127, MSR_SNOOP_RSP_0, 0xffffffffffffffffull, SNOOP_0),
2229 INTEL_UEVENT_EXTRA_REG(0x0227, MSR_SNOOP_RSP_1, 0xffffffffffffffffull, SNOOP_1),
2230 EVENT_EXTRA_END
2231 };
2232
2233 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */
2234 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */
2235 #define KNL_MCDRAM_LOCAL BIT_ULL(21)
2236 #define KNL_MCDRAM_FAR BIT_ULL(22)
2237 #define KNL_DDR_LOCAL BIT_ULL(23)
2238 #define KNL_DDR_FAR BIT_ULL(24)
2239 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \
2240 KNL_DDR_LOCAL | KNL_DDR_FAR)
2241 #define KNL_L2_READ SLM_DMND_READ
2242 #define KNL_L2_WRITE SLM_DMND_WRITE
2243 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH
2244 #define KNL_L2_ACCESS SLM_LLC_ACCESS
2245 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \
2246 KNL_DRAM_ANY | SNB_SNP_ANY | \
2247 SNB_NON_DRAM)
2248
2249 static __initconst const u64 knl_hw_cache_extra_regs
2250 [PERF_COUNT_HW_CACHE_MAX]
2251 [PERF_COUNT_HW_CACHE_OP_MAX]
2252 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2253 [C(LL)] = {
2254 [C(OP_READ)] = {
2255 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
2256 [C(RESULT_MISS)] = 0,
2257 },
2258 [C(OP_WRITE)] = {
2259 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
2260 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS,
2261 },
2262 [C(OP_PREFETCH)] = {
2263 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
2264 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS,
2265 },
2266 },
2267 };
2268
2269 /*
2270 * Used from PMIs where the LBRs are already disabled.
2271 *
2272 * This function could be called consecutively. It is required to remain in
2273 * disabled state if called consecutively.
2274 *
2275 * During consecutive calls, the same disable value will be written to related
2276 * registers, so the PMU state remains unchanged.
2277 *
2278 * intel_bts events don't coexist with intel PMU's BTS events because of
2279 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them
2280 * disabled around intel PMU's event batching etc, only inside the PMI handler.
2281 *
2282 * Avoid PEBS_ENABLE MSR access in PMIs.
2283 * The GLOBAL_CTRL has been disabled. All the counters do not count anymore.
2284 * It doesn't matter if the PEBS is enabled or not.
2285 * Usually, the PEBS status are not changed in PMIs. It's unnecessary to
2286 * access PEBS_ENABLE MSR in disable_all()/enable_all().
2287 * However, there are some cases which may change PEBS status, e.g. PMI
2288 * throttle. The PEBS_ENABLE should be updated where the status changes.
2289 */
__intel_pmu_disable_all(bool bts)2290 static __always_inline void __intel_pmu_disable_all(bool bts)
2291 {
2292 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2293
2294 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
2295
2296 if (bts && test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
2297 intel_pmu_disable_bts();
2298 }
2299
intel_pmu_disable_all(void)2300 static __always_inline void intel_pmu_disable_all(void)
2301 {
2302 __intel_pmu_disable_all(true);
2303 intel_pmu_pebs_disable_all();
2304 intel_pmu_lbr_disable_all();
2305 }
2306
__intel_pmu_enable_all(int added,bool pmi)2307 static void __intel_pmu_enable_all(int added, bool pmi)
2308 {
2309 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2310 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
2311
2312 intel_pmu_lbr_enable_all(pmi);
2313
2314 if (cpuc->fixed_ctrl_val != cpuc->active_fixed_ctrl_val) {
2315 wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, cpuc->fixed_ctrl_val);
2316 cpuc->active_fixed_ctrl_val = cpuc->fixed_ctrl_val;
2317 }
2318
2319 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
2320 intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
2321
2322 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
2323 struct perf_event *event =
2324 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
2325
2326 if (WARN_ON_ONCE(!event))
2327 return;
2328
2329 intel_pmu_enable_bts(event->hw.config);
2330 }
2331 }
2332
intel_pmu_enable_all(int added)2333 static void intel_pmu_enable_all(int added)
2334 {
2335 intel_pmu_pebs_enable_all();
2336 __intel_pmu_enable_all(added, false);
2337 }
2338
2339 static noinline int
__intel_pmu_snapshot_branch_stack(struct perf_branch_entry * entries,unsigned int cnt,unsigned long flags)2340 __intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries,
2341 unsigned int cnt, unsigned long flags)
2342 {
2343 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2344
2345 intel_pmu_lbr_read();
2346 cnt = min_t(unsigned int, cnt, x86_pmu.lbr_nr);
2347
2348 memcpy(entries, cpuc->lbr_entries, sizeof(struct perf_branch_entry) * cnt);
2349 intel_pmu_enable_all(0);
2350 local_irq_restore(flags);
2351 return cnt;
2352 }
2353
2354 static int
intel_pmu_snapshot_branch_stack(struct perf_branch_entry * entries,unsigned int cnt)2355 intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, unsigned int cnt)
2356 {
2357 unsigned long flags;
2358
2359 /* must not have branches... */
2360 local_irq_save(flags);
2361 __intel_pmu_disable_all(false); /* we don't care about BTS */
2362 __intel_pmu_lbr_disable();
2363 /* ... until here */
2364 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags);
2365 }
2366
2367 static int
intel_pmu_snapshot_arch_branch_stack(struct perf_branch_entry * entries,unsigned int cnt)2368 intel_pmu_snapshot_arch_branch_stack(struct perf_branch_entry *entries, unsigned int cnt)
2369 {
2370 unsigned long flags;
2371
2372 /* must not have branches... */
2373 local_irq_save(flags);
2374 __intel_pmu_disable_all(false); /* we don't care about BTS */
2375 __intel_pmu_arch_lbr_disable();
2376 /* ... until here */
2377 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags);
2378 }
2379
2380 /*
2381 * Workaround for:
2382 * Intel Errata AAK100 (model 26)
2383 * Intel Errata AAP53 (model 30)
2384 * Intel Errata BD53 (model 44)
2385 *
2386 * The official story:
2387 * These chips need to be 'reset' when adding counters by programming the
2388 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
2389 * in sequence on the same PMC or on different PMCs.
2390 *
2391 * In practice it appears some of these events do in fact count, and
2392 * we need to program all 4 events.
2393 */
intel_pmu_nhm_workaround(void)2394 static void intel_pmu_nhm_workaround(void)
2395 {
2396 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2397 static const unsigned long nhm_magic[4] = {
2398 0x4300B5,
2399 0x4300D2,
2400 0x4300B1,
2401 0x4300B1
2402 };
2403 struct perf_event *event;
2404 int i;
2405
2406 /*
2407 * The Errata requires below steps:
2408 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
2409 * 2) Configure 4 PERFEVTSELx with the magic events and clear
2410 * the corresponding PMCx;
2411 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
2412 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
2413 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
2414 */
2415
2416 /*
2417 * The real steps we choose are a little different from above.
2418 * A) To reduce MSR operations, we don't run step 1) as they
2419 * are already cleared before this function is called;
2420 * B) Call x86_perf_event_update to save PMCx before configuring
2421 * PERFEVTSELx with magic number;
2422 * C) With step 5), we do clear only when the PERFEVTSELx is
2423 * not used currently.
2424 * D) Call x86_perf_event_set_period to restore PMCx;
2425 */
2426
2427 /* We always operate 4 pairs of PERF Counters */
2428 for (i = 0; i < 4; i++) {
2429 event = cpuc->events[i];
2430 if (event)
2431 static_call(x86_pmu_update)(event);
2432 }
2433
2434 for (i = 0; i < 4; i++) {
2435 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
2436 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
2437 }
2438
2439 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
2440 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
2441
2442 for (i = 0; i < 4; i++) {
2443 event = cpuc->events[i];
2444
2445 if (event) {
2446 static_call(x86_pmu_set_period)(event);
2447 __x86_pmu_enable_event(&event->hw,
2448 ARCH_PERFMON_EVENTSEL_ENABLE);
2449 } else
2450 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
2451 }
2452 }
2453
intel_pmu_nhm_enable_all(int added)2454 static void intel_pmu_nhm_enable_all(int added)
2455 {
2456 if (added)
2457 intel_pmu_nhm_workaround();
2458 intel_pmu_enable_all(added);
2459 }
2460
intel_set_tfa(struct cpu_hw_events * cpuc,bool on)2461 static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on)
2462 {
2463 u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0;
2464
2465 if (cpuc->tfa_shadow != val) {
2466 cpuc->tfa_shadow = val;
2467 wrmsrl(MSR_TSX_FORCE_ABORT, val);
2468 }
2469 }
2470
intel_tfa_commit_scheduling(struct cpu_hw_events * cpuc,int idx,int cntr)2471 static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2472 {
2473 /*
2474 * We're going to use PMC3, make sure TFA is set before we touch it.
2475 */
2476 if (cntr == 3)
2477 intel_set_tfa(cpuc, true);
2478 }
2479
intel_tfa_pmu_enable_all(int added)2480 static void intel_tfa_pmu_enable_all(int added)
2481 {
2482 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2483
2484 /*
2485 * If we find PMC3 is no longer used when we enable the PMU, we can
2486 * clear TFA.
2487 */
2488 if (!test_bit(3, cpuc->active_mask))
2489 intel_set_tfa(cpuc, false);
2490
2491 intel_pmu_enable_all(added);
2492 }
2493
intel_pmu_get_status(void)2494 static inline u64 intel_pmu_get_status(void)
2495 {
2496 u64 status;
2497
2498 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
2499
2500 return status;
2501 }
2502
intel_pmu_ack_status(u64 ack)2503 static inline void intel_pmu_ack_status(u64 ack)
2504 {
2505 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
2506 }
2507
event_is_checkpointed(struct perf_event * event)2508 static inline bool event_is_checkpointed(struct perf_event *event)
2509 {
2510 return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
2511 }
2512
intel_set_masks(struct perf_event * event,int idx)2513 static inline void intel_set_masks(struct perf_event *event, int idx)
2514 {
2515 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2516
2517 if (event->attr.exclude_host)
2518 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
2519 if (event->attr.exclude_guest)
2520 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
2521 if (event_is_checkpointed(event))
2522 __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
2523 }
2524
intel_clear_masks(struct perf_event * event,int idx)2525 static inline void intel_clear_masks(struct perf_event *event, int idx)
2526 {
2527 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2528
2529 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
2530 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
2531 __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
2532 }
2533
intel_pmu_disable_fixed(struct perf_event * event)2534 static void intel_pmu_disable_fixed(struct perf_event *event)
2535 {
2536 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2537 struct hw_perf_event *hwc = &event->hw;
2538 int idx = hwc->idx;
2539 u64 mask;
2540
2541 if (is_topdown_idx(idx)) {
2542 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2543
2544 /*
2545 * When there are other active TopDown events,
2546 * don't disable the fixed counter 3.
2547 */
2548 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx))
2549 return;
2550 idx = INTEL_PMC_IDX_FIXED_SLOTS;
2551 }
2552
2553 intel_clear_masks(event, idx);
2554
2555 mask = intel_fixed_bits_by_idx(idx - INTEL_PMC_IDX_FIXED, INTEL_FIXED_BITS_MASK);
2556 cpuc->fixed_ctrl_val &= ~mask;
2557 }
2558
intel_pmu_disable_event(struct perf_event * event)2559 static void intel_pmu_disable_event(struct perf_event *event)
2560 {
2561 struct hw_perf_event *hwc = &event->hw;
2562 int idx = hwc->idx;
2563
2564 switch (idx) {
2565 case 0 ... INTEL_PMC_IDX_FIXED - 1:
2566 intel_clear_masks(event, idx);
2567 x86_pmu_disable_event(event);
2568 break;
2569 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
2570 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
2571 intel_pmu_disable_fixed(event);
2572 break;
2573 case INTEL_PMC_IDX_FIXED_BTS:
2574 intel_pmu_disable_bts();
2575 intel_pmu_drain_bts_buffer();
2576 return;
2577 case INTEL_PMC_IDX_FIXED_VLBR:
2578 intel_clear_masks(event, idx);
2579 break;
2580 default:
2581 intel_clear_masks(event, idx);
2582 pr_warn("Failed to disable the event with invalid index %d\n",
2583 idx);
2584 return;
2585 }
2586
2587 /*
2588 * Needs to be called after x86_pmu_disable_event,
2589 * so we don't trigger the event without PEBS bit set.
2590 */
2591 if (unlikely(event->attr.precise_ip))
2592 intel_pmu_pebs_disable(event);
2593 }
2594
intel_pmu_assign_event(struct perf_event * event,int idx)2595 static void intel_pmu_assign_event(struct perf_event *event, int idx)
2596 {
2597 if (is_pebs_pt(event))
2598 perf_report_aux_output_id(event, idx);
2599 }
2600
intel_pmu_needs_branch_stack(struct perf_event * event)2601 static __always_inline bool intel_pmu_needs_branch_stack(struct perf_event *event)
2602 {
2603 return event->hw.flags & PERF_X86_EVENT_NEEDS_BRANCH_STACK;
2604 }
2605
intel_pmu_del_event(struct perf_event * event)2606 static void intel_pmu_del_event(struct perf_event *event)
2607 {
2608 if (intel_pmu_needs_branch_stack(event))
2609 intel_pmu_lbr_del(event);
2610 if (event->attr.precise_ip)
2611 intel_pmu_pebs_del(event);
2612 }
2613
icl_set_topdown_event_period(struct perf_event * event)2614 static int icl_set_topdown_event_period(struct perf_event *event)
2615 {
2616 struct hw_perf_event *hwc = &event->hw;
2617 s64 left = local64_read(&hwc->period_left);
2618
2619 /*
2620 * The values in PERF_METRICS MSR are derived from fixed counter 3.
2621 * Software should start both registers, PERF_METRICS and fixed
2622 * counter 3, from zero.
2623 * Clear PERF_METRICS and Fixed counter 3 in initialization.
2624 * After that, both MSRs will be cleared for each read.
2625 * Don't need to clear them again.
2626 */
2627 if (left == x86_pmu.max_period) {
2628 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0);
2629 wrmsrl(MSR_PERF_METRICS, 0);
2630 hwc->saved_slots = 0;
2631 hwc->saved_metric = 0;
2632 }
2633
2634 if ((hwc->saved_slots) && is_slots_event(event)) {
2635 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots);
2636 wrmsrl(MSR_PERF_METRICS, hwc->saved_metric);
2637 }
2638
2639 perf_event_update_userpage(event);
2640
2641 return 0;
2642 }
2643
2644 DEFINE_STATIC_CALL(intel_pmu_set_topdown_event_period, x86_perf_event_set_period);
2645
icl_get_metrics_event_value(u64 metric,u64 slots,int idx)2646 static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx)
2647 {
2648 u32 val;
2649
2650 /*
2651 * The metric is reported as an 8bit integer fraction
2652 * summing up to 0xff.
2653 * slots-in-metric = (Metric / 0xff) * slots
2654 */
2655 val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff;
2656 return mul_u64_u32_div(slots, val, 0xff);
2657 }
2658
icl_get_topdown_value(struct perf_event * event,u64 slots,u64 metrics)2659 static u64 icl_get_topdown_value(struct perf_event *event,
2660 u64 slots, u64 metrics)
2661 {
2662 int idx = event->hw.idx;
2663 u64 delta;
2664
2665 if (is_metric_idx(idx))
2666 delta = icl_get_metrics_event_value(metrics, slots, idx);
2667 else
2668 delta = slots;
2669
2670 return delta;
2671 }
2672
__icl_update_topdown_event(struct perf_event * event,u64 slots,u64 metrics,u64 last_slots,u64 last_metrics)2673 static void __icl_update_topdown_event(struct perf_event *event,
2674 u64 slots, u64 metrics,
2675 u64 last_slots, u64 last_metrics)
2676 {
2677 u64 delta, last = 0;
2678
2679 delta = icl_get_topdown_value(event, slots, metrics);
2680 if (last_slots)
2681 last = icl_get_topdown_value(event, last_slots, last_metrics);
2682
2683 /*
2684 * The 8bit integer fraction of metric may be not accurate,
2685 * especially when the changes is very small.
2686 * For example, if only a few bad_spec happens, the fraction
2687 * may be reduced from 1 to 0. If so, the bad_spec event value
2688 * will be 0 which is definitely less than the last value.
2689 * Avoid update event->count for this case.
2690 */
2691 if (delta > last) {
2692 delta -= last;
2693 local64_add(delta, &event->count);
2694 }
2695 }
2696
update_saved_topdown_regs(struct perf_event * event,u64 slots,u64 metrics,int metric_end)2697 static void update_saved_topdown_regs(struct perf_event *event, u64 slots,
2698 u64 metrics, int metric_end)
2699 {
2700 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2701 struct perf_event *other;
2702 int idx;
2703
2704 event->hw.saved_slots = slots;
2705 event->hw.saved_metric = metrics;
2706
2707 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) {
2708 if (!is_topdown_idx(idx))
2709 continue;
2710 other = cpuc->events[idx];
2711 other->hw.saved_slots = slots;
2712 other->hw.saved_metric = metrics;
2713 }
2714 }
2715
2716 /*
2717 * Update all active Topdown events.
2718 *
2719 * The PERF_METRICS and Fixed counter 3 are read separately. The values may be
2720 * modify by a NMI. PMU has to be disabled before calling this function.
2721 */
2722
intel_update_topdown_event(struct perf_event * event,int metric_end)2723 static u64 intel_update_topdown_event(struct perf_event *event, int metric_end)
2724 {
2725 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2726 struct perf_event *other;
2727 u64 slots, metrics;
2728 bool reset = true;
2729 int idx;
2730
2731 /* read Fixed counter 3 */
2732 rdpmcl((3 | INTEL_PMC_FIXED_RDPMC_BASE), slots);
2733 if (!slots)
2734 return 0;
2735
2736 /* read PERF_METRICS */
2737 rdpmcl(INTEL_PMC_FIXED_RDPMC_METRICS, metrics);
2738
2739 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) {
2740 if (!is_topdown_idx(idx))
2741 continue;
2742 other = cpuc->events[idx];
2743 __icl_update_topdown_event(other, slots, metrics,
2744 event ? event->hw.saved_slots : 0,
2745 event ? event->hw.saved_metric : 0);
2746 }
2747
2748 /*
2749 * Check and update this event, which may have been cleared
2750 * in active_mask e.g. x86_pmu_stop()
2751 */
2752 if (event && !test_bit(event->hw.idx, cpuc->active_mask)) {
2753 __icl_update_topdown_event(event, slots, metrics,
2754 event->hw.saved_slots,
2755 event->hw.saved_metric);
2756
2757 /*
2758 * In x86_pmu_stop(), the event is cleared in active_mask first,
2759 * then drain the delta, which indicates context switch for
2760 * counting.
2761 * Save metric and slots for context switch.
2762 * Don't need to reset the PERF_METRICS and Fixed counter 3.
2763 * Because the values will be restored in next schedule in.
2764 */
2765 update_saved_topdown_regs(event, slots, metrics, metric_end);
2766 reset = false;
2767 }
2768
2769 if (reset) {
2770 /* The fixed counter 3 has to be written before the PERF_METRICS. */
2771 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0);
2772 wrmsrl(MSR_PERF_METRICS, 0);
2773 if (event)
2774 update_saved_topdown_regs(event, 0, 0, metric_end);
2775 }
2776
2777 return slots;
2778 }
2779
icl_update_topdown_event(struct perf_event * event)2780 static u64 icl_update_topdown_event(struct perf_event *event)
2781 {
2782 return intel_update_topdown_event(event, INTEL_PMC_IDX_METRIC_BASE +
2783 x86_pmu.num_topdown_events - 1);
2784 }
2785
2786 DEFINE_STATIC_CALL(intel_pmu_update_topdown_event, x86_perf_event_update);
2787
intel_pmu_read_topdown_event(struct perf_event * event)2788 static void intel_pmu_read_topdown_event(struct perf_event *event)
2789 {
2790 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2791
2792 /* Only need to call update_topdown_event() once for group read. */
2793 if ((cpuc->txn_flags & PERF_PMU_TXN_READ) &&
2794 !is_slots_event(event))
2795 return;
2796
2797 perf_pmu_disable(event->pmu);
2798 static_call(intel_pmu_update_topdown_event)(event);
2799 perf_pmu_enable(event->pmu);
2800 }
2801
intel_pmu_read_event(struct perf_event * event)2802 static void intel_pmu_read_event(struct perf_event *event)
2803 {
2804 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
2805 intel_pmu_auto_reload_read(event);
2806 else if (is_topdown_count(event))
2807 intel_pmu_read_topdown_event(event);
2808 else
2809 x86_perf_event_update(event);
2810 }
2811
intel_pmu_enable_fixed(struct perf_event * event)2812 static void intel_pmu_enable_fixed(struct perf_event *event)
2813 {
2814 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2815 struct hw_perf_event *hwc = &event->hw;
2816 u64 mask, bits = 0;
2817 int idx = hwc->idx;
2818
2819 if (is_topdown_idx(idx)) {
2820 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2821 /*
2822 * When there are other active TopDown events,
2823 * don't enable the fixed counter 3 again.
2824 */
2825 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx))
2826 return;
2827
2828 idx = INTEL_PMC_IDX_FIXED_SLOTS;
2829
2830 if (event->attr.config1 & INTEL_TD_CFG_METRIC_CLEAR)
2831 bits |= INTEL_FIXED_3_METRICS_CLEAR;
2832 }
2833
2834 intel_set_masks(event, idx);
2835
2836 /*
2837 * Enable IRQ generation (0x8), if not PEBS,
2838 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
2839 * if requested:
2840 */
2841 if (!event->attr.precise_ip)
2842 bits |= INTEL_FIXED_0_ENABLE_PMI;
2843 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
2844 bits |= INTEL_FIXED_0_USER;
2845 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
2846 bits |= INTEL_FIXED_0_KERNEL;
2847
2848 /*
2849 * ANY bit is supported in v3 and up
2850 */
2851 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
2852 bits |= INTEL_FIXED_0_ANYTHREAD;
2853
2854 idx -= INTEL_PMC_IDX_FIXED;
2855 bits = intel_fixed_bits_by_idx(idx, bits);
2856 mask = intel_fixed_bits_by_idx(idx, INTEL_FIXED_BITS_MASK);
2857
2858 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) {
2859 bits |= intel_fixed_bits_by_idx(idx, ICL_FIXED_0_ADAPTIVE);
2860 mask |= intel_fixed_bits_by_idx(idx, ICL_FIXED_0_ADAPTIVE);
2861 }
2862
2863 cpuc->fixed_ctrl_val &= ~mask;
2864 cpuc->fixed_ctrl_val |= bits;
2865 }
2866
intel_pmu_enable_event(struct perf_event * event)2867 static void intel_pmu_enable_event(struct perf_event *event)
2868 {
2869 u64 enable_mask = ARCH_PERFMON_EVENTSEL_ENABLE;
2870 struct hw_perf_event *hwc = &event->hw;
2871 int idx = hwc->idx;
2872
2873 if (unlikely(event->attr.precise_ip))
2874 intel_pmu_pebs_enable(event);
2875
2876 switch (idx) {
2877 case 0 ... INTEL_PMC_IDX_FIXED - 1:
2878 if (branch_sample_counters(event))
2879 enable_mask |= ARCH_PERFMON_EVENTSEL_BR_CNTR;
2880 intel_set_masks(event, idx);
2881 __x86_pmu_enable_event(hwc, enable_mask);
2882 break;
2883 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
2884 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
2885 intel_pmu_enable_fixed(event);
2886 break;
2887 case INTEL_PMC_IDX_FIXED_BTS:
2888 if (!__this_cpu_read(cpu_hw_events.enabled))
2889 return;
2890 intel_pmu_enable_bts(hwc->config);
2891 break;
2892 case INTEL_PMC_IDX_FIXED_VLBR:
2893 intel_set_masks(event, idx);
2894 break;
2895 default:
2896 pr_warn("Failed to enable the event with invalid index %d\n",
2897 idx);
2898 }
2899 }
2900
intel_pmu_add_event(struct perf_event * event)2901 static void intel_pmu_add_event(struct perf_event *event)
2902 {
2903 if (event->attr.precise_ip)
2904 intel_pmu_pebs_add(event);
2905 if (intel_pmu_needs_branch_stack(event))
2906 intel_pmu_lbr_add(event);
2907 }
2908
2909 /*
2910 * Save and restart an expired event. Called by NMI contexts,
2911 * so it has to be careful about preempting normal event ops:
2912 */
intel_pmu_save_and_restart(struct perf_event * event)2913 int intel_pmu_save_and_restart(struct perf_event *event)
2914 {
2915 static_call(x86_pmu_update)(event);
2916 /*
2917 * For a checkpointed counter always reset back to 0. This
2918 * avoids a situation where the counter overflows, aborts the
2919 * transaction and is then set back to shortly before the
2920 * overflow, and overflows and aborts again.
2921 */
2922 if (unlikely(event_is_checkpointed(event))) {
2923 /* No race with NMIs because the counter should not be armed */
2924 wrmsrl(event->hw.event_base, 0);
2925 local64_set(&event->hw.prev_count, 0);
2926 }
2927 return static_call(x86_pmu_set_period)(event);
2928 }
2929
intel_pmu_set_period(struct perf_event * event)2930 static int intel_pmu_set_period(struct perf_event *event)
2931 {
2932 if (unlikely(is_topdown_count(event)))
2933 return static_call(intel_pmu_set_topdown_event_period)(event);
2934
2935 return x86_perf_event_set_period(event);
2936 }
2937
intel_pmu_update(struct perf_event * event)2938 static u64 intel_pmu_update(struct perf_event *event)
2939 {
2940 if (unlikely(is_topdown_count(event)))
2941 return static_call(intel_pmu_update_topdown_event)(event);
2942
2943 return x86_perf_event_update(event);
2944 }
2945
intel_pmu_reset(void)2946 static void intel_pmu_reset(void)
2947 {
2948 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
2949 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2950 unsigned long *cntr_mask = hybrid(cpuc->pmu, cntr_mask);
2951 unsigned long *fixed_cntr_mask = hybrid(cpuc->pmu, fixed_cntr_mask);
2952 unsigned long flags;
2953 int idx;
2954
2955 if (!*(u64 *)cntr_mask)
2956 return;
2957
2958 local_irq_save(flags);
2959
2960 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
2961
2962 for_each_set_bit(idx, cntr_mask, INTEL_PMC_MAX_GENERIC) {
2963 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
2964 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
2965 }
2966 for_each_set_bit(idx, fixed_cntr_mask, INTEL_PMC_MAX_FIXED) {
2967 if (fixed_counter_disabled(idx, cpuc->pmu))
2968 continue;
2969 wrmsrl_safe(x86_pmu_fixed_ctr_addr(idx), 0ull);
2970 }
2971
2972 if (ds)
2973 ds->bts_index = ds->bts_buffer_base;
2974
2975 /* Ack all overflows and disable fixed counters */
2976 if (x86_pmu.version >= 2) {
2977 intel_pmu_ack_status(intel_pmu_get_status());
2978 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
2979 }
2980
2981 /* Reset LBRs and LBR freezing */
2982 if (x86_pmu.lbr_nr) {
2983 update_debugctlmsr(get_debugctlmsr() &
2984 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR));
2985 }
2986
2987 local_irq_restore(flags);
2988 }
2989
2990 /*
2991 * We may be running with guest PEBS events created by KVM, and the
2992 * PEBS records are logged into the guest's DS and invisible to host.
2993 *
2994 * In the case of guest PEBS overflow, we only trigger a fake event
2995 * to emulate the PEBS overflow PMI for guest PEBS counters in KVM.
2996 * The guest will then vm-entry and check the guest DS area to read
2997 * the guest PEBS records.
2998 *
2999 * The contents and other behavior of the guest event do not matter.
3000 */
x86_pmu_handle_guest_pebs(struct pt_regs * regs,struct perf_sample_data * data)3001 static void x86_pmu_handle_guest_pebs(struct pt_regs *regs,
3002 struct perf_sample_data *data)
3003 {
3004 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3005 u64 guest_pebs_idxs = cpuc->pebs_enabled & ~cpuc->intel_ctrl_host_mask;
3006 struct perf_event *event = NULL;
3007 int bit;
3008
3009 if (!unlikely(perf_guest_state()))
3010 return;
3011
3012 if (!x86_pmu.pebs_ept || !x86_pmu.pebs_active ||
3013 !guest_pebs_idxs)
3014 return;
3015
3016 for_each_set_bit(bit, (unsigned long *)&guest_pebs_idxs, X86_PMC_IDX_MAX) {
3017 event = cpuc->events[bit];
3018 if (!event->attr.precise_ip)
3019 continue;
3020
3021 perf_sample_data_init(data, 0, event->hw.last_period);
3022 if (perf_event_overflow(event, data, regs))
3023 x86_pmu_stop(event, 0);
3024
3025 /* Inject one fake event is enough. */
3026 break;
3027 }
3028 }
3029
handle_pmi_common(struct pt_regs * regs,u64 status)3030 static int handle_pmi_common(struct pt_regs *regs, u64 status)
3031 {
3032 struct perf_sample_data data;
3033 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3034 int bit;
3035 int handled = 0;
3036 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
3037
3038 inc_irq_stat(apic_perf_irqs);
3039
3040 /*
3041 * Ignore a range of extra bits in status that do not indicate
3042 * overflow by themselves.
3043 */
3044 status &= ~(GLOBAL_STATUS_COND_CHG |
3045 GLOBAL_STATUS_ASIF |
3046 GLOBAL_STATUS_LBRS_FROZEN);
3047 if (!status)
3048 return 0;
3049 /*
3050 * In case multiple PEBS events are sampled at the same time,
3051 * it is possible to have GLOBAL_STATUS bit 62 set indicating
3052 * PEBS buffer overflow and also seeing at most 3 PEBS counters
3053 * having their bits set in the status register. This is a sign
3054 * that there was at least one PEBS record pending at the time
3055 * of the PMU interrupt. PEBS counters must only be processed
3056 * via the drain_pebs() calls and not via the regular sample
3057 * processing loop coming after that the function, otherwise
3058 * phony regular samples may be generated in the sampling buffer
3059 * not marked with the EXACT tag. Another possibility is to have
3060 * one PEBS event and at least one non-PEBS event which overflows
3061 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will
3062 * not be set, yet the overflow status bit for the PEBS counter will
3063 * be on Skylake.
3064 *
3065 * To avoid this problem, we systematically ignore the PEBS-enabled
3066 * counters from the GLOBAL_STATUS mask and we always process PEBS
3067 * events via drain_pebs().
3068 */
3069 status &= ~(cpuc->pebs_enabled & x86_pmu.pebs_capable);
3070
3071 /*
3072 * PEBS overflow sets bit 62 in the global status register
3073 */
3074 if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) {
3075 u64 pebs_enabled = cpuc->pebs_enabled;
3076
3077 handled++;
3078 x86_pmu_handle_guest_pebs(regs, &data);
3079 x86_pmu.drain_pebs(regs, &data);
3080 status &= intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI;
3081
3082 /*
3083 * PMI throttle may be triggered, which stops the PEBS event.
3084 * Although cpuc->pebs_enabled is updated accordingly, the
3085 * MSR_IA32_PEBS_ENABLE is not updated. Because the
3086 * cpuc->enabled has been forced to 0 in PMI.
3087 * Update the MSR if pebs_enabled is changed.
3088 */
3089 if (pebs_enabled != cpuc->pebs_enabled)
3090 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
3091 }
3092
3093 /*
3094 * Intel PT
3095 */
3096 if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) {
3097 handled++;
3098 if (!perf_guest_handle_intel_pt_intr())
3099 intel_pt_interrupt();
3100 }
3101
3102 /*
3103 * Intel Perf metrics
3104 */
3105 if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) {
3106 handled++;
3107 static_call(intel_pmu_update_topdown_event)(NULL);
3108 }
3109
3110 /*
3111 * Checkpointed counters can lead to 'spurious' PMIs because the
3112 * rollback caused by the PMI will have cleared the overflow status
3113 * bit. Therefore always force probe these counters.
3114 */
3115 status |= cpuc->intel_cp_status;
3116
3117 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
3118 struct perf_event *event = cpuc->events[bit];
3119
3120 handled++;
3121
3122 if (!test_bit(bit, cpuc->active_mask))
3123 continue;
3124
3125 if (!intel_pmu_save_and_restart(event))
3126 continue;
3127
3128 perf_sample_data_init(&data, 0, event->hw.last_period);
3129
3130 if (has_branch_stack(event))
3131 intel_pmu_lbr_save_brstack(&data, cpuc, event);
3132
3133 if (perf_event_overflow(event, &data, regs))
3134 x86_pmu_stop(event, 0);
3135 }
3136
3137 return handled;
3138 }
3139
3140 /*
3141 * This handler is triggered by the local APIC, so the APIC IRQ handling
3142 * rules apply:
3143 */
intel_pmu_handle_irq(struct pt_regs * regs)3144 static int intel_pmu_handle_irq(struct pt_regs *regs)
3145 {
3146 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3147 bool late_ack = hybrid_bit(cpuc->pmu, late_ack);
3148 bool mid_ack = hybrid_bit(cpuc->pmu, mid_ack);
3149 int loops;
3150 u64 status;
3151 int handled;
3152 int pmu_enabled;
3153
3154 /*
3155 * Save the PMU state.
3156 * It needs to be restored when leaving the handler.
3157 */
3158 pmu_enabled = cpuc->enabled;
3159 /*
3160 * In general, the early ACK is only applied for old platforms.
3161 * For the big core starts from Haswell, the late ACK should be
3162 * applied.
3163 * For the small core after Tremont, we have to do the ACK right
3164 * before re-enabling counters, which is in the middle of the
3165 * NMI handler.
3166 */
3167 if (!late_ack && !mid_ack)
3168 apic_write(APIC_LVTPC, APIC_DM_NMI);
3169 intel_bts_disable_local();
3170 cpuc->enabled = 0;
3171 __intel_pmu_disable_all(true);
3172 handled = intel_pmu_drain_bts_buffer();
3173 handled += intel_bts_interrupt();
3174 status = intel_pmu_get_status();
3175 if (!status)
3176 goto done;
3177
3178 loops = 0;
3179 again:
3180 intel_pmu_lbr_read();
3181 intel_pmu_ack_status(status);
3182 if (++loops > 100) {
3183 static bool warned;
3184
3185 if (!warned) {
3186 WARN(1, "perfevents: irq loop stuck!\n");
3187 perf_event_print_debug();
3188 warned = true;
3189 }
3190 intel_pmu_reset();
3191 goto done;
3192 }
3193
3194 handled += handle_pmi_common(regs, status);
3195
3196 /*
3197 * Repeat if there is more work to be done:
3198 */
3199 status = intel_pmu_get_status();
3200 if (status)
3201 goto again;
3202
3203 done:
3204 if (mid_ack)
3205 apic_write(APIC_LVTPC, APIC_DM_NMI);
3206 /* Only restore PMU state when it's active. See x86_pmu_disable(). */
3207 cpuc->enabled = pmu_enabled;
3208 if (pmu_enabled)
3209 __intel_pmu_enable_all(0, true);
3210 intel_bts_enable_local();
3211
3212 /*
3213 * Only unmask the NMI after the overflow counters
3214 * have been reset. This avoids spurious NMIs on
3215 * Haswell CPUs.
3216 */
3217 if (late_ack)
3218 apic_write(APIC_LVTPC, APIC_DM_NMI);
3219 return handled;
3220 }
3221
3222 static struct event_constraint *
intel_bts_constraints(struct perf_event * event)3223 intel_bts_constraints(struct perf_event *event)
3224 {
3225 if (unlikely(intel_pmu_has_bts(event)))
3226 return &bts_constraint;
3227
3228 return NULL;
3229 }
3230
3231 /*
3232 * Note: matches a fake event, like Fixed2.
3233 */
3234 static struct event_constraint *
intel_vlbr_constraints(struct perf_event * event)3235 intel_vlbr_constraints(struct perf_event *event)
3236 {
3237 struct event_constraint *c = &vlbr_constraint;
3238
3239 if (unlikely(constraint_match(c, event->hw.config))) {
3240 event->hw.flags |= c->flags;
3241 return c;
3242 }
3243
3244 return NULL;
3245 }
3246
intel_alt_er(struct cpu_hw_events * cpuc,int idx,u64 config)3247 static int intel_alt_er(struct cpu_hw_events *cpuc,
3248 int idx, u64 config)
3249 {
3250 struct extra_reg *extra_regs = hybrid(cpuc->pmu, extra_regs);
3251 int alt_idx = idx;
3252
3253 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
3254 return idx;
3255
3256 if (idx == EXTRA_REG_RSP_0)
3257 alt_idx = EXTRA_REG_RSP_1;
3258
3259 if (idx == EXTRA_REG_RSP_1)
3260 alt_idx = EXTRA_REG_RSP_0;
3261
3262 if (config & ~extra_regs[alt_idx].valid_mask)
3263 return idx;
3264
3265 return alt_idx;
3266 }
3267
intel_fixup_er(struct perf_event * event,int idx)3268 static void intel_fixup_er(struct perf_event *event, int idx)
3269 {
3270 struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs);
3271 event->hw.extra_reg.idx = idx;
3272
3273 if (idx == EXTRA_REG_RSP_0) {
3274 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
3275 event->hw.config |= extra_regs[EXTRA_REG_RSP_0].event;
3276 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
3277 } else if (idx == EXTRA_REG_RSP_1) {
3278 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
3279 event->hw.config |= extra_regs[EXTRA_REG_RSP_1].event;
3280 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
3281 }
3282 }
3283
3284 /*
3285 * manage allocation of shared extra msr for certain events
3286 *
3287 * sharing can be:
3288 * per-cpu: to be shared between the various events on a single PMU
3289 * per-core: per-cpu + shared by HT threads
3290 */
3291 static struct event_constraint *
__intel_shared_reg_get_constraints(struct cpu_hw_events * cpuc,struct perf_event * event,struct hw_perf_event_extra * reg)3292 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
3293 struct perf_event *event,
3294 struct hw_perf_event_extra *reg)
3295 {
3296 struct event_constraint *c = &emptyconstraint;
3297 struct er_account *era;
3298 unsigned long flags;
3299 int idx = reg->idx;
3300
3301 /*
3302 * reg->alloc can be set due to existing state, so for fake cpuc we
3303 * need to ignore this, otherwise we might fail to allocate proper fake
3304 * state for this extra reg constraint. Also see the comment below.
3305 */
3306 if (reg->alloc && !cpuc->is_fake)
3307 return NULL; /* call x86_get_event_constraint() */
3308
3309 again:
3310 era = &cpuc->shared_regs->regs[idx];
3311 /*
3312 * we use spin_lock_irqsave() to avoid lockdep issues when
3313 * passing a fake cpuc
3314 */
3315 raw_spin_lock_irqsave(&era->lock, flags);
3316
3317 if (!atomic_read(&era->ref) || era->config == reg->config) {
3318
3319 /*
3320 * If its a fake cpuc -- as per validate_{group,event}() we
3321 * shouldn't touch event state and we can avoid doing so
3322 * since both will only call get_event_constraints() once
3323 * on each event, this avoids the need for reg->alloc.
3324 *
3325 * Not doing the ER fixup will only result in era->reg being
3326 * wrong, but since we won't actually try and program hardware
3327 * this isn't a problem either.
3328 */
3329 if (!cpuc->is_fake) {
3330 if (idx != reg->idx)
3331 intel_fixup_er(event, idx);
3332
3333 /*
3334 * x86_schedule_events() can call get_event_constraints()
3335 * multiple times on events in the case of incremental
3336 * scheduling(). reg->alloc ensures we only do the ER
3337 * allocation once.
3338 */
3339 reg->alloc = 1;
3340 }
3341
3342 /* lock in msr value */
3343 era->config = reg->config;
3344 era->reg = reg->reg;
3345
3346 /* one more user */
3347 atomic_inc(&era->ref);
3348
3349 /*
3350 * need to call x86_get_event_constraint()
3351 * to check if associated event has constraints
3352 */
3353 c = NULL;
3354 } else {
3355 idx = intel_alt_er(cpuc, idx, reg->config);
3356 if (idx != reg->idx) {
3357 raw_spin_unlock_irqrestore(&era->lock, flags);
3358 goto again;
3359 }
3360 }
3361 raw_spin_unlock_irqrestore(&era->lock, flags);
3362
3363 return c;
3364 }
3365
3366 static void
__intel_shared_reg_put_constraints(struct cpu_hw_events * cpuc,struct hw_perf_event_extra * reg)3367 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
3368 struct hw_perf_event_extra *reg)
3369 {
3370 struct er_account *era;
3371
3372 /*
3373 * Only put constraint if extra reg was actually allocated. Also takes
3374 * care of event which do not use an extra shared reg.
3375 *
3376 * Also, if this is a fake cpuc we shouldn't touch any event state
3377 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
3378 * either since it'll be thrown out.
3379 */
3380 if (!reg->alloc || cpuc->is_fake)
3381 return;
3382
3383 era = &cpuc->shared_regs->regs[reg->idx];
3384
3385 /* one fewer user */
3386 atomic_dec(&era->ref);
3387
3388 /* allocate again next time */
3389 reg->alloc = 0;
3390 }
3391
3392 static struct event_constraint *
intel_shared_regs_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)3393 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
3394 struct perf_event *event)
3395 {
3396 struct event_constraint *c = NULL, *d;
3397 struct hw_perf_event_extra *xreg, *breg;
3398
3399 xreg = &event->hw.extra_reg;
3400 if (xreg->idx != EXTRA_REG_NONE) {
3401 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
3402 if (c == &emptyconstraint)
3403 return c;
3404 }
3405 breg = &event->hw.branch_reg;
3406 if (breg->idx != EXTRA_REG_NONE) {
3407 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
3408 if (d == &emptyconstraint) {
3409 __intel_shared_reg_put_constraints(cpuc, xreg);
3410 c = d;
3411 }
3412 }
3413 return c;
3414 }
3415
3416 struct event_constraint *
x86_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)3417 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3418 struct perf_event *event)
3419 {
3420 struct event_constraint *event_constraints = hybrid(cpuc->pmu, event_constraints);
3421 struct event_constraint *c;
3422
3423 if (event_constraints) {
3424 for_each_event_constraint(c, event_constraints) {
3425 if (constraint_match(c, event->hw.config)) {
3426 event->hw.flags |= c->flags;
3427 return c;
3428 }
3429 }
3430 }
3431
3432 return &hybrid_var(cpuc->pmu, unconstrained);
3433 }
3434
3435 static struct event_constraint *
__intel_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)3436 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3437 struct perf_event *event)
3438 {
3439 struct event_constraint *c;
3440
3441 c = intel_vlbr_constraints(event);
3442 if (c)
3443 return c;
3444
3445 c = intel_bts_constraints(event);
3446 if (c)
3447 return c;
3448
3449 c = intel_shared_regs_constraints(cpuc, event);
3450 if (c)
3451 return c;
3452
3453 c = intel_pebs_constraints(event);
3454 if (c)
3455 return c;
3456
3457 return x86_get_event_constraints(cpuc, idx, event);
3458 }
3459
3460 static void
intel_start_scheduling(struct cpu_hw_events * cpuc)3461 intel_start_scheduling(struct cpu_hw_events *cpuc)
3462 {
3463 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3464 struct intel_excl_states *xl;
3465 int tid = cpuc->excl_thread_id;
3466
3467 /*
3468 * nothing needed if in group validation mode
3469 */
3470 if (cpuc->is_fake || !is_ht_workaround_enabled())
3471 return;
3472
3473 /*
3474 * no exclusion needed
3475 */
3476 if (WARN_ON_ONCE(!excl_cntrs))
3477 return;
3478
3479 xl = &excl_cntrs->states[tid];
3480
3481 xl->sched_started = true;
3482 /*
3483 * lock shared state until we are done scheduling
3484 * in stop_event_scheduling()
3485 * makes scheduling appear as a transaction
3486 */
3487 raw_spin_lock(&excl_cntrs->lock);
3488 }
3489
intel_commit_scheduling(struct cpu_hw_events * cpuc,int idx,int cntr)3490 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
3491 {
3492 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3493 struct event_constraint *c = cpuc->event_constraint[idx];
3494 struct intel_excl_states *xl;
3495 int tid = cpuc->excl_thread_id;
3496
3497 if (cpuc->is_fake || !is_ht_workaround_enabled())
3498 return;
3499
3500 if (WARN_ON_ONCE(!excl_cntrs))
3501 return;
3502
3503 if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
3504 return;
3505
3506 xl = &excl_cntrs->states[tid];
3507
3508 lockdep_assert_held(&excl_cntrs->lock);
3509
3510 if (c->flags & PERF_X86_EVENT_EXCL)
3511 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE;
3512 else
3513 xl->state[cntr] = INTEL_EXCL_SHARED;
3514 }
3515
3516 static void
intel_stop_scheduling(struct cpu_hw_events * cpuc)3517 intel_stop_scheduling(struct cpu_hw_events *cpuc)
3518 {
3519 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3520 struct intel_excl_states *xl;
3521 int tid = cpuc->excl_thread_id;
3522
3523 /*
3524 * nothing needed if in group validation mode
3525 */
3526 if (cpuc->is_fake || !is_ht_workaround_enabled())
3527 return;
3528 /*
3529 * no exclusion needed
3530 */
3531 if (WARN_ON_ONCE(!excl_cntrs))
3532 return;
3533
3534 xl = &excl_cntrs->states[tid];
3535
3536 xl->sched_started = false;
3537 /*
3538 * release shared state lock (acquired in intel_start_scheduling())
3539 */
3540 raw_spin_unlock(&excl_cntrs->lock);
3541 }
3542
3543 static struct event_constraint *
dyn_constraint(struct cpu_hw_events * cpuc,struct event_constraint * c,int idx)3544 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx)
3545 {
3546 WARN_ON_ONCE(!cpuc->constraint_list);
3547
3548 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
3549 struct event_constraint *cx;
3550
3551 /*
3552 * grab pre-allocated constraint entry
3553 */
3554 cx = &cpuc->constraint_list[idx];
3555
3556 /*
3557 * initialize dynamic constraint
3558 * with static constraint
3559 */
3560 *cx = *c;
3561
3562 /*
3563 * mark constraint as dynamic
3564 */
3565 cx->flags |= PERF_X86_EVENT_DYNAMIC;
3566 c = cx;
3567 }
3568
3569 return c;
3570 }
3571
3572 static struct event_constraint *
intel_get_excl_constraints(struct cpu_hw_events * cpuc,struct perf_event * event,int idx,struct event_constraint * c)3573 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
3574 int idx, struct event_constraint *c)
3575 {
3576 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3577 struct intel_excl_states *xlo;
3578 int tid = cpuc->excl_thread_id;
3579 int is_excl, i, w;
3580
3581 /*
3582 * validating a group does not require
3583 * enforcing cross-thread exclusion
3584 */
3585 if (cpuc->is_fake || !is_ht_workaround_enabled())
3586 return c;
3587
3588 /*
3589 * no exclusion needed
3590 */
3591 if (WARN_ON_ONCE(!excl_cntrs))
3592 return c;
3593
3594 /*
3595 * because we modify the constraint, we need
3596 * to make a copy. Static constraints come
3597 * from static const tables.
3598 *
3599 * only needed when constraint has not yet
3600 * been cloned (marked dynamic)
3601 */
3602 c = dyn_constraint(cpuc, c, idx);
3603
3604 /*
3605 * From here on, the constraint is dynamic.
3606 * Either it was just allocated above, or it
3607 * was allocated during a earlier invocation
3608 * of this function
3609 */
3610
3611 /*
3612 * state of sibling HT
3613 */
3614 xlo = &excl_cntrs->states[tid ^ 1];
3615
3616 /*
3617 * event requires exclusive counter access
3618 * across HT threads
3619 */
3620 is_excl = c->flags & PERF_X86_EVENT_EXCL;
3621 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) {
3622 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT;
3623 if (!cpuc->n_excl++)
3624 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1);
3625 }
3626
3627 /*
3628 * Modify static constraint with current dynamic
3629 * state of thread
3630 *
3631 * EXCLUSIVE: sibling counter measuring exclusive event
3632 * SHARED : sibling counter measuring non-exclusive event
3633 * UNUSED : sibling counter unused
3634 */
3635 w = c->weight;
3636 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {
3637 /*
3638 * exclusive event in sibling counter
3639 * our corresponding counter cannot be used
3640 * regardless of our event
3641 */
3642 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) {
3643 __clear_bit(i, c->idxmsk);
3644 w--;
3645 continue;
3646 }
3647 /*
3648 * if measuring an exclusive event, sibling
3649 * measuring non-exclusive, then counter cannot
3650 * be used
3651 */
3652 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) {
3653 __clear_bit(i, c->idxmsk);
3654 w--;
3655 continue;
3656 }
3657 }
3658
3659 /*
3660 * if we return an empty mask, then switch
3661 * back to static empty constraint to avoid
3662 * the cost of freeing later on
3663 */
3664 if (!w)
3665 c = &emptyconstraint;
3666
3667 c->weight = w;
3668
3669 return c;
3670 }
3671
3672 static struct event_constraint *
intel_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)3673 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3674 struct perf_event *event)
3675 {
3676 struct event_constraint *c1, *c2;
3677
3678 c1 = cpuc->event_constraint[idx];
3679
3680 /*
3681 * first time only
3682 * - static constraint: no change across incremental scheduling calls
3683 * - dynamic constraint: handled by intel_get_excl_constraints()
3684 */
3685 c2 = __intel_get_event_constraints(cpuc, idx, event);
3686 if (c1) {
3687 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC));
3688 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
3689 c1->weight = c2->weight;
3690 c2 = c1;
3691 }
3692
3693 if (cpuc->excl_cntrs)
3694 return intel_get_excl_constraints(cpuc, event, idx, c2);
3695
3696 /* Not all counters support the branch counter feature. */
3697 if (branch_sample_counters(event)) {
3698 c2 = dyn_constraint(cpuc, c2, idx);
3699 c2->idxmsk64 &= x86_pmu.lbr_counters;
3700 c2->weight = hweight64(c2->idxmsk64);
3701 }
3702
3703 return c2;
3704 }
3705
intel_put_excl_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)3706 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
3707 struct perf_event *event)
3708 {
3709 struct hw_perf_event *hwc = &event->hw;
3710 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3711 int tid = cpuc->excl_thread_id;
3712 struct intel_excl_states *xl;
3713
3714 /*
3715 * nothing needed if in group validation mode
3716 */
3717 if (cpuc->is_fake)
3718 return;
3719
3720 if (WARN_ON_ONCE(!excl_cntrs))
3721 return;
3722
3723 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) {
3724 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT;
3725 if (!--cpuc->n_excl)
3726 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0);
3727 }
3728
3729 /*
3730 * If event was actually assigned, then mark the counter state as
3731 * unused now.
3732 */
3733 if (hwc->idx >= 0) {
3734 xl = &excl_cntrs->states[tid];
3735
3736 /*
3737 * put_constraint may be called from x86_schedule_events()
3738 * which already has the lock held so here make locking
3739 * conditional.
3740 */
3741 if (!xl->sched_started)
3742 raw_spin_lock(&excl_cntrs->lock);
3743
3744 xl->state[hwc->idx] = INTEL_EXCL_UNUSED;
3745
3746 if (!xl->sched_started)
3747 raw_spin_unlock(&excl_cntrs->lock);
3748 }
3749 }
3750
3751 static void
intel_put_shared_regs_event_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)3752 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
3753 struct perf_event *event)
3754 {
3755 struct hw_perf_event_extra *reg;
3756
3757 reg = &event->hw.extra_reg;
3758 if (reg->idx != EXTRA_REG_NONE)
3759 __intel_shared_reg_put_constraints(cpuc, reg);
3760
3761 reg = &event->hw.branch_reg;
3762 if (reg->idx != EXTRA_REG_NONE)
3763 __intel_shared_reg_put_constraints(cpuc, reg);
3764 }
3765
intel_put_event_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)3766 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
3767 struct perf_event *event)
3768 {
3769 intel_put_shared_regs_event_constraints(cpuc, event);
3770
3771 /*
3772 * is PMU has exclusive counter restrictions, then
3773 * all events are subject to and must call the
3774 * put_excl_constraints() routine
3775 */
3776 if (cpuc->excl_cntrs)
3777 intel_put_excl_constraints(cpuc, event);
3778 }
3779
intel_pebs_aliases_core2(struct perf_event * event)3780 static void intel_pebs_aliases_core2(struct perf_event *event)
3781 {
3782 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3783 /*
3784 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3785 * (0x003c) so that we can use it with PEBS.
3786 *
3787 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3788 * PEBS capable. However we can use INST_RETIRED.ANY_P
3789 * (0x00c0), which is a PEBS capable event, to get the same
3790 * count.
3791 *
3792 * INST_RETIRED.ANY_P counts the number of cycles that retires
3793 * CNTMASK instructions. By setting CNTMASK to a value (16)
3794 * larger than the maximum number of instructions that can be
3795 * retired per cycle (4) and then inverting the condition, we
3796 * count all cycles that retire 16 or less instructions, which
3797 * is every cycle.
3798 *
3799 * Thereby we gain a PEBS capable cycle counter.
3800 */
3801 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
3802
3803 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3804 event->hw.config = alt_config;
3805 }
3806 }
3807
intel_pebs_aliases_snb(struct perf_event * event)3808 static void intel_pebs_aliases_snb(struct perf_event *event)
3809 {
3810 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3811 /*
3812 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3813 * (0x003c) so that we can use it with PEBS.
3814 *
3815 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3816 * PEBS capable. However we can use UOPS_RETIRED.ALL
3817 * (0x01c2), which is a PEBS capable event, to get the same
3818 * count.
3819 *
3820 * UOPS_RETIRED.ALL counts the number of cycles that retires
3821 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
3822 * larger than the maximum number of micro-ops that can be
3823 * retired per cycle (4) and then inverting the condition, we
3824 * count all cycles that retire 16 or less micro-ops, which
3825 * is every cycle.
3826 *
3827 * Thereby we gain a PEBS capable cycle counter.
3828 */
3829 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
3830
3831 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3832 event->hw.config = alt_config;
3833 }
3834 }
3835
intel_pebs_aliases_precdist(struct perf_event * event)3836 static void intel_pebs_aliases_precdist(struct perf_event *event)
3837 {
3838 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3839 /*
3840 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3841 * (0x003c) so that we can use it with PEBS.
3842 *
3843 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3844 * PEBS capable. However we can use INST_RETIRED.PREC_DIST
3845 * (0x01c0), which is a PEBS capable event, to get the same
3846 * count.
3847 *
3848 * The PREC_DIST event has special support to minimize sample
3849 * shadowing effects. One drawback is that it can be
3850 * only programmed on counter 1, but that seems like an
3851 * acceptable trade off.
3852 */
3853 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16);
3854
3855 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3856 event->hw.config = alt_config;
3857 }
3858 }
3859
intel_pebs_aliases_ivb(struct perf_event * event)3860 static void intel_pebs_aliases_ivb(struct perf_event *event)
3861 {
3862 if (event->attr.precise_ip < 3)
3863 return intel_pebs_aliases_snb(event);
3864 return intel_pebs_aliases_precdist(event);
3865 }
3866
intel_pebs_aliases_skl(struct perf_event * event)3867 static void intel_pebs_aliases_skl(struct perf_event *event)
3868 {
3869 if (event->attr.precise_ip < 3)
3870 return intel_pebs_aliases_core2(event);
3871 return intel_pebs_aliases_precdist(event);
3872 }
3873
intel_pmu_large_pebs_flags(struct perf_event * event)3874 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)
3875 {
3876 unsigned long flags = x86_pmu.large_pebs_flags;
3877
3878 if (event->attr.use_clockid)
3879 flags &= ~PERF_SAMPLE_TIME;
3880 if (!event->attr.exclude_kernel)
3881 flags &= ~PERF_SAMPLE_REGS_USER;
3882 if (event->attr.sample_regs_user & ~PEBS_GP_REGS)
3883 flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR);
3884 return flags;
3885 }
3886
intel_pmu_bts_config(struct perf_event * event)3887 static int intel_pmu_bts_config(struct perf_event *event)
3888 {
3889 struct perf_event_attr *attr = &event->attr;
3890
3891 if (unlikely(intel_pmu_has_bts(event))) {
3892 /* BTS is not supported by this architecture. */
3893 if (!x86_pmu.bts_active)
3894 return -EOPNOTSUPP;
3895
3896 /* BTS is currently only allowed for user-mode. */
3897 if (!attr->exclude_kernel)
3898 return -EOPNOTSUPP;
3899
3900 /* BTS is not allowed for precise events. */
3901 if (attr->precise_ip)
3902 return -EOPNOTSUPP;
3903
3904 /* disallow bts if conflicting events are present */
3905 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
3906 return -EBUSY;
3907
3908 event->destroy = hw_perf_lbr_event_destroy;
3909 }
3910
3911 return 0;
3912 }
3913
core_pmu_hw_config(struct perf_event * event)3914 static int core_pmu_hw_config(struct perf_event *event)
3915 {
3916 int ret = x86_pmu_hw_config(event);
3917
3918 if (ret)
3919 return ret;
3920
3921 return intel_pmu_bts_config(event);
3922 }
3923
3924 #define INTEL_TD_METRIC_AVAILABLE_MAX (INTEL_TD_METRIC_RETIRING + \
3925 ((x86_pmu.num_topdown_events - 1) << 8))
3926
is_available_metric_event(struct perf_event * event)3927 static bool is_available_metric_event(struct perf_event *event)
3928 {
3929 return is_metric_event(event) &&
3930 event->attr.config <= INTEL_TD_METRIC_AVAILABLE_MAX;
3931 }
3932
is_mem_loads_event(struct perf_event * event)3933 static inline bool is_mem_loads_event(struct perf_event *event)
3934 {
3935 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01);
3936 }
3937
is_mem_loads_aux_event(struct perf_event * event)3938 static inline bool is_mem_loads_aux_event(struct perf_event *event)
3939 {
3940 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82);
3941 }
3942
require_mem_loads_aux_event(struct perf_event * event)3943 static inline bool require_mem_loads_aux_event(struct perf_event *event)
3944 {
3945 if (!(x86_pmu.flags & PMU_FL_MEM_LOADS_AUX))
3946 return false;
3947
3948 if (is_hybrid())
3949 return hybrid_pmu(event->pmu)->pmu_type == hybrid_big;
3950
3951 return true;
3952 }
3953
intel_pmu_has_cap(struct perf_event * event,int idx)3954 static inline bool intel_pmu_has_cap(struct perf_event *event, int idx)
3955 {
3956 union perf_capabilities *intel_cap = &hybrid(event->pmu, intel_cap);
3957
3958 return test_bit(idx, (unsigned long *)&intel_cap->capabilities);
3959 }
3960
intel_pmu_hw_config(struct perf_event * event)3961 static int intel_pmu_hw_config(struct perf_event *event)
3962 {
3963 int ret = x86_pmu_hw_config(event);
3964
3965 if (ret)
3966 return ret;
3967
3968 ret = intel_pmu_bts_config(event);
3969 if (ret)
3970 return ret;
3971
3972 if (event->attr.precise_ip) {
3973 if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT)
3974 return -EINVAL;
3975
3976 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) {
3977 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
3978 if (!(event->attr.sample_type & ~intel_pmu_large_pebs_flags(event)) &&
3979 !has_aux_action(event)) {
3980 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS;
3981 event->attach_state |= PERF_ATTACH_SCHED_CB;
3982 }
3983 }
3984 if (x86_pmu.pebs_aliases)
3985 x86_pmu.pebs_aliases(event);
3986 }
3987
3988 if (needs_branch_stack(event)) {
3989 /* Avoid branch stack setup for counting events in SAMPLE READ */
3990 if (is_sampling_event(event) ||
3991 !(event->attr.sample_type & PERF_SAMPLE_READ))
3992 event->hw.flags |= PERF_X86_EVENT_NEEDS_BRANCH_STACK;
3993 }
3994
3995 if (branch_sample_counters(event)) {
3996 struct perf_event *leader, *sibling;
3997 int num = 0;
3998
3999 if (!(x86_pmu.flags & PMU_FL_BR_CNTR) ||
4000 (event->attr.config & ~INTEL_ARCH_EVENT_MASK))
4001 return -EINVAL;
4002
4003 /*
4004 * The branch counter logging is not supported in the call stack
4005 * mode yet, since we cannot simply flush the LBR during e.g.,
4006 * multiplexing. Also, there is no obvious usage with the call
4007 * stack mode. Simply forbids it for now.
4008 *
4009 * If any events in the group enable the branch counter logging
4010 * feature, the group is treated as a branch counter logging
4011 * group, which requires the extra space to store the counters.
4012 */
4013 leader = event->group_leader;
4014 if (branch_sample_call_stack(leader))
4015 return -EINVAL;
4016 if (branch_sample_counters(leader))
4017 num++;
4018 leader->hw.flags |= PERF_X86_EVENT_BRANCH_COUNTERS;
4019
4020 for_each_sibling_event(sibling, leader) {
4021 if (branch_sample_call_stack(sibling))
4022 return -EINVAL;
4023 if (branch_sample_counters(sibling))
4024 num++;
4025 }
4026
4027 if (num > fls(x86_pmu.lbr_counters))
4028 return -EINVAL;
4029 /*
4030 * Only applying the PERF_SAMPLE_BRANCH_COUNTERS doesn't
4031 * require any branch stack setup.
4032 * Clear the bit to avoid unnecessary branch stack setup.
4033 */
4034 if (0 == (event->attr.branch_sample_type &
4035 ~(PERF_SAMPLE_BRANCH_PLM_ALL |
4036 PERF_SAMPLE_BRANCH_COUNTERS)))
4037 event->hw.flags &= ~PERF_X86_EVENT_NEEDS_BRANCH_STACK;
4038
4039 /*
4040 * Force the leader to be a LBR event. So LBRs can be reset
4041 * with the leader event. See intel_pmu_lbr_del() for details.
4042 */
4043 if (!intel_pmu_needs_branch_stack(leader))
4044 return -EINVAL;
4045 }
4046
4047 if (intel_pmu_needs_branch_stack(event)) {
4048 ret = intel_pmu_setup_lbr_filter(event);
4049 if (ret)
4050 return ret;
4051 event->attach_state |= PERF_ATTACH_SCHED_CB;
4052
4053 /*
4054 * BTS is set up earlier in this path, so don't account twice
4055 */
4056 if (!unlikely(intel_pmu_has_bts(event))) {
4057 /* disallow lbr if conflicting events are present */
4058 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
4059 return -EBUSY;
4060
4061 event->destroy = hw_perf_lbr_event_destroy;
4062 }
4063 }
4064
4065 if (event->attr.aux_output) {
4066 if (!event->attr.precise_ip)
4067 return -EINVAL;
4068
4069 event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT;
4070 }
4071
4072 if ((event->attr.type == PERF_TYPE_HARDWARE) ||
4073 (event->attr.type == PERF_TYPE_HW_CACHE))
4074 return 0;
4075
4076 /*
4077 * Config Topdown slots and metric events
4078 *
4079 * The slots event on Fixed Counter 3 can support sampling,
4080 * which will be handled normally in x86_perf_event_update().
4081 *
4082 * Metric events don't support sampling and require being paired
4083 * with a slots event as group leader. When the slots event
4084 * is used in a metrics group, it too cannot support sampling.
4085 */
4086 if (intel_pmu_has_cap(event, PERF_CAP_METRICS_IDX) && is_topdown_event(event)) {
4087 /* The metrics_clear can only be set for the slots event */
4088 if (event->attr.config1 &&
4089 (!is_slots_event(event) || (event->attr.config1 & ~INTEL_TD_CFG_METRIC_CLEAR)))
4090 return -EINVAL;
4091
4092 if (event->attr.config2)
4093 return -EINVAL;
4094
4095 /*
4096 * The TopDown metrics events and slots event don't
4097 * support any filters.
4098 */
4099 if (event->attr.config & X86_ALL_EVENT_FLAGS)
4100 return -EINVAL;
4101
4102 if (is_available_metric_event(event)) {
4103 struct perf_event *leader = event->group_leader;
4104
4105 /* The metric events don't support sampling. */
4106 if (is_sampling_event(event))
4107 return -EINVAL;
4108
4109 /* The metric events require a slots group leader. */
4110 if (!is_slots_event(leader))
4111 return -EINVAL;
4112
4113 /*
4114 * The leader/SLOTS must not be a sampling event for
4115 * metric use; hardware requires it starts at 0 when used
4116 * in conjunction with MSR_PERF_METRICS.
4117 */
4118 if (is_sampling_event(leader))
4119 return -EINVAL;
4120
4121 event->event_caps |= PERF_EV_CAP_SIBLING;
4122 /*
4123 * Only once we have a METRICs sibling do we
4124 * need TopDown magic.
4125 */
4126 leader->hw.flags |= PERF_X86_EVENT_TOPDOWN;
4127 event->hw.flags |= PERF_X86_EVENT_TOPDOWN;
4128 }
4129 }
4130
4131 /*
4132 * The load latency event X86_CONFIG(.event=0xcd, .umask=0x01) on SPR
4133 * doesn't function quite right. As a work-around it needs to always be
4134 * co-scheduled with a auxiliary event X86_CONFIG(.event=0x03, .umask=0x82).
4135 * The actual count of this second event is irrelevant it just needs
4136 * to be active to make the first event function correctly.
4137 *
4138 * In a group, the auxiliary event must be in front of the load latency
4139 * event. The rule is to simplify the implementation of the check.
4140 * That's because perf cannot have a complete group at the moment.
4141 */
4142 if (require_mem_loads_aux_event(event) &&
4143 (event->attr.sample_type & PERF_SAMPLE_DATA_SRC) &&
4144 is_mem_loads_event(event)) {
4145 struct perf_event *leader = event->group_leader;
4146 struct perf_event *sibling = NULL;
4147
4148 /*
4149 * When this memload event is also the first event (no group
4150 * exists yet), then there is no aux event before it.
4151 */
4152 if (leader == event)
4153 return -ENODATA;
4154
4155 if (!is_mem_loads_aux_event(leader)) {
4156 for_each_sibling_event(sibling, leader) {
4157 if (is_mem_loads_aux_event(sibling))
4158 break;
4159 }
4160 if (list_entry_is_head(sibling, &leader->sibling_list, sibling_list))
4161 return -ENODATA;
4162 }
4163 }
4164
4165 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
4166 return 0;
4167
4168 if (x86_pmu.version < 3)
4169 return -EINVAL;
4170
4171 ret = perf_allow_cpu(&event->attr);
4172 if (ret)
4173 return ret;
4174
4175 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
4176
4177 return 0;
4178 }
4179
4180 /*
4181 * Currently, the only caller of this function is the atomic_switch_perf_msrs().
4182 * The host perf context helps to prepare the values of the real hardware for
4183 * a set of msrs that need to be switched atomically in a vmx transaction.
4184 *
4185 * For example, the pseudocode needed to add a new msr should look like:
4186 *
4187 * arr[(*nr)++] = (struct perf_guest_switch_msr){
4188 * .msr = the hardware msr address,
4189 * .host = the value the hardware has when it doesn't run a guest,
4190 * .guest = the value the hardware has when it runs a guest,
4191 * };
4192 *
4193 * These values have nothing to do with the emulated values the guest sees
4194 * when it uses {RD,WR}MSR, which should be handled by the KVM context,
4195 * specifically in the intel_pmu_{get,set}_msr().
4196 */
intel_guest_get_msrs(int * nr,void * data)4197 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data)
4198 {
4199 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
4200 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
4201 struct kvm_pmu *kvm_pmu = (struct kvm_pmu *)data;
4202 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
4203 u64 pebs_mask = cpuc->pebs_enabled & x86_pmu.pebs_capable;
4204 int global_ctrl, pebs_enable;
4205
4206 /*
4207 * In addition to obeying exclude_guest/exclude_host, remove bits being
4208 * used for PEBS when running a guest, because PEBS writes to virtual
4209 * addresses (not physical addresses).
4210 */
4211 *nr = 0;
4212 global_ctrl = (*nr)++;
4213 arr[global_ctrl] = (struct perf_guest_switch_msr){
4214 .msr = MSR_CORE_PERF_GLOBAL_CTRL,
4215 .host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask,
4216 .guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask & ~pebs_mask,
4217 };
4218
4219 if (!x86_pmu.pebs)
4220 return arr;
4221
4222 /*
4223 * If PMU counter has PEBS enabled it is not enough to
4224 * disable counter on a guest entry since PEBS memory
4225 * write can overshoot guest entry and corrupt guest
4226 * memory. Disabling PEBS solves the problem.
4227 *
4228 * Don't do this if the CPU already enforces it.
4229 */
4230 if (x86_pmu.pebs_no_isolation) {
4231 arr[(*nr)++] = (struct perf_guest_switch_msr){
4232 .msr = MSR_IA32_PEBS_ENABLE,
4233 .host = cpuc->pebs_enabled,
4234 .guest = 0,
4235 };
4236 return arr;
4237 }
4238
4239 if (!kvm_pmu || !x86_pmu.pebs_ept)
4240 return arr;
4241
4242 arr[(*nr)++] = (struct perf_guest_switch_msr){
4243 .msr = MSR_IA32_DS_AREA,
4244 .host = (unsigned long)cpuc->ds,
4245 .guest = kvm_pmu->ds_area,
4246 };
4247
4248 if (x86_pmu.intel_cap.pebs_baseline) {
4249 arr[(*nr)++] = (struct perf_guest_switch_msr){
4250 .msr = MSR_PEBS_DATA_CFG,
4251 .host = cpuc->active_pebs_data_cfg,
4252 .guest = kvm_pmu->pebs_data_cfg,
4253 };
4254 }
4255
4256 pebs_enable = (*nr)++;
4257 arr[pebs_enable] = (struct perf_guest_switch_msr){
4258 .msr = MSR_IA32_PEBS_ENABLE,
4259 .host = cpuc->pebs_enabled & ~cpuc->intel_ctrl_guest_mask,
4260 .guest = pebs_mask & ~cpuc->intel_ctrl_host_mask,
4261 };
4262
4263 if (arr[pebs_enable].host) {
4264 /* Disable guest PEBS if host PEBS is enabled. */
4265 arr[pebs_enable].guest = 0;
4266 } else {
4267 /* Disable guest PEBS thoroughly for cross-mapped PEBS counters. */
4268 arr[pebs_enable].guest &= ~kvm_pmu->host_cross_mapped_mask;
4269 arr[global_ctrl].guest &= ~kvm_pmu->host_cross_mapped_mask;
4270 /* Set hw GLOBAL_CTRL bits for PEBS counter when it runs for guest */
4271 arr[global_ctrl].guest |= arr[pebs_enable].guest;
4272 }
4273
4274 return arr;
4275 }
4276
core_guest_get_msrs(int * nr,void * data)4277 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr, void *data)
4278 {
4279 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
4280 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
4281 int idx;
4282
4283 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {
4284 struct perf_event *event = cpuc->events[idx];
4285
4286 arr[idx].msr = x86_pmu_config_addr(idx);
4287 arr[idx].host = arr[idx].guest = 0;
4288
4289 if (!test_bit(idx, cpuc->active_mask))
4290 continue;
4291
4292 arr[idx].host = arr[idx].guest =
4293 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
4294
4295 if (event->attr.exclude_host)
4296 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
4297 else if (event->attr.exclude_guest)
4298 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
4299 }
4300
4301 *nr = x86_pmu_max_num_counters(cpuc->pmu);
4302 return arr;
4303 }
4304
core_pmu_enable_event(struct perf_event * event)4305 static void core_pmu_enable_event(struct perf_event *event)
4306 {
4307 if (!event->attr.exclude_host)
4308 x86_pmu_enable_event(event);
4309 }
4310
core_pmu_enable_all(int added)4311 static void core_pmu_enable_all(int added)
4312 {
4313 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
4314 int idx;
4315
4316 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {
4317 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
4318
4319 if (!test_bit(idx, cpuc->active_mask) ||
4320 cpuc->events[idx]->attr.exclude_host)
4321 continue;
4322
4323 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
4324 }
4325 }
4326
hsw_hw_config(struct perf_event * event)4327 static int hsw_hw_config(struct perf_event *event)
4328 {
4329 int ret = intel_pmu_hw_config(event);
4330
4331 if (ret)
4332 return ret;
4333 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
4334 return 0;
4335 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
4336
4337 /*
4338 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
4339 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
4340 * this combination.
4341 */
4342 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
4343 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
4344 event->attr.precise_ip > 0))
4345 return -EOPNOTSUPP;
4346
4347 if (event_is_checkpointed(event)) {
4348 /*
4349 * Sampling of checkpointed events can cause situations where
4350 * the CPU constantly aborts because of a overflow, which is
4351 * then checkpointed back and ignored. Forbid checkpointing
4352 * for sampling.
4353 *
4354 * But still allow a long sampling period, so that perf stat
4355 * from KVM works.
4356 */
4357 if (event->attr.sample_period > 0 &&
4358 event->attr.sample_period < 0x7fffffff)
4359 return -EOPNOTSUPP;
4360 }
4361 return 0;
4362 }
4363
4364 static struct event_constraint counter0_constraint =
4365 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1);
4366
4367 static struct event_constraint counter1_constraint =
4368 INTEL_ALL_EVENT_CONSTRAINT(0, 0x2);
4369
4370 static struct event_constraint counter0_1_constraint =
4371 INTEL_ALL_EVENT_CONSTRAINT(0, 0x3);
4372
4373 static struct event_constraint counter2_constraint =
4374 EVENT_CONSTRAINT(0, 0x4, 0);
4375
4376 static struct event_constraint fixed0_constraint =
4377 FIXED_EVENT_CONSTRAINT(0x00c0, 0);
4378
4379 static struct event_constraint fixed0_counter0_constraint =
4380 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL);
4381
4382 static struct event_constraint fixed0_counter0_1_constraint =
4383 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000003ULL);
4384
4385 static struct event_constraint counters_1_7_constraint =
4386 INTEL_ALL_EVENT_CONSTRAINT(0, 0xfeULL);
4387
4388 static struct event_constraint *
hsw_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4389 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4390 struct perf_event *event)
4391 {
4392 struct event_constraint *c;
4393
4394 c = intel_get_event_constraints(cpuc, idx, event);
4395
4396 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
4397 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
4398 if (c->idxmsk64 & (1U << 2))
4399 return &counter2_constraint;
4400 return &emptyconstraint;
4401 }
4402
4403 return c;
4404 }
4405
4406 static struct event_constraint *
icl_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4407 icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4408 struct perf_event *event)
4409 {
4410 /*
4411 * Fixed counter 0 has less skid.
4412 * Force instruction:ppp in Fixed counter 0
4413 */
4414 if ((event->attr.precise_ip == 3) &&
4415 constraint_match(&fixed0_constraint, event->hw.config))
4416 return &fixed0_constraint;
4417
4418 return hsw_get_event_constraints(cpuc, idx, event);
4419 }
4420
4421 static struct event_constraint *
glc_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4422 glc_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4423 struct perf_event *event)
4424 {
4425 struct event_constraint *c;
4426
4427 c = icl_get_event_constraints(cpuc, idx, event);
4428
4429 /*
4430 * The :ppp indicates the Precise Distribution (PDist) facility, which
4431 * is only supported on the GP counter 0. If a :ppp event which is not
4432 * available on the GP counter 0, error out.
4433 * Exception: Instruction PDIR is only available on the fixed counter 0.
4434 */
4435 if ((event->attr.precise_ip == 3) &&
4436 !constraint_match(&fixed0_constraint, event->hw.config)) {
4437 if (c->idxmsk64 & BIT_ULL(0))
4438 return &counter0_constraint;
4439
4440 return &emptyconstraint;
4441 }
4442
4443 return c;
4444 }
4445
4446 static struct event_constraint *
glp_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4447 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4448 struct perf_event *event)
4449 {
4450 struct event_constraint *c;
4451
4452 /* :ppp means to do reduced skid PEBS which is PMC0 only. */
4453 if (event->attr.precise_ip == 3)
4454 return &counter0_constraint;
4455
4456 c = intel_get_event_constraints(cpuc, idx, event);
4457
4458 return c;
4459 }
4460
4461 static struct event_constraint *
tnt_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4462 tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4463 struct perf_event *event)
4464 {
4465 struct event_constraint *c;
4466
4467 c = intel_get_event_constraints(cpuc, idx, event);
4468
4469 /*
4470 * :ppp means to do reduced skid PEBS,
4471 * which is available on PMC0 and fixed counter 0.
4472 */
4473 if (event->attr.precise_ip == 3) {
4474 /* Force instruction:ppp on PMC0 and Fixed counter 0 */
4475 if (constraint_match(&fixed0_constraint, event->hw.config))
4476 return &fixed0_counter0_constraint;
4477
4478 return &counter0_constraint;
4479 }
4480
4481 return c;
4482 }
4483
4484 static bool allow_tsx_force_abort = true;
4485
4486 static struct event_constraint *
tfa_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4487 tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4488 struct perf_event *event)
4489 {
4490 struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event);
4491
4492 /*
4493 * Without TFA we must not use PMC3.
4494 */
4495 if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) {
4496 c = dyn_constraint(cpuc, c, idx);
4497 c->idxmsk64 &= ~(1ULL << 3);
4498 c->weight--;
4499 }
4500
4501 return c;
4502 }
4503
4504 static struct event_constraint *
adl_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4505 adl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4506 struct perf_event *event)
4507 {
4508 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
4509
4510 if (pmu->pmu_type == hybrid_big)
4511 return glc_get_event_constraints(cpuc, idx, event);
4512 else if (pmu->pmu_type == hybrid_small)
4513 return tnt_get_event_constraints(cpuc, idx, event);
4514
4515 WARN_ON(1);
4516 return &emptyconstraint;
4517 }
4518
4519 static struct event_constraint *
cmt_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4520 cmt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4521 struct perf_event *event)
4522 {
4523 struct event_constraint *c;
4524
4525 c = intel_get_event_constraints(cpuc, idx, event);
4526
4527 /*
4528 * The :ppp indicates the Precise Distribution (PDist) facility, which
4529 * is only supported on the GP counter 0 & 1 and Fixed counter 0.
4530 * If a :ppp event which is not available on the above eligible counters,
4531 * error out.
4532 */
4533 if (event->attr.precise_ip == 3) {
4534 /* Force instruction:ppp on PMC0, 1 and Fixed counter 0 */
4535 if (constraint_match(&fixed0_constraint, event->hw.config)) {
4536 /* The fixed counter 0 doesn't support LBR event logging. */
4537 if (branch_sample_counters(event))
4538 return &counter0_1_constraint;
4539 else
4540 return &fixed0_counter0_1_constraint;
4541 }
4542
4543 switch (c->idxmsk64 & 0x3ull) {
4544 case 0x1:
4545 return &counter0_constraint;
4546 case 0x2:
4547 return &counter1_constraint;
4548 case 0x3:
4549 return &counter0_1_constraint;
4550 }
4551 return &emptyconstraint;
4552 }
4553
4554 return c;
4555 }
4556
4557 static struct event_constraint *
rwc_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4558 rwc_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4559 struct perf_event *event)
4560 {
4561 struct event_constraint *c;
4562
4563 c = glc_get_event_constraints(cpuc, idx, event);
4564
4565 /* The Retire Latency is not supported by the fixed counter 0. */
4566 if (event->attr.precise_ip &&
4567 (event->attr.sample_type & PERF_SAMPLE_WEIGHT_TYPE) &&
4568 constraint_match(&fixed0_constraint, event->hw.config)) {
4569 /*
4570 * The Instruction PDIR is only available
4571 * on the fixed counter 0. Error out for this case.
4572 */
4573 if (event->attr.precise_ip == 3)
4574 return &emptyconstraint;
4575 return &counters_1_7_constraint;
4576 }
4577
4578 return c;
4579 }
4580
4581 static struct event_constraint *
mtl_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4582 mtl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4583 struct perf_event *event)
4584 {
4585 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
4586
4587 if (pmu->pmu_type == hybrid_big)
4588 return rwc_get_event_constraints(cpuc, idx, event);
4589 if (pmu->pmu_type == hybrid_small)
4590 return cmt_get_event_constraints(cpuc, idx, event);
4591
4592 WARN_ON(1);
4593 return &emptyconstraint;
4594 }
4595
adl_hw_config(struct perf_event * event)4596 static int adl_hw_config(struct perf_event *event)
4597 {
4598 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
4599
4600 if (pmu->pmu_type == hybrid_big)
4601 return hsw_hw_config(event);
4602 else if (pmu->pmu_type == hybrid_small)
4603 return intel_pmu_hw_config(event);
4604
4605 WARN_ON(1);
4606 return -EOPNOTSUPP;
4607 }
4608
adl_get_hybrid_cpu_type(void)4609 static enum hybrid_cpu_type adl_get_hybrid_cpu_type(void)
4610 {
4611 return HYBRID_INTEL_CORE;
4612 }
4613
erratum_hsw11(struct perf_event * event)4614 static inline bool erratum_hsw11(struct perf_event *event)
4615 {
4616 return (event->hw.config & INTEL_ARCH_EVENT_MASK) ==
4617 X86_CONFIG(.event=0xc0, .umask=0x01);
4618 }
4619
4620 static struct event_constraint *
arl_h_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4621 arl_h_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4622 struct perf_event *event)
4623 {
4624 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
4625
4626 if (pmu->pmu_type == hybrid_tiny)
4627 return cmt_get_event_constraints(cpuc, idx, event);
4628
4629 return mtl_get_event_constraints(cpuc, idx, event);
4630 }
4631
arl_h_hw_config(struct perf_event * event)4632 static int arl_h_hw_config(struct perf_event *event)
4633 {
4634 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
4635
4636 if (pmu->pmu_type == hybrid_tiny)
4637 return intel_pmu_hw_config(event);
4638
4639 return adl_hw_config(event);
4640 }
4641
4642 /*
4643 * The HSW11 requires a period larger than 100 which is the same as the BDM11.
4644 * A minimum period of 128 is enforced as well for the INST_RETIRED.ALL.
4645 *
4646 * The message 'interrupt took too long' can be observed on any counter which
4647 * was armed with a period < 32 and two events expired in the same NMI.
4648 * A minimum period of 32 is enforced for the rest of the events.
4649 */
hsw_limit_period(struct perf_event * event,s64 * left)4650 static void hsw_limit_period(struct perf_event *event, s64 *left)
4651 {
4652 *left = max(*left, erratum_hsw11(event) ? 128 : 32);
4653 }
4654
4655 /*
4656 * Broadwell:
4657 *
4658 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
4659 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
4660 * the two to enforce a minimum period of 128 (the smallest value that has bits
4661 * 0-5 cleared and >= 100).
4662 *
4663 * Because of how the code in x86_perf_event_set_period() works, the truncation
4664 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
4665 * to make up for the 'lost' events due to carrying the 'error' in period_left.
4666 *
4667 * Therefore the effective (average) period matches the requested period,
4668 * despite coarser hardware granularity.
4669 */
bdw_limit_period(struct perf_event * event,s64 * left)4670 static void bdw_limit_period(struct perf_event *event, s64 *left)
4671 {
4672 if (erratum_hsw11(event)) {
4673 if (*left < 128)
4674 *left = 128;
4675 *left &= ~0x3fULL;
4676 }
4677 }
4678
nhm_limit_period(struct perf_event * event,s64 * left)4679 static void nhm_limit_period(struct perf_event *event, s64 *left)
4680 {
4681 *left = max(*left, 32LL);
4682 }
4683
glc_limit_period(struct perf_event * event,s64 * left)4684 static void glc_limit_period(struct perf_event *event, s64 *left)
4685 {
4686 if (event->attr.precise_ip == 3)
4687 *left = max(*left, 128LL);
4688 }
4689
4690 PMU_FORMAT_ATTR(event, "config:0-7" );
4691 PMU_FORMAT_ATTR(umask, "config:8-15" );
4692 PMU_FORMAT_ATTR(edge, "config:18" );
4693 PMU_FORMAT_ATTR(pc, "config:19" );
4694 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
4695 PMU_FORMAT_ATTR(inv, "config:23" );
4696 PMU_FORMAT_ATTR(cmask, "config:24-31" );
4697 PMU_FORMAT_ATTR(in_tx, "config:32" );
4698 PMU_FORMAT_ATTR(in_tx_cp, "config:33" );
4699 PMU_FORMAT_ATTR(eq, "config:36" ); /* v6 + */
4700
4701 PMU_FORMAT_ATTR(metrics_clear, "config1:0"); /* PERF_CAPABILITIES.RDPMC_METRICS_CLEAR */
4702
umask2_show(struct device * dev,struct device_attribute * attr,char * page)4703 static ssize_t umask2_show(struct device *dev,
4704 struct device_attribute *attr,
4705 char *page)
4706 {
4707 u64 mask = hybrid(dev_get_drvdata(dev), config_mask) & ARCH_PERFMON_EVENTSEL_UMASK2;
4708
4709 if (mask == ARCH_PERFMON_EVENTSEL_UMASK2)
4710 return sprintf(page, "config:8-15,40-47\n");
4711
4712 /* Roll back to the old format if umask2 is not supported. */
4713 return sprintf(page, "config:8-15\n");
4714 }
4715
4716 static struct device_attribute format_attr_umask2 =
4717 __ATTR(umask, 0444, umask2_show, NULL);
4718
4719 static struct attribute *format_evtsel_ext_attrs[] = {
4720 &format_attr_umask2.attr,
4721 &format_attr_eq.attr,
4722 &format_attr_metrics_clear.attr,
4723 NULL
4724 };
4725
4726 static umode_t
evtsel_ext_is_visible(struct kobject * kobj,struct attribute * attr,int i)4727 evtsel_ext_is_visible(struct kobject *kobj, struct attribute *attr, int i)
4728 {
4729 struct device *dev = kobj_to_dev(kobj);
4730 u64 mask;
4731
4732 /*
4733 * The umask and umask2 have different formats but share the
4734 * same attr name. In update mode, the previous value of the
4735 * umask is unconditionally removed before is_visible. If
4736 * umask2 format is not enumerated, it's impossible to roll
4737 * back to the old format.
4738 * Does the check in umask2_show rather than is_visible.
4739 */
4740 if (i == 0)
4741 return attr->mode;
4742
4743 mask = hybrid(dev_get_drvdata(dev), config_mask);
4744 if (i == 1)
4745 return (mask & ARCH_PERFMON_EVENTSEL_EQ) ? attr->mode : 0;
4746
4747 /* PERF_CAPABILITIES.RDPMC_METRICS_CLEAR */
4748 if (i == 2) {
4749 union perf_capabilities intel_cap = hybrid(dev_get_drvdata(dev), intel_cap);
4750
4751 return intel_cap.rdpmc_metrics_clear ? attr->mode : 0;
4752 }
4753
4754 return 0;
4755 }
4756
4757 static struct attribute *intel_arch_formats_attr[] = {
4758 &format_attr_event.attr,
4759 &format_attr_umask.attr,
4760 &format_attr_edge.attr,
4761 &format_attr_pc.attr,
4762 &format_attr_inv.attr,
4763 &format_attr_cmask.attr,
4764 NULL,
4765 };
4766
intel_event_sysfs_show(char * page,u64 config)4767 ssize_t intel_event_sysfs_show(char *page, u64 config)
4768 {
4769 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
4770
4771 return x86_event_sysfs_show(page, config, event);
4772 }
4773
allocate_shared_regs(int cpu)4774 static struct intel_shared_regs *allocate_shared_regs(int cpu)
4775 {
4776 struct intel_shared_regs *regs;
4777 int i;
4778
4779 regs = kzalloc_node(sizeof(struct intel_shared_regs),
4780 GFP_KERNEL, cpu_to_node(cpu));
4781 if (regs) {
4782 /*
4783 * initialize the locks to keep lockdep happy
4784 */
4785 for (i = 0; i < EXTRA_REG_MAX; i++)
4786 raw_spin_lock_init(®s->regs[i].lock);
4787
4788 regs->core_id = -1;
4789 }
4790 return regs;
4791 }
4792
allocate_excl_cntrs(int cpu)4793 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
4794 {
4795 struct intel_excl_cntrs *c;
4796
4797 c = kzalloc_node(sizeof(struct intel_excl_cntrs),
4798 GFP_KERNEL, cpu_to_node(cpu));
4799 if (c) {
4800 raw_spin_lock_init(&c->lock);
4801 c->core_id = -1;
4802 }
4803 return c;
4804 }
4805
4806
intel_cpuc_prepare(struct cpu_hw_events * cpuc,int cpu)4807 int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
4808 {
4809 cpuc->pebs_record_size = x86_pmu.pebs_record_size;
4810
4811 if (is_hybrid() || x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
4812 cpuc->shared_regs = allocate_shared_regs(cpu);
4813 if (!cpuc->shared_regs)
4814 goto err;
4815 }
4816
4817 if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA | PMU_FL_BR_CNTR)) {
4818 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
4819
4820 cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu));
4821 if (!cpuc->constraint_list)
4822 goto err_shared_regs;
4823 }
4824
4825 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
4826 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
4827 if (!cpuc->excl_cntrs)
4828 goto err_constraint_list;
4829
4830 cpuc->excl_thread_id = 0;
4831 }
4832
4833 return 0;
4834
4835 err_constraint_list:
4836 kfree(cpuc->constraint_list);
4837 cpuc->constraint_list = NULL;
4838
4839 err_shared_regs:
4840 kfree(cpuc->shared_regs);
4841 cpuc->shared_regs = NULL;
4842
4843 err:
4844 return -ENOMEM;
4845 }
4846
intel_pmu_cpu_prepare(int cpu)4847 static int intel_pmu_cpu_prepare(int cpu)
4848 {
4849 return intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu);
4850 }
4851
flip_smm_bit(void * data)4852 static void flip_smm_bit(void *data)
4853 {
4854 unsigned long set = *(unsigned long *)data;
4855
4856 if (set > 0) {
4857 msr_set_bit(MSR_IA32_DEBUGCTLMSR,
4858 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
4859 } else {
4860 msr_clear_bit(MSR_IA32_DEBUGCTLMSR,
4861 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
4862 }
4863 }
4864
intel_pmu_check_counters_mask(u64 * cntr_mask,u64 * fixed_cntr_mask,u64 * intel_ctrl)4865 static void intel_pmu_check_counters_mask(u64 *cntr_mask,
4866 u64 *fixed_cntr_mask,
4867 u64 *intel_ctrl)
4868 {
4869 unsigned int bit;
4870
4871 bit = fls64(*cntr_mask);
4872 if (bit > INTEL_PMC_MAX_GENERIC) {
4873 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
4874 bit, INTEL_PMC_MAX_GENERIC);
4875 *cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_GENERIC - 1, 0);
4876 }
4877 *intel_ctrl = *cntr_mask;
4878
4879 bit = fls64(*fixed_cntr_mask);
4880 if (bit > INTEL_PMC_MAX_FIXED) {
4881 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
4882 bit, INTEL_PMC_MAX_FIXED);
4883 *fixed_cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_FIXED - 1, 0);
4884 }
4885
4886 *intel_ctrl |= *fixed_cntr_mask << INTEL_PMC_IDX_FIXED;
4887 }
4888
4889 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints,
4890 u64 cntr_mask,
4891 u64 fixed_cntr_mask,
4892 u64 intel_ctrl);
4893
4894 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs);
4895
intel_pmu_broken_perf_cap(void)4896 static inline bool intel_pmu_broken_perf_cap(void)
4897 {
4898 /* The Perf Metric (Bit 15) is always cleared */
4899 if (boot_cpu_data.x86_vfm == INTEL_METEORLAKE ||
4900 boot_cpu_data.x86_vfm == INTEL_METEORLAKE_L)
4901 return true;
4902
4903 return false;
4904 }
4905
update_pmu_cap(struct x86_hybrid_pmu * pmu)4906 static void update_pmu_cap(struct x86_hybrid_pmu *pmu)
4907 {
4908 unsigned int sub_bitmaps, eax, ebx, ecx, edx;
4909
4910 cpuid(ARCH_PERFMON_EXT_LEAF, &sub_bitmaps, &ebx, &ecx, &edx);
4911
4912 if (ebx & ARCH_PERFMON_EXT_UMASK2)
4913 pmu->config_mask |= ARCH_PERFMON_EVENTSEL_UMASK2;
4914 if (ebx & ARCH_PERFMON_EXT_EQ)
4915 pmu->config_mask |= ARCH_PERFMON_EVENTSEL_EQ;
4916
4917 if (sub_bitmaps & ARCH_PERFMON_NUM_COUNTER_LEAF_BIT) {
4918 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_NUM_COUNTER_LEAF,
4919 &eax, &ebx, &ecx, &edx);
4920 pmu->cntr_mask64 = eax;
4921 pmu->fixed_cntr_mask64 = ebx;
4922 }
4923
4924 if (!intel_pmu_broken_perf_cap()) {
4925 /* Perf Metric (Bit 15) and PEBS via PT (Bit 16) are hybrid enumeration */
4926 rdmsrl(MSR_IA32_PERF_CAPABILITIES, pmu->intel_cap.capabilities);
4927 }
4928 }
4929
intel_pmu_check_hybrid_pmus(struct x86_hybrid_pmu * pmu)4930 static void intel_pmu_check_hybrid_pmus(struct x86_hybrid_pmu *pmu)
4931 {
4932 intel_pmu_check_counters_mask(&pmu->cntr_mask64, &pmu->fixed_cntr_mask64,
4933 &pmu->intel_ctrl);
4934 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64);
4935 pmu->unconstrained = (struct event_constraint)
4936 __EVENT_CONSTRAINT(0, pmu->cntr_mask64,
4937 0, x86_pmu_num_counters(&pmu->pmu), 0, 0);
4938
4939 if (pmu->intel_cap.perf_metrics)
4940 pmu->intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS;
4941 else
4942 pmu->intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS);
4943
4944 if (pmu->intel_cap.pebs_output_pt_available)
4945 pmu->pmu.capabilities |= PERF_PMU_CAP_AUX_OUTPUT;
4946 else
4947 pmu->pmu.capabilities &= ~PERF_PMU_CAP_AUX_OUTPUT;
4948
4949 intel_pmu_check_event_constraints(pmu->event_constraints,
4950 pmu->cntr_mask64,
4951 pmu->fixed_cntr_mask64,
4952 pmu->intel_ctrl);
4953
4954 intel_pmu_check_extra_regs(pmu->extra_regs);
4955 }
4956
find_hybrid_pmu_for_cpu(void)4957 static struct x86_hybrid_pmu *find_hybrid_pmu_for_cpu(void)
4958 {
4959 u8 cpu_type = get_this_hybrid_cpu_type();
4960 int i;
4961
4962 /*
4963 * This is running on a CPU model that is known to have hybrid
4964 * configurations. But the CPU told us it is not hybrid, shame
4965 * on it. There should be a fixup function provided for these
4966 * troublesome CPUs (->get_hybrid_cpu_type).
4967 */
4968 if (cpu_type == HYBRID_INTEL_NONE) {
4969 if (x86_pmu.get_hybrid_cpu_type)
4970 cpu_type = x86_pmu.get_hybrid_cpu_type();
4971 else
4972 return NULL;
4973 }
4974
4975 /*
4976 * This essentially just maps between the 'hybrid_cpu_type'
4977 * and 'hybrid_pmu_type' enums except for ARL-H processor
4978 * which needs to compare atom uarch native id since ARL-H
4979 * contains two different atom uarchs.
4980 */
4981 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
4982 enum hybrid_pmu_type pmu_type = x86_pmu.hybrid_pmu[i].pmu_type;
4983 u32 native_id;
4984
4985 if (cpu_type == HYBRID_INTEL_CORE && pmu_type == hybrid_big)
4986 return &x86_pmu.hybrid_pmu[i];
4987 if (cpu_type == HYBRID_INTEL_ATOM) {
4988 if (x86_pmu.num_hybrid_pmus == 2 && pmu_type == hybrid_small)
4989 return &x86_pmu.hybrid_pmu[i];
4990
4991 native_id = get_this_hybrid_cpu_native_id();
4992 if (native_id == skt_native_id && pmu_type == hybrid_small)
4993 return &x86_pmu.hybrid_pmu[i];
4994 if (native_id == cmt_native_id && pmu_type == hybrid_tiny)
4995 return &x86_pmu.hybrid_pmu[i];
4996 }
4997 }
4998
4999 return NULL;
5000 }
5001
init_hybrid_pmu(int cpu)5002 static bool init_hybrid_pmu(int cpu)
5003 {
5004 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
5005 struct x86_hybrid_pmu *pmu = find_hybrid_pmu_for_cpu();
5006
5007 if (WARN_ON_ONCE(!pmu || (pmu->pmu.type == -1))) {
5008 cpuc->pmu = NULL;
5009 return false;
5010 }
5011
5012 /* Only check and dump the PMU information for the first CPU */
5013 if (!cpumask_empty(&pmu->supported_cpus))
5014 goto end;
5015
5016 if (this_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT))
5017 update_pmu_cap(pmu);
5018
5019 intel_pmu_check_hybrid_pmus(pmu);
5020
5021 if (!check_hw_exists(&pmu->pmu, pmu->cntr_mask, pmu->fixed_cntr_mask))
5022 return false;
5023
5024 pr_info("%s PMU driver: ", pmu->name);
5025
5026 if (pmu->intel_cap.pebs_output_pt_available)
5027 pr_cont("PEBS-via-PT ");
5028
5029 pr_cont("\n");
5030
5031 x86_pmu_show_pmu_cap(&pmu->pmu);
5032
5033 end:
5034 cpumask_set_cpu(cpu, &pmu->supported_cpus);
5035 cpuc->pmu = &pmu->pmu;
5036
5037 return true;
5038 }
5039
intel_pmu_cpu_starting(int cpu)5040 static void intel_pmu_cpu_starting(int cpu)
5041 {
5042 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
5043 int core_id = topology_core_id(cpu);
5044 int i;
5045
5046 if (is_hybrid() && !init_hybrid_pmu(cpu))
5047 return;
5048
5049 init_debug_store_on_cpu(cpu);
5050 /*
5051 * Deal with CPUs that don't clear their LBRs on power-up.
5052 */
5053 intel_pmu_lbr_reset();
5054
5055 cpuc->lbr_sel = NULL;
5056
5057 if (x86_pmu.flags & PMU_FL_TFA) {
5058 WARN_ON_ONCE(cpuc->tfa_shadow);
5059 cpuc->tfa_shadow = ~0ULL;
5060 intel_set_tfa(cpuc, false);
5061 }
5062
5063 if (x86_pmu.version > 1)
5064 flip_smm_bit(&x86_pmu.attr_freeze_on_smi);
5065
5066 /*
5067 * Disable perf metrics if any added CPU doesn't support it.
5068 *
5069 * Turn off the check for a hybrid architecture, because the
5070 * architecture MSR, MSR_IA32_PERF_CAPABILITIES, only indicate
5071 * the architecture features. The perf metrics is a model-specific
5072 * feature for now. The corresponding bit should always be 0 on
5073 * a hybrid platform, e.g., Alder Lake.
5074 */
5075 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) {
5076 union perf_capabilities perf_cap;
5077
5078 rdmsrl(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities);
5079 if (!perf_cap.perf_metrics) {
5080 x86_pmu.intel_cap.perf_metrics = 0;
5081 x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS);
5082 }
5083 }
5084
5085 if (!cpuc->shared_regs)
5086 return;
5087
5088 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
5089 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
5090 struct intel_shared_regs *pc;
5091
5092 pc = per_cpu(cpu_hw_events, i).shared_regs;
5093 if (pc && pc->core_id == core_id) {
5094 cpuc->kfree_on_online[0] = cpuc->shared_regs;
5095 cpuc->shared_regs = pc;
5096 break;
5097 }
5098 }
5099 cpuc->shared_regs->core_id = core_id;
5100 cpuc->shared_regs->refcnt++;
5101 }
5102
5103 if (x86_pmu.lbr_sel_map)
5104 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
5105
5106 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
5107 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
5108 struct cpu_hw_events *sibling;
5109 struct intel_excl_cntrs *c;
5110
5111 sibling = &per_cpu(cpu_hw_events, i);
5112 c = sibling->excl_cntrs;
5113 if (c && c->core_id == core_id) {
5114 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
5115 cpuc->excl_cntrs = c;
5116 if (!sibling->excl_thread_id)
5117 cpuc->excl_thread_id = 1;
5118 break;
5119 }
5120 }
5121 cpuc->excl_cntrs->core_id = core_id;
5122 cpuc->excl_cntrs->refcnt++;
5123 }
5124 }
5125
free_excl_cntrs(struct cpu_hw_events * cpuc)5126 static void free_excl_cntrs(struct cpu_hw_events *cpuc)
5127 {
5128 struct intel_excl_cntrs *c;
5129
5130 c = cpuc->excl_cntrs;
5131 if (c) {
5132 if (c->core_id == -1 || --c->refcnt == 0)
5133 kfree(c);
5134 cpuc->excl_cntrs = NULL;
5135 }
5136
5137 kfree(cpuc->constraint_list);
5138 cpuc->constraint_list = NULL;
5139 }
5140
intel_pmu_cpu_dying(int cpu)5141 static void intel_pmu_cpu_dying(int cpu)
5142 {
5143 fini_debug_store_on_cpu(cpu);
5144 }
5145
intel_cpuc_finish(struct cpu_hw_events * cpuc)5146 void intel_cpuc_finish(struct cpu_hw_events *cpuc)
5147 {
5148 struct intel_shared_regs *pc;
5149
5150 pc = cpuc->shared_regs;
5151 if (pc) {
5152 if (pc->core_id == -1 || --pc->refcnt == 0)
5153 kfree(pc);
5154 cpuc->shared_regs = NULL;
5155 }
5156
5157 free_excl_cntrs(cpuc);
5158 }
5159
intel_pmu_cpu_dead(int cpu)5160 static void intel_pmu_cpu_dead(int cpu)
5161 {
5162 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
5163
5164 intel_cpuc_finish(cpuc);
5165
5166 if (is_hybrid() && cpuc->pmu)
5167 cpumask_clear_cpu(cpu, &hybrid_pmu(cpuc->pmu)->supported_cpus);
5168 }
5169
intel_pmu_sched_task(struct perf_event_pmu_context * pmu_ctx,bool sched_in)5170 static void intel_pmu_sched_task(struct perf_event_pmu_context *pmu_ctx,
5171 bool sched_in)
5172 {
5173 intel_pmu_pebs_sched_task(pmu_ctx, sched_in);
5174 intel_pmu_lbr_sched_task(pmu_ctx, sched_in);
5175 }
5176
intel_pmu_swap_task_ctx(struct perf_event_pmu_context * prev_epc,struct perf_event_pmu_context * next_epc)5177 static void intel_pmu_swap_task_ctx(struct perf_event_pmu_context *prev_epc,
5178 struct perf_event_pmu_context *next_epc)
5179 {
5180 intel_pmu_lbr_swap_task_ctx(prev_epc, next_epc);
5181 }
5182
intel_pmu_check_period(struct perf_event * event,u64 value)5183 static int intel_pmu_check_period(struct perf_event *event, u64 value)
5184 {
5185 return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0;
5186 }
5187
intel_aux_output_init(void)5188 static void intel_aux_output_init(void)
5189 {
5190 /* Refer also intel_pmu_aux_output_match() */
5191 if (x86_pmu.intel_cap.pebs_output_pt_available)
5192 x86_pmu.assign = intel_pmu_assign_event;
5193 }
5194
intel_pmu_aux_output_match(struct perf_event * event)5195 static int intel_pmu_aux_output_match(struct perf_event *event)
5196 {
5197 /* intel_pmu_assign_event() is needed, refer intel_aux_output_init() */
5198 if (!x86_pmu.intel_cap.pebs_output_pt_available)
5199 return 0;
5200
5201 return is_intel_pt_event(event);
5202 }
5203
intel_pmu_filter(struct pmu * pmu,int cpu,bool * ret)5204 static void intel_pmu_filter(struct pmu *pmu, int cpu, bool *ret)
5205 {
5206 struct x86_hybrid_pmu *hpmu = hybrid_pmu(pmu);
5207
5208 *ret = !cpumask_test_cpu(cpu, &hpmu->supported_cpus);
5209 }
5210
5211 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
5212
5213 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
5214
5215 PMU_FORMAT_ATTR(frontend, "config1:0-23");
5216
5217 PMU_FORMAT_ATTR(snoop_rsp, "config1:0-63");
5218
5219 static struct attribute *intel_arch3_formats_attr[] = {
5220 &format_attr_event.attr,
5221 &format_attr_umask.attr,
5222 &format_attr_edge.attr,
5223 &format_attr_pc.attr,
5224 &format_attr_any.attr,
5225 &format_attr_inv.attr,
5226 &format_attr_cmask.attr,
5227 NULL,
5228 };
5229
5230 static struct attribute *hsw_format_attr[] = {
5231 &format_attr_in_tx.attr,
5232 &format_attr_in_tx_cp.attr,
5233 &format_attr_offcore_rsp.attr,
5234 &format_attr_ldlat.attr,
5235 NULL
5236 };
5237
5238 static struct attribute *nhm_format_attr[] = {
5239 &format_attr_offcore_rsp.attr,
5240 &format_attr_ldlat.attr,
5241 NULL
5242 };
5243
5244 static struct attribute *slm_format_attr[] = {
5245 &format_attr_offcore_rsp.attr,
5246 NULL
5247 };
5248
5249 static struct attribute *cmt_format_attr[] = {
5250 &format_attr_offcore_rsp.attr,
5251 &format_attr_ldlat.attr,
5252 &format_attr_snoop_rsp.attr,
5253 NULL
5254 };
5255
5256 static struct attribute *skl_format_attr[] = {
5257 &format_attr_frontend.attr,
5258 NULL,
5259 };
5260
5261 static __initconst const struct x86_pmu core_pmu = {
5262 .name = "core",
5263 .handle_irq = x86_pmu_handle_irq,
5264 .disable_all = x86_pmu_disable_all,
5265 .enable_all = core_pmu_enable_all,
5266 .enable = core_pmu_enable_event,
5267 .disable = x86_pmu_disable_event,
5268 .hw_config = core_pmu_hw_config,
5269 .schedule_events = x86_schedule_events,
5270 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
5271 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
5272 .fixedctr = MSR_ARCH_PERFMON_FIXED_CTR0,
5273 .event_map = intel_pmu_event_map,
5274 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
5275 .apic = 1,
5276 .large_pebs_flags = LARGE_PEBS_FLAGS,
5277
5278 /*
5279 * Intel PMCs cannot be accessed sanely above 32-bit width,
5280 * so we install an artificial 1<<31 period regardless of
5281 * the generic event period:
5282 */
5283 .max_period = (1ULL<<31) - 1,
5284 .get_event_constraints = intel_get_event_constraints,
5285 .put_event_constraints = intel_put_event_constraints,
5286 .event_constraints = intel_core_event_constraints,
5287 .guest_get_msrs = core_guest_get_msrs,
5288 .format_attrs = intel_arch_formats_attr,
5289 .events_sysfs_show = intel_event_sysfs_show,
5290
5291 /*
5292 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
5293 * together with PMU version 1 and thus be using core_pmu with
5294 * shared_regs. We need following callbacks here to allocate
5295 * it properly.
5296 */
5297 .cpu_prepare = intel_pmu_cpu_prepare,
5298 .cpu_starting = intel_pmu_cpu_starting,
5299 .cpu_dying = intel_pmu_cpu_dying,
5300 .cpu_dead = intel_pmu_cpu_dead,
5301
5302 .check_period = intel_pmu_check_period,
5303
5304 .lbr_reset = intel_pmu_lbr_reset_64,
5305 .lbr_read = intel_pmu_lbr_read_64,
5306 .lbr_save = intel_pmu_lbr_save,
5307 .lbr_restore = intel_pmu_lbr_restore,
5308 };
5309
5310 static __initconst const struct x86_pmu intel_pmu = {
5311 .name = "Intel",
5312 .handle_irq = intel_pmu_handle_irq,
5313 .disable_all = intel_pmu_disable_all,
5314 .enable_all = intel_pmu_enable_all,
5315 .enable = intel_pmu_enable_event,
5316 .disable = intel_pmu_disable_event,
5317 .add = intel_pmu_add_event,
5318 .del = intel_pmu_del_event,
5319 .read = intel_pmu_read_event,
5320 .set_period = intel_pmu_set_period,
5321 .update = intel_pmu_update,
5322 .hw_config = intel_pmu_hw_config,
5323 .schedule_events = x86_schedule_events,
5324 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
5325 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
5326 .fixedctr = MSR_ARCH_PERFMON_FIXED_CTR0,
5327 .event_map = intel_pmu_event_map,
5328 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
5329 .apic = 1,
5330 .large_pebs_flags = LARGE_PEBS_FLAGS,
5331 /*
5332 * Intel PMCs cannot be accessed sanely above 32 bit width,
5333 * so we install an artificial 1<<31 period regardless of
5334 * the generic event period:
5335 */
5336 .max_period = (1ULL << 31) - 1,
5337 .get_event_constraints = intel_get_event_constraints,
5338 .put_event_constraints = intel_put_event_constraints,
5339 .pebs_aliases = intel_pebs_aliases_core2,
5340
5341 .format_attrs = intel_arch3_formats_attr,
5342 .events_sysfs_show = intel_event_sysfs_show,
5343
5344 .cpu_prepare = intel_pmu_cpu_prepare,
5345 .cpu_starting = intel_pmu_cpu_starting,
5346 .cpu_dying = intel_pmu_cpu_dying,
5347 .cpu_dead = intel_pmu_cpu_dead,
5348
5349 .guest_get_msrs = intel_guest_get_msrs,
5350 .sched_task = intel_pmu_sched_task,
5351 .swap_task_ctx = intel_pmu_swap_task_ctx,
5352
5353 .check_period = intel_pmu_check_period,
5354
5355 .aux_output_match = intel_pmu_aux_output_match,
5356
5357 .lbr_reset = intel_pmu_lbr_reset_64,
5358 .lbr_read = intel_pmu_lbr_read_64,
5359 .lbr_save = intel_pmu_lbr_save,
5360 .lbr_restore = intel_pmu_lbr_restore,
5361
5362 /*
5363 * SMM has access to all 4 rings and while traditionally SMM code only
5364 * ran in CPL0, 2021-era firmware is starting to make use of CPL3 in SMM.
5365 *
5366 * Since the EVENTSEL.{USR,OS} CPL filtering makes no distinction
5367 * between SMM or not, this results in what should be pure userspace
5368 * counters including SMM data.
5369 *
5370 * This is a clear privilege issue, therefore globally disable
5371 * counting SMM by default.
5372 */
5373 .attr_freeze_on_smi = 1,
5374 };
5375
intel_clovertown_quirk(void)5376 static __init void intel_clovertown_quirk(void)
5377 {
5378 /*
5379 * PEBS is unreliable due to:
5380 *
5381 * AJ67 - PEBS may experience CPL leaks
5382 * AJ68 - PEBS PMI may be delayed by one event
5383 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
5384 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
5385 *
5386 * AJ67 could be worked around by restricting the OS/USR flags.
5387 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
5388 *
5389 * AJ106 could possibly be worked around by not allowing LBR
5390 * usage from PEBS, including the fixup.
5391 * AJ68 could possibly be worked around by always programming
5392 * a pebs_event_reset[0] value and coping with the lost events.
5393 *
5394 * But taken together it might just make sense to not enable PEBS on
5395 * these chips.
5396 */
5397 pr_warn("PEBS disabled due to CPU errata\n");
5398 x86_pmu.pebs = 0;
5399 x86_pmu.pebs_constraints = NULL;
5400 }
5401
5402 static const struct x86_cpu_id isolation_ucodes[] = {
5403 X86_MATCH_VFM_STEPS(INTEL_HASWELL, 3, 3, 0x0000001f),
5404 X86_MATCH_VFM_STEPS(INTEL_HASWELL_L, 1, 1, 0x0000001e),
5405 X86_MATCH_VFM_STEPS(INTEL_HASWELL_G, 1, 1, 0x00000015),
5406 X86_MATCH_VFM_STEPS(INTEL_HASWELL_X, 2, 2, 0x00000037),
5407 X86_MATCH_VFM_STEPS(INTEL_HASWELL_X, 4, 4, 0x0000000a),
5408 X86_MATCH_VFM_STEPS(INTEL_BROADWELL, 4, 4, 0x00000023),
5409 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_G, 1, 1, 0x00000014),
5410 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 2, 2, 0x00000010),
5411 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 3, 3, 0x07000009),
5412 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 4, 4, 0x0f000009),
5413 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 5, 5, 0x0e000002),
5414 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_X, 1, 1, 0x0b000014),
5415 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 3, 3, 0x00000021),
5416 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 4, 7, 0x00000000),
5417 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 11, 11, 0x00000000),
5418 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_L, 3, 3, 0x0000007c),
5419 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE, 3, 3, 0x0000007c),
5420 X86_MATCH_VFM_STEPS(INTEL_KABYLAKE, 9, 13, 0x0000004e),
5421 X86_MATCH_VFM_STEPS(INTEL_KABYLAKE_L, 9, 12, 0x0000004e),
5422 {}
5423 };
5424
intel_check_pebs_isolation(void)5425 static void intel_check_pebs_isolation(void)
5426 {
5427 x86_pmu.pebs_no_isolation = !x86_match_min_microcode_rev(isolation_ucodes);
5428 }
5429
intel_pebs_isolation_quirk(void)5430 static __init void intel_pebs_isolation_quirk(void)
5431 {
5432 WARN_ON_ONCE(x86_pmu.check_microcode);
5433 x86_pmu.check_microcode = intel_check_pebs_isolation;
5434 intel_check_pebs_isolation();
5435 }
5436
5437 static const struct x86_cpu_id pebs_ucodes[] = {
5438 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE, 7, 7, 0x00000028),
5439 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE_X, 6, 6, 0x00000618),
5440 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE_X, 7, 7, 0x0000070c),
5441 {}
5442 };
5443
intel_snb_pebs_broken(void)5444 static bool intel_snb_pebs_broken(void)
5445 {
5446 return !x86_match_min_microcode_rev(pebs_ucodes);
5447 }
5448
intel_snb_check_microcode(void)5449 static void intel_snb_check_microcode(void)
5450 {
5451 if (intel_snb_pebs_broken() == x86_pmu.pebs_broken)
5452 return;
5453
5454 /*
5455 * Serialized by the microcode lock..
5456 */
5457 if (x86_pmu.pebs_broken) {
5458 pr_info("PEBS enabled due to microcode update\n");
5459 x86_pmu.pebs_broken = 0;
5460 } else {
5461 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
5462 x86_pmu.pebs_broken = 1;
5463 }
5464 }
5465
is_lbr_from(unsigned long msr)5466 static bool is_lbr_from(unsigned long msr)
5467 {
5468 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr;
5469
5470 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr;
5471 }
5472
5473 /*
5474 * Under certain circumstances, access certain MSR may cause #GP.
5475 * The function tests if the input MSR can be safely accessed.
5476 */
check_msr(unsigned long msr,u64 mask)5477 static bool check_msr(unsigned long msr, u64 mask)
5478 {
5479 u64 val_old, val_new, val_tmp;
5480
5481 /*
5482 * Disable the check for real HW, so we don't
5483 * mess with potentially enabled registers:
5484 */
5485 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR))
5486 return true;
5487
5488 /*
5489 * Read the current value, change it and read it back to see if it
5490 * matches, this is needed to detect certain hardware emulators
5491 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
5492 */
5493 if (rdmsrl_safe(msr, &val_old))
5494 return false;
5495
5496 /*
5497 * Only change the bits which can be updated by wrmsrl.
5498 */
5499 val_tmp = val_old ^ mask;
5500
5501 if (is_lbr_from(msr))
5502 val_tmp = lbr_from_signext_quirk_wr(val_tmp);
5503
5504 if (wrmsrl_safe(msr, val_tmp) ||
5505 rdmsrl_safe(msr, &val_new))
5506 return false;
5507
5508 /*
5509 * Quirk only affects validation in wrmsr(), so wrmsrl()'s value
5510 * should equal rdmsrl()'s even with the quirk.
5511 */
5512 if (val_new != val_tmp)
5513 return false;
5514
5515 if (is_lbr_from(msr))
5516 val_old = lbr_from_signext_quirk_wr(val_old);
5517
5518 /* Here it's sure that the MSR can be safely accessed.
5519 * Restore the old value and return.
5520 */
5521 wrmsrl(msr, val_old);
5522
5523 return true;
5524 }
5525
intel_sandybridge_quirk(void)5526 static __init void intel_sandybridge_quirk(void)
5527 {
5528 x86_pmu.check_microcode = intel_snb_check_microcode;
5529 cpus_read_lock();
5530 intel_snb_check_microcode();
5531 cpus_read_unlock();
5532 }
5533
5534 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
5535 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
5536 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
5537 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
5538 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
5539 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
5540 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
5541 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
5542 };
5543
intel_arch_events_quirk(void)5544 static __init void intel_arch_events_quirk(void)
5545 {
5546 int bit;
5547
5548 /* disable event that reported as not present by cpuid */
5549 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
5550 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
5551 pr_warn("CPUID marked event: \'%s\' unavailable\n",
5552 intel_arch_events_map[bit].name);
5553 }
5554 }
5555
intel_nehalem_quirk(void)5556 static __init void intel_nehalem_quirk(void)
5557 {
5558 union cpuid10_ebx ebx;
5559
5560 ebx.full = x86_pmu.events_maskl;
5561 if (ebx.split.no_branch_misses_retired) {
5562 /*
5563 * Erratum AAJ80 detected, we work it around by using
5564 * the BR_MISP_EXEC.ANY event. This will over-count
5565 * branch-misses, but it's still much better than the
5566 * architectural event which is often completely bogus:
5567 */
5568 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
5569 ebx.split.no_branch_misses_retired = 0;
5570 x86_pmu.events_maskl = ebx.full;
5571 pr_info("CPU erratum AAJ80 worked around\n");
5572 }
5573 }
5574
5575 /*
5576 * enable software workaround for errata:
5577 * SNB: BJ122
5578 * IVB: BV98
5579 * HSW: HSD29
5580 *
5581 * Only needed when HT is enabled. However detecting
5582 * if HT is enabled is difficult (model specific). So instead,
5583 * we enable the workaround in the early boot, and verify if
5584 * it is needed in a later initcall phase once we have valid
5585 * topology information to check if HT is actually enabled
5586 */
intel_ht_bug(void)5587 static __init void intel_ht_bug(void)
5588 {
5589 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
5590
5591 x86_pmu.start_scheduling = intel_start_scheduling;
5592 x86_pmu.commit_scheduling = intel_commit_scheduling;
5593 x86_pmu.stop_scheduling = intel_stop_scheduling;
5594 }
5595
5596 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
5597 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
5598
5599 /* Haswell special events */
5600 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1");
5601 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2");
5602 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4");
5603 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2");
5604 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1");
5605 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1");
5606 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2");
5607 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4");
5608 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2");
5609 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1");
5610 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
5611 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
5612
5613 static struct attribute *hsw_events_attrs[] = {
5614 EVENT_PTR(td_slots_issued),
5615 EVENT_PTR(td_slots_retired),
5616 EVENT_PTR(td_fetch_bubbles),
5617 EVENT_PTR(td_total_slots),
5618 EVENT_PTR(td_total_slots_scale),
5619 EVENT_PTR(td_recovery_bubbles),
5620 EVENT_PTR(td_recovery_bubbles_scale),
5621 NULL
5622 };
5623
5624 static struct attribute *hsw_mem_events_attrs[] = {
5625 EVENT_PTR(mem_ld_hsw),
5626 EVENT_PTR(mem_st_hsw),
5627 NULL,
5628 };
5629
5630 static struct attribute *hsw_tsx_events_attrs[] = {
5631 EVENT_PTR(tx_start),
5632 EVENT_PTR(tx_commit),
5633 EVENT_PTR(tx_abort),
5634 EVENT_PTR(tx_capacity),
5635 EVENT_PTR(tx_conflict),
5636 EVENT_PTR(el_start),
5637 EVENT_PTR(el_commit),
5638 EVENT_PTR(el_abort),
5639 EVENT_PTR(el_capacity),
5640 EVENT_PTR(el_conflict),
5641 EVENT_PTR(cycles_t),
5642 EVENT_PTR(cycles_ct),
5643 NULL
5644 };
5645
5646 EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80");
5647 EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2");
5648 EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80");
5649 EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2");
5650
5651 static struct attribute *icl_events_attrs[] = {
5652 EVENT_PTR(mem_ld_hsw),
5653 EVENT_PTR(mem_st_hsw),
5654 NULL,
5655 };
5656
5657 static struct attribute *icl_td_events_attrs[] = {
5658 EVENT_PTR(slots),
5659 EVENT_PTR(td_retiring),
5660 EVENT_PTR(td_bad_spec),
5661 EVENT_PTR(td_fe_bound),
5662 EVENT_PTR(td_be_bound),
5663 NULL,
5664 };
5665
5666 static struct attribute *icl_tsx_events_attrs[] = {
5667 EVENT_PTR(tx_start),
5668 EVENT_PTR(tx_abort),
5669 EVENT_PTR(tx_commit),
5670 EVENT_PTR(tx_capacity_read),
5671 EVENT_PTR(tx_capacity_write),
5672 EVENT_PTR(tx_conflict),
5673 EVENT_PTR(el_start),
5674 EVENT_PTR(el_abort),
5675 EVENT_PTR(el_commit),
5676 EVENT_PTR(el_capacity_read),
5677 EVENT_PTR(el_capacity_write),
5678 EVENT_PTR(el_conflict),
5679 EVENT_PTR(cycles_t),
5680 EVENT_PTR(cycles_ct),
5681 NULL,
5682 };
5683
5684
5685 EVENT_ATTR_STR(mem-stores, mem_st_spr, "event=0xcd,umask=0x2");
5686 EVENT_ATTR_STR(mem-loads-aux, mem_ld_aux, "event=0x03,umask=0x82");
5687
5688 static struct attribute *glc_events_attrs[] = {
5689 EVENT_PTR(mem_ld_hsw),
5690 EVENT_PTR(mem_st_spr),
5691 EVENT_PTR(mem_ld_aux),
5692 NULL,
5693 };
5694
5695 static struct attribute *glc_td_events_attrs[] = {
5696 EVENT_PTR(slots),
5697 EVENT_PTR(td_retiring),
5698 EVENT_PTR(td_bad_spec),
5699 EVENT_PTR(td_fe_bound),
5700 EVENT_PTR(td_be_bound),
5701 EVENT_PTR(td_heavy_ops),
5702 EVENT_PTR(td_br_mispredict),
5703 EVENT_PTR(td_fetch_lat),
5704 EVENT_PTR(td_mem_bound),
5705 NULL,
5706 };
5707
5708 static struct attribute *glc_tsx_events_attrs[] = {
5709 EVENT_PTR(tx_start),
5710 EVENT_PTR(tx_abort),
5711 EVENT_PTR(tx_commit),
5712 EVENT_PTR(tx_capacity_read),
5713 EVENT_PTR(tx_capacity_write),
5714 EVENT_PTR(tx_conflict),
5715 EVENT_PTR(cycles_t),
5716 EVENT_PTR(cycles_ct),
5717 NULL,
5718 };
5719
freeze_on_smi_show(struct device * cdev,struct device_attribute * attr,char * buf)5720 static ssize_t freeze_on_smi_show(struct device *cdev,
5721 struct device_attribute *attr,
5722 char *buf)
5723 {
5724 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi);
5725 }
5726
5727 static DEFINE_MUTEX(freeze_on_smi_mutex);
5728
freeze_on_smi_store(struct device * cdev,struct device_attribute * attr,const char * buf,size_t count)5729 static ssize_t freeze_on_smi_store(struct device *cdev,
5730 struct device_attribute *attr,
5731 const char *buf, size_t count)
5732 {
5733 unsigned long val;
5734 ssize_t ret;
5735
5736 ret = kstrtoul(buf, 0, &val);
5737 if (ret)
5738 return ret;
5739
5740 if (val > 1)
5741 return -EINVAL;
5742
5743 mutex_lock(&freeze_on_smi_mutex);
5744
5745 if (x86_pmu.attr_freeze_on_smi == val)
5746 goto done;
5747
5748 x86_pmu.attr_freeze_on_smi = val;
5749
5750 cpus_read_lock();
5751 on_each_cpu(flip_smm_bit, &val, 1);
5752 cpus_read_unlock();
5753 done:
5754 mutex_unlock(&freeze_on_smi_mutex);
5755
5756 return count;
5757 }
5758
update_tfa_sched(void * ignored)5759 static void update_tfa_sched(void *ignored)
5760 {
5761 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
5762
5763 /*
5764 * check if PMC3 is used
5765 * and if so force schedule out for all event types all contexts
5766 */
5767 if (test_bit(3, cpuc->active_mask))
5768 perf_pmu_resched(x86_get_pmu(smp_processor_id()));
5769 }
5770
show_sysctl_tfa(struct device * cdev,struct device_attribute * attr,char * buf)5771 static ssize_t show_sysctl_tfa(struct device *cdev,
5772 struct device_attribute *attr,
5773 char *buf)
5774 {
5775 return snprintf(buf, 40, "%d\n", allow_tsx_force_abort);
5776 }
5777
set_sysctl_tfa(struct device * cdev,struct device_attribute * attr,const char * buf,size_t count)5778 static ssize_t set_sysctl_tfa(struct device *cdev,
5779 struct device_attribute *attr,
5780 const char *buf, size_t count)
5781 {
5782 bool val;
5783 ssize_t ret;
5784
5785 ret = kstrtobool(buf, &val);
5786 if (ret)
5787 return ret;
5788
5789 /* no change */
5790 if (val == allow_tsx_force_abort)
5791 return count;
5792
5793 allow_tsx_force_abort = val;
5794
5795 cpus_read_lock();
5796 on_each_cpu(update_tfa_sched, NULL, 1);
5797 cpus_read_unlock();
5798
5799 return count;
5800 }
5801
5802
5803 static DEVICE_ATTR_RW(freeze_on_smi);
5804
branches_show(struct device * cdev,struct device_attribute * attr,char * buf)5805 static ssize_t branches_show(struct device *cdev,
5806 struct device_attribute *attr,
5807 char *buf)
5808 {
5809 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr);
5810 }
5811
5812 static DEVICE_ATTR_RO(branches);
5813
branch_counter_nr_show(struct device * cdev,struct device_attribute * attr,char * buf)5814 static ssize_t branch_counter_nr_show(struct device *cdev,
5815 struct device_attribute *attr,
5816 char *buf)
5817 {
5818 return snprintf(buf, PAGE_SIZE, "%d\n", fls(x86_pmu.lbr_counters));
5819 }
5820
5821 static DEVICE_ATTR_RO(branch_counter_nr);
5822
branch_counter_width_show(struct device * cdev,struct device_attribute * attr,char * buf)5823 static ssize_t branch_counter_width_show(struct device *cdev,
5824 struct device_attribute *attr,
5825 char *buf)
5826 {
5827 return snprintf(buf, PAGE_SIZE, "%d\n", LBR_INFO_BR_CNTR_BITS);
5828 }
5829
5830 static DEVICE_ATTR_RO(branch_counter_width);
5831
5832 static struct attribute *lbr_attrs[] = {
5833 &dev_attr_branches.attr,
5834 &dev_attr_branch_counter_nr.attr,
5835 &dev_attr_branch_counter_width.attr,
5836 NULL
5837 };
5838
5839 static umode_t
lbr_is_visible(struct kobject * kobj,struct attribute * attr,int i)5840 lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5841 {
5842 /* branches */
5843 if (i == 0)
5844 return x86_pmu.lbr_nr ? attr->mode : 0;
5845
5846 return (x86_pmu.flags & PMU_FL_BR_CNTR) ? attr->mode : 0;
5847 }
5848
5849 static char pmu_name_str[30];
5850
5851 static DEVICE_STRING_ATTR_RO(pmu_name, 0444, pmu_name_str);
5852
5853 static struct attribute *intel_pmu_caps_attrs[] = {
5854 &dev_attr_pmu_name.attr.attr,
5855 NULL
5856 };
5857
5858 static DEVICE_ATTR(allow_tsx_force_abort, 0644,
5859 show_sysctl_tfa,
5860 set_sysctl_tfa);
5861
5862 static struct attribute *intel_pmu_attrs[] = {
5863 &dev_attr_freeze_on_smi.attr,
5864 &dev_attr_allow_tsx_force_abort.attr,
5865 NULL,
5866 };
5867
5868 static umode_t
default_is_visible(struct kobject * kobj,struct attribute * attr,int i)5869 default_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5870 {
5871 if (attr == &dev_attr_allow_tsx_force_abort.attr)
5872 return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0;
5873
5874 return attr->mode;
5875 }
5876
5877 static umode_t
tsx_is_visible(struct kobject * kobj,struct attribute * attr,int i)5878 tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5879 {
5880 return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0;
5881 }
5882
5883 static umode_t
pebs_is_visible(struct kobject * kobj,struct attribute * attr,int i)5884 pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5885 {
5886 return x86_pmu.pebs ? attr->mode : 0;
5887 }
5888
5889 static umode_t
mem_is_visible(struct kobject * kobj,struct attribute * attr,int i)5890 mem_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5891 {
5892 if (attr == &event_attr_mem_ld_aux.attr.attr)
5893 return x86_pmu.flags & PMU_FL_MEM_LOADS_AUX ? attr->mode : 0;
5894
5895 return pebs_is_visible(kobj, attr, i);
5896 }
5897
5898 static umode_t
exra_is_visible(struct kobject * kobj,struct attribute * attr,int i)5899 exra_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5900 {
5901 return x86_pmu.version >= 2 ? attr->mode : 0;
5902 }
5903
5904 static umode_t
td_is_visible(struct kobject * kobj,struct attribute * attr,int i)5905 td_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5906 {
5907 /*
5908 * Hide the perf metrics topdown events
5909 * if the feature is not enumerated.
5910 */
5911 if (x86_pmu.num_topdown_events)
5912 return x86_pmu.intel_cap.perf_metrics ? attr->mode : 0;
5913
5914 return attr->mode;
5915 }
5916
5917 static struct attribute_group group_events_td = {
5918 .name = "events",
5919 .is_visible = td_is_visible,
5920 };
5921
5922 static struct attribute_group group_events_mem = {
5923 .name = "events",
5924 .is_visible = mem_is_visible,
5925 };
5926
5927 static struct attribute_group group_events_tsx = {
5928 .name = "events",
5929 .is_visible = tsx_is_visible,
5930 };
5931
5932 static struct attribute_group group_caps_gen = {
5933 .name = "caps",
5934 .attrs = intel_pmu_caps_attrs,
5935 };
5936
5937 static struct attribute_group group_caps_lbr = {
5938 .name = "caps",
5939 .attrs = lbr_attrs,
5940 .is_visible = lbr_is_visible,
5941 };
5942
5943 static struct attribute_group group_format_extra = {
5944 .name = "format",
5945 .is_visible = exra_is_visible,
5946 };
5947
5948 static struct attribute_group group_format_extra_skl = {
5949 .name = "format",
5950 .is_visible = exra_is_visible,
5951 };
5952
5953 static struct attribute_group group_format_evtsel_ext = {
5954 .name = "format",
5955 .attrs = format_evtsel_ext_attrs,
5956 .is_visible = evtsel_ext_is_visible,
5957 };
5958
5959 static struct attribute_group group_default = {
5960 .attrs = intel_pmu_attrs,
5961 .is_visible = default_is_visible,
5962 };
5963
5964 static const struct attribute_group *attr_update[] = {
5965 &group_events_td,
5966 &group_events_mem,
5967 &group_events_tsx,
5968 &group_caps_gen,
5969 &group_caps_lbr,
5970 &group_format_extra,
5971 &group_format_extra_skl,
5972 &group_format_evtsel_ext,
5973 &group_default,
5974 NULL,
5975 };
5976
5977 EVENT_ATTR_STR_HYBRID(slots, slots_adl, "event=0x00,umask=0x4", hybrid_big);
5978 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_adl, "event=0xc2,umask=0x0;event=0x00,umask=0x80", hybrid_big_small);
5979 EVENT_ATTR_STR_HYBRID(topdown-bad-spec, td_bad_spec_adl, "event=0x73,umask=0x0;event=0x00,umask=0x81", hybrid_big_small);
5980 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_adl, "event=0x71,umask=0x0;event=0x00,umask=0x82", hybrid_big_small);
5981 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_adl, "event=0x74,umask=0x0;event=0x00,umask=0x83", hybrid_big_small);
5982 EVENT_ATTR_STR_HYBRID(topdown-heavy-ops, td_heavy_ops_adl, "event=0x00,umask=0x84", hybrid_big);
5983 EVENT_ATTR_STR_HYBRID(topdown-br-mispredict, td_br_mis_adl, "event=0x00,umask=0x85", hybrid_big);
5984 EVENT_ATTR_STR_HYBRID(topdown-fetch-lat, td_fetch_lat_adl, "event=0x00,umask=0x86", hybrid_big);
5985 EVENT_ATTR_STR_HYBRID(topdown-mem-bound, td_mem_bound_adl, "event=0x00,umask=0x87", hybrid_big);
5986
5987 static struct attribute *adl_hybrid_events_attrs[] = {
5988 EVENT_PTR(slots_adl),
5989 EVENT_PTR(td_retiring_adl),
5990 EVENT_PTR(td_bad_spec_adl),
5991 EVENT_PTR(td_fe_bound_adl),
5992 EVENT_PTR(td_be_bound_adl),
5993 EVENT_PTR(td_heavy_ops_adl),
5994 EVENT_PTR(td_br_mis_adl),
5995 EVENT_PTR(td_fetch_lat_adl),
5996 EVENT_PTR(td_mem_bound_adl),
5997 NULL,
5998 };
5999
6000 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_lnl, "event=0xc2,umask=0x02;event=0x00,umask=0x80", hybrid_big_small);
6001 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_lnl, "event=0x9c,umask=0x01;event=0x00,umask=0x82", hybrid_big_small);
6002 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_lnl, "event=0xa4,umask=0x02;event=0x00,umask=0x83", hybrid_big_small);
6003
6004 static struct attribute *lnl_hybrid_events_attrs[] = {
6005 EVENT_PTR(slots_adl),
6006 EVENT_PTR(td_retiring_lnl),
6007 EVENT_PTR(td_bad_spec_adl),
6008 EVENT_PTR(td_fe_bound_lnl),
6009 EVENT_PTR(td_be_bound_lnl),
6010 EVENT_PTR(td_heavy_ops_adl),
6011 EVENT_PTR(td_br_mis_adl),
6012 EVENT_PTR(td_fetch_lat_adl),
6013 EVENT_PTR(td_mem_bound_adl),
6014 NULL
6015 };
6016
6017 /* The event string must be in PMU IDX order. */
6018 EVENT_ATTR_STR_HYBRID(topdown-retiring,
6019 td_retiring_arl_h,
6020 "event=0xc2,umask=0x02;event=0x00,umask=0x80;event=0xc2,umask=0x0",
6021 hybrid_big_small_tiny);
6022 EVENT_ATTR_STR_HYBRID(topdown-bad-spec,
6023 td_bad_spec_arl_h,
6024 "event=0x73,umask=0x0;event=0x00,umask=0x81;event=0x73,umask=0x0",
6025 hybrid_big_small_tiny);
6026 EVENT_ATTR_STR_HYBRID(topdown-fe-bound,
6027 td_fe_bound_arl_h,
6028 "event=0x9c,umask=0x01;event=0x00,umask=0x82;event=0x71,umask=0x0",
6029 hybrid_big_small_tiny);
6030 EVENT_ATTR_STR_HYBRID(topdown-be-bound,
6031 td_be_bound_arl_h,
6032 "event=0xa4,umask=0x02;event=0x00,umask=0x83;event=0x74,umask=0x0",
6033 hybrid_big_small_tiny);
6034
6035 static struct attribute *arl_h_hybrid_events_attrs[] = {
6036 EVENT_PTR(slots_adl),
6037 EVENT_PTR(td_retiring_arl_h),
6038 EVENT_PTR(td_bad_spec_arl_h),
6039 EVENT_PTR(td_fe_bound_arl_h),
6040 EVENT_PTR(td_be_bound_arl_h),
6041 EVENT_PTR(td_heavy_ops_adl),
6042 EVENT_PTR(td_br_mis_adl),
6043 EVENT_PTR(td_fetch_lat_adl),
6044 EVENT_PTR(td_mem_bound_adl),
6045 NULL,
6046 };
6047
6048 /* Must be in IDX order */
6049 EVENT_ATTR_STR_HYBRID(mem-loads, mem_ld_adl, "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3", hybrid_big_small);
6050 EVENT_ATTR_STR_HYBRID(mem-stores, mem_st_adl, "event=0xd0,umask=0x6;event=0xcd,umask=0x2", hybrid_big_small);
6051 EVENT_ATTR_STR_HYBRID(mem-loads-aux, mem_ld_aux_adl, "event=0x03,umask=0x82", hybrid_big);
6052
6053 static struct attribute *adl_hybrid_mem_attrs[] = {
6054 EVENT_PTR(mem_ld_adl),
6055 EVENT_PTR(mem_st_adl),
6056 EVENT_PTR(mem_ld_aux_adl),
6057 NULL,
6058 };
6059
6060 static struct attribute *mtl_hybrid_mem_attrs[] = {
6061 EVENT_PTR(mem_ld_adl),
6062 EVENT_PTR(mem_st_adl),
6063 NULL
6064 };
6065
6066 EVENT_ATTR_STR_HYBRID(mem-loads,
6067 mem_ld_arl_h,
6068 "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3;event=0xd0,umask=0x5,ldlat=3",
6069 hybrid_big_small_tiny);
6070 EVENT_ATTR_STR_HYBRID(mem-stores,
6071 mem_st_arl_h,
6072 "event=0xd0,umask=0x6;event=0xcd,umask=0x2;event=0xd0,umask=0x6",
6073 hybrid_big_small_tiny);
6074
6075 static struct attribute *arl_h_hybrid_mem_attrs[] = {
6076 EVENT_PTR(mem_ld_arl_h),
6077 EVENT_PTR(mem_st_arl_h),
6078 NULL,
6079 };
6080
6081 EVENT_ATTR_STR_HYBRID(tx-start, tx_start_adl, "event=0xc9,umask=0x1", hybrid_big);
6082 EVENT_ATTR_STR_HYBRID(tx-commit, tx_commit_adl, "event=0xc9,umask=0x2", hybrid_big);
6083 EVENT_ATTR_STR_HYBRID(tx-abort, tx_abort_adl, "event=0xc9,umask=0x4", hybrid_big);
6084 EVENT_ATTR_STR_HYBRID(tx-conflict, tx_conflict_adl, "event=0x54,umask=0x1", hybrid_big);
6085 EVENT_ATTR_STR_HYBRID(cycles-t, cycles_t_adl, "event=0x3c,in_tx=1", hybrid_big);
6086 EVENT_ATTR_STR_HYBRID(cycles-ct, cycles_ct_adl, "event=0x3c,in_tx=1,in_tx_cp=1", hybrid_big);
6087 EVENT_ATTR_STR_HYBRID(tx-capacity-read, tx_capacity_read_adl, "event=0x54,umask=0x80", hybrid_big);
6088 EVENT_ATTR_STR_HYBRID(tx-capacity-write, tx_capacity_write_adl, "event=0x54,umask=0x2", hybrid_big);
6089
6090 static struct attribute *adl_hybrid_tsx_attrs[] = {
6091 EVENT_PTR(tx_start_adl),
6092 EVENT_PTR(tx_abort_adl),
6093 EVENT_PTR(tx_commit_adl),
6094 EVENT_PTR(tx_capacity_read_adl),
6095 EVENT_PTR(tx_capacity_write_adl),
6096 EVENT_PTR(tx_conflict_adl),
6097 EVENT_PTR(cycles_t_adl),
6098 EVENT_PTR(cycles_ct_adl),
6099 NULL,
6100 };
6101
6102 FORMAT_ATTR_HYBRID(in_tx, hybrid_big);
6103 FORMAT_ATTR_HYBRID(in_tx_cp, hybrid_big);
6104 FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small_tiny);
6105 FORMAT_ATTR_HYBRID(ldlat, hybrid_big_small_tiny);
6106 FORMAT_ATTR_HYBRID(frontend, hybrid_big);
6107
6108 #define ADL_HYBRID_RTM_FORMAT_ATTR \
6109 FORMAT_HYBRID_PTR(in_tx), \
6110 FORMAT_HYBRID_PTR(in_tx_cp)
6111
6112 #define ADL_HYBRID_FORMAT_ATTR \
6113 FORMAT_HYBRID_PTR(offcore_rsp), \
6114 FORMAT_HYBRID_PTR(ldlat), \
6115 FORMAT_HYBRID_PTR(frontend)
6116
6117 static struct attribute *adl_hybrid_extra_attr_rtm[] = {
6118 ADL_HYBRID_RTM_FORMAT_ATTR,
6119 ADL_HYBRID_FORMAT_ATTR,
6120 NULL
6121 };
6122
6123 static struct attribute *adl_hybrid_extra_attr[] = {
6124 ADL_HYBRID_FORMAT_ATTR,
6125 NULL
6126 };
6127
6128 FORMAT_ATTR_HYBRID(snoop_rsp, hybrid_small_tiny);
6129
6130 static struct attribute *mtl_hybrid_extra_attr_rtm[] = {
6131 ADL_HYBRID_RTM_FORMAT_ATTR,
6132 ADL_HYBRID_FORMAT_ATTR,
6133 FORMAT_HYBRID_PTR(snoop_rsp),
6134 NULL
6135 };
6136
6137 static struct attribute *mtl_hybrid_extra_attr[] = {
6138 ADL_HYBRID_FORMAT_ATTR,
6139 FORMAT_HYBRID_PTR(snoop_rsp),
6140 NULL
6141 };
6142
is_attr_for_this_pmu(struct kobject * kobj,struct attribute * attr)6143 static bool is_attr_for_this_pmu(struct kobject *kobj, struct attribute *attr)
6144 {
6145 struct device *dev = kobj_to_dev(kobj);
6146 struct x86_hybrid_pmu *pmu =
6147 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
6148 struct perf_pmu_events_hybrid_attr *pmu_attr =
6149 container_of(attr, struct perf_pmu_events_hybrid_attr, attr.attr);
6150
6151 return pmu->pmu_type & pmu_attr->pmu_type;
6152 }
6153
hybrid_events_is_visible(struct kobject * kobj,struct attribute * attr,int i)6154 static umode_t hybrid_events_is_visible(struct kobject *kobj,
6155 struct attribute *attr, int i)
6156 {
6157 return is_attr_for_this_pmu(kobj, attr) ? attr->mode : 0;
6158 }
6159
hybrid_find_supported_cpu(struct x86_hybrid_pmu * pmu)6160 static inline int hybrid_find_supported_cpu(struct x86_hybrid_pmu *pmu)
6161 {
6162 int cpu = cpumask_first(&pmu->supported_cpus);
6163
6164 return (cpu >= nr_cpu_ids) ? -1 : cpu;
6165 }
6166
hybrid_tsx_is_visible(struct kobject * kobj,struct attribute * attr,int i)6167 static umode_t hybrid_tsx_is_visible(struct kobject *kobj,
6168 struct attribute *attr, int i)
6169 {
6170 struct device *dev = kobj_to_dev(kobj);
6171 struct x86_hybrid_pmu *pmu =
6172 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
6173 int cpu = hybrid_find_supported_cpu(pmu);
6174
6175 return (cpu >= 0) && is_attr_for_this_pmu(kobj, attr) && cpu_has(&cpu_data(cpu), X86_FEATURE_RTM) ? attr->mode : 0;
6176 }
6177
hybrid_format_is_visible(struct kobject * kobj,struct attribute * attr,int i)6178 static umode_t hybrid_format_is_visible(struct kobject *kobj,
6179 struct attribute *attr, int i)
6180 {
6181 struct device *dev = kobj_to_dev(kobj);
6182 struct x86_hybrid_pmu *pmu =
6183 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
6184 struct perf_pmu_format_hybrid_attr *pmu_attr =
6185 container_of(attr, struct perf_pmu_format_hybrid_attr, attr.attr);
6186 int cpu = hybrid_find_supported_cpu(pmu);
6187
6188 return (cpu >= 0) && (pmu->pmu_type & pmu_attr->pmu_type) ? attr->mode : 0;
6189 }
6190
hybrid_td_is_visible(struct kobject * kobj,struct attribute * attr,int i)6191 static umode_t hybrid_td_is_visible(struct kobject *kobj,
6192 struct attribute *attr, int i)
6193 {
6194 struct device *dev = kobj_to_dev(kobj);
6195 struct x86_hybrid_pmu *pmu =
6196 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
6197
6198 if (!is_attr_for_this_pmu(kobj, attr))
6199 return 0;
6200
6201
6202 /* Only the big core supports perf metrics */
6203 if (pmu->pmu_type == hybrid_big)
6204 return pmu->intel_cap.perf_metrics ? attr->mode : 0;
6205
6206 return attr->mode;
6207 }
6208
6209 static struct attribute_group hybrid_group_events_td = {
6210 .name = "events",
6211 .is_visible = hybrid_td_is_visible,
6212 };
6213
6214 static struct attribute_group hybrid_group_events_mem = {
6215 .name = "events",
6216 .is_visible = hybrid_events_is_visible,
6217 };
6218
6219 static struct attribute_group hybrid_group_events_tsx = {
6220 .name = "events",
6221 .is_visible = hybrid_tsx_is_visible,
6222 };
6223
6224 static struct attribute_group hybrid_group_format_extra = {
6225 .name = "format",
6226 .is_visible = hybrid_format_is_visible,
6227 };
6228
intel_hybrid_get_attr_cpus(struct device * dev,struct device_attribute * attr,char * buf)6229 static ssize_t intel_hybrid_get_attr_cpus(struct device *dev,
6230 struct device_attribute *attr,
6231 char *buf)
6232 {
6233 struct x86_hybrid_pmu *pmu =
6234 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
6235
6236 return cpumap_print_to_pagebuf(true, buf, &pmu->supported_cpus);
6237 }
6238
6239 static DEVICE_ATTR(cpus, S_IRUGO, intel_hybrid_get_attr_cpus, NULL);
6240 static struct attribute *intel_hybrid_cpus_attrs[] = {
6241 &dev_attr_cpus.attr,
6242 NULL,
6243 };
6244
6245 static struct attribute_group hybrid_group_cpus = {
6246 .attrs = intel_hybrid_cpus_attrs,
6247 };
6248
6249 static const struct attribute_group *hybrid_attr_update[] = {
6250 &hybrid_group_events_td,
6251 &hybrid_group_events_mem,
6252 &hybrid_group_events_tsx,
6253 &group_caps_gen,
6254 &group_caps_lbr,
6255 &hybrid_group_format_extra,
6256 &group_format_evtsel_ext,
6257 &group_default,
6258 &hybrid_group_cpus,
6259 NULL,
6260 };
6261
6262 static struct attribute *empty_attrs;
6263
intel_pmu_check_event_constraints(struct event_constraint * event_constraints,u64 cntr_mask,u64 fixed_cntr_mask,u64 intel_ctrl)6264 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints,
6265 u64 cntr_mask,
6266 u64 fixed_cntr_mask,
6267 u64 intel_ctrl)
6268 {
6269 struct event_constraint *c;
6270
6271 if (!event_constraints)
6272 return;
6273
6274 /*
6275 * event on fixed counter2 (REF_CYCLES) only works on this
6276 * counter, so do not extend mask to generic counters
6277 */
6278 for_each_event_constraint(c, event_constraints) {
6279 /*
6280 * Don't extend the topdown slots and metrics
6281 * events to the generic counters.
6282 */
6283 if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) {
6284 /*
6285 * Disable topdown slots and metrics events,
6286 * if slots event is not in CPUID.
6287 */
6288 if (!(INTEL_PMC_MSK_FIXED_SLOTS & intel_ctrl))
6289 c->idxmsk64 = 0;
6290 c->weight = hweight64(c->idxmsk64);
6291 continue;
6292 }
6293
6294 if (c->cmask == FIXED_EVENT_FLAGS) {
6295 /* Disabled fixed counters which are not in CPUID */
6296 c->idxmsk64 &= intel_ctrl;
6297
6298 /*
6299 * Don't extend the pseudo-encoding to the
6300 * generic counters
6301 */
6302 if (!use_fixed_pseudo_encoding(c->code))
6303 c->idxmsk64 |= cntr_mask;
6304 }
6305 c->idxmsk64 &= cntr_mask | (fixed_cntr_mask << INTEL_PMC_IDX_FIXED);
6306 c->weight = hweight64(c->idxmsk64);
6307 }
6308 }
6309
intel_pmu_check_extra_regs(struct extra_reg * extra_regs)6310 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs)
6311 {
6312 struct extra_reg *er;
6313
6314 /*
6315 * Access extra MSR may cause #GP under certain circumstances.
6316 * E.g. KVM doesn't support offcore event
6317 * Check all extra_regs here.
6318 */
6319 if (!extra_regs)
6320 return;
6321
6322 for (er = extra_regs; er->msr; er++) {
6323 er->extra_msr_access = check_msr(er->msr, 0x11UL);
6324 /* Disable LBR select mapping */
6325 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
6326 x86_pmu.lbr_sel_map = NULL;
6327 }
6328 }
6329
intel_pmu_v6_addr_offset(int index,bool eventsel)6330 static inline int intel_pmu_v6_addr_offset(int index, bool eventsel)
6331 {
6332 return MSR_IA32_PMC_V6_STEP * index;
6333 }
6334
6335 static const struct { enum hybrid_pmu_type id; char *name; } intel_hybrid_pmu_type_map[] __initconst = {
6336 { hybrid_small, "cpu_atom" },
6337 { hybrid_big, "cpu_core" },
6338 { hybrid_tiny, "cpu_lowpower" },
6339 };
6340
intel_pmu_init_hybrid(enum hybrid_pmu_type pmus)6341 static __always_inline int intel_pmu_init_hybrid(enum hybrid_pmu_type pmus)
6342 {
6343 unsigned long pmus_mask = pmus;
6344 struct x86_hybrid_pmu *pmu;
6345 int idx = 0, bit;
6346
6347 x86_pmu.num_hybrid_pmus = hweight_long(pmus_mask);
6348 x86_pmu.hybrid_pmu = kcalloc(x86_pmu.num_hybrid_pmus,
6349 sizeof(struct x86_hybrid_pmu),
6350 GFP_KERNEL);
6351 if (!x86_pmu.hybrid_pmu)
6352 return -ENOMEM;
6353
6354 static_branch_enable(&perf_is_hybrid);
6355 x86_pmu.filter = intel_pmu_filter;
6356
6357 for_each_set_bit(bit, &pmus_mask, ARRAY_SIZE(intel_hybrid_pmu_type_map)) {
6358 pmu = &x86_pmu.hybrid_pmu[idx++];
6359 pmu->pmu_type = intel_hybrid_pmu_type_map[bit].id;
6360 pmu->name = intel_hybrid_pmu_type_map[bit].name;
6361
6362 pmu->cntr_mask64 = x86_pmu.cntr_mask64;
6363 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64;
6364 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64);
6365 pmu->config_mask = X86_RAW_EVENT_MASK;
6366 pmu->unconstrained = (struct event_constraint)
6367 __EVENT_CONSTRAINT(0, pmu->cntr_mask64,
6368 0, x86_pmu_num_counters(&pmu->pmu), 0, 0);
6369
6370 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities;
6371 if (pmu->pmu_type & hybrid_small_tiny) {
6372 pmu->intel_cap.perf_metrics = 0;
6373 pmu->intel_cap.pebs_output_pt_available = 1;
6374 pmu->mid_ack = true;
6375 } else if (pmu->pmu_type & hybrid_big) {
6376 pmu->intel_cap.perf_metrics = 1;
6377 pmu->intel_cap.pebs_output_pt_available = 0;
6378 pmu->late_ack = true;
6379 }
6380 }
6381
6382 return 0;
6383 }
6384
intel_pmu_ref_cycles_ext(void)6385 static __always_inline void intel_pmu_ref_cycles_ext(void)
6386 {
6387 if (!(x86_pmu.events_maskl & (INTEL_PMC_MSK_FIXED_REF_CYCLES >> INTEL_PMC_IDX_FIXED)))
6388 intel_perfmon_event_map[PERF_COUNT_HW_REF_CPU_CYCLES] = 0x013c;
6389 }
6390
intel_pmu_init_glc(struct pmu * pmu)6391 static __always_inline void intel_pmu_init_glc(struct pmu *pmu)
6392 {
6393 x86_pmu.late_ack = true;
6394 x86_pmu.limit_period = glc_limit_period;
6395 x86_pmu.pebs_aliases = NULL;
6396 x86_pmu.pebs_prec_dist = true;
6397 x86_pmu.pebs_block = true;
6398 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6399 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6400 x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
6401 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
6402 x86_pmu.lbr_pt_coexist = true;
6403 x86_pmu.num_topdown_events = 8;
6404 static_call_update(intel_pmu_update_topdown_event,
6405 &icl_update_topdown_event);
6406 static_call_update(intel_pmu_set_topdown_event_period,
6407 &icl_set_topdown_event_period);
6408
6409 memcpy(hybrid_var(pmu, hw_cache_event_ids), glc_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6410 memcpy(hybrid_var(pmu, hw_cache_extra_regs), glc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6411 hybrid(pmu, event_constraints) = intel_glc_event_constraints;
6412 hybrid(pmu, pebs_constraints) = intel_glc_pebs_event_constraints;
6413
6414 intel_pmu_ref_cycles_ext();
6415 }
6416
intel_pmu_init_grt(struct pmu * pmu)6417 static __always_inline void intel_pmu_init_grt(struct pmu *pmu)
6418 {
6419 x86_pmu.mid_ack = true;
6420 x86_pmu.limit_period = glc_limit_period;
6421 x86_pmu.pebs_aliases = NULL;
6422 x86_pmu.pebs_prec_dist = true;
6423 x86_pmu.pebs_block = true;
6424 x86_pmu.lbr_pt_coexist = true;
6425 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6426 x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
6427
6428 memcpy(hybrid_var(pmu, hw_cache_event_ids), glp_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6429 memcpy(hybrid_var(pmu, hw_cache_extra_regs), tnt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6430 hybrid_var(pmu, hw_cache_event_ids)[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
6431 hybrid(pmu, event_constraints) = intel_grt_event_constraints;
6432 hybrid(pmu, pebs_constraints) = intel_grt_pebs_event_constraints;
6433 hybrid(pmu, extra_regs) = intel_grt_extra_regs;
6434
6435 intel_pmu_ref_cycles_ext();
6436 }
6437
intel_pmu_init_lnc(struct pmu * pmu)6438 static __always_inline void intel_pmu_init_lnc(struct pmu *pmu)
6439 {
6440 intel_pmu_init_glc(pmu);
6441 hybrid(pmu, event_constraints) = intel_lnc_event_constraints;
6442 hybrid(pmu, pebs_constraints) = intel_lnc_pebs_event_constraints;
6443 hybrid(pmu, extra_regs) = intel_lnc_extra_regs;
6444 }
6445
intel_pmu_init_skt(struct pmu * pmu)6446 static __always_inline void intel_pmu_init_skt(struct pmu *pmu)
6447 {
6448 intel_pmu_init_grt(pmu);
6449 hybrid(pmu, event_constraints) = intel_skt_event_constraints;
6450 hybrid(pmu, extra_regs) = intel_cmt_extra_regs;
6451 }
6452
intel_pmu_init(void)6453 __init int intel_pmu_init(void)
6454 {
6455 struct attribute **extra_skl_attr = &empty_attrs;
6456 struct attribute **extra_attr = &empty_attrs;
6457 struct attribute **td_attr = &empty_attrs;
6458 struct attribute **mem_attr = &empty_attrs;
6459 struct attribute **tsx_attr = &empty_attrs;
6460 union cpuid10_edx edx;
6461 union cpuid10_eax eax;
6462 union cpuid10_ebx ebx;
6463 unsigned int fixed_mask;
6464 bool pmem = false;
6465 int version, i;
6466 char *name;
6467 struct x86_hybrid_pmu *pmu;
6468
6469 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
6470 switch (boot_cpu_data.x86) {
6471 case 0x6:
6472 return p6_pmu_init();
6473 case 0xb:
6474 return knc_pmu_init();
6475 case 0xf:
6476 return p4_pmu_init();
6477 }
6478 return -ENODEV;
6479 }
6480
6481 /*
6482 * Check whether the Architectural PerfMon supports
6483 * Branch Misses Retired hw_event or not.
6484 */
6485 cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full);
6486 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
6487 return -ENODEV;
6488
6489 version = eax.split.version_id;
6490 if (version < 2)
6491 x86_pmu = core_pmu;
6492 else
6493 x86_pmu = intel_pmu;
6494
6495 x86_pmu.version = version;
6496 x86_pmu.cntr_mask64 = GENMASK_ULL(eax.split.num_counters - 1, 0);
6497 x86_pmu.cntval_bits = eax.split.bit_width;
6498 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
6499
6500 x86_pmu.events_maskl = ebx.full;
6501 x86_pmu.events_mask_len = eax.split.mask_length;
6502
6503 x86_pmu.pebs_events_mask = intel_pmu_pebs_mask(x86_pmu.cntr_mask64);
6504 x86_pmu.pebs_capable = PEBS_COUNTER_MASK;
6505
6506 /*
6507 * Quirk: v2 perfmon does not report fixed-purpose events, so
6508 * assume at least 3 events, when not running in a hypervisor:
6509 */
6510 if (version > 1 && version < 5) {
6511 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR);
6512
6513 x86_pmu.fixed_cntr_mask64 =
6514 GENMASK_ULL(max((int)edx.split.num_counters_fixed, assume) - 1, 0);
6515 } else if (version >= 5)
6516 x86_pmu.fixed_cntr_mask64 = fixed_mask;
6517
6518 if (boot_cpu_has(X86_FEATURE_PDCM)) {
6519 u64 capabilities;
6520
6521 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
6522 x86_pmu.intel_cap.capabilities = capabilities;
6523 }
6524
6525 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) {
6526 x86_pmu.lbr_reset = intel_pmu_lbr_reset_32;
6527 x86_pmu.lbr_read = intel_pmu_lbr_read_32;
6528 }
6529
6530 if (boot_cpu_has(X86_FEATURE_ARCH_LBR))
6531 intel_pmu_arch_lbr_init();
6532
6533 intel_ds_init();
6534
6535 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
6536
6537 if (version >= 5) {
6538 x86_pmu.intel_cap.anythread_deprecated = edx.split.anythread_deprecated;
6539 if (x86_pmu.intel_cap.anythread_deprecated)
6540 pr_cont(" AnyThread deprecated, ");
6541 }
6542
6543 /*
6544 * Install the hw-cache-events table:
6545 */
6546 switch (boot_cpu_data.x86_vfm) {
6547 case INTEL_CORE_YONAH:
6548 pr_cont("Core events, ");
6549 name = "core";
6550 break;
6551
6552 case INTEL_CORE2_MEROM:
6553 x86_add_quirk(intel_clovertown_quirk);
6554 fallthrough;
6555
6556 case INTEL_CORE2_MEROM_L:
6557 case INTEL_CORE2_PENRYN:
6558 case INTEL_CORE2_DUNNINGTON:
6559 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
6560 sizeof(hw_cache_event_ids));
6561
6562 intel_pmu_lbr_init_core();
6563
6564 x86_pmu.event_constraints = intel_core2_event_constraints;
6565 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
6566 pr_cont("Core2 events, ");
6567 name = "core2";
6568 break;
6569
6570 case INTEL_NEHALEM:
6571 case INTEL_NEHALEM_EP:
6572 case INTEL_NEHALEM_EX:
6573 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
6574 sizeof(hw_cache_event_ids));
6575 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
6576 sizeof(hw_cache_extra_regs));
6577
6578 intel_pmu_lbr_init_nhm();
6579
6580 x86_pmu.event_constraints = intel_nehalem_event_constraints;
6581 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
6582 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
6583 x86_pmu.extra_regs = intel_nehalem_extra_regs;
6584 x86_pmu.limit_period = nhm_limit_period;
6585
6586 mem_attr = nhm_mem_events_attrs;
6587
6588 /* UOPS_ISSUED.STALLED_CYCLES */
6589 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
6590 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
6591 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
6592 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
6593 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
6594
6595 intel_pmu_pebs_data_source_nhm();
6596 x86_add_quirk(intel_nehalem_quirk);
6597 x86_pmu.pebs_no_tlb = 1;
6598 extra_attr = nhm_format_attr;
6599
6600 pr_cont("Nehalem events, ");
6601 name = "nehalem";
6602 break;
6603
6604 case INTEL_ATOM_BONNELL:
6605 case INTEL_ATOM_BONNELL_MID:
6606 case INTEL_ATOM_SALTWELL:
6607 case INTEL_ATOM_SALTWELL_MID:
6608 case INTEL_ATOM_SALTWELL_TABLET:
6609 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
6610 sizeof(hw_cache_event_ids));
6611
6612 intel_pmu_lbr_init_atom();
6613
6614 x86_pmu.event_constraints = intel_gen_event_constraints;
6615 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
6616 x86_pmu.pebs_aliases = intel_pebs_aliases_core2;
6617 pr_cont("Atom events, ");
6618 name = "bonnell";
6619 break;
6620
6621 case INTEL_ATOM_SILVERMONT:
6622 case INTEL_ATOM_SILVERMONT_D:
6623 case INTEL_ATOM_SILVERMONT_MID:
6624 case INTEL_ATOM_AIRMONT:
6625 case INTEL_ATOM_AIRMONT_MID:
6626 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
6627 sizeof(hw_cache_event_ids));
6628 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
6629 sizeof(hw_cache_extra_regs));
6630
6631 intel_pmu_lbr_init_slm();
6632
6633 x86_pmu.event_constraints = intel_slm_event_constraints;
6634 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
6635 x86_pmu.extra_regs = intel_slm_extra_regs;
6636 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6637 td_attr = slm_events_attrs;
6638 extra_attr = slm_format_attr;
6639 pr_cont("Silvermont events, ");
6640 name = "silvermont";
6641 break;
6642
6643 case INTEL_ATOM_GOLDMONT:
6644 case INTEL_ATOM_GOLDMONT_D:
6645 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
6646 sizeof(hw_cache_event_ids));
6647 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
6648 sizeof(hw_cache_extra_regs));
6649
6650 intel_pmu_lbr_init_skl();
6651
6652 x86_pmu.event_constraints = intel_slm_event_constraints;
6653 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints;
6654 x86_pmu.extra_regs = intel_glm_extra_regs;
6655 /*
6656 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
6657 * for precise cycles.
6658 * :pp is identical to :ppp
6659 */
6660 x86_pmu.pebs_aliases = NULL;
6661 x86_pmu.pebs_prec_dist = true;
6662 x86_pmu.lbr_pt_coexist = true;
6663 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6664 td_attr = glm_events_attrs;
6665 extra_attr = slm_format_attr;
6666 pr_cont("Goldmont events, ");
6667 name = "goldmont";
6668 break;
6669
6670 case INTEL_ATOM_GOLDMONT_PLUS:
6671 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
6672 sizeof(hw_cache_event_ids));
6673 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs,
6674 sizeof(hw_cache_extra_regs));
6675
6676 intel_pmu_lbr_init_skl();
6677
6678 x86_pmu.event_constraints = intel_slm_event_constraints;
6679 x86_pmu.extra_regs = intel_glm_extra_regs;
6680 /*
6681 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
6682 * for precise cycles.
6683 */
6684 x86_pmu.pebs_aliases = NULL;
6685 x86_pmu.pebs_prec_dist = true;
6686 x86_pmu.lbr_pt_coexist = true;
6687 x86_pmu.pebs_capable = ~0ULL;
6688 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6689 x86_pmu.flags |= PMU_FL_PEBS_ALL;
6690 x86_pmu.get_event_constraints = glp_get_event_constraints;
6691 td_attr = glm_events_attrs;
6692 /* Goldmont Plus has 4-wide pipeline */
6693 event_attr_td_total_slots_scale_glm.event_str = "4";
6694 extra_attr = slm_format_attr;
6695 pr_cont("Goldmont plus events, ");
6696 name = "goldmont_plus";
6697 break;
6698
6699 case INTEL_ATOM_TREMONT_D:
6700 case INTEL_ATOM_TREMONT:
6701 case INTEL_ATOM_TREMONT_L:
6702 x86_pmu.late_ack = true;
6703 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
6704 sizeof(hw_cache_event_ids));
6705 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs,
6706 sizeof(hw_cache_extra_regs));
6707 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
6708
6709 intel_pmu_lbr_init_skl();
6710
6711 x86_pmu.event_constraints = intel_slm_event_constraints;
6712 x86_pmu.extra_regs = intel_tnt_extra_regs;
6713 /*
6714 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
6715 * for precise cycles.
6716 */
6717 x86_pmu.pebs_aliases = NULL;
6718 x86_pmu.pebs_prec_dist = true;
6719 x86_pmu.lbr_pt_coexist = true;
6720 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6721 x86_pmu.get_event_constraints = tnt_get_event_constraints;
6722 td_attr = tnt_events_attrs;
6723 extra_attr = slm_format_attr;
6724 pr_cont("Tremont events, ");
6725 name = "Tremont";
6726 break;
6727
6728 case INTEL_ATOM_GRACEMONT:
6729 intel_pmu_init_grt(NULL);
6730 intel_pmu_pebs_data_source_grt();
6731 x86_pmu.pebs_latency_data = grt_latency_data;
6732 x86_pmu.get_event_constraints = tnt_get_event_constraints;
6733 td_attr = tnt_events_attrs;
6734 mem_attr = grt_mem_attrs;
6735 extra_attr = nhm_format_attr;
6736 pr_cont("Gracemont events, ");
6737 name = "gracemont";
6738 break;
6739
6740 case INTEL_ATOM_CRESTMONT:
6741 case INTEL_ATOM_CRESTMONT_X:
6742 intel_pmu_init_grt(NULL);
6743 x86_pmu.extra_regs = intel_cmt_extra_regs;
6744 intel_pmu_pebs_data_source_cmt();
6745 x86_pmu.pebs_latency_data = cmt_latency_data;
6746 x86_pmu.get_event_constraints = cmt_get_event_constraints;
6747 td_attr = cmt_events_attrs;
6748 mem_attr = grt_mem_attrs;
6749 extra_attr = cmt_format_attr;
6750 pr_cont("Crestmont events, ");
6751 name = "crestmont";
6752 break;
6753
6754 case INTEL_WESTMERE:
6755 case INTEL_WESTMERE_EP:
6756 case INTEL_WESTMERE_EX:
6757 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
6758 sizeof(hw_cache_event_ids));
6759 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
6760 sizeof(hw_cache_extra_regs));
6761
6762 intel_pmu_lbr_init_nhm();
6763
6764 x86_pmu.event_constraints = intel_westmere_event_constraints;
6765 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
6766 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
6767 x86_pmu.extra_regs = intel_westmere_extra_regs;
6768 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6769
6770 mem_attr = nhm_mem_events_attrs;
6771
6772 /* UOPS_ISSUED.STALLED_CYCLES */
6773 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
6774 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
6775 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
6776 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
6777 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
6778
6779 intel_pmu_pebs_data_source_nhm();
6780 extra_attr = nhm_format_attr;
6781 pr_cont("Westmere events, ");
6782 name = "westmere";
6783 break;
6784
6785 case INTEL_SANDYBRIDGE:
6786 case INTEL_SANDYBRIDGE_X:
6787 x86_add_quirk(intel_sandybridge_quirk);
6788 x86_add_quirk(intel_ht_bug);
6789 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
6790 sizeof(hw_cache_event_ids));
6791 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
6792 sizeof(hw_cache_extra_regs));
6793
6794 intel_pmu_lbr_init_snb();
6795
6796 x86_pmu.event_constraints = intel_snb_event_constraints;
6797 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
6798 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
6799 if (boot_cpu_data.x86_vfm == INTEL_SANDYBRIDGE_X)
6800 x86_pmu.extra_regs = intel_snbep_extra_regs;
6801 else
6802 x86_pmu.extra_regs = intel_snb_extra_regs;
6803
6804
6805 /* all extra regs are per-cpu when HT is on */
6806 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6807 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6808
6809 td_attr = snb_events_attrs;
6810 mem_attr = snb_mem_events_attrs;
6811
6812 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
6813 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
6814 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
6815 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
6816 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
6817 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
6818
6819 extra_attr = nhm_format_attr;
6820
6821 pr_cont("SandyBridge events, ");
6822 name = "sandybridge";
6823 break;
6824
6825 case INTEL_IVYBRIDGE:
6826 case INTEL_IVYBRIDGE_X:
6827 x86_add_quirk(intel_ht_bug);
6828 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
6829 sizeof(hw_cache_event_ids));
6830 /* dTLB-load-misses on IVB is different than SNB */
6831 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
6832
6833 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
6834 sizeof(hw_cache_extra_regs));
6835
6836 intel_pmu_lbr_init_snb();
6837
6838 x86_pmu.event_constraints = intel_ivb_event_constraints;
6839 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
6840 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
6841 x86_pmu.pebs_prec_dist = true;
6842 if (boot_cpu_data.x86_vfm == INTEL_IVYBRIDGE_X)
6843 x86_pmu.extra_regs = intel_snbep_extra_regs;
6844 else
6845 x86_pmu.extra_regs = intel_snb_extra_regs;
6846 /* all extra regs are per-cpu when HT is on */
6847 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6848 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6849
6850 td_attr = snb_events_attrs;
6851 mem_attr = snb_mem_events_attrs;
6852
6853 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
6854 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
6855 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
6856
6857 extra_attr = nhm_format_attr;
6858
6859 pr_cont("IvyBridge events, ");
6860 name = "ivybridge";
6861 break;
6862
6863
6864 case INTEL_HASWELL:
6865 case INTEL_HASWELL_X:
6866 case INTEL_HASWELL_L:
6867 case INTEL_HASWELL_G:
6868 x86_add_quirk(intel_ht_bug);
6869 x86_add_quirk(intel_pebs_isolation_quirk);
6870 x86_pmu.late_ack = true;
6871 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6872 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6873
6874 intel_pmu_lbr_init_hsw();
6875
6876 x86_pmu.event_constraints = intel_hsw_event_constraints;
6877 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
6878 x86_pmu.extra_regs = intel_snbep_extra_regs;
6879 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
6880 x86_pmu.pebs_prec_dist = true;
6881 /* all extra regs are per-cpu when HT is on */
6882 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6883 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6884
6885 x86_pmu.hw_config = hsw_hw_config;
6886 x86_pmu.get_event_constraints = hsw_get_event_constraints;
6887 x86_pmu.limit_period = hsw_limit_period;
6888 x86_pmu.lbr_double_abort = true;
6889 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
6890 hsw_format_attr : nhm_format_attr;
6891 td_attr = hsw_events_attrs;
6892 mem_attr = hsw_mem_events_attrs;
6893 tsx_attr = hsw_tsx_events_attrs;
6894 pr_cont("Haswell events, ");
6895 name = "haswell";
6896 break;
6897
6898 case INTEL_BROADWELL:
6899 case INTEL_BROADWELL_D:
6900 case INTEL_BROADWELL_G:
6901 case INTEL_BROADWELL_X:
6902 x86_add_quirk(intel_pebs_isolation_quirk);
6903 x86_pmu.late_ack = true;
6904 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6905 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6906
6907 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
6908 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
6909 BDW_L3_MISS|HSW_SNOOP_DRAM;
6910 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
6911 HSW_SNOOP_DRAM;
6912 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
6913 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
6914 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
6915 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
6916
6917 intel_pmu_lbr_init_hsw();
6918
6919 x86_pmu.event_constraints = intel_bdw_event_constraints;
6920 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints;
6921 x86_pmu.extra_regs = intel_snbep_extra_regs;
6922 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
6923 x86_pmu.pebs_prec_dist = true;
6924 /* all extra regs are per-cpu when HT is on */
6925 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6926 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6927
6928 x86_pmu.hw_config = hsw_hw_config;
6929 x86_pmu.get_event_constraints = hsw_get_event_constraints;
6930 x86_pmu.limit_period = bdw_limit_period;
6931 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
6932 hsw_format_attr : nhm_format_attr;
6933 td_attr = hsw_events_attrs;
6934 mem_attr = hsw_mem_events_attrs;
6935 tsx_attr = hsw_tsx_events_attrs;
6936 pr_cont("Broadwell events, ");
6937 name = "broadwell";
6938 break;
6939
6940 case INTEL_XEON_PHI_KNL:
6941 case INTEL_XEON_PHI_KNM:
6942 memcpy(hw_cache_event_ids,
6943 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6944 memcpy(hw_cache_extra_regs,
6945 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6946 intel_pmu_lbr_init_knl();
6947
6948 x86_pmu.event_constraints = intel_slm_event_constraints;
6949 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
6950 x86_pmu.extra_regs = intel_knl_extra_regs;
6951
6952 /* all extra regs are per-cpu when HT is on */
6953 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6954 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6955 extra_attr = slm_format_attr;
6956 pr_cont("Knights Landing/Mill events, ");
6957 name = "knights-landing";
6958 break;
6959
6960 case INTEL_SKYLAKE_X:
6961 pmem = true;
6962 fallthrough;
6963 case INTEL_SKYLAKE_L:
6964 case INTEL_SKYLAKE:
6965 case INTEL_KABYLAKE_L:
6966 case INTEL_KABYLAKE:
6967 case INTEL_COMETLAKE_L:
6968 case INTEL_COMETLAKE:
6969 x86_add_quirk(intel_pebs_isolation_quirk);
6970 x86_pmu.late_ack = true;
6971 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6972 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6973 intel_pmu_lbr_init_skl();
6974
6975 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */
6976 event_attr_td_recovery_bubbles.event_str_noht =
6977 "event=0xd,umask=0x1,cmask=1";
6978 event_attr_td_recovery_bubbles.event_str_ht =
6979 "event=0xd,umask=0x1,cmask=1,any=1";
6980
6981 x86_pmu.event_constraints = intel_skl_event_constraints;
6982 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints;
6983 x86_pmu.extra_regs = intel_skl_extra_regs;
6984 x86_pmu.pebs_aliases = intel_pebs_aliases_skl;
6985 x86_pmu.pebs_prec_dist = true;
6986 /* all extra regs are per-cpu when HT is on */
6987 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6988 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6989
6990 x86_pmu.hw_config = hsw_hw_config;
6991 x86_pmu.get_event_constraints = hsw_get_event_constraints;
6992 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
6993 hsw_format_attr : nhm_format_attr;
6994 extra_skl_attr = skl_format_attr;
6995 td_attr = hsw_events_attrs;
6996 mem_attr = hsw_mem_events_attrs;
6997 tsx_attr = hsw_tsx_events_attrs;
6998 intel_pmu_pebs_data_source_skl(pmem);
6999
7000 /*
7001 * Processors with CPUID.RTM_ALWAYS_ABORT have TSX deprecated by default.
7002 * TSX force abort hooks are not required on these systems. Only deploy
7003 * workaround when microcode has not enabled X86_FEATURE_RTM_ALWAYS_ABORT.
7004 */
7005 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) &&
7006 !boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT)) {
7007 x86_pmu.flags |= PMU_FL_TFA;
7008 x86_pmu.get_event_constraints = tfa_get_event_constraints;
7009 x86_pmu.enable_all = intel_tfa_pmu_enable_all;
7010 x86_pmu.commit_scheduling = intel_tfa_commit_scheduling;
7011 }
7012
7013 pr_cont("Skylake events, ");
7014 name = "skylake";
7015 break;
7016
7017 case INTEL_ICELAKE_X:
7018 case INTEL_ICELAKE_D:
7019 x86_pmu.pebs_ept = 1;
7020 pmem = true;
7021 fallthrough;
7022 case INTEL_ICELAKE_L:
7023 case INTEL_ICELAKE:
7024 case INTEL_TIGERLAKE_L:
7025 case INTEL_TIGERLAKE:
7026 case INTEL_ROCKETLAKE:
7027 x86_pmu.late_ack = true;
7028 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
7029 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7030 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
7031 intel_pmu_lbr_init_skl();
7032
7033 x86_pmu.event_constraints = intel_icl_event_constraints;
7034 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints;
7035 x86_pmu.extra_regs = intel_icl_extra_regs;
7036 x86_pmu.pebs_aliases = NULL;
7037 x86_pmu.pebs_prec_dist = true;
7038 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
7039 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
7040
7041 x86_pmu.hw_config = hsw_hw_config;
7042 x86_pmu.get_event_constraints = icl_get_event_constraints;
7043 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7044 hsw_format_attr : nhm_format_attr;
7045 extra_skl_attr = skl_format_attr;
7046 mem_attr = icl_events_attrs;
7047 td_attr = icl_td_events_attrs;
7048 tsx_attr = icl_tsx_events_attrs;
7049 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
7050 x86_pmu.lbr_pt_coexist = true;
7051 intel_pmu_pebs_data_source_skl(pmem);
7052 x86_pmu.num_topdown_events = 4;
7053 static_call_update(intel_pmu_update_topdown_event,
7054 &icl_update_topdown_event);
7055 static_call_update(intel_pmu_set_topdown_event_period,
7056 &icl_set_topdown_event_period);
7057 pr_cont("Icelake events, ");
7058 name = "icelake";
7059 break;
7060
7061 case INTEL_SAPPHIRERAPIDS_X:
7062 case INTEL_EMERALDRAPIDS_X:
7063 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
7064 x86_pmu.extra_regs = intel_glc_extra_regs;
7065 pr_cont("Sapphire Rapids events, ");
7066 name = "sapphire_rapids";
7067 goto glc_common;
7068
7069 case INTEL_GRANITERAPIDS_X:
7070 case INTEL_GRANITERAPIDS_D:
7071 x86_pmu.extra_regs = intel_rwc_extra_regs;
7072 pr_cont("Granite Rapids events, ");
7073 name = "granite_rapids";
7074
7075 glc_common:
7076 intel_pmu_init_glc(NULL);
7077 x86_pmu.pebs_ept = 1;
7078 x86_pmu.hw_config = hsw_hw_config;
7079 x86_pmu.get_event_constraints = glc_get_event_constraints;
7080 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7081 hsw_format_attr : nhm_format_attr;
7082 extra_skl_attr = skl_format_attr;
7083 mem_attr = glc_events_attrs;
7084 td_attr = glc_td_events_attrs;
7085 tsx_attr = glc_tsx_events_attrs;
7086 intel_pmu_pebs_data_source_skl(true);
7087 break;
7088
7089 case INTEL_ALDERLAKE:
7090 case INTEL_ALDERLAKE_L:
7091 case INTEL_RAPTORLAKE:
7092 case INTEL_RAPTORLAKE_P:
7093 case INTEL_RAPTORLAKE_S:
7094 /*
7095 * Alder Lake has 2 types of CPU, core and atom.
7096 *
7097 * Initialize the common PerfMon capabilities here.
7098 */
7099 intel_pmu_init_hybrid(hybrid_big_small);
7100
7101 x86_pmu.pebs_latency_data = grt_latency_data;
7102 x86_pmu.get_event_constraints = adl_get_event_constraints;
7103 x86_pmu.hw_config = adl_hw_config;
7104 x86_pmu.get_hybrid_cpu_type = adl_get_hybrid_cpu_type;
7105
7106 td_attr = adl_hybrid_events_attrs;
7107 mem_attr = adl_hybrid_mem_attrs;
7108 tsx_attr = adl_hybrid_tsx_attrs;
7109 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7110 adl_hybrid_extra_attr_rtm : adl_hybrid_extra_attr;
7111
7112 /* Initialize big core specific PerfMon capabilities.*/
7113 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
7114 intel_pmu_init_glc(&pmu->pmu);
7115 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) {
7116 pmu->cntr_mask64 <<= 2;
7117 pmu->cntr_mask64 |= 0x3;
7118 pmu->fixed_cntr_mask64 <<= 1;
7119 pmu->fixed_cntr_mask64 |= 0x1;
7120 } else {
7121 pmu->cntr_mask64 = x86_pmu.cntr_mask64;
7122 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64;
7123 }
7124
7125 /*
7126 * Quirk: For some Alder Lake machine, when all E-cores are disabled in
7127 * a BIOS, the leaf 0xA will enumerate all counters of P-cores. However,
7128 * the X86_FEATURE_HYBRID_CPU is still set. The above codes will
7129 * mistakenly add extra counters for P-cores. Correct the number of
7130 * counters here.
7131 */
7132 if ((x86_pmu_num_counters(&pmu->pmu) > 8) || (x86_pmu_num_counters_fixed(&pmu->pmu) > 4)) {
7133 pmu->cntr_mask64 = x86_pmu.cntr_mask64;
7134 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64;
7135 }
7136
7137 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64);
7138 pmu->unconstrained = (struct event_constraint)
7139 __EVENT_CONSTRAINT(0, pmu->cntr_mask64,
7140 0, x86_pmu_num_counters(&pmu->pmu), 0, 0);
7141
7142 pmu->extra_regs = intel_glc_extra_regs;
7143
7144 /* Initialize Atom core specific PerfMon capabilities.*/
7145 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
7146 intel_pmu_init_grt(&pmu->pmu);
7147
7148 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
7149 intel_pmu_pebs_data_source_adl();
7150 pr_cont("Alderlake Hybrid events, ");
7151 name = "alderlake_hybrid";
7152 break;
7153
7154 case INTEL_METEORLAKE:
7155 case INTEL_METEORLAKE_L:
7156 case INTEL_ARROWLAKE_U:
7157 intel_pmu_init_hybrid(hybrid_big_small);
7158
7159 x86_pmu.pebs_latency_data = cmt_latency_data;
7160 x86_pmu.get_event_constraints = mtl_get_event_constraints;
7161 x86_pmu.hw_config = adl_hw_config;
7162
7163 td_attr = adl_hybrid_events_attrs;
7164 mem_attr = mtl_hybrid_mem_attrs;
7165 tsx_attr = adl_hybrid_tsx_attrs;
7166 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7167 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
7168
7169 /* Initialize big core specific PerfMon capabilities.*/
7170 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
7171 intel_pmu_init_glc(&pmu->pmu);
7172 pmu->extra_regs = intel_rwc_extra_regs;
7173
7174 /* Initialize Atom core specific PerfMon capabilities.*/
7175 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
7176 intel_pmu_init_grt(&pmu->pmu);
7177 pmu->extra_regs = intel_cmt_extra_regs;
7178
7179 intel_pmu_pebs_data_source_mtl();
7180 pr_cont("Meteorlake Hybrid events, ");
7181 name = "meteorlake_hybrid";
7182 break;
7183
7184 case INTEL_LUNARLAKE_M:
7185 case INTEL_ARROWLAKE:
7186 intel_pmu_init_hybrid(hybrid_big_small);
7187
7188 x86_pmu.pebs_latency_data = lnl_latency_data;
7189 x86_pmu.get_event_constraints = mtl_get_event_constraints;
7190 x86_pmu.hw_config = adl_hw_config;
7191
7192 td_attr = lnl_hybrid_events_attrs;
7193 mem_attr = mtl_hybrid_mem_attrs;
7194 tsx_attr = adl_hybrid_tsx_attrs;
7195 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7196 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
7197
7198 /* Initialize big core specific PerfMon capabilities.*/
7199 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
7200 intel_pmu_init_lnc(&pmu->pmu);
7201
7202 /* Initialize Atom core specific PerfMon capabilities.*/
7203 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
7204 intel_pmu_init_skt(&pmu->pmu);
7205
7206 intel_pmu_pebs_data_source_lnl();
7207 pr_cont("Lunarlake Hybrid events, ");
7208 name = "lunarlake_hybrid";
7209 break;
7210
7211 case INTEL_ARROWLAKE_H:
7212 intel_pmu_init_hybrid(hybrid_big_small_tiny);
7213
7214 x86_pmu.pebs_latency_data = arl_h_latency_data;
7215 x86_pmu.get_event_constraints = arl_h_get_event_constraints;
7216 x86_pmu.hw_config = arl_h_hw_config;
7217
7218 td_attr = arl_h_hybrid_events_attrs;
7219 mem_attr = arl_h_hybrid_mem_attrs;
7220 tsx_attr = adl_hybrid_tsx_attrs;
7221 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7222 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
7223
7224 /* Initialize big core specific PerfMon capabilities. */
7225 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
7226 intel_pmu_init_lnc(&pmu->pmu);
7227
7228 /* Initialize Atom core specific PerfMon capabilities. */
7229 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
7230 intel_pmu_init_skt(&pmu->pmu);
7231
7232 /* Initialize Lower Power Atom specific PerfMon capabilities. */
7233 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_TINY_IDX];
7234 intel_pmu_init_grt(&pmu->pmu);
7235 pmu->extra_regs = intel_cmt_extra_regs;
7236
7237 intel_pmu_pebs_data_source_arl_h();
7238 pr_cont("ArrowLake-H Hybrid events, ");
7239 name = "arrowlake_h_hybrid";
7240 break;
7241
7242 default:
7243 switch (x86_pmu.version) {
7244 case 1:
7245 x86_pmu.event_constraints = intel_v1_event_constraints;
7246 pr_cont("generic architected perfmon v1, ");
7247 name = "generic_arch_v1";
7248 break;
7249 case 2:
7250 case 3:
7251 case 4:
7252 /*
7253 * default constraints for v2 and up
7254 */
7255 x86_pmu.event_constraints = intel_gen_event_constraints;
7256 pr_cont("generic architected perfmon, ");
7257 name = "generic_arch_v2+";
7258 break;
7259 default:
7260 /*
7261 * The default constraints for v5 and up can support up to
7262 * 16 fixed counters. For the fixed counters 4 and later,
7263 * the pseudo-encoding is applied.
7264 * The constraints may be cut according to the CPUID enumeration
7265 * by inserting the EVENT_CONSTRAINT_END.
7266 */
7267 if (fls64(x86_pmu.fixed_cntr_mask64) > INTEL_PMC_MAX_FIXED)
7268 x86_pmu.fixed_cntr_mask64 &= GENMASK_ULL(INTEL_PMC_MAX_FIXED - 1, 0);
7269 intel_v5_gen_event_constraints[fls64(x86_pmu.fixed_cntr_mask64)].weight = -1;
7270 x86_pmu.event_constraints = intel_v5_gen_event_constraints;
7271 pr_cont("generic architected perfmon, ");
7272 name = "generic_arch_v5+";
7273 break;
7274 }
7275 }
7276
7277 snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name);
7278
7279 if (!is_hybrid()) {
7280 group_events_td.attrs = td_attr;
7281 group_events_mem.attrs = mem_attr;
7282 group_events_tsx.attrs = tsx_attr;
7283 group_format_extra.attrs = extra_attr;
7284 group_format_extra_skl.attrs = extra_skl_attr;
7285
7286 x86_pmu.attr_update = attr_update;
7287 } else {
7288 hybrid_group_events_td.attrs = td_attr;
7289 hybrid_group_events_mem.attrs = mem_attr;
7290 hybrid_group_events_tsx.attrs = tsx_attr;
7291 hybrid_group_format_extra.attrs = extra_attr;
7292
7293 x86_pmu.attr_update = hybrid_attr_update;
7294 }
7295
7296 intel_pmu_check_counters_mask(&x86_pmu.cntr_mask64,
7297 &x86_pmu.fixed_cntr_mask64,
7298 &x86_pmu.intel_ctrl);
7299
7300 /* AnyThread may be deprecated on arch perfmon v5 or later */
7301 if (x86_pmu.intel_cap.anythread_deprecated)
7302 x86_pmu.format_attrs = intel_arch_formats_attr;
7303
7304 intel_pmu_check_event_constraints(x86_pmu.event_constraints,
7305 x86_pmu.cntr_mask64,
7306 x86_pmu.fixed_cntr_mask64,
7307 x86_pmu.intel_ctrl);
7308 /*
7309 * Access LBR MSR may cause #GP under certain circumstances.
7310 * Check all LBR MSR here.
7311 * Disable LBR access if any LBR MSRs can not be accessed.
7312 */
7313 if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL))
7314 x86_pmu.lbr_nr = 0;
7315 for (i = 0; i < x86_pmu.lbr_nr; i++) {
7316 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
7317 check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
7318 x86_pmu.lbr_nr = 0;
7319 }
7320
7321 if (x86_pmu.lbr_nr) {
7322 intel_pmu_lbr_init();
7323
7324 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr);
7325
7326 /* only support branch_stack snapshot for perfmon >= v2 */
7327 if (x86_pmu.disable_all == intel_pmu_disable_all) {
7328 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) {
7329 static_call_update(perf_snapshot_branch_stack,
7330 intel_pmu_snapshot_arch_branch_stack);
7331 } else {
7332 static_call_update(perf_snapshot_branch_stack,
7333 intel_pmu_snapshot_branch_stack);
7334 }
7335 }
7336 }
7337
7338 intel_pmu_check_extra_regs(x86_pmu.extra_regs);
7339
7340 /* Support full width counters using alternative MSR range */
7341 if (x86_pmu.intel_cap.full_width_write) {
7342 x86_pmu.max_period = x86_pmu.cntval_mask >> 1;
7343 x86_pmu.perfctr = MSR_IA32_PMC0;
7344 pr_cont("full-width counters, ");
7345 }
7346
7347 /* Support V6+ MSR Aliasing */
7348 if (x86_pmu.version >= 6) {
7349 x86_pmu.perfctr = MSR_IA32_PMC_V6_GP0_CTR;
7350 x86_pmu.eventsel = MSR_IA32_PMC_V6_GP0_CFG_A;
7351 x86_pmu.fixedctr = MSR_IA32_PMC_V6_FX0_CTR;
7352 x86_pmu.addr_offset = intel_pmu_v6_addr_offset;
7353 }
7354
7355 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics)
7356 x86_pmu.intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS;
7357
7358 if (x86_pmu.intel_cap.pebs_timing_info)
7359 x86_pmu.flags |= PMU_FL_RETIRE_LATENCY;
7360
7361 intel_aux_output_init();
7362
7363 return 0;
7364 }
7365
7366 /*
7367 * HT bug: phase 2 init
7368 * Called once we have valid topology information to check
7369 * whether or not HT is enabled
7370 * If HT is off, then we disable the workaround
7371 */
fixup_ht_bug(void)7372 static __init int fixup_ht_bug(void)
7373 {
7374 int c;
7375 /*
7376 * problem not present on this CPU model, nothing to do
7377 */
7378 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
7379 return 0;
7380
7381 if (topology_max_smt_threads() > 1) {
7382 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
7383 return 0;
7384 }
7385
7386 cpus_read_lock();
7387
7388 hardlockup_detector_perf_stop();
7389
7390 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
7391
7392 x86_pmu.start_scheduling = NULL;
7393 x86_pmu.commit_scheduling = NULL;
7394 x86_pmu.stop_scheduling = NULL;
7395
7396 hardlockup_detector_perf_restart();
7397
7398 for_each_online_cpu(c)
7399 free_excl_cntrs(&per_cpu(cpu_hw_events, c));
7400
7401 cpus_read_unlock();
7402 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
7403 return 0;
7404 }
7405 subsys_initcall(fixup_ht_bug)
7406