1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Following copyright information was take from the original file 4 * <drivers/char/tpm/tpm_tis_core.h> where the definitions were moved 5 * from: 6 * 7 * Copyright (C) 2005, 2006 IBM Corporation 8 * Copyright (C) 2014, 2015 Intel Corporation 9 * 10 * Authors: 11 * Leendert van Doorn <leendert@watson.ibm.com> 12 * Kylene Hall <kjhall@us.ibm.com> 13 * 14 * Maintained by: <tpmdd-devel@lists.sourceforge.net> 15 * 16 * Device driver for TCG/TCPA TPM (trusted platform module). 17 * Specifications at www.trustedcomputinggroup.org 18 * 19 * This device driver implements the TPM interface as defined in 20 * the TCG TPM Interface Spec version 1.2, revision 1.0. 21 */ 22 23 #ifndef __LINUX_TPM_PTP_H__ 24 #define __LINUX_TPM_PTP_H__ 25 26 /* 27 * TCG PC Client Platform TPM Profile (PTP) Specification 28 * https://trustedcomputinggroup.org/resource/pc-client-platform-tpm-profile-ptp-specification/ 29 */ 30 31 /* TIS/FIFO macros and definitions */ 32 33 enum tis_access { 34 TPM_ACCESS_VALID = 0x80, 35 TPM_ACCESS_ACTIVE_LOCALITY = 0x20, /* (R) */ 36 TPM_ACCESS_RELINQUISH_LOCALITY = 0x20, /* (W) */ 37 TPM_ACCESS_REQUEST_PENDING = 0x04, /* (W) */ 38 TPM_ACCESS_REQUEST_USE = 0x02, /* (W) */ 39 }; 40 41 enum tis_status { 42 TPM_STS_VALID = 0x80, /* (R) */ 43 TPM_STS_COMMAND_READY = 0x40, /* (R) */ 44 TPM_STS_DATA_AVAIL = 0x10, /* (R) */ 45 TPM_STS_DATA_EXPECT = 0x08, /* (R) */ 46 TPM_STS_GO = 0x20, /* (W) */ 47 TPM_STS_RESPONSE_RETRY = 0x02, /* (R) */ 48 TPM_STS_READ_ZERO = 0x23, /* bits that must be zero on read */ 49 }; 50 51 enum tis_int_flags { 52 TPM_GLOBAL_INT_ENABLE = 0x80000000, 53 TPM_INTF_BURST_COUNT_STATIC = 0x100, 54 TPM_INTF_CMD_READY_INT = 0x080, 55 TPM_INTF_INT_EDGE_FALLING = 0x040, 56 TPM_INTF_INT_EDGE_RISING = 0x020, 57 TPM_INTF_INT_LEVEL_LOW = 0x010, 58 TPM_INTF_INT_LEVEL_HIGH = 0x008, 59 TPM_INTF_LOCALITY_CHANGE_INT = 0x004, 60 TPM_INTF_STS_VALID_INT = 0x002, 61 TPM_INTF_DATA_AVAIL_INT = 0x001, 62 }; 63 64 enum tis_defaults { 65 TIS_MEM_LEN = 0x5000, 66 TIS_SHORT_TIMEOUT = 750, /* ms */ 67 TIS_LONG_TIMEOUT = 4000, /* 4 secs */ 68 TIS_TIMEOUT_MIN_ATML = 14700, /* usecs */ 69 TIS_TIMEOUT_MAX_ATML = 15000, /* usecs */ 70 }; 71 72 #define TIS_MEM_X86_LPC_BASE 0xFED40000 73 #define INTEL_LEGACY_BLK_BASE_ADDR 0xFED08000 74 75 enum tis_x86_defaults { 76 TIS_MEM_X86_LEN = 0x5000, 77 ILB_REMAP_SIZE = 0x100, 78 LPC_CNTRL_OFFSET = 0x84, 79 LPC_CLKRUN_EN = (1 << 2), 80 }; 81 82 /* 83 * Some timeout values are needed before it is known whether the chip is 84 * TPM 1.0 or TPM 2.0. 85 */ 86 #define TIS_TIMEOUT_A_MAX max_t(int, TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_A) 87 #define TIS_TIMEOUT_B_MAX max_t(int, TIS_LONG_TIMEOUT, TPM2_TIMEOUT_B) 88 #define TIS_TIMEOUT_C_MAX max_t(int, TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_C) 89 #define TIS_TIMEOUT_D_MAX max_t(int, TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_D) 90 91 #define TPM_ACCESS(l) (0x0000 | ((l) << 12)) 92 #define TPM_INT_ENABLE(l) (0x0008 | ((l) << 12)) 93 #define TPM_INT_VECTOR(l) (0x000C | ((l) << 12)) 94 #define TPM_INT_STATUS(l) (0x0010 | ((l) << 12)) 95 #define TPM_INTF_CAPS(l) (0x0014 | ((l) << 12)) 96 #define TPM_STS(l) (0x0018 | ((l) << 12)) 97 #define TPM_STS3(l) (0x001b | ((l) << 12)) 98 #define TPM_DATA_FIFO(l) (0x0024 | ((l) << 12)) 99 #define TPM_INTF_ID(l) (0x0030 | ((l) << 12)) 100 101 #define TPM_DID_VID(l) (0x0F00 | ((l) << 12)) 102 #define TPM_RID(l) (0x0F04 | ((l) << 12)) 103 104 /* TPM HW Interface and Capabilities */ 105 #define TPM_TIS_INTF_ACTIVE 0x00 106 #define TPM_CRB_INTF_ACTIVE 0x01 107 108 #define TPM_INTID_INTERFACE_TYPE GENMASK(3, 0) 109 #define TPM_INTID_INTERFACE_VERSION GENMASK(7, 4) 110 #define TPM_INTID_CAP_LOCALITY BIT(8) 111 #define TPM_INTID_CAP_TIS BIT(13) 112 #define TPM_INTID_CAP_CRB BIT(14) 113 #define TPM_INTID_CAP_IF_RES GENMASK(16, 15) 114 #define TPM_INTID_INTERFACE_SELECTOR GENMASK(18, 17) 115 #define TPM_INTID_INTF_SEL_LOCK BIT(19) 116 117 #define TPM_TIS_INTF_12 0x00 118 #define TPM_TIS_INTF_13 0x02 119 #define TPM2_TIS_INTF_13 0x03 120 121 #define TPM_INTF_DATA_AVAIL_INT_SUPPORT BIT(0) 122 #define TPM_INTF_STS_VALID_INT_SUPPORT BIT(1) 123 #define TPM_INTF_LOCALITY_CHANGE_INT_SUPPORT BIT(2) 124 #define TPM_INTF_INTERRUPT_LEVEL_HIGH BIT(3) 125 #define TPM_INTF_INTERRUPT_LEVEL_LOW BIT(4) 126 #define TPM_INTF_INTERRUPT_EDGE_RISING BIT(5) 127 #define TPM_INTF_INTERRUPT_EDGE_FALLING BIT(6) 128 #define TPM_INTF_COMMAND_READY_INT_SUPPORT BIT(7) 129 #define TPM_INTF_BURST_COUNT_STATIC BIT(8) 130 #define TPM_INTF_DATA_TRANSFER_SIZE_SUPPORT GENMASK(10, 9) 131 #define TPM_INTF_INTERFACE_VERSION GENMASK(30, 28) 132 133 #endif 134