1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 *
6 * Derived from arch/arm/include/asm/kvm_host.h:
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
9 */
10
11 #ifndef __ARM64_KVM_HOST_H__
12 #define __ARM64_KVM_HOST_H__
13
14 #include <linux/arm-smccc.h>
15 #include <linux/bitmap.h>
16 #include <linux/types.h>
17 #include <linux/jump_label.h>
18 #include <linux/kvm_types.h>
19 #include <linux/maple_tree.h>
20 #include <linux/percpu.h>
21 #include <linux/psci.h>
22 #include <asm/arch_gicv3.h>
23 #include <asm/barrier.h>
24 #include <asm/cpufeature.h>
25 #include <asm/cputype.h>
26 #include <asm/daifflags.h>
27 #include <asm/fpsimd.h>
28 #include <asm/kvm.h>
29 #include <asm/kvm_asm.h>
30 #include <asm/vncr_mapping.h>
31
32 #define __KVM_HAVE_ARCH_INTC_INITIALIZED
33
34 #define KVM_HALT_POLL_NS_DEFAULT 500000
35
36 #include <kvm/arm_vgic.h>
37 #include <kvm/arm_arch_timer.h>
38 #include <kvm/arm_pmu.h>
39
40 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
41
42 #define KVM_VCPU_MAX_FEATURES 9
43 #define KVM_VCPU_VALID_FEATURES (BIT(KVM_VCPU_MAX_FEATURES) - 1)
44
45 #define KVM_REQ_SLEEP \
46 KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
47 #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1)
48 #define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2)
49 #define KVM_REQ_RECORD_STEAL KVM_ARCH_REQ(3)
50 #define KVM_REQ_RELOAD_GICv4 KVM_ARCH_REQ(4)
51 #define KVM_REQ_RELOAD_PMU KVM_ARCH_REQ(5)
52 #define KVM_REQ_SUSPEND KVM_ARCH_REQ(6)
53 #define KVM_REQ_RESYNC_PMU_EL0 KVM_ARCH_REQ(7)
54 #define KVM_REQ_NESTED_S2_UNMAP KVM_ARCH_REQ(8)
55 #define KVM_REQ_GUEST_HYP_IRQ_PENDING KVM_ARCH_REQ(9)
56 #define KVM_REQ_MAP_L1_VNCR_EL2 KVM_ARCH_REQ(10)
57 #define KVM_REQ_VGIC_PROCESS_UPDATE KVM_ARCH_REQ(11)
58
59 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \
60 KVM_DIRTY_LOG_INITIALLY_SET)
61
62 #define KVM_HAVE_MMU_RWLOCK
63
64 /*
65 * Mode of operation configurable with kvm-arm.mode early param.
66 * See Documentation/admin-guide/kernel-parameters.txt for more information.
67 */
68 enum kvm_mode {
69 KVM_MODE_DEFAULT,
70 KVM_MODE_PROTECTED,
71 KVM_MODE_NV,
72 KVM_MODE_NONE,
73 };
74 #ifdef CONFIG_KVM
75 enum kvm_mode kvm_get_mode(void);
76 #else
kvm_get_mode(void)77 static inline enum kvm_mode kvm_get_mode(void) { return KVM_MODE_NONE; };
78 #endif
79
80 extern unsigned int __ro_after_init kvm_sve_max_vl;
81 extern unsigned int __ro_after_init kvm_host_sve_max_vl;
82 int __init kvm_arm_init_sve(void);
83
84 u32 __attribute_const__ kvm_target_cpu(void);
85 void kvm_reset_vcpu(struct kvm_vcpu *vcpu);
86 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu);
87
88 struct kvm_hyp_memcache {
89 phys_addr_t head;
90 unsigned long nr_pages;
91 struct pkvm_mapping *mapping; /* only used from EL1 */
92
93 #define HYP_MEMCACHE_ACCOUNT_STAGE2 BIT(1)
94 unsigned long flags;
95 };
96
push_hyp_memcache(struct kvm_hyp_memcache * mc,phys_addr_t * p,phys_addr_t (* to_pa)(void * virt))97 static inline void push_hyp_memcache(struct kvm_hyp_memcache *mc,
98 phys_addr_t *p,
99 phys_addr_t (*to_pa)(void *virt))
100 {
101 *p = mc->head;
102 mc->head = to_pa(p);
103 mc->nr_pages++;
104 }
105
pop_hyp_memcache(struct kvm_hyp_memcache * mc,void * (* to_va)(phys_addr_t phys))106 static inline void *pop_hyp_memcache(struct kvm_hyp_memcache *mc,
107 void *(*to_va)(phys_addr_t phys))
108 {
109 phys_addr_t *p = to_va(mc->head & PAGE_MASK);
110
111 if (!mc->nr_pages)
112 return NULL;
113
114 mc->head = *p;
115 mc->nr_pages--;
116
117 return p;
118 }
119
__topup_hyp_memcache(struct kvm_hyp_memcache * mc,unsigned long min_pages,void * (* alloc_fn)(void * arg),phys_addr_t (* to_pa)(void * virt),void * arg)120 static inline int __topup_hyp_memcache(struct kvm_hyp_memcache *mc,
121 unsigned long min_pages,
122 void *(*alloc_fn)(void *arg),
123 phys_addr_t (*to_pa)(void *virt),
124 void *arg)
125 {
126 while (mc->nr_pages < min_pages) {
127 phys_addr_t *p = alloc_fn(arg);
128
129 if (!p)
130 return -ENOMEM;
131 push_hyp_memcache(mc, p, to_pa);
132 }
133
134 return 0;
135 }
136
__free_hyp_memcache(struct kvm_hyp_memcache * mc,void (* free_fn)(void * virt,void * arg),void * (* to_va)(phys_addr_t phys),void * arg)137 static inline void __free_hyp_memcache(struct kvm_hyp_memcache *mc,
138 void (*free_fn)(void *virt, void *arg),
139 void *(*to_va)(phys_addr_t phys),
140 void *arg)
141 {
142 while (mc->nr_pages)
143 free_fn(pop_hyp_memcache(mc, to_va), arg);
144 }
145
146 void free_hyp_memcache(struct kvm_hyp_memcache *mc);
147 int topup_hyp_memcache(struct kvm_hyp_memcache *mc, unsigned long min_pages);
148
149 struct kvm_vmid {
150 atomic64_t id;
151 };
152
153 struct kvm_s2_mmu {
154 struct kvm_vmid vmid;
155
156 /*
157 * stage2 entry level table
158 *
159 * Two kvm_s2_mmu structures in the same VM can point to the same
160 * pgd here. This happens when running a guest using a
161 * translation regime that isn't affected by its own stage-2
162 * translation, such as a non-VHE hypervisor running at vEL2, or
163 * for vEL1/EL0 with vHCR_EL2.VM == 0. In that case, we use the
164 * canonical stage-2 page tables.
165 */
166 phys_addr_t pgd_phys;
167 struct kvm_pgtable *pgt;
168
169 /*
170 * VTCR value used on the host. For a non-NV guest (or a NV
171 * guest that runs in a context where its own S2 doesn't
172 * apply), its T0SZ value reflects that of the IPA size.
173 *
174 * For a shadow S2 MMU, T0SZ reflects the PARange exposed to
175 * the guest.
176 */
177 u64 vtcr;
178
179 /* The last vcpu id that ran on each physical CPU */
180 int __percpu *last_vcpu_ran;
181
182 #define KVM_ARM_EAGER_SPLIT_CHUNK_SIZE_DEFAULT 0
183 /*
184 * Memory cache used to split
185 * KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE worth of huge pages. It
186 * is used to allocate stage2 page tables while splitting huge
187 * pages. The choice of KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE
188 * influences both the capacity of the split page cache, and
189 * how often KVM reschedules. Be wary of raising CHUNK_SIZE
190 * too high.
191 *
192 * Protected by kvm->slots_lock.
193 */
194 struct kvm_mmu_memory_cache split_page_cache;
195 uint64_t split_page_chunk_size;
196
197 struct kvm_arch *arch;
198
199 /*
200 * For a shadow stage-2 MMU, the virtual vttbr used by the
201 * host to parse the guest S2.
202 * This either contains:
203 * - the virtual VTTBR programmed by the guest hypervisor with
204 * CnP cleared
205 * - The value 1 (VMID=0, BADDR=0, CnP=1) if invalid
206 *
207 * We also cache the full VTCR which gets used for TLB invalidation,
208 * taking the ARM ARM's "Any of the bits in VTCR_EL2 are permitted
209 * to be cached in a TLB" to the letter.
210 */
211 u64 tlb_vttbr;
212 u64 tlb_vtcr;
213
214 /*
215 * true when this represents a nested context where virtual
216 * HCR_EL2.VM == 1
217 */
218 bool nested_stage2_enabled;
219
220 #ifdef CONFIG_PTDUMP_STAGE2_DEBUGFS
221 struct dentry *shadow_pt_debugfs_dentry;
222 #endif
223
224 /*
225 * true when this MMU needs to be unmapped before being used for a new
226 * purpose.
227 */
228 bool pending_unmap;
229
230 /*
231 * 0: Nobody is currently using this, check vttbr for validity
232 * >0: Somebody is actively using this.
233 */
234 atomic_t refcnt;
235 };
236
237 struct kvm_arch_memory_slot {
238 };
239
240 /**
241 * struct kvm_smccc_features: Descriptor of the hypercall services exposed to the guests
242 *
243 * @std_bmap: Bitmap of standard secure service calls
244 * @std_hyp_bmap: Bitmap of standard hypervisor service calls
245 * @vendor_hyp_bmap: Bitmap of vendor specific hypervisor service calls
246 */
247 struct kvm_smccc_features {
248 unsigned long std_bmap;
249 unsigned long std_hyp_bmap;
250 unsigned long vendor_hyp_bmap; /* Function numbers 0-63 */
251 unsigned long vendor_hyp_bmap_2; /* Function numbers 64-127 */
252 };
253
254 typedef u16 pkvm_handle_t;
255
256 struct kvm_protected_vm {
257 pkvm_handle_t handle;
258 struct kvm_hyp_memcache teardown_mc;
259 struct kvm_hyp_memcache stage2_teardown_mc;
260 bool is_protected;
261 bool is_created;
262
263 /*
264 * True when the guest is being torn down. When in this state, the
265 * guest's vCPUs can't be loaded anymore, but its pages can be
266 * reclaimed by the host.
267 */
268 bool is_dying;
269 };
270
271 struct kvm_mpidr_data {
272 u64 mpidr_mask;
273 DECLARE_FLEX_ARRAY(u16, cmpidr_to_idx);
274 };
275
kvm_mpidr_index(struct kvm_mpidr_data * data,u64 mpidr)276 static inline u16 kvm_mpidr_index(struct kvm_mpidr_data *data, u64 mpidr)
277 {
278 unsigned long index = 0, mask = data->mpidr_mask;
279 unsigned long aff = mpidr & MPIDR_HWID_BITMASK;
280
281 bitmap_gather(&index, &aff, &mask, fls(mask));
282
283 return index;
284 }
285
286 struct kvm_sysreg_masks;
287
288 enum fgt_group_id {
289 __NO_FGT_GROUP__,
290 HFGRTR_GROUP,
291 HFGWTR_GROUP = HFGRTR_GROUP,
292 HDFGRTR_GROUP,
293 HDFGWTR_GROUP = HDFGRTR_GROUP,
294 HFGITR_GROUP,
295 HAFGRTR_GROUP,
296 HFGRTR2_GROUP,
297 HFGWTR2_GROUP = HFGRTR2_GROUP,
298 HDFGRTR2_GROUP,
299 HDFGWTR2_GROUP = HDFGRTR2_GROUP,
300 HFGITR2_GROUP,
301 ICH_HFGRTR_GROUP,
302 ICH_HFGWTR_GROUP = ICH_HFGRTR_GROUP,
303 ICH_HFGITR_GROUP,
304
305 /* Must be last */
306 __NR_FGT_GROUP_IDS__
307 };
308
309 struct kvm_arch {
310 struct kvm_s2_mmu mmu;
311
312 /*
313 * Fine-Grained UNDEF, mimicking the FGT layout defined by the
314 * architecture. We track them globally, as we present the
315 * same feature-set to all vcpus.
316 *
317 * Index 0 is currently spare.
318 */
319 u64 fgu[__NR_FGT_GROUP_IDS__];
320
321 /*
322 * Stage 2 paging state for VMs with nested S2 using a virtual
323 * VMID.
324 */
325 struct kvm_s2_mmu *nested_mmus;
326 size_t nested_mmus_size;
327 int nested_mmus_next;
328
329 /* Interrupt controller */
330 struct vgic_dist vgic;
331
332 /* Timers */
333 struct arch_timer_vm_data timer_data;
334
335 /* Mandated version of PSCI */
336 u32 psci_version;
337
338 /* Protects VM-scoped configuration data */
339 struct mutex config_lock;
340
341 /*
342 * If we encounter a data abort without valid instruction syndrome
343 * information, report this to user space. User space can (and
344 * should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is
345 * supported.
346 */
347 #define KVM_ARCH_FLAG_RETURN_NISV_IO_ABORT_TO_USER 0
348 /* Memory Tagging Extension enabled for the guest */
349 #define KVM_ARCH_FLAG_MTE_ENABLED 1
350 /* At least one vCPU has ran in the VM */
351 #define KVM_ARCH_FLAG_HAS_RAN_ONCE 2
352 /* The vCPU feature set for the VM is configured */
353 #define KVM_ARCH_FLAG_VCPU_FEATURES_CONFIGURED 3
354 /* PSCI SYSTEM_SUSPEND enabled for the guest */
355 #define KVM_ARCH_FLAG_SYSTEM_SUSPEND_ENABLED 4
356 /* VM counter offset */
357 #define KVM_ARCH_FLAG_VM_COUNTER_OFFSET 5
358 /* Timer PPIs made immutable */
359 #define KVM_ARCH_FLAG_TIMER_PPIS_IMMUTABLE 6
360 /* Initial ID reg values loaded */
361 #define KVM_ARCH_FLAG_ID_REGS_INITIALIZED 7
362 /* Fine-Grained UNDEF initialised */
363 #define KVM_ARCH_FLAG_FGU_INITIALIZED 8
364 /* SVE exposed to guest */
365 #define KVM_ARCH_FLAG_GUEST_HAS_SVE 9
366 /* MIDR_EL1, REVIDR_EL1, and AIDR_EL1 are writable from userspace */
367 #define KVM_ARCH_FLAG_WRITABLE_IMP_ID_REGS 10
368 /* Unhandled SEAs are taken to userspace */
369 #define KVM_ARCH_FLAG_EXIT_SEA 11
370 unsigned long flags;
371
372 /* VM-wide vCPU feature set */
373 DECLARE_BITMAP(vcpu_features, KVM_VCPU_MAX_FEATURES);
374
375 /* MPIDR to vcpu index mapping, optional */
376 struct kvm_mpidr_data *mpidr_data;
377
378 /*
379 * VM-wide PMU filter, implemented as a bitmap and big enough for
380 * up to 2^10 events (ARMv8.0) or 2^16 events (ARMv8.1+).
381 */
382 unsigned long *pmu_filter;
383 struct arm_pmu *arm_pmu;
384
385 cpumask_var_t supported_cpus;
386
387 /* Maximum number of counters for the guest */
388 u8 nr_pmu_counters;
389
390 /* Hypercall features firmware registers' descriptor */
391 struct kvm_smccc_features smccc_feat;
392 struct maple_tree smccc_filter;
393
394 /*
395 * Emulated CPU ID registers per VM
396 * (Op0, Op1, CRn, CRm, Op2) of the ID registers to be saved in it
397 * is (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8.
398 *
399 * These emulated idregs are VM-wide, but accessed from the context of a vCPU.
400 * Atomic access to multiple idregs are guarded by kvm_arch.config_lock.
401 */
402 #define IDREG_IDX(id) (((sys_reg_CRm(id) - 1) << 3) | sys_reg_Op2(id))
403 #define KVM_ARM_ID_REG_NUM (IDREG_IDX(sys_reg(3, 0, 0, 7, 7)) + 1)
404 u64 id_regs[KVM_ARM_ID_REG_NUM];
405
406 u64 midr_el1;
407 u64 revidr_el1;
408 u64 aidr_el1;
409 u64 ctr_el0;
410
411 /* Masks for VNCR-backed and general EL2 sysregs */
412 struct kvm_sysreg_masks *sysreg_masks;
413
414 /* Count the number of VNCR_EL2 currently mapped */
415 atomic_t vncr_map_count;
416
417 /*
418 * For an untrusted host VM, 'pkvm.handle' is used to lookup
419 * the associated pKVM instance in the hypervisor.
420 */
421 struct kvm_protected_vm pkvm;
422
423 #ifdef CONFIG_PTDUMP_STAGE2_DEBUGFS
424 /* Nested virtualization info */
425 struct dentry *debugfs_nv_dentry;
426 #endif
427 };
428
429 struct kvm_vcpu_fault_info {
430 u64 esr_el2; /* Hyp Syndrom Register */
431 u64 far_el2; /* Hyp Fault Address Register */
432 u64 hpfar_el2; /* Hyp IPA Fault Address Register */
433 u64 disr_el1; /* Deferred [SError] Status Register */
434 };
435
436 /*
437 * VNCR() just places the VNCR_capable registers in the enum after
438 * __VNCR_START__, and the value (after correction) to be an 8-byte offset
439 * from the VNCR base. As we don't require the enum to be otherwise ordered,
440 * we need the terrible hack below to ensure that we correctly size the
441 * sys_regs array, no matter what.
442 *
443 * The __MAX__ macro has been lifted from Sean Eron Anderson's wonderful
444 * treasure trove of bit hacks:
445 * https://graphics.stanford.edu/~seander/bithacks.html#IntegerMinOrMax
446 */
447 #define __MAX__(x,y) ((x) ^ (((x) ^ (y)) & -((x) < (y))))
448 #define VNCR(r) \
449 __before_##r, \
450 r = __VNCR_START__ + ((VNCR_ ## r) / 8), \
451 __after_##r = __MAX__(__before_##r - 1, r)
452
453 enum vcpu_sysreg {
454 __INVALID_SYSREG__, /* 0 is reserved as an invalid value */
455 MPIDR_EL1, /* MultiProcessor Affinity Register */
456 CLIDR_EL1, /* Cache Level ID Register */
457 CSSELR_EL1, /* Cache Size Selection Register */
458 TPIDR_EL0, /* Thread ID, User R/W */
459 TPIDRRO_EL0, /* Thread ID, User R/O */
460 TPIDR_EL1, /* Thread ID, Privileged */
461 CNTKCTL_EL1, /* Timer Control Register (EL1) */
462 PAR_EL1, /* Physical Address Register */
463 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */
464 OSLSR_EL1, /* OS Lock Status Register */
465 DISR_EL1, /* Deferred Interrupt Status Register */
466
467 /* Performance Monitors Registers */
468 PMCR_EL0, /* Control Register */
469 PMSELR_EL0, /* Event Counter Selection Register */
470 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */
471 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30,
472 PMCCNTR_EL0, /* Cycle Counter Register */
473 PMEVTYPER0_EL0, /* Event Type Register (0-30) */
474 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30,
475 PMCCFILTR_EL0, /* Cycle Count Filter Register */
476 PMCNTENSET_EL0, /* Count Enable Set Register */
477 PMINTENSET_EL1, /* Interrupt Enable Set Register */
478 PMOVSSET_EL0, /* Overflow Flag Status Set Register */
479 PMUSERENR_EL0, /* User Enable Register */
480
481 /* Pointer Authentication Registers in a strict increasing order. */
482 APIAKEYLO_EL1,
483 APIAKEYHI_EL1,
484 APIBKEYLO_EL1,
485 APIBKEYHI_EL1,
486 APDAKEYLO_EL1,
487 APDAKEYHI_EL1,
488 APDBKEYLO_EL1,
489 APDBKEYHI_EL1,
490 APGAKEYLO_EL1,
491 APGAKEYHI_EL1,
492
493 /* Memory Tagging Extension registers */
494 RGSR_EL1, /* Random Allocation Tag Seed Register */
495 GCR_EL1, /* Tag Control Register */
496 TFSRE0_EL1, /* Tag Fault Status Register (EL0) */
497
498 POR_EL0, /* Permission Overlay Register 0 (EL0) */
499
500 /* FP/SIMD/SVE */
501 SVCR,
502 FPMR,
503
504 /* 32bit specific registers. */
505 DACR32_EL2, /* Domain Access Control Register */
506 IFSR32_EL2, /* Instruction Fault Status Register */
507 FPEXC32_EL2, /* Floating-Point Exception Control Register */
508 DBGVCR32_EL2, /* Debug Vector Catch Register */
509
510 /* EL2 registers */
511 ACTLR_EL2, /* Auxiliary Control Register (EL2) */
512 CPTR_EL2, /* Architectural Feature Trap Register (EL2) */
513 HACR_EL2, /* Hypervisor Auxiliary Control Register */
514 ZCR_EL2, /* SVE Control Register (EL2) */
515 TTBR0_EL2, /* Translation Table Base Register 0 (EL2) */
516 TTBR1_EL2, /* Translation Table Base Register 1 (EL2) */
517 TCR_EL2, /* Translation Control Register (EL2) */
518 PIRE0_EL2, /* Permission Indirection Register 0 (EL2) */
519 PIR_EL2, /* Permission Indirection Register 1 (EL2) */
520 POR_EL2, /* Permission Overlay Register 2 (EL2) */
521 SPSR_EL2, /* EL2 saved program status register */
522 ELR_EL2, /* EL2 exception link register */
523 AFSR0_EL2, /* Auxiliary Fault Status Register 0 (EL2) */
524 AFSR1_EL2, /* Auxiliary Fault Status Register 1 (EL2) */
525 ESR_EL2, /* Exception Syndrome Register (EL2) */
526 FAR_EL2, /* Fault Address Register (EL2) */
527 HPFAR_EL2, /* Hypervisor IPA Fault Address Register */
528 MAIR_EL2, /* Memory Attribute Indirection Register (EL2) */
529 AMAIR_EL2, /* Auxiliary Memory Attribute Indirection Register (EL2) */
530 VBAR_EL2, /* Vector Base Address Register (EL2) */
531 RVBAR_EL2, /* Reset Vector Base Address Register */
532 CONTEXTIDR_EL2, /* Context ID Register (EL2) */
533 SP_EL2, /* EL2 Stack Pointer */
534 CNTHP_CTL_EL2,
535 CNTHP_CVAL_EL2,
536 CNTHV_CTL_EL2,
537 CNTHV_CVAL_EL2,
538
539 /* Anything from this can be RES0/RES1 sanitised */
540 MARKER(__SANITISED_REG_START__),
541 SCTLR_EL2, /* System Control Register (EL2) */
542 TCR2_EL2, /* Extended Translation Control Register (EL2) */
543 SCTLR2_EL2, /* System Control Register 2 (EL2) */
544 MDCR_EL2, /* Monitor Debug Configuration Register (EL2) */
545 CNTHCTL_EL2, /* Counter-timer Hypervisor Control register */
546
547 /* Any VNCR-capable reg goes after this point */
548 MARKER(__VNCR_START__),
549
550 VNCR(SCTLR_EL1),/* System Control Register */
551 VNCR(ACTLR_EL1),/* Auxiliary Control Register */
552 VNCR(CPACR_EL1),/* Coprocessor Access Control */
553 VNCR(ZCR_EL1), /* SVE Control */
554 VNCR(TTBR0_EL1),/* Translation Table Base Register 0 */
555 VNCR(TTBR1_EL1),/* Translation Table Base Register 1 */
556 VNCR(TCR_EL1), /* Translation Control Register */
557 VNCR(TCR2_EL1), /* Extended Translation Control Register */
558 VNCR(SCTLR2_EL1), /* System Control Register 2 */
559 VNCR(ESR_EL1), /* Exception Syndrome Register */
560 VNCR(AFSR0_EL1),/* Auxiliary Fault Status Register 0 */
561 VNCR(AFSR1_EL1),/* Auxiliary Fault Status Register 1 */
562 VNCR(FAR_EL1), /* Fault Address Register */
563 VNCR(MAIR_EL1), /* Memory Attribute Indirection Register */
564 VNCR(VBAR_EL1), /* Vector Base Address Register */
565 VNCR(CONTEXTIDR_EL1), /* Context ID Register */
566 VNCR(AMAIR_EL1),/* Aux Memory Attribute Indirection Register */
567 VNCR(MDSCR_EL1),/* Monitor Debug System Control Register */
568 VNCR(ELR_EL1),
569 VNCR(SP_EL1),
570 VNCR(SPSR_EL1),
571 VNCR(TFSR_EL1), /* Tag Fault Status Register (EL1) */
572 VNCR(VPIDR_EL2),/* Virtualization Processor ID Register */
573 VNCR(VMPIDR_EL2),/* Virtualization Multiprocessor ID Register */
574 VNCR(HCR_EL2), /* Hypervisor Configuration Register */
575 VNCR(HSTR_EL2), /* Hypervisor System Trap Register */
576 VNCR(VTTBR_EL2),/* Virtualization Translation Table Base Register */
577 VNCR(VTCR_EL2), /* Virtualization Translation Control Register */
578 VNCR(TPIDR_EL2),/* EL2 Software Thread ID Register */
579 VNCR(HCRX_EL2), /* Extended Hypervisor Configuration Register */
580
581 /* Permission Indirection Extension registers */
582 VNCR(PIR_EL1), /* Permission Indirection Register 1 (EL1) */
583 VNCR(PIRE0_EL1), /* Permission Indirection Register 0 (EL1) */
584
585 VNCR(POR_EL1), /* Permission Overlay Register 1 (EL1) */
586
587 /* FEAT_RAS registers */
588 VNCR(VDISR_EL2),
589 VNCR(VSESR_EL2),
590
591 VNCR(HFGRTR_EL2),
592 VNCR(HFGWTR_EL2),
593 VNCR(HFGITR_EL2),
594 VNCR(HDFGRTR_EL2),
595 VNCR(HDFGWTR_EL2),
596 VNCR(HAFGRTR_EL2),
597 VNCR(HFGRTR2_EL2),
598 VNCR(HFGWTR2_EL2),
599 VNCR(HFGITR2_EL2),
600 VNCR(HDFGRTR2_EL2),
601 VNCR(HDFGWTR2_EL2),
602
603 VNCR(VNCR_EL2),
604
605 VNCR(CNTVOFF_EL2),
606 VNCR(CNTV_CVAL_EL0),
607 VNCR(CNTV_CTL_EL0),
608 VNCR(CNTP_CVAL_EL0),
609 VNCR(CNTP_CTL_EL0),
610
611 VNCR(ICH_LR0_EL2),
612 VNCR(ICH_LR1_EL2),
613 VNCR(ICH_LR2_EL2),
614 VNCR(ICH_LR3_EL2),
615 VNCR(ICH_LR4_EL2),
616 VNCR(ICH_LR5_EL2),
617 VNCR(ICH_LR6_EL2),
618 VNCR(ICH_LR7_EL2),
619 VNCR(ICH_LR8_EL2),
620 VNCR(ICH_LR9_EL2),
621 VNCR(ICH_LR10_EL2),
622 VNCR(ICH_LR11_EL2),
623 VNCR(ICH_LR12_EL2),
624 VNCR(ICH_LR13_EL2),
625 VNCR(ICH_LR14_EL2),
626 VNCR(ICH_LR15_EL2),
627
628 VNCR(ICH_AP0R0_EL2),
629 VNCR(ICH_AP0R1_EL2),
630 VNCR(ICH_AP0R2_EL2),
631 VNCR(ICH_AP0R3_EL2),
632 VNCR(ICH_AP1R0_EL2),
633 VNCR(ICH_AP1R1_EL2),
634 VNCR(ICH_AP1R2_EL2),
635 VNCR(ICH_AP1R3_EL2),
636 VNCR(ICH_HCR_EL2),
637 VNCR(ICH_VMCR_EL2),
638
639 VNCR(ICH_HFGRTR_EL2),
640 VNCR(ICH_HFGWTR_EL2),
641 VNCR(ICH_HFGITR_EL2),
642
643 NR_SYS_REGS /* Nothing after this line! */
644 };
645
646 struct resx {
647 u64 res0;
648 u64 res1;
649 };
650
651 struct kvm_sysreg_masks {
652 struct resx mask[NR_SYS_REGS - __SANITISED_REG_START__];
653 };
654
__kvm_get_sysreg_resx(struct kvm_arch * arch,enum vcpu_sysreg sr)655 static inline struct resx __kvm_get_sysreg_resx(struct kvm_arch *arch,
656 enum vcpu_sysreg sr)
657 {
658 struct kvm_sysreg_masks *masks;
659
660 masks = arch->sysreg_masks;
661 if (likely(masks &&
662 sr >= __SANITISED_REG_START__ && sr < NR_SYS_REGS))
663 return masks->mask[sr - __SANITISED_REG_START__];
664
665 return (struct resx){};
666 }
667
668 #define kvm_get_sysreg_resx(k, sr) __kvm_get_sysreg_resx(&(k)->arch, (sr))
669
__kvm_set_sysreg_resx(struct kvm_arch * arch,enum vcpu_sysreg sr,struct resx resx)670 static inline void __kvm_set_sysreg_resx(struct kvm_arch *arch,
671 enum vcpu_sysreg sr, struct resx resx)
672 {
673 arch->sysreg_masks->mask[sr - __SANITISED_REG_START__] = resx;
674 }
675
676 #define kvm_set_sysreg_resx(k, sr, resx) \
677 __kvm_set_sysreg_resx(&(k)->arch, (sr), (resx))
678
679 struct fgt_masks {
680 const char *str;
681 u64 mask;
682 u64 nmask;
683 u64 res0;
684 u64 res1;
685 };
686
687 extern struct fgt_masks hfgrtr_masks;
688 extern struct fgt_masks hfgwtr_masks;
689 extern struct fgt_masks hfgitr_masks;
690 extern struct fgt_masks hdfgrtr_masks;
691 extern struct fgt_masks hdfgwtr_masks;
692 extern struct fgt_masks hafgrtr_masks;
693 extern struct fgt_masks hfgrtr2_masks;
694 extern struct fgt_masks hfgwtr2_masks;
695 extern struct fgt_masks hfgitr2_masks;
696 extern struct fgt_masks hdfgrtr2_masks;
697 extern struct fgt_masks hdfgwtr2_masks;
698 extern struct fgt_masks ich_hfgrtr_masks;
699 extern struct fgt_masks ich_hfgwtr_masks;
700 extern struct fgt_masks ich_hfgitr_masks;
701
702 extern struct fgt_masks kvm_nvhe_sym(hfgrtr_masks);
703 extern struct fgt_masks kvm_nvhe_sym(hfgwtr_masks);
704 extern struct fgt_masks kvm_nvhe_sym(hfgitr_masks);
705 extern struct fgt_masks kvm_nvhe_sym(hdfgrtr_masks);
706 extern struct fgt_masks kvm_nvhe_sym(hdfgwtr_masks);
707 extern struct fgt_masks kvm_nvhe_sym(hafgrtr_masks);
708 extern struct fgt_masks kvm_nvhe_sym(hfgrtr2_masks);
709 extern struct fgt_masks kvm_nvhe_sym(hfgwtr2_masks);
710 extern struct fgt_masks kvm_nvhe_sym(hfgitr2_masks);
711 extern struct fgt_masks kvm_nvhe_sym(hdfgrtr2_masks);
712 extern struct fgt_masks kvm_nvhe_sym(hdfgwtr2_masks);
713 extern struct fgt_masks kvm_nvhe_sym(ich_hfgrtr_masks);
714 extern struct fgt_masks kvm_nvhe_sym(ich_hfgwtr_masks);
715 extern struct fgt_masks kvm_nvhe_sym(ich_hfgitr_masks);
716
717 struct kvm_cpu_context {
718 struct user_pt_regs regs; /* sp = sp_el0 */
719
720 u64 spsr_abt;
721 u64 spsr_und;
722 u64 spsr_irq;
723 u64 spsr_fiq;
724
725 struct user_fpsimd_state fp_regs;
726
727 u64 sys_regs[NR_SYS_REGS];
728
729 struct kvm_vcpu *__hyp_running_vcpu;
730
731 /* This pointer has to be 4kB aligned. */
732 u64 *vncr_array;
733 };
734
735 struct cpu_sve_state {
736 __u64 zcr_el1;
737
738 /*
739 * Ordering is important since __sve_save_state/__sve_restore_state
740 * relies on it.
741 */
742 __u32 fpsr;
743 __u32 fpcr;
744
745 /* Must be SVE_VQ_BYTES (128 bit) aligned. */
746 __u8 sve_regs[];
747 };
748
749 /*
750 * This structure is instantiated on a per-CPU basis, and contains
751 * data that is:
752 *
753 * - tied to a single physical CPU, and
754 * - either have a lifetime that does not extend past vcpu_put()
755 * - or is an invariant for the lifetime of the system
756 *
757 * Use host_data_ptr(field) as a way to access a pointer to such a
758 * field.
759 */
760 struct kvm_host_data {
761 #define KVM_HOST_DATA_FLAG_HAS_SPE 0
762 #define KVM_HOST_DATA_FLAG_HAS_TRBE 1
763 #define KVM_HOST_DATA_FLAG_TRBE_ENABLED 2
764 #define KVM_HOST_DATA_FLAG_EL1_TRACING_CONFIGURED 3
765 #define KVM_HOST_DATA_FLAG_VCPU_IN_HYP_CONTEXT 4
766 #define KVM_HOST_DATA_FLAG_L1_VNCR_MAPPED 5
767 #define KVM_HOST_DATA_FLAG_HAS_BRBE 6
768 unsigned long flags;
769
770 struct kvm_cpu_context host_ctxt;
771
772 /*
773 * Hyp VA.
774 * sve_state is only used in pKVM and if system_supports_sve().
775 */
776 struct cpu_sve_state *sve_state;
777
778 /* Used by pKVM only. */
779 u64 fpmr;
780
781 /* Ownership of the FP regs */
782 enum {
783 FP_STATE_FREE,
784 FP_STATE_HOST_OWNED,
785 FP_STATE_GUEST_OWNED,
786 } fp_owner;
787
788 /*
789 * host_debug_state contains the host registers which are
790 * saved and restored during world switches.
791 */
792 struct {
793 /* {Break,watch}point registers */
794 struct kvm_guest_debug_arch regs;
795 /* Statistical profiling extension */
796 u64 pmscr_el1;
797 u64 pmblimitr_el1;
798 /* Self-hosted trace */
799 u64 trfcr_el1;
800 u64 trblimitr_el1;
801 /* Values of trap registers for the host before guest entry. */
802 u64 mdcr_el2;
803 u64 brbcr_el1;
804 } host_debug_state;
805
806 /* Guest trace filter value */
807 u64 trfcr_while_in_guest;
808
809 /* Number of programmable event counters (PMCR_EL0.N) for this CPU */
810 unsigned int nr_event_counters;
811
812 /* Number of debug breakpoints/watchpoints for this CPU (minus 1) */
813 unsigned int debug_brps;
814 unsigned int debug_wrps;
815
816 /* Last vgic_irq part of the AP list recorded in an LR */
817 struct vgic_irq *last_lr_irq;
818
819 /* PPI state tracking for GICv5-based guests */
820 struct {
821 DECLARE_BITMAP(pendr, VGIC_V5_NR_PRIVATE_IRQS);
822
823 /* The saved state of the regs when leaving the guest */
824 DECLARE_BITMAP(activer_exit, VGIC_V5_NR_PRIVATE_IRQS);
825 } vgic_v5_ppi_state;
826 };
827
828 struct kvm_host_psci_config {
829 /* PSCI version used by host. */
830 u32 version;
831 u32 smccc_version;
832
833 /* Function IDs used by host if version is v0.1. */
834 struct psci_0_1_function_ids function_ids_0_1;
835
836 bool psci_0_1_cpu_suspend_implemented;
837 bool psci_0_1_cpu_on_implemented;
838 bool psci_0_1_cpu_off_implemented;
839 bool psci_0_1_migrate_implemented;
840 };
841
842 extern struct kvm_host_psci_config kvm_nvhe_sym(kvm_host_psci_config);
843 #define kvm_host_psci_config CHOOSE_NVHE_SYM(kvm_host_psci_config)
844
845 extern s64 kvm_nvhe_sym(hyp_physvirt_offset);
846 #define hyp_physvirt_offset CHOOSE_NVHE_SYM(hyp_physvirt_offset)
847
848 extern u64 kvm_nvhe_sym(hyp_cpu_logical_map)[NR_CPUS];
849 #define hyp_cpu_logical_map CHOOSE_NVHE_SYM(hyp_cpu_logical_map)
850
851 struct vcpu_reset_state {
852 unsigned long pc;
853 unsigned long r0;
854 bool be;
855 bool reset;
856 };
857
858 struct vncr_tlb;
859
860 struct kvm_vcpu_arch {
861 struct kvm_cpu_context ctxt;
862
863 /*
864 * Guest floating point state
865 *
866 * The architecture has two main floating point extensions,
867 * the original FPSIMD and SVE. These have overlapping
868 * register views, with the FPSIMD V registers occupying the
869 * low 128 bits of the SVE Z registers. When the core
870 * floating point code saves the register state of a task it
871 * records which view it saved in fp_type.
872 */
873 void *sve_state;
874 enum fp_type fp_type;
875 unsigned int sve_max_vl;
876
877 /* Stage 2 paging state used by the hardware on next switch */
878 struct kvm_s2_mmu *hw_mmu;
879
880 /* Values of trap registers for the guest. */
881 u64 hcr_el2;
882 u64 hcrx_el2;
883 u64 mdcr_el2;
884
885 struct {
886 u64 r;
887 u64 w;
888 } fgt[__NR_FGT_GROUP_IDS__];
889
890 /* Exception Information */
891 struct kvm_vcpu_fault_info fault;
892
893 /* Configuration flags, set once and for all before the vcpu can run */
894 u8 cflags;
895
896 /* Input flags to the hypervisor code, potentially cleared after use */
897 u8 iflags;
898
899 /* State flags for kernel bookkeeping, unused by the hypervisor code */
900 u16 sflags;
901
902 /*
903 * Don't run the guest (internal implementation need).
904 *
905 * Contrary to the flags above, this is set/cleared outside of
906 * a vcpu context, and thus cannot be mixed with the flags
907 * themselves (or the flag accesses need to be made atomic).
908 */
909 bool pause;
910
911 /*
912 * We maintain more than a single set of debug registers to support
913 * debugging the guest from the host and to maintain separate host and
914 * guest state during world switches. vcpu_debug_state are the debug
915 * registers of the vcpu as the guest sees them.
916 *
917 * external_debug_state contains the debug values we want to debug the
918 * guest. This is set via the KVM_SET_GUEST_DEBUG ioctl.
919 */
920 struct kvm_guest_debug_arch vcpu_debug_state;
921 struct kvm_guest_debug_arch external_debug_state;
922 u64 external_mdscr_el1;
923
924 enum {
925 VCPU_DEBUG_FREE,
926 VCPU_DEBUG_HOST_OWNED,
927 VCPU_DEBUG_GUEST_OWNED,
928 } debug_owner;
929
930 /* VGIC state */
931 struct vgic_cpu vgic_cpu;
932 struct arch_timer_cpu timer_cpu;
933 struct kvm_pmu pmu;
934
935 /* vcpu power state */
936 struct kvm_mp_state mp_state;
937 spinlock_t mp_state_lock;
938
939 /* Cache some mmu pages needed inside spinlock regions */
940 struct kvm_mmu_memory_cache mmu_page_cache;
941
942 /* Pages to top-up the pKVM/EL2 guest pool */
943 struct kvm_hyp_memcache pkvm_memcache;
944
945 /* Virtual SError ESR to restore when HCR_EL2.VSE is set */
946 u64 vsesr_el2;
947
948 /* Additional reset state */
949 struct vcpu_reset_state reset_state;
950
951 /* Guest PV state */
952 struct {
953 u64 last_steal;
954 gpa_t base;
955 } steal;
956
957 /* Per-vcpu CCSIDR override or NULL */
958 u32 *ccsidr;
959
960 /* Per-vcpu TLB for VNCR_EL2 -- NULL when !NV */
961 struct vncr_tlb *vncr_tlb;
962
963 /* Hyp-readable copy of kvm_vcpu::pid */
964 pid_t pid;
965 };
966
967 /*
968 * Each 'flag' is composed of a comma-separated triplet:
969 *
970 * - the flag-set it belongs to in the vcpu->arch structure
971 * - the value for that flag
972 * - the mask for that flag
973 *
974 * __vcpu_single_flag() builds such a triplet for a single-bit flag.
975 * unpack_vcpu_flag() extract the flag value from the triplet for
976 * direct use outside of the flag accessors.
977 */
978 #define __vcpu_single_flag(_set, _f) _set, (_f), (_f)
979
980 #define __unpack_flag(_set, _f, _m) _f
981 #define unpack_vcpu_flag(...) __unpack_flag(__VA_ARGS__)
982
983 #define __build_check_flag(v, flagset, f, m) \
984 do { \
985 typeof(v->arch.flagset) *_fset; \
986 \
987 /* Check that the flags fit in the mask */ \
988 BUILD_BUG_ON(HWEIGHT(m) != HWEIGHT((f) | (m))); \
989 /* Check that the flags fit in the type */ \
990 BUILD_BUG_ON((sizeof(*_fset) * 8) <= __fls(m)); \
991 } while (0)
992
993 #define __vcpu_get_flag(v, flagset, f, m) \
994 ({ \
995 __build_check_flag(v, flagset, f, m); \
996 \
997 READ_ONCE(v->arch.flagset) & (m); \
998 })
999
1000 /*
1001 * Note that the set/clear accessors must be preempt-safe in order to
1002 * avoid nesting them with load/put which also manipulate flags...
1003 */
1004 #ifdef __KVM_NVHE_HYPERVISOR__
1005 /* the nVHE hypervisor is always non-preemptible */
1006 #define __vcpu_flags_preempt_disable()
1007 #define __vcpu_flags_preempt_enable()
1008 #else
1009 #define __vcpu_flags_preempt_disable() preempt_disable()
1010 #define __vcpu_flags_preempt_enable() preempt_enable()
1011 #endif
1012
1013 #define __vcpu_set_flag(v, flagset, f, m) \
1014 do { \
1015 typeof(v->arch.flagset) *fset; \
1016 \
1017 __build_check_flag(v, flagset, f, m); \
1018 \
1019 fset = &v->arch.flagset; \
1020 __vcpu_flags_preempt_disable(); \
1021 if (HWEIGHT(m) > 1) \
1022 *fset &= ~(m); \
1023 *fset |= (f); \
1024 __vcpu_flags_preempt_enable(); \
1025 } while (0)
1026
1027 #define __vcpu_clear_flag(v, flagset, f, m) \
1028 do { \
1029 typeof(v->arch.flagset) *fset; \
1030 \
1031 __build_check_flag(v, flagset, f, m); \
1032 \
1033 fset = &v->arch.flagset; \
1034 __vcpu_flags_preempt_disable(); \
1035 *fset &= ~(m); \
1036 __vcpu_flags_preempt_enable(); \
1037 } while (0)
1038
1039 #define __vcpu_test_and_clear_flag(v, flagset, f, m) \
1040 ({ \
1041 typeof(v->arch.flagset) set; \
1042 \
1043 set = __vcpu_get_flag(v, flagset, f, m); \
1044 __vcpu_clear_flag(v, flagset, f, m); \
1045 \
1046 set; \
1047 })
1048
1049 #define vcpu_get_flag(v, ...) __vcpu_get_flag((v), __VA_ARGS__)
1050 #define vcpu_set_flag(v, ...) __vcpu_set_flag((v), __VA_ARGS__)
1051 #define vcpu_clear_flag(v, ...) __vcpu_clear_flag((v), __VA_ARGS__)
1052 #define vcpu_test_and_clear_flag(v, ...) \
1053 __vcpu_test_and_clear_flag((v), __VA_ARGS__)
1054
1055 /* KVM_ARM_VCPU_INIT completed */
1056 #define VCPU_INITIALIZED __vcpu_single_flag(cflags, BIT(0))
1057 /* SVE config completed */
1058 #define VCPU_SVE_FINALIZED __vcpu_single_flag(cflags, BIT(1))
1059 /* pKVM VCPU setup completed */
1060 #define VCPU_PKVM_FINALIZED __vcpu_single_flag(cflags, BIT(2))
1061
1062 /* Exception pending */
1063 #define PENDING_EXCEPTION __vcpu_single_flag(iflags, BIT(0))
1064 /*
1065 * PC increment. Overlaps with EXCEPT_MASK on purpose so that it can't
1066 * be set together with an exception...
1067 */
1068 #define INCREMENT_PC __vcpu_single_flag(iflags, BIT(1))
1069 /* Target EL/MODE (not a single flag, but let's abuse the macro) */
1070 #define EXCEPT_MASK __vcpu_single_flag(iflags, GENMASK(3, 1))
1071
1072 /* Helpers to encode exceptions with minimum fuss */
1073 #define __EXCEPT_MASK_VAL unpack_vcpu_flag(EXCEPT_MASK)
1074 #define __EXCEPT_SHIFT __builtin_ctzl(__EXCEPT_MASK_VAL)
1075 #define __vcpu_except_flags(_f) iflags, (_f << __EXCEPT_SHIFT), __EXCEPT_MASK_VAL
1076
1077 /*
1078 * When PENDING_EXCEPTION is set, EXCEPT_MASK can take the following
1079 * values:
1080 *
1081 * For AArch32 EL1:
1082 */
1083 #define EXCEPT_AA32_UND __vcpu_except_flags(0)
1084 #define EXCEPT_AA32_IABT __vcpu_except_flags(1)
1085 #define EXCEPT_AA32_DABT __vcpu_except_flags(2)
1086 /* For AArch64: */
1087 #define EXCEPT_AA64_EL1_SYNC __vcpu_except_flags(0)
1088 #define EXCEPT_AA64_EL1_IRQ __vcpu_except_flags(1)
1089 #define EXCEPT_AA64_EL1_FIQ __vcpu_except_flags(2)
1090 #define EXCEPT_AA64_EL1_SERR __vcpu_except_flags(3)
1091 /* For AArch64 with NV: */
1092 #define EXCEPT_AA64_EL2_SYNC __vcpu_except_flags(4)
1093 #define EXCEPT_AA64_EL2_IRQ __vcpu_except_flags(5)
1094 #define EXCEPT_AA64_EL2_FIQ __vcpu_except_flags(6)
1095 #define EXCEPT_AA64_EL2_SERR __vcpu_except_flags(7)
1096
1097 /* Physical CPU not in supported_cpus */
1098 #define ON_UNSUPPORTED_CPU __vcpu_single_flag(sflags, BIT(0))
1099 /* WFIT instruction trapped */
1100 #define IN_WFIT __vcpu_single_flag(sflags, BIT(1))
1101 /* vcpu system registers loaded on physical CPU */
1102 #define SYSREGS_ON_CPU __vcpu_single_flag(sflags, BIT(2))
1103 /* Software step state is Active-pending for external debug */
1104 #define HOST_SS_ACTIVE_PENDING __vcpu_single_flag(sflags, BIT(3))
1105 /* Software step state is Active pending for guest debug */
1106 #define GUEST_SS_ACTIVE_PENDING __vcpu_single_flag(sflags, BIT(4))
1107 /* PMUSERENR for the guest EL0 is on physical CPU */
1108 #define PMUSERENR_ON_CPU __vcpu_single_flag(sflags, BIT(5))
1109 /* WFI instruction trapped */
1110 #define IN_WFI __vcpu_single_flag(sflags, BIT(6))
1111 /* KVM is currently emulating a nested ERET */
1112 #define IN_NESTED_ERET __vcpu_single_flag(sflags, BIT(7))
1113 /* SError pending for nested guest */
1114 #define NESTED_SERROR_PENDING __vcpu_single_flag(sflags, BIT(8))
1115
1116
1117 /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */
1118 #define vcpu_sve_pffr(vcpu) (kern_hyp_va((vcpu)->arch.sve_state) + \
1119 sve_ffr_offset((vcpu)->arch.sve_max_vl))
1120
1121 #define vcpu_sve_max_vq(vcpu) sve_vq_from_vl((vcpu)->arch.sve_max_vl)
1122
1123 #define vcpu_sve_zcr_elx(vcpu) \
1124 (unlikely(is_hyp_ctxt(vcpu)) ? ZCR_EL2 : ZCR_EL1)
1125
1126 #define sve_state_size_from_vl(sve_max_vl) ({ \
1127 size_t __size_ret; \
1128 unsigned int __vq; \
1129 \
1130 if (WARN_ON(!sve_vl_valid(sve_max_vl))) { \
1131 __size_ret = 0; \
1132 } else { \
1133 __vq = sve_vq_from_vl(sve_max_vl); \
1134 __size_ret = SVE_SIG_REGS_SIZE(__vq); \
1135 } \
1136 \
1137 __size_ret; \
1138 })
1139
1140 #define vcpu_sve_state_size(vcpu) sve_state_size_from_vl((vcpu)->arch.sve_max_vl)
1141
1142 #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \
1143 KVM_GUESTDBG_USE_SW_BP | \
1144 KVM_GUESTDBG_USE_HW | \
1145 KVM_GUESTDBG_SINGLESTEP)
1146
1147 #define kvm_has_sve(kvm) (system_supports_sve() && \
1148 test_bit(KVM_ARCH_FLAG_GUEST_HAS_SVE, &(kvm)->arch.flags))
1149
1150 #ifdef __KVM_NVHE_HYPERVISOR__
1151 #define vcpu_has_sve(vcpu) kvm_has_sve(kern_hyp_va((vcpu)->kvm))
1152 #else
1153 #define vcpu_has_sve(vcpu) kvm_has_sve((vcpu)->kvm)
1154 #endif
1155
1156 #ifdef CONFIG_ARM64_PTR_AUTH
1157 #define vcpu_has_ptrauth(vcpu) \
1158 ((cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) || \
1159 cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) && \
1160 (vcpu_has_feature(vcpu, KVM_ARM_VCPU_PTRAUTH_ADDRESS) || \
1161 vcpu_has_feature(vcpu, KVM_ARM_VCPU_PTRAUTH_GENERIC)))
1162 #else
1163 #define vcpu_has_ptrauth(vcpu) false
1164 #endif
1165
1166 #define vcpu_on_unsupported_cpu(vcpu) \
1167 vcpu_get_flag(vcpu, ON_UNSUPPORTED_CPU)
1168
1169 #define vcpu_set_on_unsupported_cpu(vcpu) \
1170 vcpu_set_flag(vcpu, ON_UNSUPPORTED_CPU)
1171
1172 #define vcpu_clear_on_unsupported_cpu(vcpu) \
1173 vcpu_clear_flag(vcpu, ON_UNSUPPORTED_CPU)
1174
1175 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.regs)
1176
1177 /*
1178 * Only use __vcpu_sys_reg/ctxt_sys_reg if you know you want the
1179 * memory backed version of a register, and not the one most recently
1180 * accessed by a running VCPU. For example, for userspace access or
1181 * for system registers that are never context switched, but only
1182 * emulated.
1183 *
1184 * Don't bother with VNCR-based accesses in the nVHE code, it has no
1185 * business dealing with NV.
1186 */
___ctxt_sys_reg(const struct kvm_cpu_context * ctxt,int r)1187 static inline u64 *___ctxt_sys_reg(const struct kvm_cpu_context *ctxt, int r)
1188 {
1189 #if !defined (__KVM_NVHE_HYPERVISOR__)
1190 if (unlikely(cpus_have_final_cap(ARM64_HAS_NESTED_VIRT) &&
1191 r >= __VNCR_START__ && ctxt->vncr_array))
1192 return &ctxt->vncr_array[r - __VNCR_START__];
1193 #endif
1194 return (u64 *)&ctxt->sys_regs[r];
1195 }
1196
1197 #define __ctxt_sys_reg(c,r) \
1198 ({ \
1199 BUILD_BUG_ON(__builtin_constant_p(r) && \
1200 (r) >= NR_SYS_REGS); \
1201 ___ctxt_sys_reg(c, r); \
1202 })
1203
1204 #define ctxt_sys_reg(c,r) (*__ctxt_sys_reg(c,r))
1205
1206 u64 kvm_vcpu_apply_reg_masks(const struct kvm_vcpu *, enum vcpu_sysreg, u64);
1207
1208 #define __vcpu_assign_sys_reg(v, r, val) \
1209 do { \
1210 const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \
1211 u64 __v = (val); \
1212 if (vcpu_has_nv((v)) && (r) >= __SANITISED_REG_START__) \
1213 __v = kvm_vcpu_apply_reg_masks((v), (r), __v); \
1214 \
1215 ctxt_sys_reg(ctxt, (r)) = __v; \
1216 } while (0)
1217
1218 #define __vcpu_rmw_sys_reg(v, r, op, val) \
1219 do { \
1220 const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \
1221 u64 __v = ctxt_sys_reg(ctxt, (r)); \
1222 __v op (val); \
1223 if (vcpu_has_nv((v)) && (r) >= __SANITISED_REG_START__) \
1224 __v = kvm_vcpu_apply_reg_masks((v), (r), __v); \
1225 \
1226 ctxt_sys_reg(ctxt, (r)) = __v; \
1227 } while (0)
1228
1229 #define __vcpu_sys_reg(v,r) \
1230 ({ \
1231 const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \
1232 u64 __v = ctxt_sys_reg(ctxt, (r)); \
1233 if (vcpu_has_nv((v)) && (r) >= __SANITISED_REG_START__) \
1234 __v = kvm_vcpu_apply_reg_masks((v), (r), __v); \
1235 __v; \
1236 })
1237
1238 u64 vcpu_read_sys_reg(const struct kvm_vcpu *, enum vcpu_sysreg);
1239 void vcpu_write_sys_reg(struct kvm_vcpu *, u64, enum vcpu_sysreg);
1240
1241 struct kvm_vm_stat {
1242 struct kvm_vm_stat_generic generic;
1243 };
1244
1245 struct kvm_vcpu_stat {
1246 struct kvm_vcpu_stat_generic generic;
1247 u64 hvc_exit_stat;
1248 u64 wfe_exit_stat;
1249 u64 wfi_exit_stat;
1250 u64 mmio_exit_user;
1251 u64 mmio_exit_kernel;
1252 u64 signal_exits;
1253 u64 exits;
1254 };
1255
1256 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
1257 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
1258 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
1259 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
1260
1261 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu);
1262 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices);
1263
1264 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu,
1265 struct kvm_vcpu_events *events);
1266
1267 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu,
1268 struct kvm_vcpu_events *events);
1269
1270 void kvm_arm_halt_guest(struct kvm *kvm);
1271 void kvm_arm_resume_guest(struct kvm *kvm);
1272
1273 #define vcpu_has_run_once(vcpu) (!!READ_ONCE((vcpu)->pid))
1274
1275 #ifndef __KVM_NVHE_HYPERVISOR__
1276 #define kvm_call_hyp_nvhe(f, ...) \
1277 ({ \
1278 struct arm_smccc_res res; \
1279 \
1280 arm_smccc_1_1_hvc(KVM_HOST_SMCCC_FUNC(f), \
1281 ##__VA_ARGS__, &res); \
1282 WARN_ON(res.a0 != SMCCC_RET_SUCCESS); \
1283 \
1284 res.a1; \
1285 })
1286
1287 /*
1288 * The isb() below is there to guarantee the same behaviour on VHE as on !VHE,
1289 * where the eret to EL1 acts as a context synchronization event.
1290 */
1291 #define kvm_call_hyp(f, ...) \
1292 do { \
1293 if (has_vhe()) { \
1294 f(__VA_ARGS__); \
1295 isb(); \
1296 } else { \
1297 kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \
1298 } \
1299 } while(0)
1300
1301 #define kvm_call_hyp_ret(f, ...) \
1302 ({ \
1303 typeof(f(__VA_ARGS__)) ret; \
1304 \
1305 if (has_vhe()) { \
1306 ret = f(__VA_ARGS__); \
1307 } else { \
1308 ret = kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \
1309 } \
1310 \
1311 ret; \
1312 })
1313 #else /* __KVM_NVHE_HYPERVISOR__ */
1314 #define kvm_call_hyp(f, ...) f(__VA_ARGS__)
1315 #define kvm_call_hyp_ret(f, ...) f(__VA_ARGS__)
1316 #define kvm_call_hyp_nvhe(f, ...) f(__VA_ARGS__)
1317 #endif /* __KVM_NVHE_HYPERVISOR__ */
1318
1319 int handle_exit(struct kvm_vcpu *vcpu, int exception_index);
1320 void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index);
1321
1322 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu);
1323 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu);
1324 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu);
1325 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu);
1326 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu);
1327 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu);
1328 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu);
1329
1330 void kvm_sys_regs_create_debugfs(struct kvm *kvm);
1331 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu);
1332
1333 int __init kvm_sys_reg_table_init(void);
1334 struct sys_reg_desc;
1335 int __init populate_sysreg_config(const struct sys_reg_desc *sr,
1336 unsigned int idx);
1337 int __init populate_nv_trap_config(void);
1338
1339 void kvm_calculate_traps(struct kvm_vcpu *vcpu);
1340
1341 /* MMIO helpers */
1342 void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data);
1343 unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len);
1344
1345 int kvm_handle_mmio_return(struct kvm_vcpu *vcpu);
1346 int io_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa);
1347
1348 /*
1349 * Returns true if a Performance Monitoring Interrupt (PMI), a.k.a. perf event,
1350 * arrived in guest context. For arm64, any event that arrives while a vCPU is
1351 * loaded is considered to be "in guest".
1352 */
kvm_arch_pmi_in_guest(struct kvm_vcpu * vcpu)1353 static inline bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu)
1354 {
1355 return IS_ENABLED(CONFIG_GUEST_PERF_EVENTS) && !!vcpu;
1356 }
1357
1358 long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu);
1359 gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu);
1360 void kvm_update_stolen_time(struct kvm_vcpu *vcpu);
1361
1362 bool kvm_arm_pvtime_supported(void);
1363 int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu,
1364 struct kvm_device_attr *attr);
1365 int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu,
1366 struct kvm_device_attr *attr);
1367 int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu,
1368 struct kvm_device_attr *attr);
1369
1370 extern unsigned int __ro_after_init kvm_arm_vmid_bits;
1371 int __init kvm_arm_vmid_alloc_init(void);
1372 void __init kvm_arm_vmid_alloc_free(void);
1373 void kvm_arm_vmid_update(struct kvm_vmid *kvm_vmid);
1374 void kvm_arm_vmid_clear_active(void);
1375
kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch * vcpu_arch)1376 static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch)
1377 {
1378 vcpu_arch->steal.base = INVALID_GPA;
1379 }
1380
kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch * vcpu_arch)1381 static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch)
1382 {
1383 return (vcpu_arch->steal.base != INVALID_GPA);
1384 }
1385
1386 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);
1387
1388 DECLARE_KVM_HYP_PER_CPU(struct kvm_host_data, kvm_host_data);
1389
1390 /*
1391 * How we access per-CPU host data depends on the where we access it from,
1392 * and the mode we're in:
1393 *
1394 * - VHE and nVHE hypervisor bits use their locally defined instance
1395 *
1396 * - the rest of the kernel use either the VHE or nVHE one, depending on
1397 * the mode we're running in.
1398 *
1399 * Unless we're in protected mode, fully deprivileged, and the nVHE
1400 * per-CPU stuff is exclusively accessible to the protected EL2 code.
1401 * In this case, the EL1 code uses the *VHE* data as its private state
1402 * (which makes sense in a way as there shouldn't be any shared state
1403 * between the host and the hypervisor).
1404 *
1405 * Yes, this is all totally trivial. Shoot me now.
1406 */
1407 #if defined(__KVM_NVHE_HYPERVISOR__) || defined(__KVM_VHE_HYPERVISOR__)
1408 #define host_data_ptr(f) (&this_cpu_ptr(&kvm_host_data)->f)
1409 #else
1410 #define host_data_ptr(f) \
1411 (static_branch_unlikely(&kvm_protected_mode_initialized) ? \
1412 &this_cpu_ptr(&kvm_host_data)->f : \
1413 &this_cpu_ptr_hyp_sym(kvm_host_data)->f)
1414 #endif
1415
1416 #define host_data_test_flag(flag) \
1417 (test_bit(KVM_HOST_DATA_FLAG_##flag, host_data_ptr(flags)))
1418 #define host_data_set_flag(flag) \
1419 set_bit(KVM_HOST_DATA_FLAG_##flag, host_data_ptr(flags))
1420 #define host_data_clear_flag(flag) \
1421 clear_bit(KVM_HOST_DATA_FLAG_##flag, host_data_ptr(flags))
1422
1423 /* Check whether the FP regs are owned by the guest */
guest_owns_fp_regs(void)1424 static inline bool guest_owns_fp_regs(void)
1425 {
1426 return *host_data_ptr(fp_owner) == FP_STATE_GUEST_OWNED;
1427 }
1428
1429 /* Check whether the FP regs are owned by the host */
host_owns_fp_regs(void)1430 static inline bool host_owns_fp_regs(void)
1431 {
1432 return *host_data_ptr(fp_owner) == FP_STATE_HOST_OWNED;
1433 }
1434
kvm_init_host_cpu_context(struct kvm_cpu_context * cpu_ctxt)1435 static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt)
1436 {
1437 /* The host's MPIDR is immutable, so let's set it up at boot time */
1438 ctxt_sys_reg(cpu_ctxt, MPIDR_EL1) = read_cpuid_mpidr();
1439 }
1440
kvm_system_needs_idmapped_vectors(void)1441 static inline bool kvm_system_needs_idmapped_vectors(void)
1442 {
1443 return cpus_have_final_cap(ARM64_SPECTRE_V3A);
1444 }
1445
1446 void kvm_init_host_debug_data(void);
1447 void kvm_debug_init_vhe(void);
1448 void kvm_vcpu_load_debug(struct kvm_vcpu *vcpu);
1449 void kvm_vcpu_put_debug(struct kvm_vcpu *vcpu);
1450 void kvm_debug_set_guest_ownership(struct kvm_vcpu *vcpu);
1451 void kvm_debug_handle_oslar(struct kvm_vcpu *vcpu, u64 val);
1452
1453 #define kvm_vcpu_os_lock_enabled(vcpu) \
1454 (!!(__vcpu_sys_reg(vcpu, OSLSR_EL1) & OSLSR_EL1_OSLK))
1455
1456 #define kvm_debug_regs_in_use(vcpu) \
1457 ((vcpu)->arch.debug_owner != VCPU_DEBUG_FREE)
1458 #define kvm_host_owns_debug_regs(vcpu) \
1459 ((vcpu)->arch.debug_owner == VCPU_DEBUG_HOST_OWNED)
1460 #define kvm_guest_owns_debug_regs(vcpu) \
1461 ((vcpu)->arch.debug_owner == VCPU_DEBUG_GUEST_OWNED)
1462
1463 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
1464 struct kvm_device_attr *attr);
1465 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
1466 struct kvm_device_attr *attr);
1467 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
1468 struct kvm_device_attr *attr);
1469
1470 int kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm,
1471 struct kvm_arm_copy_mte_tags *copy_tags);
1472 int kvm_vm_ioctl_set_counter_offset(struct kvm *kvm,
1473 struct kvm_arm_counter_offset *offset);
1474 int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm,
1475 struct reg_mask_range *range);
1476
1477 /* Guest/host FPSIMD coordination helpers */
1478 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu);
1479 void kvm_arch_vcpu_ctxflush_fp(struct kvm_vcpu *vcpu);
1480 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu);
1481 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu);
1482
kvm_pmu_counter_deferred(struct perf_event_attr * attr)1483 static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr)
1484 {
1485 return (!has_vhe() && attr->exclude_host);
1486 }
1487
1488 #ifdef CONFIG_KVM
1489 void kvm_set_pmu_events(u64 set, struct perf_event_attr *attr);
1490 void kvm_clr_pmu_events(u64 clr);
1491 bool kvm_set_pmuserenr(u64 val);
1492 void kvm_enable_trbe(void);
1493 void kvm_disable_trbe(void);
1494 void kvm_tracing_set_el1_configuration(u64 trfcr_while_in_guest);
1495 #else
kvm_set_pmu_events(u64 set,struct perf_event_attr * attr)1496 static inline void kvm_set_pmu_events(u64 set, struct perf_event_attr *attr) {}
kvm_clr_pmu_events(u64 clr)1497 static inline void kvm_clr_pmu_events(u64 clr) {}
kvm_set_pmuserenr(u64 val)1498 static inline bool kvm_set_pmuserenr(u64 val)
1499 {
1500 return false;
1501 }
kvm_enable_trbe(void)1502 static inline void kvm_enable_trbe(void) {}
kvm_disable_trbe(void)1503 static inline void kvm_disable_trbe(void) {}
kvm_tracing_set_el1_configuration(u64 trfcr_while_in_guest)1504 static inline void kvm_tracing_set_el1_configuration(u64 trfcr_while_in_guest) {}
1505 #endif
1506
1507 void kvm_vcpu_load_vhe(struct kvm_vcpu *vcpu);
1508 void kvm_vcpu_put_vhe(struct kvm_vcpu *vcpu);
1509
1510 int __init kvm_set_ipa_limit(void);
1511 u32 kvm_get_pa_bits(struct kvm *kvm);
1512
1513 #define __KVM_HAVE_ARCH_VM_ALLOC
1514 struct kvm *kvm_arch_alloc_vm(void);
1515
1516 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS
1517
1518 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS_RANGE
1519
1520 #define kvm_vm_is_protected(kvm) (is_protected_kvm_enabled() && (kvm)->arch.pkvm.is_protected)
1521
1522 #define vcpu_is_protected(vcpu) kvm_vm_is_protected((vcpu)->kvm)
1523
1524 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature);
1525 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu);
1526
1527 #define kvm_arm_vcpu_sve_finalized(vcpu) vcpu_get_flag(vcpu, VCPU_SVE_FINALIZED)
1528
1529 #define kvm_has_mte(kvm) \
1530 (system_supports_mte() && \
1531 test_bit(KVM_ARCH_FLAG_MTE_ENABLED, &(kvm)->arch.flags))
1532
1533 #define kvm_supports_32bit_el0() \
1534 (system_supports_32bit_el0() && \
1535 !static_branch_unlikely(&arm64_mismatched_32bit_el0))
1536
1537 #define kvm_vm_has_ran_once(kvm) \
1538 (test_bit(KVM_ARCH_FLAG_HAS_RAN_ONCE, &(kvm)->arch.flags))
1539
__vcpu_has_feature(const struct kvm_arch * ka,int feature)1540 static inline bool __vcpu_has_feature(const struct kvm_arch *ka, int feature)
1541 {
1542 return test_bit(feature, ka->vcpu_features);
1543 }
1544
1545 #define kvm_vcpu_has_feature(k, f) __vcpu_has_feature(&(k)->arch, (f))
1546 #define vcpu_has_feature(v, f) __vcpu_has_feature(&(v)->kvm->arch, (f))
1547
1548 #define kvm_vcpu_initialized(v) vcpu_get_flag(v, VCPU_INITIALIZED)
1549
1550 int kvm_trng_call(struct kvm_vcpu *vcpu);
1551 #ifdef CONFIG_KVM
1552 extern phys_addr_t hyp_mem_base;
1553 extern phys_addr_t hyp_mem_size;
1554 void __init kvm_hyp_reserve(void);
1555 #else
kvm_hyp_reserve(void)1556 static inline void kvm_hyp_reserve(void) { }
1557 #endif
1558
1559 void kvm_arm_vcpu_power_off(struct kvm_vcpu *vcpu);
1560 bool kvm_arm_vcpu_stopped(struct kvm_vcpu *vcpu);
1561
__vm_id_reg(struct kvm_arch * ka,u32 reg)1562 static inline u64 *__vm_id_reg(struct kvm_arch *ka, u32 reg)
1563 {
1564 switch (reg) {
1565 case sys_reg(3, 0, 0, 1, 0) ... sys_reg(3, 0, 0, 7, 7):
1566 return &ka->id_regs[IDREG_IDX(reg)];
1567 case SYS_CTR_EL0:
1568 return &ka->ctr_el0;
1569 case SYS_MIDR_EL1:
1570 return &ka->midr_el1;
1571 case SYS_REVIDR_EL1:
1572 return &ka->revidr_el1;
1573 case SYS_AIDR_EL1:
1574 return &ka->aidr_el1;
1575 default:
1576 WARN_ON_ONCE(1);
1577 return NULL;
1578 }
1579 }
1580
1581 #define kvm_read_vm_id_reg(kvm, reg) \
1582 ({ u64 __val = *__vm_id_reg(&(kvm)->arch, reg); __val; })
1583
1584 void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val);
1585
1586 #define __expand_field_sign_unsigned(id, fld, val) \
1587 ((u64)SYS_FIELD_VALUE(id, fld, val))
1588
1589 #define __expand_field_sign_signed(id, fld, val) \
1590 ({ \
1591 u64 __val = SYS_FIELD_VALUE(id, fld, val); \
1592 sign_extend64(__val, id##_##fld##_WIDTH - 1); \
1593 })
1594
1595 #define get_idreg_field_unsigned(kvm, id, fld) \
1596 ({ \
1597 u64 __val = kvm_read_vm_id_reg((kvm), SYS_##id); \
1598 FIELD_GET(id##_##fld##_MASK, __val); \
1599 })
1600
1601 #define get_idreg_field_signed(kvm, id, fld) \
1602 ({ \
1603 u64 __val = get_idreg_field_unsigned(kvm, id, fld); \
1604 sign_extend64(__val, id##_##fld##_WIDTH - 1); \
1605 })
1606
1607 #define get_idreg_field_enum(kvm, id, fld) \
1608 get_idreg_field_unsigned(kvm, id, fld)
1609
1610 #define kvm_cmp_feat_signed(kvm, id, fld, op, limit) \
1611 (get_idreg_field_signed((kvm), id, fld) op __expand_field_sign_signed(id, fld, limit))
1612
1613 #define kvm_cmp_feat_unsigned(kvm, id, fld, op, limit) \
1614 (get_idreg_field_unsigned((kvm), id, fld) op __expand_field_sign_unsigned(id, fld, limit))
1615
1616 #define kvm_cmp_feat(kvm, id, fld, op, limit) \
1617 (id##_##fld##_SIGNED ? \
1618 kvm_cmp_feat_signed(kvm, id, fld, op, limit) : \
1619 kvm_cmp_feat_unsigned(kvm, id, fld, op, limit))
1620
1621 #define __kvm_has_feat(kvm, id, fld, limit) \
1622 kvm_cmp_feat(kvm, id, fld, >=, limit)
1623
1624 #define kvm_has_feat(kvm, ...) __kvm_has_feat(kvm, __VA_ARGS__)
1625
1626 #define __kvm_has_feat_enum(kvm, id, fld, val) \
1627 kvm_cmp_feat_unsigned(kvm, id, fld, ==, val)
1628
1629 #define kvm_has_feat_enum(kvm, ...) __kvm_has_feat_enum(kvm, __VA_ARGS__)
1630
1631 #define kvm_has_feat_range(kvm, id, fld, min, max) \
1632 (kvm_cmp_feat(kvm, id, fld, >=, min) && \
1633 kvm_cmp_feat(kvm, id, fld, <=, max))
1634
1635 /* Check for a given level of PAuth support */
1636 #define kvm_has_pauth(k, l) \
1637 ({ \
1638 bool pa, pi, pa3; \
1639 \
1640 pa = kvm_has_feat((k), ID_AA64ISAR1_EL1, APA, l); \
1641 pa &= kvm_has_feat((k), ID_AA64ISAR1_EL1, GPA, IMP); \
1642 pi = kvm_has_feat((k), ID_AA64ISAR1_EL1, API, l); \
1643 pi &= kvm_has_feat((k), ID_AA64ISAR1_EL1, GPI, IMP); \
1644 pa3 = kvm_has_feat((k), ID_AA64ISAR2_EL1, APA3, l); \
1645 pa3 &= kvm_has_feat((k), ID_AA64ISAR2_EL1, GPA3, IMP); \
1646 \
1647 (pa + pi + pa3) == 1; \
1648 })
1649
1650 #define kvm_has_fpmr(k) \
1651 (system_supports_fpmr() && \
1652 kvm_has_feat((k), ID_AA64PFR2_EL1, FPMR, IMP))
1653
1654 #define kvm_has_tcr2(k) \
1655 (kvm_has_feat((k), ID_AA64MMFR3_EL1, TCRX, IMP))
1656
1657 #define kvm_has_s1pie(k) \
1658 (kvm_has_feat((k), ID_AA64MMFR3_EL1, S1PIE, IMP))
1659
1660 #define kvm_has_s1poe(k) \
1661 (system_supports_poe() && \
1662 kvm_has_feat((k), ID_AA64MMFR3_EL1, S1POE, IMP))
1663
1664 #define kvm_has_ras(k) \
1665 (kvm_has_feat((k), ID_AA64PFR0_EL1, RAS, IMP))
1666
1667 #define kvm_has_sctlr2(k) \
1668 (kvm_has_feat((k), ID_AA64MMFR3_EL1, SCTLRX, IMP))
1669
kvm_arch_has_irq_bypass(void)1670 static inline bool kvm_arch_has_irq_bypass(void)
1671 {
1672 return true;
1673 }
1674
1675 void compute_fgu(struct kvm *kvm, enum fgt_group_id fgt);
1676 struct resx get_reg_fixed_bits(struct kvm *kvm, enum vcpu_sysreg reg);
1677 void check_feature_map(void);
1678 void kvm_vcpu_load_fgt(struct kvm_vcpu *vcpu);
1679
__fgt_reg_to_group_id(enum vcpu_sysreg reg)1680 static __always_inline enum fgt_group_id __fgt_reg_to_group_id(enum vcpu_sysreg reg)
1681 {
1682 switch (reg) {
1683 case HFGRTR_EL2:
1684 case HFGWTR_EL2:
1685 return HFGRTR_GROUP;
1686 case HFGITR_EL2:
1687 return HFGITR_GROUP;
1688 case HDFGRTR_EL2:
1689 case HDFGWTR_EL2:
1690 return HDFGRTR_GROUP;
1691 case HAFGRTR_EL2:
1692 return HAFGRTR_GROUP;
1693 case HFGRTR2_EL2:
1694 case HFGWTR2_EL2:
1695 return HFGRTR2_GROUP;
1696 case HFGITR2_EL2:
1697 return HFGITR2_GROUP;
1698 case HDFGRTR2_EL2:
1699 case HDFGWTR2_EL2:
1700 return HDFGRTR2_GROUP;
1701 case ICH_HFGRTR_EL2:
1702 case ICH_HFGWTR_EL2:
1703 return ICH_HFGRTR_GROUP;
1704 case ICH_HFGITR_EL2:
1705 return ICH_HFGITR_GROUP;
1706 default:
1707 BUILD_BUG_ON(1);
1708 }
1709 }
1710
1711 #define vcpu_fgt(vcpu, reg) \
1712 ({ \
1713 enum fgt_group_id id = __fgt_reg_to_group_id(reg); \
1714 u64 *p; \
1715 switch (reg) { \
1716 case HFGWTR_EL2: \
1717 case HDFGWTR_EL2: \
1718 case HFGWTR2_EL2: \
1719 case HDFGWTR2_EL2: \
1720 case ICH_HFGWTR_EL2: \
1721 p = &(vcpu)->arch.fgt[id].w; \
1722 break; \
1723 default: \
1724 p = &(vcpu)->arch.fgt[id].r; \
1725 break; \
1726 } \
1727 \
1728 p; \
1729 })
1730
1731 long kvm_get_cap_for_kvm_ioctl(unsigned int ioctl, long *ext);
1732
1733 #endif /* __ARM64_KVM_HOST_H__ */
1734