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Searched refs:tg (Results 1 – 25 of 58) sorted by relevance

123

/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_timing_generator.h117 #define DCE110TG_FROM_TG(tg)\ argument
118 container_of(tg, struct dce110_timing_generator, base)
121 struct dce110_timing_generator *tg,
128 struct timing_generator *tg,
136 struct timing_generator *tg,
140 bool dce110_timing_generator_enable_crtc(struct timing_generator *tg);
141 bool dce110_timing_generator_disable_crtc(struct timing_generator *tg);
144 struct timing_generator *tg,
151 struct timing_generator *tg);
154 struct timing_generator *tg,
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H A Ddce110_timing_generator.c66 struct timing_generator *tg, in dce110_timing_generator_apply_front_porch_workaround() argument
92 struct timing_generator *tg) in dce110_timing_generator_is_in_vertical_blank() argument
97 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); in dce110_timing_generator_is_in_vertical_blank()
100 value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_is_in_vertical_blank()
106 struct timing_generator *tg, in dce110_timing_generator_set_early_control() argument
110 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); in dce110_timing_generator_set_early_control()
113 regval = dm_read_reg(tg->ctx, address); in dce110_timing_generator_set_early_control()
116 dm_write_reg(tg->ctx, address, regval); in dce110_timing_generator_set_early_control()
123 bool dce110_timing_generator_enable_crtc(struct timing_generator *tg) in dce110_timing_generator_enable_crtc() argument
127 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); in dce110_timing_generator_enable_crtc()
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H A Ddce110_timing_generator_v.c42 tg->ctx->logger
53 static bool dce110_timing_generator_v_enable_crtc(struct timing_generator *tg) in dce110_timing_generator_v_enable_crtc() argument
64 dm_write_reg(tg->ctx, in dce110_timing_generator_v_enable_crtc()
69 dm_write_reg(tg->ctx, mmCRTCV_MASTER_UPDATE_MODE, value); in dce110_timing_generator_v_enable_crtc()
74 dm_write_reg(tg->ctx, in dce110_timing_generator_v_enable_crtc()
80 static bool dce110_timing_generator_v_disable_crtc(struct timing_generator *tg) in dce110_timing_generator_v_disable_crtc() argument
84 value = dm_read_reg(tg->ctx, in dce110_timing_generator_v_disable_crtc()
90 dm_write_reg(tg->ctx, in dce110_timing_generator_v_disable_crtc()
99 static void dce110_timing_generator_v_blank_crtc(struct timing_generator *tg) in dce110_timing_generator_v_blank_crtc() argument
102 uint32_t value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_v_blank_crtc()
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/linux/drivers/gpu/drm/amd/display/dc/dce120/
H A Ddce120_timing_generator.c86 struct timing_generator *tg) in dce120_timing_generator_is_in_vertical_blank() argument
89 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); in dce120_timing_generator_is_in_vertical_blank()
91 tg->ctx, in dce120_timing_generator_is_in_vertical_blank()
102 struct timing_generator *tg, in dce120_timing_generator_validate_timing() argument
111 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); in dce120_timing_generator_validate_timing()
114 tg, in dce120_timing_generator_validate_timing()
128 static bool dce120_tg_validate_timing(struct timing_generator *tg, in dce120_tg_validate_timing() argument
131 return dce120_timing_generator_validate_timing(tg, timing, SIGNAL_TYPE_NONE); in dce120_tg_validate_timing()
136 static bool dce120_timing_generator_enable_crtc(struct timing_generator *tg) in dce120_timing_generator_enable_crtc() argument
139 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); in dce120_timing_generator_enable_crtc()
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/linux/kernel/sched/
H A Dautogroup.h16 struct task_group *tg; member
23 extern void autogroup_free(struct task_group *tg);
25 static inline bool task_group_is_autogroup(struct task_group *tg) in task_group_is_autogroup() argument
27 return !!tg->autogroup; in task_group_is_autogroup()
30 extern bool task_wants_autogroup(struct task_struct *p, struct task_group *tg);
33 autogroup_task_group(struct task_struct *p, struct task_group *tg) in autogroup_task_group() argument
38 if (enabled && task_wants_autogroup(p, tg)) in autogroup_task_group()
39 return p->signal->autogroup->tg; in autogroup_task_group()
41 return tg; in autogroup_task_group()
44 extern int autogroup_path(struct task_group *tg, char *buf, int buflen);
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H A Dautogroup.c37 autogroup_default.tg = &root_task_group; in autogroup_init()
44 void autogroup_free(struct task_group *tg) in autogroup_free() argument
46 kfree(tg->autogroup); in autogroup_free()
55 ag->tg->rt_se = NULL; in autogroup_destroy()
56 ag->tg->rt_rq = NULL; in autogroup_destroy()
58 sched_release_group(ag->tg); in autogroup_destroy()
59 sched_destroy_group(ag->tg); in autogroup_destroy()
90 struct task_group *tg; in autogroup_create() local
95 tg = sched_create_group(&root_task_group); in autogroup_create()
96 if (IS_ERR(tg)) in autogroup_create()
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H A Dext.h75 void scx_tg_init(struct task_group *tg);
76 int scx_tg_online(struct task_group *tg);
77 void scx_tg_offline(struct task_group *tg);
81 void scx_group_set_weight(struct task_group *tg, unsigned long cgrp_weight);
82 void scx_group_set_idle(struct task_group *tg, bool idle);
83 void scx_group_set_bandwidth(struct task_group *tg, u64 period_us, u64 quota_us, u64 burst_us);
85 static inline void scx_tg_init(struct task_group *tg) {} in scx_tg_init() argument
86 static inline int scx_tg_online(struct task_group *tg) { return 0; } in scx_tg_online() argument
87 static inline void scx_tg_offline(struct task_group *tg) {} in scx_tg_offline() argument
91 static inline void scx_group_set_weight(struct task_group *tg, unsigned long cgrp_weight) {} in scx_group_set_weight() argument
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H A Drt.c93 rt_rq->tg = &root_task_group; in init_rt_rq()
181 WARN_ON(!rt_group_sched_enabled() && rt_rq->tg != &root_task_group); in rq_of_rt_rq()
187 WARN_ON(!rt_group_sched_enabled() && rt_se->rt_rq->tg != &root_task_group); in rt_rq_of_se()
195 WARN_ON(!rt_group_sched_enabled() && rt_rq->tg != &root_task_group); in rq_of_rt_se()
199 void unregister_rt_sched_group(struct task_group *tg) in unregister_rt_sched_group() argument
204 if (tg->rt_se) in unregister_rt_sched_group()
205 destroy_rt_bandwidth(&tg->rt_bandwidth); in unregister_rt_sched_group()
208 void free_rt_sched_group(struct task_group *tg) in free_rt_sched_group() argument
216 if (tg->rt_rq) in free_rt_sched_group()
217 kfree(tg->rt_rq[i]); in free_rt_sched_group()
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H A Dcore.c1427 int tg_nop(struct task_group *tg, void *data) in tg_nop() argument
1882 struct task_group *tg = &root_task_group; in uclamp_update_root_tg() local
1884 uclamp_se_set(&tg->uclamp_req[UCLAMP_MIN], in uclamp_update_root_tg()
1886 uclamp_se_set(&tg->uclamp_req[UCLAMP_MAX], in uclamp_update_root_tg()
4683 struct task_group *tg; in sched_cgroup_fork() local
4684 tg = container_of(kargs->cset->subsys[cpu_cgrp_id], in sched_cgroup_fork()
4686 tg = autogroup_task_group(p, tg); in sched_cgroup_fork()
4687 p->sched_task_group = tg; in sched_cgroup_fork()
8962 static inline void alloc_uclamp_sched_group(struct task_group *tg, in alloc_uclamp_sched_group() argument
8969 uclamp_se_set(&tg->uclamp_req[clamp_id], in alloc_uclamp_sched_group()
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H A Dsched.h561 extern int tg_nop(struct task_group *tg, void *data);
564 extern void free_fair_sched_group(struct task_group *tg);
565 extern int alloc_fair_sched_group(struct task_group *tg, struct task_group *parent);
566 extern void online_fair_sched_group(struct task_group *tg);
567 extern void unregister_fair_sched_group(struct task_group *tg);
569 static inline void free_fair_sched_group(struct task_group *tg) { } in free_fair_sched_group() argument
570 static inline int alloc_fair_sched_group(struct task_group *tg, struct task_group *parent) in alloc_fair_sched_group() argument
574 static inline void online_fair_sched_group(struct task_group *tg) { } in online_fair_sched_group() argument
575 static inline void unregister_fair_sched_group(struct task_group *tg) { } in unregister_fair_sched_group() argument
578 extern void init_tg_cfs_entry(struct task_group *tg, struct cfs_rq *cfs_rq,
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/linux/drivers/gpu/drm/amd/display/dc/dce60/
H A Ddce60_timing_generator.c87 static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_100hz) in program_pix_dur() argument
91 + DCE110TG_FROM_TG(tg)->offsets.dmif; in program_pix_dur()
92 uint32_t value = dm_read_reg(tg->ctx, addr); in program_pix_dur()
105 dm_write_reg(tg->ctx, addr, value); in program_pix_dur()
108 static void program_timing(struct timing_generator *tg, in program_timing() argument
119 program_pix_dur(tg, timing->pix_clk_100hz); in program_timing()
121 dce110_tg_program_timing(tg, timing, 0, 0, 0, 0, 0, 0, use_vbios); in program_timing()
125 struct timing_generator *tg, in dce60_timing_generator_enable_advanced_request() argument
129 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); in dce60_timing_generator_enable_advanced_request()
131 uint32_t value = dm_read_reg(tg->ctx, addr); in dce60_timing_generator_enable_advanced_request()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c166 struct timing_generator *tg) in dcn201_init_blank() argument
180 tg->funcs->get_otg_active_size(tg, in dcn201_init_blank()
185 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); in dcn201_init_blank()
273 struct timing_generator *tg = res_pool->timing_generators[i]; in dcn201_init_hw() local
275 if (tg->funcs->is_tg_enabled(tg)) { in dcn201_init_hw()
276 dcn201_init_blank(dc, tg); in dcn201_init_hw()
281 struct timing_generator *tg = res_pool->timing_generators[i]; in dcn201_init_hw() local
283 if (tg->funcs->is_tg_enabled(tg)) in dcn201_init_hw()
284 tg->funcs->lock(tg); in dcn201_init_hw()
305 struct timing_generator *tg = res_pool->timing_generators[i]; in dcn201_init_hw() local
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.c286 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL) { in dcn20_setup_gsl_group_as_lock()
287 pipe_ctx->stream_res.tg->funcs->set_gsl( in dcn20_setup_gsl_group_as_lock()
288 pipe_ctx->stream_res.tg, in dcn20_setup_gsl_group_as_lock()
290 if (pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) in dcn20_setup_gsl_group_as_lock()
291 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( in dcn20_setup_gsl_group_as_lock()
292 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); in dcn20_setup_gsl_group_as_lock()
407 struct timing_generator *tg) in dcn20_init_blank() argument
422 tg->funcs->get_otg_active_size(tg, in dcn20_init_blank()
427 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); in dcn20_init_blank()
753 struct timing_generator *tg = is_phantom ? pipe_ctx->stream_res.tg : NULL; in dcn20_disable_plane() local
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/linux/drivers/gpu/drm/amd/display/dc/link/accessories/
H A Dlink_dp_cts.c99 pipes[i]->stream_res.tg->funcs->disable_crtc(pipes[i]->stream_res.tg); in dp_retrain_link_dp_test()
141 pipes[i]->stream_res.tg->funcs->enable_crtc(pipes[i]->stream_res.tg); in dp_retrain_link_dp_test()
508 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) { in set_crtc_test_pattern()
510 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, in set_crtc_test_pattern()
547 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) { in set_crtc_test_pattern()
549 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, in set_crtc_test_pattern()
879 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) { in dp_set_test_pattern()
885 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst; in dp_set_test_pattern()
892 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable( in dp_set_test_pattern()
893 pipe_ctx->stream_res.tg); in dp_set_test_pattern()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dce/
H A Ddce_hwseq.c56 if (lock && pipe->stream_res.tg->funcs->is_blanked && in dce_pipe_control_lock()
57 pipe->stream_res.tg->funcs->is_blanked(pipe->stream_res.tg)) in dce_pipe_control_lock()
60 val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], in dce_pipe_control_lock()
71 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
76 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
82 uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst]); in dce_pipe_control_lock()
83 REG_WRITE(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst], value); in dce_pipe_control_lock()
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_hw_sequencer.c296 struct timing_generator *tg) in hwss_wait_for_blank_complete() argument
301 if (!tg->funcs->is_blanked) in hwss_wait_for_blank_complete()
304 if (tg->funcs->is_blanked(tg)) in hwss_wait_for_blank_complete()
701 if (pipe_ctx && pipe_ctx->stream_res.tg && in set_drr_and_clear_adjust_pending()
702 pipe_ctx->stream_res.tg->funcs->set_drr) in set_drr_and_clear_adjust_pending()
703 pipe_ctx->stream_res.tg->funcs->set_drr( in set_drr_and_clear_adjust_pending()
704 pipe_ctx->stream_res.tg, params); in set_drr_and_clear_adjust_pending()
1628 struct timing_generator *tg, int opp_inst[MAX_PIPES], int opp_head_count, in hwss_add_optc_set_odm_combine() argument
1632 seq_state->steps[*seq_state->num_steps].params.set_odm_combine_params.tg = tg; in hwss_add_optc_set_odm_combine()
1646 struct timing_generator *tg, struct dc_crtc_timing *timing) in hwss_add_optc_set_odm_bypass() argument
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/linux/drivers/iio/chemical/
H A Dsgp40.c172 struct sgp40_tg_measure tg = {.command = {0x26, 0x0F}}; in sgp40_measure_resistance_raw() local
179 tg.rht_ticks = cpu_to_be16(ticks16); in sgp40_measure_resistance_raw()
180 tg.rht_crc = crc8(sgp40_crc8_table, (u8 *)&tg.rht_ticks, 2, SGP40_CRC8_INIT); in sgp40_measure_resistance_raw()
184 tg.temp_ticks = cpu_to_be16(ticks16); in sgp40_measure_resistance_raw()
185 tg.temp_crc = crc8(sgp40_crc8_table, (u8 *)&tg.temp_ticks, 2, SGP40_CRC8_INIT); in sgp40_measure_resistance_raw()
189 ret = i2c_master_send(client, (const char *)&tg, sizeof(tg)); in sgp40_measure_resistance_raw()
190 if (ret != sizeof(tg)) { in sgp40_measure_resistance_raw()
191 dev_warn(data->dev, "i2c_master_send ret: %d sizeof: %zu\n", ret, sizeof(tg)); in sgp40_measure_resistance_raw()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c780 dc->res_pool->dccg, pipe_ctx->stream_res.tg->inst, in dcn401_enable_stream_timing()
789 pipe_ctx->stream_res.tg->funcs->set_odm_combine( in dcn401_enable_stream_timing()
790 pipe_ctx->stream_res.tg, in dcn401_enable_stream_timing()
798 …s_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, DPREFCLK, pipe_ctx->stream_res.tg->inst); in dcn401_enable_stream_timing()
805 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true); in dcn401_enable_stream_timing()
826 pipe_ctx->stream_res.tg->funcs->program_timing( in dcn401_enable_stream_timing()
827 pipe_ctx->stream_res.tg, in dcn401_enable_stream_timing()
854 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) { in dcn401_enable_stream_timing()
866 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) in dcn401_enable_stream_timing()
867 pipe_ctx->stream_res.tg->funcs->set_static_screen_control( in dcn401_enable_stream_timing()
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/linux/arch/powerpc/kernel/
H A Dsmp.c832 struct thread_groups *tg = &tglp->property_tgs[property_idx++]; in parse_thread_groups() local
834 tg->property = thread_group_array[i]; in parse_thread_groups()
835 tg->nr_groups = thread_group_array[i + 1]; in parse_thread_groups()
836 tg->threads_per_group = thread_group_array[i + 2]; in parse_thread_groups()
837 total_threads = tg->nr_groups * tg->threads_per_group; in parse_thread_groups()
842 tg->thread_list[j] = thread_list[j]; in parse_thread_groups()
867 static int get_cpu_thread_group_start(int cpu, struct thread_groups *tg) in get_cpu_thread_group_start() argument
872 for (i = 0; i < tg->nr_groups; i++) { in get_cpu_thread_group_start()
873 int group_start = i * tg->threads_per_group; in get_cpu_thread_group_start()
875 for (j = 0; j < tg->threads_per_group; j++) { in get_cpu_thread_group_start()
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/linux/drivers/firmware/efi/libstub/
H A Darm64.c60 u64 tg; in check_platform_features() local
74 tg = (read_cpuid(ID_AA64MMFR0_EL1) >> ID_AA64MMFR0_EL1_TGRAN_SHIFT) & 0xf; in check_platform_features()
75 if (tg < ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN || tg > ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX) { in check_platform_features()
/linux/drivers/gpu/drm/amd/display/dc/hwss/
H A Dhw_sequencer.h197 struct timing_generator *tg; member
205 struct timing_generator *tg; member
238 struct timing_generator *tg; member
270 struct timing_generator *tg; member
279 struct timing_generator *tg; member
284 struct timing_generator *tg; member
290 struct timing_generator *tg; member
295 struct timing_generator *tg; member
306 struct timing_generator *tg; member
440 struct timing_generator *tg; member
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/linux/drivers/hwtracing/coresight/
H A Dcoresight-cti-platform.c317 struct cti_trig_grp *tg = NULL; in cti_plat_process_filter_sigs() local
328 tg = kzalloc(sizeof(*tg), GFP_KERNEL); in cti_plat_process_filter_sigs()
329 if (!tg) in cti_plat_process_filter_sigs()
332 err = cti_plat_read_trig_group(tg, fwnode, CTI_DT_FILTER_OUT_SIGS); in cti_plat_process_filter_sigs()
334 drvdata->config.trig_out_filter |= tg->used_mask; in cti_plat_process_filter_sigs()
336 kfree(tg); in cti_plat_process_filter_sigs()
/linux/drivers/gpu/drm/amd/display/dc/irq/dce110/
H A Dirq_service_dce110.c214 struct timing_generator *tg; in dce110_vblank_set() local
219 tg = dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg; in dce110_vblank_set()
222 if (!tg || !tg->funcs->arm_vert_intr(tg, 2)) { in dce110_vblank_set()
/linux/drivers/net/ethernet/microchip/vcap/
H A Dvcap_api_kunit.c335 .tg = NULL, in vcap_api_set_bit_1_test()
352 .tg = NULL, in vcap_api_set_bit_0_test()
755 const struct vcap_typegroup *tg; in vcap_api_keyfield_typegroup_test() local
757 tg = vcap_keyfield_typegroup(&test_vctrl, VCAP_TYPE_IS2, VCAP_KFS_MAC_ETYPE); in vcap_api_keyfield_typegroup_test()
758 KUNIT_EXPECT_PTR_NE(test, NULL, tg); in vcap_api_keyfield_typegroup_test()
759 KUNIT_EXPECT_EQ(test, 0, tg[0].offset); in vcap_api_keyfield_typegroup_test()
760 KUNIT_EXPECT_EQ(test, 2, tg[0].width); in vcap_api_keyfield_typegroup_test()
761 KUNIT_EXPECT_EQ(test, 2, tg[0].value); in vcap_api_keyfield_typegroup_test()
762 KUNIT_EXPECT_EQ(test, 156, tg[1].offset); in vcap_api_keyfield_typegroup_test()
763 KUNIT_EXPECT_EQ(test, 1, tg[1].width); in vcap_api_keyfield_typegroup_test()
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/linux/drivers/gpu/drm/
H A Ddrm_connector.c3532 struct drm_tile_group *tg = container_of(kref, struct drm_tile_group, refcount); in drm_tile_group_free() local
3533 struct drm_device *dev = tg->dev; in drm_tile_group_free()
3536 idr_remove(&dev->mode_config.tile_idr, tg->id); in drm_tile_group_free()
3538 kfree(tg); in drm_tile_group_free()
3549 struct drm_tile_group *tg) in drm_mode_put_tile_group() argument
3551 kref_put(&tg->refcount, drm_tile_group_free); in drm_mode_put_tile_group()
3568 struct drm_tile_group *tg; in drm_mode_get_tile_group() local
3572 idr_for_each_entry(&dev->mode_config.tile_idr, tg, id) { in drm_mode_get_tile_group()
3573 if (!memcmp(tg->group_data, topology, 8)) { in drm_mode_get_tile_group()
3574 if (!kref_get_unless_zero(&tg->refcount)) in drm_mode_get_tile_group()
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