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Searched refs:supported_reset (Results 1 – 25 of 28) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
H A Djpeg_v3_0.c135 adev->jpeg.supported_reset = in jpeg_v3_0_sw_init()
138 adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in jpeg_v3_0_sw_init()
H A Djpeg_v5_3_0.c105 adev->jpeg.supported_reset = in jpeg_v5_3_0_sw_init()
108 adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in jpeg_v5_3_0_sw_init()
H A Djpeg_v5_0_0.c123 adev->jpeg.supported_reset = in jpeg_v5_0_0_sw_init()
126 adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in jpeg_v5_0_0_sw_init()
H A Djpeg_v2_5.c170 adev->jpeg.supported_reset = in jpeg_v2_5_sw_init()
173 adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in jpeg_v2_5_sw_init()
H A Djpeg_v4_0.c146 adev->jpeg.supported_reset = in jpeg_v4_0_sw_init()
149 adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in jpeg_v4_0_sw_init()
H A Djpeg_v2_0.c120 adev->jpeg.supported_reset = in jpeg_v2_0_sw_init()
123 adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in jpeg_v2_0_sw_init()
H A Djpeg_v4_0_5.c177 adev->jpeg.supported_reset = in jpeg_v4_0_5_sw_init()
180 adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in jpeg_v4_0_5_sw_init()
H A Djpeg_v5_0_2.c183 adev->jpeg.supported_reset = in jpeg_v5_0_2_sw_init()
185 adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in jpeg_v5_0_2_sw_init()
H A Damdgpu_userq.c67 if (adev->sdma.supported_reset & reset_type) in amdgpu_userq_is_reset_type_supported()
72 if (adev->vcn.supported_reset & reset_type) in amdgpu_userq_is_reset_type_supported()
76 if (adev->jpeg.supported_reset & reset_type) in amdgpu_userq_is_reset_type_supported()
H A Djpeg_v5_0_1.c211 adev->jpeg.supported_reset = in jpeg_v5_0_1_sw_init()
214 adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in jpeg_v5_0_1_sw_init()
H A Damdgpu_sdma.c468 return amdgpu_show_reset_mask(buf, adev->sdma.supported_reset); in amdgpu_get_sdma_reset_mask()
H A Djpeg_v4_0_3.c219 adev->jpeg.supported_reset = in jpeg_v4_0_3_sw_init()
222 adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in jpeg_v4_0_3_sw_init()
H A Dvcn_v5_0_0.c188 adev->vcn.supported_reset = in vcn_v5_0_0_sw_init()
191 adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in vcn_v5_0_0_sw_init()
H A Damdgpu_jpeg.c436 return amdgpu_show_reset_mask(buf, adev->jpeg.supported_reset); in amdgpu_get_jpeg_reset_mask()
H A Damdgpu_device.c6879 ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset) in amdgpu_show_reset_mask() argument
6883 if (supported_reset == 0) { in amdgpu_show_reset_mask()
6890 if (supported_reset & AMDGPU_RESET_TYPE_SOFT_RESET) in amdgpu_show_reset_mask()
6893 if (supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE) in amdgpu_show_reset_mask()
6896 if (supported_reset & AMDGPU_RESET_TYPE_PER_PIPE) in amdgpu_show_reset_mask()
6899 if (supported_reset & AMDGPU_RESET_TYPE_FULL) in amdgpu_show_reset_mask()
H A Dvcn_v4_0_5.c219 adev->vcn.supported_reset = amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); in vcn_v4_0_5_sw_init()
221 adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in vcn_v4_0_5_sw_init()
H A Dsdma_v7_1.c1343 adev->sdma.supported_reset = in sdma_v7_1_sw_init()
1347 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in sdma_v7_1_sw_init()
H A Dvcn_v5_0_1.c120 adev->vcn.supported_reset = in vcn_v5_0_1_late_init()
128 adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in vcn_v5_0_1_late_init()
H A Dsdma_v7_0.c1356 adev->sdma.supported_reset = in sdma_v7_0_sw_init()
1360 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in sdma_v7_0_sw_init()
H A Dsdma_v6_0.c1371 adev->sdma.supported_reset = in sdma_v6_0_sw_init()
1375 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in sdma_v6_0_sw_init()
H A Dvcn_v2_0.c218 adev->vcn.supported_reset = in vcn_v2_0_sw_init()
221 adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in vcn_v2_0_sw_init()
H A Dvcn_v4_0_3.c156 adev->vcn.supported_reset = in vcn_v4_0_3_late_init()
162 adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in vcn_v4_0_3_late_init()
H A Dvcn_v4_0.c240 adev->vcn.supported_reset = in vcn_v4_0_sw_init()
243 adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in vcn_v4_0_sw_init()
H A Dvcn_v2_5.c386 adev->vcn.supported_reset = in vcn_v2_5_sw_init()
389 adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in vcn_v2_5_sw_init()
H A Dvcn_v3_0.c294 adev->vcn.supported_reset = in vcn_v3_0_sw_init()
297 adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in vcn_v3_0_sw_init()

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