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Searched refs:sseu (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/i915/gt/
H A Dintel_sseu.h109 intel_sseu_from_device_info(const struct sseu_dev_info *sseu) in intel_sseu_from_device_info() argument
112 .slice_mask = sseu->slice_mask, in intel_sseu_from_device_info()
113 .subslice_mask = sseu->subslice_mask.hsw[0], in intel_sseu_from_device_info()
114 .min_eus_per_subslice = sseu->max_eus_per_subslice, in intel_sseu_from_device_info()
115 .max_eus_per_subslice = sseu->max_eus_per_subslice, in intel_sseu_from_device_info()
122 intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice, in intel_sseu_has_subslice() argument
125 if (slice >= sseu->max_slices || in intel_sseu_has_subslice()
126 subslice >= sseu->max_subslices) in intel_sseu_has_subslice()
129 if (sseu->has_xehp_dss) in intel_sseu_has_subslice()
130 return test_bit(subslice, sseu->subslice_mask.xehp); in intel_sseu_has_subslice()
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H A Dintel_context_sseu.c18 const struct intel_sseu sseu) in gen8_emit_rpcs_config() argument
33 *cs++ = intel_sseu_make_rpcs(rq->engine->gt, &sseu); in gen8_emit_rpcs_config()
41 gen8_modify_rpcs(struct intel_context *ce, const struct intel_sseu sseu) in gen8_modify_rpcs() argument
66 ret = gen8_emit_rpcs_config(rq, ce, sseu); in gen8_modify_rpcs()
76 const struct intel_sseu sseu) in intel_context_reconfigure_sseu() argument
87 if (!memcmp(&ce->sseu, &sseu, sizeof(sseu))) in intel_context_reconfigure_sseu()
90 ret = gen8_modify_rpcs(ce, sseu); in intel_context_reconfigure_sseu()
92 ce->sseu = sseu; in intel_context_reconfigure_sseu()
H A Dintel_gt_mcr.h58 intel_sseu_has_subslice(&(gt_)->info.sseu, 0, ss_) : \
59 intel_sseu_has_subslice(&(gt_)->info.sseu, group_, instance_))
H A Dintel_gt_types.h275 struct sseu_dev_info sseu; member
H A Dintel_context.c401 ce->sseu = engine->sseu; in intel_context_init()
H A Dintel_context.h48 const struct intel_sseu sseu);
H A Dintel_engine_cs.c820 int ss_per_ccs = info->sseu.max_subslices / I915_MAX_CCS; in engine_mask_apply_compute_fuses()
830 ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask, in engine_mask_apply_compute_fuses()
1279 engine->sseu = in engine_setup_common()
1280 intel_sseu_from_device_info(&engine->gt->info.sseu); in engine_setup_common()
/linux/drivers/gpu/drm/i915/gem/
H A Di915_gem_context.c819 struct intel_sseu *sseu; in set_proto_ctx_sseu() local
855 sseu = &pe->sseu; in set_proto_ctx_sseu()
865 sseu = &pc->legacy_rcs_sseu; in set_proto_ctx_sseu()
868 ret = i915_gem_user_to_context_sseu(to_gt(i915), &user_sseu, sseu); in set_proto_ctx_sseu()
970 struct intel_sseu sseu) in intel_context_set_gem() argument
1000 if (sseu.slice_mask && !WARN_ON(ce->engine->class != RENDER_CLASS)) in intel_context_set_gem()
1001 ret = intel_context_reconfigure_sseu(ce, sseu); in intel_context_set_gem()
1127 struct intel_sseu sseu = {}; in default_engines() local
1146 sseu = rcs_sseu; in default_engines()
1148 ret = intel_context_set_gem(ce, ctx, sseu); in default_engines()
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/linux/drivers/gpu/drm/i915/gem/selftests/
H A Di915_gem_context.c1170 unsigned int slices = hweight32(ce->engine->sseu.slice_mask); in __sseu_finish()
1211 struct intel_sseu sseu) in __sseu_test() argument
1222 ret = intel_context_reconfigure_sseu(ce, sseu); in __sseu_test()
1227 hweight32(sseu.slice_mask), spin); in __sseu_test()
1272 if (hweight32(engine->sseu.slice_mask) < 2) in __igt_ctx_sseu()
1275 if (!engine->gt->info.sseu.has_slice_pg) in __igt_ctx_sseu()
1282 pg_sseu = engine->sseu; in __igt_ctx_sseu()
1285 ~(~0 << (hweight32(engine->sseu.subslice_mask) / 2)); in __igt_ctx_sseu()
1289 hweight32(engine->sseu.slice_mask), in __igt_ctx_sseu()
1303 ret = __sseu_test(name, flags, ce, obj, engine->sseu); in __igt_ctx_sseu()
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/linux/drivers/gpu/drm/i915/
H A Di915_perf_types.h445 struct intel_sseu sseu; member
/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_ads.c900 hweight8(gt->info.sseu.slice_mask)); in __guc_ads_init()