| /linux/arch/x86/kvm/mmu/ |
| H A D | spte.c | 95 u64 spte = generation_mmio_spte_mask(gen); in make_mmio_spte() local
99 spte |= vcpu->kvm->arch.shadow_mmio_value | access; in make_mmio_spte()
100 spte |= gpa | shadow_nonpresent_or_rsvd_mask; in make_mmio_spte()
101 spte |= (gpa & shadow_nonpresent_or_rsvd_mask) in make_mmio_spte()
104 return spte; in make_mmio_spte()
164 bool spte_needs_atomic_update(u64 spte) in spte_needs_atomic_update() argument
167 if (!is_writable_pte(spte) && is_mmu_writable_spte(spte)) in spte_needs_atomic_update()
174 if (!spte_ad_enabled(spte)) in spte_needs_atomic_update()
183 return is_writable_pte(spte) && !(spte & shadow_dirty_mask); in spte_needs_atomic_update()
193 u64 spte = SPTE_MMU_PRESENT_MASK; in make_spte() local
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| H A D | spte.h | 228 static inline bool is_frozen_spte(u64 spte) in is_frozen_spte() argument
230 return spte == FROZEN_SPTE; in is_frozen_spte()
266 static inline struct kvm_mmu_page *spte_to_child_sp(u64 spte) in spte_to_child_sp() argument
268 return to_shadow_page(spte & SPTE_BASE_ADDR_MASK); in spte_to_child_sp()
303 static inline bool is_mmio_spte(struct kvm *kvm, u64 spte) in is_mmio_spte() argument
305 return (spte & shadow_mmio_mask) == kvm->arch.shadow_mmio_value && in is_mmio_spte()
314 static inline bool is_ept_ve_possible(u64 spte) in is_ept_ve_possible() argument
317 !(spte & VMX_EPT_SUPPRESS_VE_BIT) && in is_ept_ve_possible()
318 (spte & VMX_EPT_RWX_MASK) != VMX_EPT_MISCONFIG_WX_VALUE; in is_ept_ve_possible()
326 static inline bool spte_ad_enabled(u64 spte) in spte_ad_enabled() argument
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| H A D | mmutrace.h | 216 TP_PROTO(u64 *sptep, gfn_t gfn, u64 spte),
217 TP_ARGS(sptep, gfn, spte),
229 __entry->access = spte & ACC_ALL;
230 __entry->gen = get_mmio_spte_generation(spte);
316 TP_PROTO(u64 spte, unsigned int kvm_gen, unsigned int spte_gen),
317 TP_ARGS(spte, kvm_gen, spte_gen),
322 __field(u64, spte)
328 __entry->spte = spte;
331 TP_printk("spte %llx kvm_gen %x spte-gen %x valid %d", __entry->spte,
344 __field(u64, spte)
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| H A D | mmu.c | 175 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \ argument
178 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
179 __shadow_walk_next(&(_walker), spte))
184 static void mmu_spte_set(u64 *sptep, u64 spte);
295 u64 spte = make_mmio_spte(vcpu, gfn, access); in mark_mmio_spte() local
297 trace_mark_mmio_spte(sptep, gfn, spte); in mark_mmio_spte()
298 mmu_spte_set(sptep, spte); in mark_mmio_spte()
301 static gfn_t get_mmio_spte_gfn(u64 spte) in get_mmio_spte_gfn() argument
303 u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask; in get_mmio_spte_gfn()
305 gpa |= (spte >> SHADOW_NONPRESENT_OR_RSVD_MASK_LEN) in get_mmio_spte_gfn()
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| H A D | paging_tmpl.h | 152 struct kvm_mmu_page *sp, u64 *spte, in FNAME()
169 drop_spte(vcpu->kvm, spte); in FNAME()
533 u64 *spte, pt_element_t gpte) in FNAME()
538 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte)) in FNAME()
545 return kvm_mmu_prefetch_sptes(vcpu, gfn, spte, 1, pte_access); in FNAME()
576 u64 *spte; in FNAME() local
595 spte = sp->spt + i; in FNAME()
597 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { in FNAME()
598 if (spte == sptep) in FNAME()
601 if (is_shadow_present_pte(*spte)) in FNAME()
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| H A D | tdp_mmu.h | 114 u64 *spte);
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| H A D | tdp_mmu.c | 1240 u64 spte = make_nonleaf_spte(sp->spt, !kvm_ad_enabled); in tdp_mmu_link_sp() local
1244 ret = tdp_mmu_set_spte_atomic(kvm, iter, spte); in tdp_mmu_link_sp()
1248 tdp_mmu_iter_set_spte(kvm, iter, spte); in tdp_mmu_link_sp()
1969 u64 *spte) in kvm_tdp_mmu_fast_pf_get_last_sptep() argument
1977 *spte = iter.old_spte; in kvm_tdp_mmu_fast_pf_get_last_sptep()
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| H A D | mmu_internal.h | 407 void disallowed_hugepage_adjust(struct kvm_page_fault *fault, u64 spte, int cur_level);
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| /linux/Documentation/virt/kvm/ |
| H A D | locking.rst | 78 write-protect. That means we just need to change the W bit of the spte.
81 on the spte:
88 On fast page fault path, we will use cmpxchg to atomically set the spte W
89 bit if spte.HOST_WRITEABLE = 1 and spte.WRITE_PROTECT = 1, to restore the saved
90 R/X bits if for an access-traced spte, or both. This is safe because whenever
106 | spte is the shadow page table entry corresponding with gpte and |
107 | spte = pfn1 |
115 | old_spte = *spte; | |
119 | | spte = 0; |
126 | | spte = pfn1; |
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| /linux/Documentation/virt/kvm/x86/ |
| H A D | mmu.rst | 55 spte shadow pte (referring to pfns)
125 A nonleaf spte allows the hardware mmu to reach the leaf pages and
128 A leaf spte corresponds to either one or two translations encoded into
251 parent_ptes bit 0 is zero, only one spte points at this page and
252 parent_ptes points at this single spte, otherwise, there exists multiple
272 Only present on 32-bit hosts, where a 64-bit spte cannot be written
341 - check for valid generation number in the spte (see "Fast invalidation of
360 - walk the shadow page table to find the spte for the translation,
363 - If this is an mmio request, cache the mmio info to the spte and set some
364 reserved bit on the spte (see callers of kvm_mmu_set_mmio_spte_mask)
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| /linux/mm/ |
| H A D | hugetlb.c | 6886 pte_t *spte = NULL; in huge_pmd_share() local
6896 spte = hugetlb_walk(svma, saddr, in huge_pmd_share()
6898 if (spte) { in huge_pmd_share()
6899 ptdesc_pmd_pts_inc(virt_to_ptdesc(spte)); in huge_pmd_share()
6905 if (!spte) in huge_pmd_share()
6911 (pmd_t *)((unsigned long)spte & PAGE_MASK)); in huge_pmd_share()
6914 ptdesc_pmd_pts_dec(virt_to_ptdesc(spte)); in huge_pmd_share()
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ |
| H A D | vmm.c | 472 bool spte = !!pgt->pte[ptei].s.sptes; in nvkm_vmm_ref_hwpt() local
475 if (spte != next) in nvkm_vmm_ref_hwpt()
479 if (!spte) { in nvkm_vmm_ref_hwpt()
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