xref: /linux/drivers/gpu/drm/nouveau/include/nvrm/535.113.01/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h (revision 0ea5c948cb64bab5bc7a5516774eb8536f05aa0d)
1 #ifndef __src_common_sdk_nvidia_inc_ctrl_ctrl0073_ctrl0073dfp_h__
2 #define __src_common_sdk_nvidia_inc_ctrl_ctrl0073_ctrl0073dfp_h__
3 
4 /* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
5 
6 /*
7  * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
8  * SPDX-License-Identifier: MIT
9  *
10  * Permission is hereby granted, free of charge, to any person obtaining a
11  * copy of this software and associated documentation files (the "Software"),
12  * to deal in the Software without restriction, including without limitation
13  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
14  * and/or sell copies of the Software, and to permit persons to whom the
15  * Software is furnished to do so, subject to the following conditions:
16  *
17  * The above copyright notice and this permission notice shall be included in
18  * all copies or substantial portions of the Software.
19  *
20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
25  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26  * DEALINGS IN THE SOFTWARE.
27  */
28 
29 #define NV0073_CTRL_CMD_DFP_GET_INFO (0x731140U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_INFO_PARAMS_MESSAGE_ID" */
30 
31 typedef struct NV0073_CTRL_DFP_GET_INFO_PARAMS {
32     NvU32 subDeviceInstance;
33     NvU32 displayId;
34     NvU32 flags;
35     NvU32 flags2;
36 } NV0073_CTRL_DFP_GET_INFO_PARAMS;
37 
38 #define NV0073_CTRL_DFP_FLAGS_SIGNAL                                       2:0
39 #define NV0073_CTRL_DFP_FLAGS_SIGNAL_TMDS                       (0x00000000U)
40 #define NV0073_CTRL_DFP_FLAGS_SIGNAL_LVDS                       (0x00000001U)
41 #define NV0073_CTRL_DFP_FLAGS_SIGNAL_SDI                        (0x00000002U)
42 #define NV0073_CTRL_DFP_FLAGS_SIGNAL_DISPLAYPORT                (0x00000003U)
43 #define NV0073_CTRL_DFP_FLAGS_SIGNAL_DSI                        (0x00000004U)
44 #define NV0073_CTRL_DFP_FLAGS_SIGNAL_WRBK                       (0x00000005U)
45 #define NV0073_CTRL_DFP_FLAGS_LANE                                         5:3
46 #define NV0073_CTRL_DFP_FLAGS_LANE_NONE                         (0x00000000U)
47 #define NV0073_CTRL_DFP_FLAGS_LANE_SINGLE                       (0x00000001U)
48 #define NV0073_CTRL_DFP_FLAGS_LANE_DUAL                         (0x00000002U)
49 #define NV0073_CTRL_DFP_FLAGS_LANE_QUAD                         (0x00000003U)
50 #define NV0073_CTRL_DFP_FLAGS_LANE_OCT                          (0x00000004U)
51 #define NV0073_CTRL_DFP_FLAGS_LIMIT                                        6:6
52 #define NV0073_CTRL_DFP_FLAGS_LIMIT_DISABLE                     (0x00000000U)
53 #define NV0073_CTRL_DFP_FLAGS_LIMIT_60HZ_RR                     (0x00000001U)
54 #define NV0073_CTRL_DFP_FLAGS_SLI_SCALER                                   7:7
55 #define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_NORMAL                 (0x00000000U)
56 #define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_DISABLE                (0x00000001U)
57 #define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE                                 8:8
58 #define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_FALSE                (0x00000000U)
59 #define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_TRUE                 (0x00000001U)
60 #define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE                        9:9
61 #define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_FALSE       (0x00000000U)
62 #define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_TRUE        (0x00000001U)
63 #define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE                         10:10
64 #define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_FALSE          (0x00000000U)
65 #define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_TRUE           (0x00000001U)
66 #define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE                    11:11
67 #define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_FALSE     (0x00000000U)
68 #define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_TRUE      (0x00000001U)
69 #define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE                    12:12
70 #define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_FALSE     (0x00000000U)
71 #define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_TRUE      (0x00000001U)
72 #define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED                               14:14
73 #define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_FALSE                (0x00000000U)
74 #define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_TRUE                 (0x00000001U)
75 #define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT                       15:15
76 #define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_FALSE        (0x00000000U)
77 #define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_TRUE         (0x00000001U)
78 #define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT                         16:16
79 #define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_NONE           (0x00000000U)
80 #define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_PREFER_RBR     (0x00000001U)
81 #define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW                                 19:17
82 #define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_1_62GBPS               (0x00000001U)
83 #define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_2_70GBPS               (0x00000002U)
84 #define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_5_40GBPS               (0x00000003U)
85 #define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_8_10GBPS               (0x00000004U)
86 #define NV0073_CTRL_DFP_FLAGS_LINK                                       21:20
87 #define NV0073_CTRL_DFP_FLAGS_LINK_NONE                         (0x00000000U)
88 #define NV0073_CTRL_DFP_FLAGS_LINK_SINGLE                       (0x00000001U)
89 #define NV0073_CTRL_DFP_FLAGS_LINK_DUAL                         (0x00000002U)
90 #define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID                           22:22
91 #define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_FALSE            (0x00000000U)
92 #define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_TRUE             (0x00000001U)
93 #define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID                              24:23
94 #define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_NONE            (0x00000000U)
95 #define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_A               (0x00000001U)
96 #define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_B               (0x00000002U)
97 #define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_GANGED          (0x00000003U)
98 #define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED                   25:25
99 #define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_FALSE    (0x00000000U)
100 #define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_TRUE     (0x00000001U)
101 #define NV0073_CTRL_DFP_FLAGS_DP_PHY_REPEATER_COUNT                      29:26
102 #define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE                        30:30
103 #define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_FALSE         (0x00000000U)
104 #define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_TRUE          (0x00000001U)
105 
106 #define NV0073_CTRL_CMD_DFP_SET_ELD_AUDIO_CAPS                         (0x731144U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS_MESSAGE_ID" */
107 
108 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_ELD_BUFFER                      96U
109 
110 typedef struct NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS {
111     NvU32 subDeviceInstance;
112     NvU32 displayId;
113     NvU32 numELDSize;
114     NvU8  bufferELD[NV0073_CTRL_DFP_ELD_AUDIO_CAPS_ELD_BUFFER];
115     NvU32 maxFreqSupported;
116     NvU32 ctrl;
117     NvU32 deviceEntry;
118 } NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS;
119 
120 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_PD                                     0:0
121 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_PD_FALSE              (0x00000000U)
122 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_PD_TRUE               (0x00000001U)
123 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_ELDV                                   1:1
124 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_ELDV_FALSE            (0x00000000U)
125 #define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_ELDV_TRUE             (0x00000001U)
126 
127 #define NV0073_CTRL_CMD_DFP_SET_AUDIO_ENABLE                (0x731150U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS_MESSAGE_ID" */
128 
129 typedef struct NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS {
130     NvU32  subDeviceInstance;
131     NvU32  displayId;
132     NvBool enable;
133 } NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS;
134 
135 typedef NvU32 NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG;
136 
137 typedef struct NV0073_CTRL_DFP_ASSIGN_SOR_INFO {
138     NvU32 displayMask;
139     NvU32 sorType;
140 } NV0073_CTRL_DFP_ASSIGN_SOR_INFO;
141 
142 #define NV0073_CTRL_CMD_DFP_ASSIGN_SOR           (0x731152U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS_MESSAGE_ID" */
143 
144 #define NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS  4U
145 
146 typedef struct NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS {
147     NvU32                                 subDeviceInstance;
148     NvU32                                 displayId;
149     NvU8                                  sorExcludeMask;
150     NvU32                                 slaveDisplayId;
151     NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG forceSublinkConfig;
152     NvBool                                bIs2Head1Or;
153     NvU32                                 sorAssignList[NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS];
154     NV0073_CTRL_DFP_ASSIGN_SOR_INFO       sorAssignListWithTag[NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS];
155     NvU8                                  reservedSorMask;
156     NvU32                                 flags;
157 } NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS;
158 
159 #define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_AUDIO                                      0:0
160 #define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_AUDIO_OPTIMAL                    (0x00000001U)
161 #define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_AUDIO_DEFAULT                    (0x00000000U)
162 #define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_ACTIVE_SOR_NOT_AUDIO_CAPABLE               1:1
163 #define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_ACTIVE_SOR_NOT_AUDIO_CAPABLE_NO  (0x00000000U)
164 #define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_ACTIVE_SOR_NOT_AUDIO_CAPABLE_YES (0x00000001U)
165 
166 #endif
167