xref: /linux/drivers/ptp/ptp_ocp.c (revision d8674294aefef02266c4d47ad10131f1bffbe534) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2020 Facebook */
3 
4 #include <linux/bits.h>
5 #include <linux/err.h>
6 #include <linux/kernel.h>
7 #include <linux/module.h>
8 #include <linux/debugfs.h>
9 #include <linux/init.h>
10 #include <linux/pci.h>
11 #include <linux/serial_8250.h>
12 #include <linux/clkdev.h>
13 #include <linux/clk-provider.h>
14 #include <linux/platform_device.h>
15 #include <linux/platform_data/i2c-xiic.h>
16 #include <linux/platform_data/i2c-ocores.h>
17 #include <linux/ptp_clock_kernel.h>
18 #include <linux/spi/spi.h>
19 #include <linux/spi/xilinx_spi.h>
20 #include <linux/spi/altera.h>
21 #include <net/devlink.h>
22 #include <linux/i2c.h>
23 #include <linux/iopoll.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/nvmem-consumer.h>
26 #include <linux/crc16.h>
27 #include <linux/dpll.h>
28 #include <linux/unaligned.h>
29 #include <linux/delay.h>
30 #include <linux/firmware.h>
31 
32 #define PCI_DEVICE_ID_META_TIMECARD		0x0400
33 
34 #define PCI_VENDOR_ID_CELESTICA			0x18d4
35 #define PCI_DEVICE_ID_CELESTICA_TIMECARD	0x1008
36 
37 #define PCI_VENDOR_ID_OROLIA			0x1ad7
38 #define PCI_DEVICE_ID_OROLIA_ARTCARD		0xa000
39 
40 #define PCI_VENDOR_ID_ADVA			0xad5a
41 #define PCI_DEVICE_ID_ADVA_TIMECARD		0x0400
42 #define PCI_DEVICE_ID_ADVA_TIMECARD_X1		0x0410
43 
44 static struct class timecard_class = {
45 	.name		= "timecard",
46 };
47 
48 struct ocp_reg {
49 	u32	ctrl;
50 	u32	status;
51 	u32	select;
52 	u32	version;
53 	u32	time_ns;
54 	u32	time_sec;
55 	u32	__pad0[2];
56 	u32	adjust_ns;
57 	u32	adjust_sec;
58 	u32	__pad1[2];
59 	u32	offset_ns;
60 	u32	offset_window_ns;
61 	u32	__pad2[2];
62 	u32	drift_ns;
63 	u32	drift_window_ns;
64 	u32	__pad3[6];
65 	u32	servo_offset_p;
66 	u32	servo_offset_i;
67 	u32	servo_drift_p;
68 	u32	servo_drift_i;
69 	u32	status_offset;
70 	u32	status_drift;
71 };
72 
73 struct ptp_ocp_servo_conf {
74 	u32	servo_offset_p;
75 	u32	servo_offset_i;
76 	u32	servo_drift_p;
77 	u32	servo_drift_i;
78 };
79 
80 /*
81  * Combined servo + board-variant parameters for ADVA boards.
82  * Embedded in the resource table .extra so a single ptp_ocp_adva_board_init()
83  * can handle both ADVA and ADVA-X1 without per-variant init functions.
84  */
85 struct ptp_ocp_adva_info {
86 	struct ptp_ocp_servo_conf	servo;
87 	u32				flash_start;
88 	const struct ocp_sma_op		*sma_op;
89 	u8				signals_nr;
90 	u8				freq_in_nr;
91 	const struct ocp_attr_group	*attr_groups;
92 	/* x1: TAP CPLD present */
93 	bool				has_cpld;
94 };
95 
96 #define OCP_CTRL_ENABLE		BIT(0)
97 #define OCP_CTRL_ADJUST_TIME	BIT(1)
98 #define OCP_CTRL_ADJUST_OFFSET	BIT(2)
99 #define OCP_CTRL_ADJUST_DRIFT	BIT(3)
100 #define OCP_CTRL_ADJUST_SERVO	BIT(8)
101 #define OCP_CTRL_READ_TIME_REQ	BIT(30)
102 #define OCP_CTRL_READ_TIME_DONE	BIT(31)
103 
104 #define OCP_STATUS_IN_SYNC	BIT(0)
105 #define OCP_STATUS_IN_HOLDOVER	BIT(1)
106 
107 #define OCP_SELECT_CLK_NONE	0
108 #define OCP_SELECT_CLK_REG	0xfe
109 
110 struct tod_reg {
111 	u32	ctrl;
112 	u32	status;
113 	u32	uart_polarity;
114 	u32	version;
115 	u32	adj_sec;
116 	u32	__pad0[3];
117 	u32	uart_baud;
118 	u32	__pad1[3];
119 	u32	utc_status;
120 	u32	leap;
121 };
122 
123 #define TOD_CTRL_PROTOCOL	BIT(28)
124 #define TOD_CTRL_DISABLE_FMT_A	BIT(17)
125 #define TOD_CTRL_DISABLE_FMT_B	BIT(16)
126 #define TOD_CTRL_ENABLE		BIT(0)
127 #define TOD_CTRL_GNSS_MASK	GENMASK(3, 0)
128 #define TOD_CTRL_GNSS_SHIFT	24
129 
130 #define TOD_STATUS_UTC_MASK		GENMASK(7, 0)
131 #define TOD_STATUS_UTC_VALID		BIT(8)
132 #define TOD_STATUS_LEAP_ANNOUNCE	BIT(12)
133 #define TOD_STATUS_LEAP_VALID		BIT(16)
134 
135 struct ts_reg {
136 	u32	enable;
137 	u32	error;
138 	u32	polarity;
139 	u32	version;
140 	u32	__pad0[4];
141 	u32	cable_delay;
142 	u32	__pad1[3];
143 	u32	intr;
144 	u32	intr_mask;
145 	u32	event_count;
146 	u32	__pad2[1];
147 	u32	ts_count;
148 	u32	time_ns;
149 	u32	time_sec;
150 	u32	data_width;
151 	u32	data;
152 };
153 
154 struct pps_reg {
155 	u32	ctrl;
156 	u32	status;
157 	u32	__pad0[6];
158 	u32	cable_delay;
159 };
160 
161 #define PPS_STATUS_FILTER_ERR	BIT(0)
162 #define PPS_STATUS_SUPERV_ERR	BIT(1)
163 
164 struct img_reg {
165 	u32	version;
166 };
167 
168 struct gpio_reg {
169 	u32	gpio1;
170 	u32	__pad0;
171 	u32	gpio2;
172 	/* adva_x1: I2C bus ownership register; reserved on other variants */
173 	u32	i2c_bus_ctrl;
174 };
175 
176 struct irig_master_reg {
177 	u32	ctrl;
178 	u32	status;
179 	u32	__pad0;
180 	u32	version;
181 	u32	adj_sec;
182 	u32	mode_ctrl;
183 };
184 
185 #define IRIG_M_CTRL_ENABLE	BIT(0)
186 
187 struct irig_slave_reg {
188 	u32	ctrl;
189 	u32	status;
190 	u32	__pad0;
191 	u32	version;
192 	u32	adj_sec;
193 	u32	mode_ctrl;
194 };
195 
196 #define IRIG_S_CTRL_ENABLE	BIT(0)
197 
198 struct dcf_master_reg {
199 	u32	ctrl;
200 	u32	status;
201 	u32	__pad0;
202 	u32	version;
203 	u32	adj_sec;
204 };
205 
206 #define DCF_M_CTRL_ENABLE	BIT(0)
207 
208 struct dcf_slave_reg {
209 	u32	ctrl;
210 	u32	status;
211 	u32	__pad0;
212 	u32	version;
213 	u32	adj_sec;
214 };
215 
216 #define DCF_S_CTRL_ENABLE	BIT(0)
217 
218 struct signal_reg {
219 	u32	enable;
220 	u32	status;
221 	u32	polarity;
222 	u32	version;
223 	u32	__pad0[4];
224 	u32	cable_delay;
225 	u32	__pad1[3];
226 	u32	intr;
227 	u32	intr_mask;
228 	u32	__pad2[2];
229 	u32	start_ns;
230 	u32	start_sec;
231 	u32	pulse_ns;
232 	u32	pulse_sec;
233 	u32	period_ns;
234 	u32	period_sec;
235 	u32	repeat_count;
236 };
237 
238 struct frequency_reg {
239 	u32	ctrl;
240 	u32	status;
241 };
242 
243 struct board_config_reg {
244 	u32 mro50_serial_activate;
245 };
246 
247 #define FREQ_STATUS_VALID	BIT(31)
248 #define FREQ_STATUS_ERROR	BIT(30)
249 #define FREQ_STATUS_OVERRUN	BIT(29)
250 #define FREQ_STATUS_MASK	GENMASK(23, 0)
251 
252 struct ptp_ocp_flash_info {
253 	const char *name;
254 	int pci_offset;
255 	int data_size;
256 	void *data;
257 };
258 
259 struct ptp_ocp_firmware_header {
260 	char magic[4];
261 	__be16 pci_vendor_id;
262 	__be16 pci_device_id;
263 	__be32 image_size;
264 	__be16 hw_revision;
265 	__be16 crc;
266 };
267 
268 #define OCP_FIRMWARE_MAGIC_HEADER "OCPC"
269 
270 struct ptp_ocp_i2c_info {
271 	const char *name;
272 	unsigned long fixed_rate;
273 	size_t data_size;
274 	void *data;
275 };
276 
277 struct ptp_ocp_ext_info {
278 	int index;
279 	irqreturn_t (*irq_fcn)(int irq, void *priv);
280 	int (*enable)(void *priv, u32 req, bool enable);
281 };
282 
283 struct ptp_ocp_ext_src {
284 	void __iomem		*mem;
285 	struct ptp_ocp		*bp;
286 	struct ptp_ocp_ext_info	*info;
287 	int			irq_vec;
288 };
289 
290 enum ptp_ocp_sma_mode {
291 	SMA_MODE_IN,
292 	SMA_MODE_OUT,
293 };
294 
295 static struct dpll_pin_frequency ptp_ocp_sma_freq[] = {
296 	DPLL_PIN_FREQUENCY_1PPS,
297 	DPLL_PIN_FREQUENCY_10MHZ,
298 	DPLL_PIN_FREQUENCY_IRIG_B,
299 	DPLL_PIN_FREQUENCY_DCF77,
300 };
301 
302 struct ptp_ocp_sma_connector {
303 	enum	ptp_ocp_sma_mode mode;
304 	bool	fixed_fcn;
305 	bool	fixed_dir;
306 	bool	disabled;
307 	u8	default_fcn;
308 	struct dpll_pin		   *dpll_pin;
309 	struct dpll_pin_properties dpll_prop;
310 	dpll_tracker		   tracker;
311 };
312 
313 struct ocp_attr_group {
314 	u64 cap;
315 	const struct attribute_group *group;
316 };
317 
318 struct ocp_selector {
319 	const char *name;
320 	int value;
321 	u64 frequency;
322 };
323 
324 struct ocp_sma_op {
325 	const struct ocp_selector *tbl[2];
326 	void (*init)(struct ptp_ocp *bp);
327 	u32 (*get)(struct ptp_ocp *bp, int sma_nr);
328 	int (*set_inputs)(struct ptp_ocp *bp, int sma_nr, u32 val);
329 	int (*set_output)(struct ptp_ocp *bp, int sma_nr, u32 val);
330 };
331 
332 #define OCP_CAP_BASIC	BIT(0)
333 #define OCP_CAP_SIGNAL	BIT(1)
334 #define OCP_CAP_FREQ	BIT(2)
335 
336 struct ptp_ocp_signal {
337 	ktime_t		period;
338 	ktime_t		pulse;
339 	ktime_t		phase;
340 	ktime_t		start;
341 	int		duty;
342 	bool		polarity;
343 	bool		running;
344 };
345 
346 struct ptp_ocp_serial_port {
347 	int line;
348 	int baud;
349 };
350 
351 #define OCP_BOARD_ID_LEN		13
352 #define OCP_SERIAL_LEN			6
353 #define OCP_SMA_NUM			4
354 #define OCP_SIGNAL_NUM			4
355 #define OCP_FREQ_NUM			4
356 
357 enum {
358 	PORT_GNSS,
359 	PORT_GNSS2,
360 	PORT_MAC, /* miniature atomic clock */
361 	PORT_NMEA,
362 
363 	__PORT_COUNT,
364 };
365 
366 struct ptp_ocp {
367 	struct pci_dev		*pdev;
368 	struct device		dev;
369 	spinlock_t		lock;
370 	struct ocp_reg __iomem	*reg;
371 	struct tod_reg __iomem	*tod;
372 	struct pps_reg __iomem	*pps_to_ext;
373 	struct pps_reg __iomem	*pps_to_clk;
374 	struct board_config_reg __iomem	*board_config;
375 	struct gpio_reg __iomem	*pps_select;
376 	struct gpio_reg __iomem	*sma_map1;
377 	struct gpio_reg __iomem	*sma_map2;
378 	struct irig_master_reg	__iomem *irig_out;
379 	struct irig_slave_reg	__iomem *irig_in;
380 	struct dcf_master_reg	__iomem *dcf_out;
381 	struct dcf_slave_reg	__iomem *dcf_in;
382 	struct tod_reg		__iomem *nmea_out;
383 	struct frequency_reg	__iomem *freq_in[OCP_FREQ_NUM];
384 	struct ptp_ocp_ext_src	*signal_out[OCP_SIGNAL_NUM];
385 	struct ptp_ocp_ext_src	*pps;
386 	struct ptp_ocp_ext_src	*ts0;
387 	struct ptp_ocp_ext_src	*ts1;
388 	struct ptp_ocp_ext_src	*ts2;
389 	struct ptp_ocp_ext_src	*ts3;
390 	struct ptp_ocp_ext_src	*ts4;
391 	struct ocp_art_gpio_reg __iomem *art_sma;
392 	struct img_reg __iomem	*image;
393 	struct ptp_clock	*ptp;
394 	struct ptp_clock_info	ptp_info;
395 	struct platform_device	*i2c_ctrl;
396 	struct platform_device	*spi_flash;
397 	struct clk_hw		*i2c_clk;
398 	struct timer_list	watchdog;
399 	const struct attribute_group **attr_group;
400 	const struct ptp_ocp_eeprom_map *eeprom_map;
401 	struct dentry		*debug_root;
402 	bool			sync;
403 	time64_t		gnss_lost;
404 	struct delayed_work	sync_work;
405 	int			id;
406 	int			n_irqs;
407 	struct ptp_ocp_serial_port	port[__PORT_COUNT];
408 	bool			fw_loader;
409 	u8			fw_tag;
410 	u16			fw_version;
411 	u8			board_id[OCP_BOARD_ID_LEN];
412 	u8			serial[OCP_SERIAL_LEN];
413 	bool			has_eeprom_data;
414 	u32			pps_req_map;
415 	int			flash_start;
416 	u32			utc_tai_offset;
417 	u32			ts_window_adjust;
418 	u64			fw_cap;
419 	struct ptp_ocp_signal	signal[OCP_SIGNAL_NUM];
420 	struct ptp_ocp_sma_connector sma[OCP_SMA_NUM];
421 	const struct ocp_sma_op *sma_op;
422 	struct dpll_device *dpll;
423 	dpll_tracker tracker;
424 	int signals_nr;
425 	int freq_in_nr;
426 	/* adva_x1 CPLD I2C (internal use only) */
427 	/* serialises CPLD operations */
428 	struct mutex		cpld_lock;
429 	/* guards cpld_i2c_adap_nr against the bus notifier */
430 	spinlock_t		cpld_adap_lock;
431 	/* I2C adapter nr; -1 if absent.  Under cpld_adap_lock */
432 	int			cpld_i2c_adap_nr;
433 	/* claimed adapter; valid under cpld_lock */
434 	struct i2c_adapter	*cpld_adap;
435 	/* scratch, write half then read half; valid under cpld_lock */
436 	u8			*cpld_buf;
437 	/* Lattice device ID; 0 if unread */
438 	u32			cpld_id;
439 	/* USERCODE of the image in the part; valid once cpld_usercode_ok */
440 	u32			cpld_usercode;
441 	/* cpld_usercode has been read since the last flash */
442 	bool			cpld_usercode_ok;
443 	/* one-shot ID read finished, successfully or not; under cpld_lock */
444 	bool			cpld_id_tried;
445 	/* failed ID read attempts so far; under cpld_lock */
446 	unsigned int		cpld_id_attempts;
447 	/* x1 TAP CPLD present */
448 	bool			has_cpld;
449 	/* EN_CFG_TP issued but not yet REFRESH'd */
450 	bool			cpld_in_config_mode;
451 };
452 
453 #define OCP_REQ_TIMESTAMP	BIT(0)
454 #define OCP_REQ_PPS		BIT(1)
455 
456 struct ocp_resource {
457 	unsigned long offset;
458 	int size;
459 	int irq_vec;
460 	int (*setup)(struct ptp_ocp *bp, struct ocp_resource *r);
461 	void *extra;
462 	unsigned long bp_offset;
463 	const char * const name;
464 };
465 
466 static int ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r);
467 static int ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r);
468 static int ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r);
469 static int ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r);
470 static int ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r);
471 static int ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
472 static irqreturn_t ptp_ocp_ts_irq(int irq, void *priv);
473 static irqreturn_t ptp_ocp_signal_irq(int irq, void *priv);
474 static int ptp_ocp_ts_enable(void *priv, u32 req, bool enable);
475 static int ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,
476 				      struct ptp_perout_request *req);
477 static int ptp_ocp_signal_enable(void *priv, u32 req, bool enable);
478 static int ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr);
479 
480 static int ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
481 
482 static int ptp_ocp_adva_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
483 
484 static const struct ocp_sma_op ocp_adva_sma_op;
485 static const struct ocp_sma_op ocp_adva_x1_sma_op;
486 
487 /* Flash component naming the CPLD image, as reported by ->info_get(). */
488 #define ADVA_CPLD_COMPONENT	"fw.cpld"
489 
490 static int adva_x1_cpld_flash(struct ptp_ocp *bp, struct devlink *devlink,
491 			      const struct firmware *fw,
492 			      struct netlink_ext_ack *extack);
493 
494 static const struct ocp_attr_group fb_timecard_groups[];
495 
496 static const struct ocp_attr_group art_timecard_groups[];
497 
498 static const struct ocp_attr_group adva_timecard_groups[];
499 
500 static const struct ocp_attr_group adva_timecard_x1_groups[];
501 
502 struct ptp_ocp_eeprom_map {
503 	u16	off;
504 	u16	len;
505 	u32	bp_offset;
506 	const void * const tag;
507 };
508 
509 #define EEPROM_ENTRY(addr, member)				\
510 	.off = addr,						\
511 	.len = sizeof_field(struct ptp_ocp, member),		\
512 	.bp_offset = offsetof(struct ptp_ocp, member)
513 
514 #define BP_MAP_ENTRY_ADDR(bp, map) ({				\
515 	(void *)((uintptr_t)(bp) + (map)->bp_offset);		\
516 })
517 
518 static struct ptp_ocp_eeprom_map fb_eeprom_map[] = {
519 	{ EEPROM_ENTRY(0x43, board_id) },
520 	{ EEPROM_ENTRY(0x00, serial), .tag = "mac" },
521 	{ }
522 };
523 
524 static struct ptp_ocp_eeprom_map art_eeprom_map[] = {
525 	{ EEPROM_ENTRY(0x200 + 0x43, board_id) },
526 	{ EEPROM_ENTRY(0x200 + 0x63, serial) },
527 	{ }
528 };
529 
530 #define bp_assign_entry(bp, res, val) ({				\
531 	uintptr_t addr = (uintptr_t)(bp) + (res)->bp_offset;		\
532 	*(typeof(val) *)addr = val;					\
533 })
534 
535 #define OCP_RES_LOCATION(member) \
536 	.name = #member, .bp_offset = offsetof(struct ptp_ocp, member)
537 
538 #define OCP_MEM_RESOURCE(member) \
539 	OCP_RES_LOCATION(member), .setup = ptp_ocp_register_mem
540 
541 #define OCP_SERIAL_RESOURCE(member) \
542 	OCP_RES_LOCATION(member), .setup = ptp_ocp_register_serial
543 
544 #define OCP_I2C_RESOURCE(member) \
545 	OCP_RES_LOCATION(member), .setup = ptp_ocp_register_i2c
546 
547 #define OCP_SPI_RESOURCE(member) \
548 	OCP_RES_LOCATION(member), .setup = ptp_ocp_register_spi
549 
550 #define OCP_EXT_RESOURCE(member) \
551 	OCP_RES_LOCATION(member), .setup = ptp_ocp_register_ext
552 
553 /* This is the MSI vector mapping used.
554  * 0: PPS (TS5)
555  * 1: TS0
556  * 2: TS1
557  * 3: GNSS1
558  * 4: GNSS2
559  * 5: MAC
560  * 6: TS2
561  * 7: I2C controller
562  * 8: HWICAP (notused)
563  * 9: SPI Flash
564  * 10: NMEA
565  * 11: Signal Generator 1
566  * 12: Signal Generator 2
567  * 13: Signal Generator 3
568  * 14: Signal Generator 4
569  * 15: TS3
570  * 16: TS4
571  --
572  * 8: Orolia TS1
573  * 10: Orolia TS2
574  * 11: Orolia TS0 (GNSS)
575  * 12: Orolia PPS
576  * 14: Orolia TS3
577  * 15: Orolia TS4
578  */
579 
580 static struct ocp_resource ocp_fb_resource[] = {
581 	{
582 		OCP_MEM_RESOURCE(reg),
583 		.offset = 0x01000000, .size = 0x10000,
584 	},
585 	{
586 		OCP_EXT_RESOURCE(ts0),
587 		.offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
588 		.extra = &(struct ptp_ocp_ext_info) {
589 			.index = 0,
590 			.irq_fcn = ptp_ocp_ts_irq,
591 			.enable = ptp_ocp_ts_enable,
592 		},
593 	},
594 	{
595 		OCP_EXT_RESOURCE(ts1),
596 		.offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
597 		.extra = &(struct ptp_ocp_ext_info) {
598 			.index = 1,
599 			.irq_fcn = ptp_ocp_ts_irq,
600 			.enable = ptp_ocp_ts_enable,
601 		},
602 	},
603 	{
604 		OCP_EXT_RESOURCE(ts2),
605 		.offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
606 		.extra = &(struct ptp_ocp_ext_info) {
607 			.index = 2,
608 			.irq_fcn = ptp_ocp_ts_irq,
609 			.enable = ptp_ocp_ts_enable,
610 		},
611 	},
612 	{
613 		OCP_EXT_RESOURCE(ts3),
614 		.offset = 0x01110000, .size = 0x10000, .irq_vec = 15,
615 		.extra = &(struct ptp_ocp_ext_info) {
616 			.index = 3,
617 			.irq_fcn = ptp_ocp_ts_irq,
618 			.enable = ptp_ocp_ts_enable,
619 		},
620 	},
621 	{
622 		OCP_EXT_RESOURCE(ts4),
623 		.offset = 0x01120000, .size = 0x10000, .irq_vec = 16,
624 		.extra = &(struct ptp_ocp_ext_info) {
625 			.index = 4,
626 			.irq_fcn = ptp_ocp_ts_irq,
627 			.enable = ptp_ocp_ts_enable,
628 		},
629 	},
630 	/* Timestamp for PHC and/or PPS generator */
631 	{
632 		OCP_EXT_RESOURCE(pps),
633 		.offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
634 		.extra = &(struct ptp_ocp_ext_info) {
635 			.index = 5,
636 			.irq_fcn = ptp_ocp_ts_irq,
637 			.enable = ptp_ocp_ts_enable,
638 		},
639 	},
640 	{
641 		OCP_EXT_RESOURCE(signal_out[0]),
642 		.offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
643 		.extra = &(struct ptp_ocp_ext_info) {
644 			.index = 1,
645 			.irq_fcn = ptp_ocp_signal_irq,
646 			.enable = ptp_ocp_signal_enable,
647 		},
648 	},
649 	{
650 		OCP_EXT_RESOURCE(signal_out[1]),
651 		.offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
652 		.extra = &(struct ptp_ocp_ext_info) {
653 			.index = 2,
654 			.irq_fcn = ptp_ocp_signal_irq,
655 			.enable = ptp_ocp_signal_enable,
656 		},
657 	},
658 	{
659 		OCP_EXT_RESOURCE(signal_out[2]),
660 		.offset = 0x010F0000, .size = 0x10000, .irq_vec = 13,
661 		.extra = &(struct ptp_ocp_ext_info) {
662 			.index = 3,
663 			.irq_fcn = ptp_ocp_signal_irq,
664 			.enable = ptp_ocp_signal_enable,
665 		},
666 	},
667 	{
668 		OCP_EXT_RESOURCE(signal_out[3]),
669 		.offset = 0x01100000, .size = 0x10000, .irq_vec = 14,
670 		.extra = &(struct ptp_ocp_ext_info) {
671 			.index = 4,
672 			.irq_fcn = ptp_ocp_signal_irq,
673 			.enable = ptp_ocp_signal_enable,
674 		},
675 	},
676 	{
677 		OCP_MEM_RESOURCE(pps_to_ext),
678 		.offset = 0x01030000, .size = 0x10000,
679 	},
680 	{
681 		OCP_MEM_RESOURCE(pps_to_clk),
682 		.offset = 0x01040000, .size = 0x10000,
683 	},
684 	{
685 		OCP_MEM_RESOURCE(tod),
686 		.offset = 0x01050000, .size = 0x10000,
687 	},
688 	{
689 		OCP_MEM_RESOURCE(irig_in),
690 		.offset = 0x01070000, .size = 0x10000,
691 	},
692 	{
693 		OCP_MEM_RESOURCE(irig_out),
694 		.offset = 0x01080000, .size = 0x10000,
695 	},
696 	{
697 		OCP_MEM_RESOURCE(dcf_in),
698 		.offset = 0x01090000, .size = 0x10000,
699 	},
700 	{
701 		OCP_MEM_RESOURCE(dcf_out),
702 		.offset = 0x010A0000, .size = 0x10000,
703 	},
704 	{
705 		OCP_MEM_RESOURCE(nmea_out),
706 		.offset = 0x010B0000, .size = 0x10000,
707 	},
708 	{
709 		OCP_MEM_RESOURCE(image),
710 		.offset = 0x00020000, .size = 0x1000,
711 	},
712 	{
713 		OCP_MEM_RESOURCE(pps_select),
714 		.offset = 0x00130000, .size = 0x1000,
715 	},
716 	{
717 		OCP_MEM_RESOURCE(sma_map1),
718 		.offset = 0x00140000, .size = 0x1000,
719 	},
720 	{
721 		OCP_MEM_RESOURCE(sma_map2),
722 		.offset = 0x00220000, .size = 0x1000,
723 	},
724 	{
725 		OCP_I2C_RESOURCE(i2c_ctrl),
726 		.offset = 0x00150000, .size = 0x10000, .irq_vec = 7,
727 		.extra = &(struct ptp_ocp_i2c_info) {
728 			.name = "xiic-i2c",
729 			.fixed_rate = 50000000,
730 			.data_size = sizeof(struct xiic_i2c_platform_data),
731 			.data = &(struct xiic_i2c_platform_data) {
732 				.num_devices = 2,
733 				.devices = (struct i2c_board_info[]) {
734 					{ I2C_BOARD_INFO("24c02", 0x50) },
735 					{ I2C_BOARD_INFO("24mac402", 0x58),
736 					  .platform_data = "mac" },
737 				},
738 			},
739 		},
740 	},
741 	{
742 		OCP_SERIAL_RESOURCE(port[PORT_GNSS]),
743 		.offset = 0x00160000 + 0x1000, .irq_vec = 3,
744 		.extra = &(struct ptp_ocp_serial_port) {
745 			.baud = 115200,
746 		},
747 	},
748 	{
749 		OCP_SERIAL_RESOURCE(port[PORT_GNSS2]),
750 		.offset = 0x00170000 + 0x1000, .irq_vec = 4,
751 		.extra = &(struct ptp_ocp_serial_port) {
752 			.baud = 115200,
753 		},
754 	},
755 	{
756 		OCP_SERIAL_RESOURCE(port[PORT_MAC]),
757 		.offset = 0x00180000 + 0x1000, .irq_vec = 5,
758 		.extra = &(struct ptp_ocp_serial_port) {
759 			.baud = 57600,
760 		},
761 	},
762 	{
763 		OCP_SERIAL_RESOURCE(port[PORT_NMEA]),
764 		.offset = 0x00190000 + 0x1000, .irq_vec = 10,
765 	},
766 	{
767 		OCP_SPI_RESOURCE(spi_flash),
768 		.offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
769 		.extra = &(struct ptp_ocp_flash_info) {
770 			.name = "xilinx_spi", .pci_offset = 0,
771 			.data_size = sizeof(struct xspi_platform_data),
772 			.data = &(struct xspi_platform_data) {
773 				.num_chipselect = 1,
774 				.bits_per_word = 8,
775 				.num_devices = 1,
776 				.force_irq = true,
777 				.devices = &(struct spi_board_info) {
778 					.modalias = "spi-nor",
779 				},
780 			},
781 		},
782 	},
783 	{
784 		OCP_MEM_RESOURCE(freq_in[0]),
785 		.offset = 0x01200000, .size = 0x10000,
786 	},
787 	{
788 		OCP_MEM_RESOURCE(freq_in[1]),
789 		.offset = 0x01210000, .size = 0x10000,
790 	},
791 	{
792 		OCP_MEM_RESOURCE(freq_in[2]),
793 		.offset = 0x01220000, .size = 0x10000,
794 	},
795 	{
796 		OCP_MEM_RESOURCE(freq_in[3]),
797 		.offset = 0x01230000, .size = 0x10000,
798 	},
799 	{
800 		.setup = ptp_ocp_fb_board_init,
801 		.extra = &(struct ptp_ocp_servo_conf) {
802 			.servo_offset_p = 0x2000,
803 			.servo_offset_i = 0x1000,
804 			.servo_drift_p = 0,
805 			.servo_drift_i = 0,
806 		},
807 	},
808 	{ }
809 };
810 
811 #define OCP_ART_CONFIG_SIZE		144
812 #define OCP_ART_TEMP_TABLE_SIZE		368
813 
814 struct ocp_art_gpio_reg {
815 	struct {
816 		u32	gpio;
817 		u32	__pad[3];
818 	} map[4];
819 };
820 
821 static struct ocp_resource ocp_art_resource[] = {
822 	{
823 		OCP_MEM_RESOURCE(reg),
824 		.offset = 0x01000000, .size = 0x10000,
825 	},
826 	{
827 		OCP_SERIAL_RESOURCE(port[PORT_GNSS]),
828 		.offset = 0x00160000 + 0x1000, .irq_vec = 3,
829 		.extra = &(struct ptp_ocp_serial_port) {
830 			.baud = 115200,
831 		},
832 	},
833 	{
834 		OCP_MEM_RESOURCE(art_sma),
835 		.offset = 0x003C0000, .size = 0x1000,
836 	},
837 	/* Timestamp associated with GNSS1 receiver PPS */
838 	{
839 		OCP_EXT_RESOURCE(ts0),
840 		.offset = 0x360000, .size = 0x20, .irq_vec = 12,
841 		.extra = &(struct ptp_ocp_ext_info) {
842 			.index = 0,
843 			.irq_fcn = ptp_ocp_ts_irq,
844 			.enable = ptp_ocp_ts_enable,
845 		},
846 	},
847 	{
848 		OCP_EXT_RESOURCE(ts1),
849 		.offset = 0x380000, .size = 0x20, .irq_vec = 8,
850 		.extra = &(struct ptp_ocp_ext_info) {
851 			.index = 1,
852 			.irq_fcn = ptp_ocp_ts_irq,
853 			.enable = ptp_ocp_ts_enable,
854 		},
855 	},
856 	{
857 		OCP_EXT_RESOURCE(ts2),
858 		.offset = 0x390000, .size = 0x20, .irq_vec = 10,
859 		.extra = &(struct ptp_ocp_ext_info) {
860 			.index = 2,
861 			.irq_fcn = ptp_ocp_ts_irq,
862 			.enable = ptp_ocp_ts_enable,
863 		},
864 	},
865 	{
866 		OCP_EXT_RESOURCE(ts3),
867 		.offset = 0x3A0000, .size = 0x20, .irq_vec = 14,
868 		.extra = &(struct ptp_ocp_ext_info) {
869 			.index = 3,
870 			.irq_fcn = ptp_ocp_ts_irq,
871 			.enable = ptp_ocp_ts_enable,
872 		},
873 	},
874 	{
875 		OCP_EXT_RESOURCE(ts4),
876 		.offset = 0x3B0000, .size = 0x20, .irq_vec = 15,
877 		.extra = &(struct ptp_ocp_ext_info) {
878 			.index = 4,
879 			.irq_fcn = ptp_ocp_ts_irq,
880 			.enable = ptp_ocp_ts_enable,
881 		},
882 	},
883 	/* Timestamp associated with Internal PPS of the card */
884 	{
885 		OCP_EXT_RESOURCE(pps),
886 		.offset = 0x00330000, .size = 0x20, .irq_vec = 11,
887 		.extra = &(struct ptp_ocp_ext_info) {
888 			.index = 5,
889 			.irq_fcn = ptp_ocp_ts_irq,
890 			.enable = ptp_ocp_ts_enable,
891 		},
892 	},
893 	{
894 		OCP_SPI_RESOURCE(spi_flash),
895 		.offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
896 		.extra = &(struct ptp_ocp_flash_info) {
897 			.name = "spi_altera", .pci_offset = 0,
898 			.data_size = sizeof(struct altera_spi_platform_data),
899 			.data = &(struct altera_spi_platform_data) {
900 				.num_chipselect = 1,
901 				.num_devices = 1,
902 				.devices = &(struct spi_board_info) {
903 					.modalias = "spi-nor",
904 				},
905 			},
906 		},
907 	},
908 	{
909 		OCP_I2C_RESOURCE(i2c_ctrl),
910 		.offset = 0x350000, .size = 0x100, .irq_vec = 4,
911 		.extra = &(struct ptp_ocp_i2c_info) {
912 			.name = "ocores-i2c",
913 			.fixed_rate = 400000,
914 			.data_size = sizeof(struct ocores_i2c_platform_data),
915 			.data = &(struct ocores_i2c_platform_data) {
916 				.clock_khz = 125000,
917 				.bus_khz = 400,
918 				.num_devices = 1,
919 				.devices = &(struct i2c_board_info) {
920 					I2C_BOARD_INFO("24c08", 0x50),
921 				},
922 			},
923 		},
924 	},
925 	{
926 		OCP_SERIAL_RESOURCE(port[PORT_MAC]),
927 		.offset = 0x00190000, .irq_vec = 7,
928 		.extra = &(struct ptp_ocp_serial_port) {
929 			.baud = 9600,
930 		},
931 	},
932 	{
933 		OCP_MEM_RESOURCE(board_config),
934 		.offset = 0x210000, .size = 0x1000,
935 	},
936 	{
937 		.setup = ptp_ocp_art_board_init,
938 		.extra = &(struct ptp_ocp_servo_conf) {
939 			.servo_offset_p = 0x2000,
940 			.servo_offset_i = 0x1000,
941 			.servo_drift_p = 0,
942 			.servo_drift_i = 0,
943 		},
944 	},
945 	{ }
946 };
947 
948 static struct ocp_resource ocp_adva_resource[] = {
949 	{
950 		OCP_MEM_RESOURCE(reg),
951 		.offset = 0x01000000, .size = 0x10000,
952 	},
953 	{
954 		OCP_EXT_RESOURCE(ts0),
955 		.offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
956 		.extra = &(struct ptp_ocp_ext_info) {
957 			.index = 0,
958 			.irq_fcn = ptp_ocp_ts_irq,
959 			.enable = ptp_ocp_ts_enable,
960 		},
961 	},
962 	{
963 		OCP_EXT_RESOURCE(ts1),
964 		.offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
965 		.extra = &(struct ptp_ocp_ext_info) {
966 			.index = 1,
967 			.irq_fcn = ptp_ocp_ts_irq,
968 			.enable = ptp_ocp_ts_enable,
969 		},
970 	},
971 	{
972 		OCP_EXT_RESOURCE(ts2),
973 		.offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
974 		.extra = &(struct ptp_ocp_ext_info) {
975 			.index = 2,
976 			.irq_fcn = ptp_ocp_ts_irq,
977 			.enable = ptp_ocp_ts_enable,
978 		},
979 	},
980 	/* Timestamp for PHC and/or PPS generator */
981 	{
982 		OCP_EXT_RESOURCE(pps),
983 		.offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
984 		.extra = &(struct ptp_ocp_ext_info) {
985 			.index = 5,
986 			.irq_fcn = ptp_ocp_ts_irq,
987 			.enable = ptp_ocp_ts_enable,
988 		},
989 	},
990 	{
991 		OCP_EXT_RESOURCE(signal_out[0]),
992 		.offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
993 		.extra = &(struct ptp_ocp_ext_info) {
994 			.index = 1,
995 			.irq_fcn = ptp_ocp_signal_irq,
996 			.enable = ptp_ocp_signal_enable,
997 		},
998 	},
999 	{
1000 		OCP_EXT_RESOURCE(signal_out[1]),
1001 		.offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
1002 		.extra = &(struct ptp_ocp_ext_info) {
1003 			.index = 2,
1004 			.irq_fcn = ptp_ocp_signal_irq,
1005 			.enable = ptp_ocp_signal_enable,
1006 		},
1007 	},
1008 	{
1009 		OCP_MEM_RESOURCE(pps_to_ext),
1010 		.offset = 0x01030000, .size = 0x10000,
1011 	},
1012 	{
1013 		OCP_MEM_RESOURCE(pps_to_clk),
1014 		.offset = 0x01040000, .size = 0x10000,
1015 	},
1016 	{
1017 		OCP_MEM_RESOURCE(tod),
1018 		.offset = 0x01050000, .size = 0x10000,
1019 	},
1020 	{
1021 		OCP_MEM_RESOURCE(image),
1022 		.offset = 0x00020000, .size = 0x1000,
1023 	},
1024 	{
1025 		OCP_MEM_RESOURCE(pps_select),
1026 		.offset = 0x00130000, .size = 0x1000,
1027 	},
1028 	{
1029 		OCP_MEM_RESOURCE(sma_map1),
1030 		.offset = 0x00140000, .size = 0x1000,
1031 	},
1032 	{
1033 		OCP_MEM_RESOURCE(sma_map2),
1034 		.offset = 0x00220000, .size = 0x1000,
1035 	},
1036 	{
1037 		OCP_SERIAL_RESOURCE(port[PORT_GNSS]),
1038 		.offset = 0x00160000 + 0x1000, .irq_vec = 3,
1039 		.extra = &(struct ptp_ocp_serial_port) {
1040 			.baud = 9600,
1041 		},
1042 	},
1043 	{
1044 		OCP_SERIAL_RESOURCE(port[PORT_MAC]),
1045 		.offset = 0x00180000 + 0x1000, .irq_vec = 5,
1046 		.extra = &(struct ptp_ocp_serial_port) {
1047 			.baud = 115200,
1048 		},
1049 	},
1050 	{
1051 		OCP_MEM_RESOURCE(freq_in[0]),
1052 		.offset = 0x01200000, .size = 0x10000,
1053 	},
1054 	{
1055 		OCP_MEM_RESOURCE(freq_in[1]),
1056 		.offset = 0x01210000, .size = 0x10000,
1057 	},
1058 	{
1059 		OCP_SPI_RESOURCE(spi_flash),
1060 		.offset = 0x00310400, .size = 0x10000, .irq_vec = 9,
1061 		.extra = &(struct ptp_ocp_flash_info) {
1062 			.name = "spi_altera", .pci_offset = 0,
1063 			.data_size = sizeof(struct altera_spi_platform_data),
1064 			.data = &(struct altera_spi_platform_data) {
1065 				.num_chipselect = 1,
1066 				.num_devices = 1,
1067 				.devices = &(struct spi_board_info) {
1068 					.modalias = "spi-nor",
1069 				},
1070 			},
1071 		},
1072 	},
1073 	{
1074 		OCP_I2C_RESOURCE(i2c_ctrl),
1075 		.offset = 0x150000, .size = 0x100, .irq_vec = 7,
1076 		.extra = &(struct ptp_ocp_i2c_info) {
1077 			.name = "ocores-i2c",
1078 			.fixed_rate = 50000000,
1079 			.data_size = sizeof(struct ocores_i2c_platform_data),
1080 			.data = &(struct ocores_i2c_platform_data) {
1081 				.clock_khz = 50000,
1082 				.bus_khz = 100,
1083 				.reg_io_width = 4, // 32-bit/4-byte
1084 				.reg_shift = 2, // 32-bit addressing
1085 				.num_devices = 2,
1086 				.devices = (struct i2c_board_info[]) {
1087 					{ I2C_BOARD_INFO("24c02", 0x50) },
1088 					{ I2C_BOARD_INFO("24mac402", 0x58),
1089 					 .platform_data = "mac" },
1090 				},
1091 			},
1092 		},
1093 	},
1094 	{
1095 		.setup = ptp_ocp_adva_board_init,
1096 		.extra = &(struct ptp_ocp_adva_info) {
1097 			.servo = {
1098 				.servo_offset_p = 0xc000,
1099 				.servo_offset_i = 0x1000,
1100 				.servo_drift_p = 0,
1101 				.servo_drift_i = 0,
1102 			},
1103 			.flash_start  = 0xA00000,
1104 			.sma_op       = &ocp_adva_sma_op,
1105 			.signals_nr   = 2,
1106 			.freq_in_nr   = 2,
1107 			.attr_groups  = adva_timecard_groups,
1108 		},
1109 	},
1110 	{ }
1111 };
1112 
1113 static struct ocp_resource ocp_adva_x1_resource[] = {
1114 	{
1115 		OCP_MEM_RESOURCE(reg),
1116 		.offset = 0x01000000, .size = 0x10000,
1117 	},
1118 	{
1119 		OCP_EXT_RESOURCE(ts0),
1120 		.offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
1121 		.extra = &(struct ptp_ocp_ext_info) {
1122 			.index = 0,
1123 			.irq_fcn = ptp_ocp_ts_irq,
1124 			.enable = ptp_ocp_ts_enable,
1125 		},
1126 	},
1127 	{
1128 		OCP_EXT_RESOURCE(ts1),
1129 		.offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
1130 		.extra = &(struct ptp_ocp_ext_info) {
1131 			.index = 1,
1132 			.irq_fcn = ptp_ocp_ts_irq,
1133 			.enable = ptp_ocp_ts_enable,
1134 		},
1135 	},
1136 	{
1137 		OCP_EXT_RESOURCE(ts2),
1138 		.offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
1139 		.extra = &(struct ptp_ocp_ext_info) {
1140 			.index = 2,
1141 			.irq_fcn = ptp_ocp_ts_irq,
1142 			.enable = ptp_ocp_ts_enable,
1143 		},
1144 	},
1145 	{
1146 		OCP_EXT_RESOURCE(ts3),
1147 		.offset = 0x01110000, .size = 0x10000, .irq_vec = 15,
1148 		.extra = &(struct ptp_ocp_ext_info) {
1149 			.index = 3,
1150 			.irq_fcn = ptp_ocp_ts_irq,
1151 			.enable = ptp_ocp_ts_enable,
1152 		},
1153 	},
1154 	{
1155 		OCP_EXT_RESOURCE(ts4),
1156 		.offset = 0x01120000, .size = 0x10000, .irq_vec = 16,
1157 		.extra = &(struct ptp_ocp_ext_info) {
1158 			.index = 4,
1159 			.irq_fcn = ptp_ocp_ts_irq,
1160 			.enable = ptp_ocp_ts_enable,
1161 		},
1162 	},
1163 	/* Timestamp for PHC and/or PPS generator */
1164 	{
1165 		OCP_EXT_RESOURCE(pps),
1166 		.offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
1167 		.extra = &(struct ptp_ocp_ext_info) {
1168 			.index = 5,
1169 			.irq_fcn = ptp_ocp_ts_irq,
1170 			.enable = ptp_ocp_ts_enable,
1171 		},
1172 	},
1173 	{
1174 		OCP_EXT_RESOURCE(signal_out[0]),
1175 		.offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
1176 		.extra = &(struct ptp_ocp_ext_info) {
1177 			.index = 1,
1178 			.irq_fcn = ptp_ocp_signal_irq,
1179 			.enable = ptp_ocp_signal_enable,
1180 		},
1181 	},
1182 	{
1183 		OCP_EXT_RESOURCE(signal_out[1]),
1184 		.offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
1185 		.extra = &(struct ptp_ocp_ext_info) {
1186 			.index = 2,
1187 			.irq_fcn = ptp_ocp_signal_irq,
1188 			.enable = ptp_ocp_signal_enable,
1189 		},
1190 	},
1191 	{
1192 		OCP_EXT_RESOURCE(signal_out[2]),
1193 		.offset = 0x010F0000, .size = 0x10000, .irq_vec = 13,
1194 		.extra = &(struct ptp_ocp_ext_info) {
1195 			.index = 3,
1196 			.irq_fcn = ptp_ocp_signal_irq,
1197 			.enable = ptp_ocp_signal_enable,
1198 		},
1199 	},
1200 	{
1201 		OCP_EXT_RESOURCE(signal_out[3]),
1202 		.offset = 0x01100000, .size = 0x10000, .irq_vec = 14,
1203 		.extra = &(struct ptp_ocp_ext_info) {
1204 			.index = 4,
1205 			.irq_fcn = ptp_ocp_signal_irq,
1206 			.enable = ptp_ocp_signal_enable,
1207 		},
1208 	},
1209 	{
1210 		OCP_MEM_RESOURCE(pps_to_ext),
1211 		.offset = 0x01030000, .size = 0x10000,
1212 	},
1213 	{
1214 		OCP_MEM_RESOURCE(pps_to_clk),
1215 		.offset = 0x01040000, .size = 0x10000,
1216 	},
1217 	{
1218 		OCP_MEM_RESOURCE(tod),
1219 		.offset = 0x01050000, .size = 0x10000,
1220 	},
1221 	{
1222 		OCP_MEM_RESOURCE(image),
1223 		.offset = 0x00020000, .size = 0x1000,
1224 	},
1225 	{
1226 		OCP_MEM_RESOURCE(pps_select),
1227 		.offset = 0x00130000, .size = 0x1000,
1228 	},
1229 	{
1230 		OCP_MEM_RESOURCE(sma_map1),
1231 		.offset = 0x00140000, .size = 0x1000,
1232 	},
1233 	{
1234 		OCP_MEM_RESOURCE(sma_map2),
1235 		.offset = 0x00220000, .size = 0x1000,
1236 	},
1237 	{
1238 		OCP_SERIAL_RESOURCE(port[PORT_GNSS]),
1239 		.offset = 0x00160000 + 0x1000, .irq_vec = 3,
1240 		.extra = &(struct ptp_ocp_serial_port) {
1241 			.baud = 9600,
1242 		},
1243 	},
1244 	{
1245 		OCP_SERIAL_RESOURCE(port[PORT_MAC]),
1246 		.offset = 0x00180000 + 0x1000, .irq_vec = 5,
1247 		.extra = &(struct ptp_ocp_serial_port) {
1248 			.baud = 115200,
1249 		},
1250 	},
1251 	{
1252 		OCP_MEM_RESOURCE(freq_in[0]),
1253 		.offset = 0x01200000, .size = 0x10000,
1254 	},
1255 	{
1256 		OCP_MEM_RESOURCE(freq_in[1]),
1257 		.offset = 0x01210000, .size = 0x10000,
1258 	},
1259 	{
1260 		OCP_MEM_RESOURCE(freq_in[2]),
1261 		.offset = 0x01220000, .size = 0x10000,
1262 	},
1263 	{
1264 		OCP_MEM_RESOURCE(freq_in[3]),
1265 		.offset = 0x01230000, .size = 0x10000,
1266 	},
1267 	{
1268 		OCP_SPI_RESOURCE(spi_flash),
1269 		.offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
1270 		.extra = &(struct ptp_ocp_flash_info) {
1271 			.name = "xilinx_spi", .pci_offset = 0,
1272 			.data_size = sizeof(struct xspi_platform_data),
1273 			.data = &(struct xspi_platform_data) {
1274 				.num_chipselect = 1,
1275 				.bits_per_word = 8,
1276 				.num_devices = 1,
1277 				.force_irq = true,
1278 				.devices = &(struct spi_board_info) {
1279 					.modalias = "spi-nor",
1280 				},
1281 			},
1282 		},
1283 	},
1284 	{
1285 		OCP_I2C_RESOURCE(i2c_ctrl),
1286 		.offset = 0x00150000, .size = 0x10000, .irq_vec = 7,
1287 		.extra = &(struct ptp_ocp_i2c_info) {
1288 			.name = "xiic-i2c",
1289 			.fixed_rate = 50000000,
1290 			.data_size = sizeof(struct xiic_i2c_platform_data),
1291 			.data = &(struct xiic_i2c_platform_data) {
1292 				.num_devices = 2,
1293 				.devices = (struct i2c_board_info[]) {
1294 					{ I2C_BOARD_INFO("24c02", 0x50) },
1295 					{ I2C_BOARD_INFO("24mac402", 0x58),
1296 					  .platform_data = "mac" },
1297 				},
1298 			},
1299 		},
1300 	},
1301 	{
1302 		.setup = ptp_ocp_adva_board_init,
1303 		.extra = &(struct ptp_ocp_adva_info) {
1304 			.servo = {
1305 				.servo_offset_p = 0xc000,
1306 				.servo_offset_i = 0x1000,
1307 				.servo_drift_p = 0,
1308 				.servo_drift_i = 0,
1309 			},
1310 			.flash_start  = 0x1000000,
1311 			.sma_op       = &ocp_adva_x1_sma_op,
1312 			.signals_nr   = 4,
1313 			.freq_in_nr   = 4,
1314 			.attr_groups  = adva_timecard_x1_groups,
1315 			.has_cpld     = true,
1316 		},
1317 	},
1318 	{ }
1319 };
1320 
1321 static const struct pci_device_id ptp_ocp_pcidev_id[] = {
1322 	{ PCI_DEVICE_DATA(META, TIMECARD, &ocp_fb_resource) },
1323 	{ PCI_DEVICE_DATA(CELESTICA, TIMECARD, &ocp_fb_resource) },
1324 	{ PCI_DEVICE_DATA(OROLIA, ARTCARD, &ocp_art_resource) },
1325 	{ PCI_DEVICE_DATA(ADVA, TIMECARD, &ocp_adva_resource) },
1326 	{ PCI_DEVICE_DATA(ADVA, TIMECARD_X1, &ocp_adva_x1_resource) },
1327 	{ }
1328 };
1329 MODULE_DEVICE_TABLE(pci, ptp_ocp_pcidev_id);
1330 
1331 static DEFINE_MUTEX(ptp_ocp_lock);
1332 static DEFINE_IDR(ptp_ocp_idr);
1333 
1334 static const struct ocp_selector ptp_ocp_clock[] = {
1335 	{ .name = "NONE",	.value = 0 },
1336 	{ .name = "TOD",	.value = 1 },
1337 	{ .name = "IRIG",	.value = 2 },
1338 	{ .name = "PPS",	.value = 3 },
1339 	{ .name = "PTP",	.value = 4 },
1340 	{ .name = "RTC",	.value = 5 },
1341 	{ .name = "DCF",	.value = 6 },
1342 	{ .name = "REGS",	.value = 0xfe },
1343 	{ .name = "EXT",	.value = 0xff },
1344 	{ }
1345 };
1346 
1347 #define SMA_DISABLE		BIT(16)
1348 #define SMA_ENABLE		BIT(15)
1349 #define SMA_SELECT_MASK		GENMASK(14, 0)
1350 
1351 static const struct ocp_selector ptp_ocp_sma_in[] = {
1352 	{ .name = "10Mhz",  .value = 0x0000,      .frequency = 10000000 },
1353 	{ .name = "PPS1",   .value = 0x0001,      .frequency = 1 },
1354 	{ .name = "PPS2",   .value = 0x0002,      .frequency = 1 },
1355 	{ .name = "TS1",    .value = 0x0004,      .frequency = 0 },
1356 	{ .name = "TS2",    .value = 0x0008,      .frequency = 0 },
1357 	{ .name = "IRIG",   .value = 0x0010,      .frequency = 10000 },
1358 	{ .name = "DCF",    .value = 0x0020,      .frequency = 77500 },
1359 	{ .name = "TS3",    .value = 0x0040,      .frequency = 0 },
1360 	{ .name = "TS4",    .value = 0x0080,      .frequency = 0 },
1361 	{ .name = "FREQ1",  .value = 0x0100,      .frequency = 0 },
1362 	{ .name = "FREQ2",  .value = 0x0200,      .frequency = 0 },
1363 	{ .name = "FREQ3",  .value = 0x0400,      .frequency = 0 },
1364 	{ .name = "FREQ4",  .value = 0x0800,      .frequency = 0 },
1365 	{ .name = "None",   .value = SMA_DISABLE, .frequency = 0 },
1366 	{ }
1367 };
1368 
1369 static const struct ocp_selector ptp_ocp_sma_out[] = {
1370 	{ .name = "10Mhz",	.value = 0x0000,  .frequency = 10000000 },
1371 	{ .name = "PHC",	.value = 0x0001,  .frequency = 1 },
1372 	{ .name = "MAC",	.value = 0x0002,  .frequency = 1 },
1373 	{ .name = "GNSS1",	.value = 0x0004,  .frequency = 1 },
1374 	{ .name = "GNSS2",	.value = 0x0008,  .frequency = 1 },
1375 	{ .name = "IRIG",	.value = 0x0010,  .frequency = 10000 },
1376 	{ .name = "DCF",	.value = 0x0020,  .frequency = 77000 },
1377 	{ .name = "GEN1",	.value = 0x0040 },
1378 	{ .name = "GEN2",	.value = 0x0080 },
1379 	{ .name = "GEN3",	.value = 0x0100 },
1380 	{ .name = "GEN4",	.value = 0x0200 },
1381 	{ .name = "GND",	.value = 0x2000 },
1382 	{ .name = "VCC",	.value = 0x4000 },
1383 	{ }
1384 };
1385 
1386 static const struct ocp_selector ptp_ocp_art_sma_in[] = {
1387 	{ .name = "PPS1",	.value = 0x0001,  .frequency = 1 },
1388 	{ .name = "10Mhz",	.value = 0x0008,  .frequency = 1000000 },
1389 	{ }
1390 };
1391 
1392 static const struct ocp_selector ptp_ocp_art_sma_out[] = {
1393 	{ .name = "PHC",	.value = 0x0002,  .frequency = 1 },
1394 	{ .name = "GNSS",	.value = 0x0004,  .frequency = 1 },
1395 	{ .name = "10Mhz",	.value = 0x0010,  .frequency = 10000000 },
1396 	{ }
1397 };
1398 
1399 static const struct ocp_selector ptp_ocp_adva_sma_in[] = {
1400 	{ .name = "10Mhz",	.value = 0x0000,      .frequency = 10000000},
1401 	{ .name = "PPS1",	.value = 0x0001,      .frequency = 1 },
1402 	{ .name = "PPS2",	.value = 0x0002,      .frequency = 1 },
1403 	{ .name = "TS1",	.value = 0x0004,      .frequency = 0 },
1404 	{ .name = "TS2",	.value = 0x0008,      .frequency = 0 },
1405 	{ .name = "FREQ1",	.value = 0x0100,      .frequency = 0 },
1406 	{ .name = "FREQ2",	.value = 0x0200,      .frequency = 0 },
1407 	{ .name = "None",	.value = SMA_DISABLE, .frequency = 0 },
1408 	{ }
1409 };
1410 
1411 static const struct ocp_selector ptp_ocp_adva_sma_out[] = {
1412 	{ .name = "10Mhz",	.value = 0x0000,  .frequency = 10000000},
1413 	{ .name = "PHC",	.value = 0x0001,  .frequency = 1 },
1414 	{ .name = "MAC",	.value = 0x0002,  .frequency = 1 },
1415 	{ .name = "GNSS1",	.value = 0x0004,  .frequency = 1 },
1416 	{ .name = "GEN1",	.value = 0x0040 },
1417 	{ .name = "GEN2",	.value = 0x0080 },
1418 	{ .name = "GND",	.value = 0x2000 },
1419 	{ .name = "VCC",	.value = 0x4000 },
1420 	{ }
1421 };
1422 
1423 static const struct ocp_selector ptp_ocp_adva_x1_sma_in[] = {
1424 	{ .name = "PPS1",	.value = 0x0001,      .frequency = 1 },
1425 	{ .name = "TS1",	.value = 0x0004,      .frequency = 0 },
1426 	{ .name = "TS2",	.value = 0x0008,      .frequency = 0 },
1427 	{ .name = "TS3",    .value = 0x0040,      .frequency = 0 },
1428 	{ .name = "TS4",    .value = 0x0080,      .frequency = 0 },
1429 	{ .name = "FREQ1",	.value = 0x0100,      .frequency = 0 },
1430 	{ .name = "FREQ2",	.value = 0x0200,      .frequency = 0 },
1431 	{ .name = "FREQ3",  .value = 0x0400,      .frequency = 0 },
1432 	{ .name = "FREQ4",  .value = 0x0800,      .frequency = 0 },
1433 	{ .name = "None",	.value = SMA_DISABLE, .frequency = 0 },
1434 	{ }
1435 };
1436 
1437 static const struct ocp_selector ptp_ocp_adva_x1_sma_out[] = {
1438 	{ .name = "10Mhz",	.value = 0x0000,  .frequency = 10000000},
1439 	{ .name = "PHC",	.value = 0x0001,  .frequency = 1 },
1440 	{ .name = "MAC",	.value = 0x0002,  .frequency = 1 },
1441 	{ .name = "GNSS1",	.value = 0x0004,  .frequency = 1 },
1442 	{ .name = "GEN1",	.value = 0x0040 },
1443 	{ .name = "GEN2",	.value = 0x0080 },
1444 	{ .name = "GEN3",	.value = 0x0100 },
1445 	{ .name = "GEN4",	.value = 0x0200 },
1446 	{ .name = "GND",	.value = 0x2000 },
1447 	{ .name = "VCC",	.value = 0x4000 },
1448 	{ }
1449 };
1450 
1451 static void
1452 ptp_ocp_sma_init(struct ptp_ocp *bp)
1453 {
1454 	return bp->sma_op->init(bp);
1455 }
1456 
1457 static u32
1458 ptp_ocp_sma_get(struct ptp_ocp *bp, int sma_nr)
1459 {
1460 	return bp->sma_op->get(bp, sma_nr);
1461 }
1462 
1463 static int
1464 ptp_ocp_sma_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
1465 {
1466 	return bp->sma_op->set_inputs(bp, sma_nr, val);
1467 }
1468 
1469 static int
1470 ptp_ocp_sma_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
1471 {
1472 	return bp->sma_op->set_output(bp, sma_nr, val);
1473 }
1474 
1475 static const char *
1476 ptp_ocp_select_name_from_val(const struct ocp_selector *tbl, int val)
1477 {
1478 	int i;
1479 
1480 	for (i = 0; tbl[i].name; i++)
1481 		if (tbl[i].value == val)
1482 			return tbl[i].name;
1483 	return NULL;
1484 }
1485 
1486 static int
1487 ptp_ocp_select_val_from_name(const struct ocp_selector *tbl, const char *name)
1488 {
1489 	const char *select;
1490 	int i;
1491 
1492 	for (i = 0; tbl[i].name; i++) {
1493 		select = tbl[i].name;
1494 		if (!strncasecmp(name, select, strlen(select)))
1495 			return tbl[i].value;
1496 	}
1497 	return -EINVAL;
1498 }
1499 
1500 static ssize_t
1501 ptp_ocp_select_table_show(const struct ocp_selector *tbl, char *buf)
1502 {
1503 	ssize_t count;
1504 	int i;
1505 
1506 	count = 0;
1507 	for (i = 0; tbl[i].name; i++)
1508 		count += sysfs_emit_at(buf, count, "%s ", tbl[i].name);
1509 	if (count)
1510 		count--;
1511 	count += sysfs_emit_at(buf, count, "\n");
1512 	return count;
1513 }
1514 
1515 static int
1516 __ptp_ocp_gettime_locked(struct ptp_ocp *bp, struct timespec64 *ts,
1517 			 struct ptp_system_timestamp *sts)
1518 {
1519 	u32 ctrl, time_sec, time_ns;
1520 	int i;
1521 
1522 	ptp_read_system_prets(sts);
1523 
1524 	ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
1525 	iowrite32(ctrl, &bp->reg->ctrl);
1526 
1527 	for (i = 0; i < 100; i++) {
1528 		ctrl = ioread32(&bp->reg->ctrl);
1529 		if (ctrl & OCP_CTRL_READ_TIME_DONE)
1530 			break;
1531 	}
1532 	ptp_read_system_postts(sts);
1533 
1534 	if (sts && bp->ts_window_adjust)
1535 		sts->post_sts.systime -= bp->ts_window_adjust;
1536 
1537 	time_ns = ioread32(&bp->reg->time_ns);
1538 	time_sec = ioread32(&bp->reg->time_sec);
1539 
1540 	ts->tv_sec = time_sec;
1541 	ts->tv_nsec = time_ns;
1542 
1543 	return ctrl & OCP_CTRL_READ_TIME_DONE ? 0 : -ETIMEDOUT;
1544 }
1545 
1546 static int
1547 ptp_ocp_gettimex(struct ptp_clock_info *ptp_info, struct timespec64 *ts,
1548 		 struct ptp_system_timestamp *sts)
1549 {
1550 	struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1551 	unsigned long flags;
1552 	int err;
1553 
1554 	spin_lock_irqsave(&bp->lock, flags);
1555 	err = __ptp_ocp_gettime_locked(bp, ts, sts);
1556 	spin_unlock_irqrestore(&bp->lock, flags);
1557 
1558 	return err;
1559 }
1560 
1561 static void
1562 __ptp_ocp_settime_locked(struct ptp_ocp *bp, const struct timespec64 *ts)
1563 {
1564 	u32 ctrl, time_sec, time_ns;
1565 	u32 select;
1566 
1567 	time_ns = ts->tv_nsec;
1568 	time_sec = ts->tv_sec;
1569 
1570 	select = ioread32(&bp->reg->select);
1571 	iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1572 
1573 	iowrite32(time_ns, &bp->reg->adjust_ns);
1574 	iowrite32(time_sec, &bp->reg->adjust_sec);
1575 
1576 	ctrl = OCP_CTRL_ADJUST_TIME | OCP_CTRL_ENABLE;
1577 	iowrite32(ctrl, &bp->reg->ctrl);
1578 
1579 	/* restore clock selection */
1580 	iowrite32(select >> 16, &bp->reg->select);
1581 }
1582 
1583 static int
1584 ptp_ocp_settime(struct ptp_clock_info *ptp_info, const struct timespec64 *ts)
1585 {
1586 	struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1587 	unsigned long flags;
1588 
1589 	spin_lock_irqsave(&bp->lock, flags);
1590 	__ptp_ocp_settime_locked(bp, ts);
1591 	spin_unlock_irqrestore(&bp->lock, flags);
1592 
1593 	return 0;
1594 }
1595 
1596 static void
1597 __ptp_ocp_adjtime_locked(struct ptp_ocp *bp, u32 adj_val)
1598 {
1599 	u32 select, ctrl;
1600 
1601 	select = ioread32(&bp->reg->select);
1602 	iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1603 
1604 	iowrite32(adj_val, &bp->reg->offset_ns);
1605 	iowrite32(NSEC_PER_SEC, &bp->reg->offset_window_ns);
1606 
1607 	ctrl = OCP_CTRL_ADJUST_OFFSET | OCP_CTRL_ENABLE;
1608 	iowrite32(ctrl, &bp->reg->ctrl);
1609 
1610 	/* restore clock selection */
1611 	iowrite32(select >> 16, &bp->reg->select);
1612 }
1613 
1614 static void
1615 ptp_ocp_adjtime_coarse(struct ptp_ocp *bp, s64 delta_ns)
1616 {
1617 	struct timespec64 ts;
1618 	unsigned long flags;
1619 	int err;
1620 
1621 	spin_lock_irqsave(&bp->lock, flags);
1622 	err = __ptp_ocp_gettime_locked(bp, &ts, NULL);
1623 	if (likely(!err)) {
1624 		set_normalized_timespec64(&ts, ts.tv_sec,
1625 					  ts.tv_nsec + delta_ns);
1626 		__ptp_ocp_settime_locked(bp, &ts);
1627 	}
1628 	spin_unlock_irqrestore(&bp->lock, flags);
1629 }
1630 
1631 static int
1632 ptp_ocp_adjtime(struct ptp_clock_info *ptp_info, s64 delta_ns)
1633 {
1634 	struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1635 	unsigned long flags;
1636 	u32 adj_ns, sign;
1637 
1638 	if (delta_ns > NSEC_PER_SEC || -delta_ns > NSEC_PER_SEC) {
1639 		ptp_ocp_adjtime_coarse(bp, delta_ns);
1640 		return 0;
1641 	}
1642 
1643 	sign = delta_ns < 0 ? BIT(31) : 0;
1644 	adj_ns = sign ? -delta_ns : delta_ns;
1645 
1646 	spin_lock_irqsave(&bp->lock, flags);
1647 	__ptp_ocp_adjtime_locked(bp, sign | adj_ns);
1648 	spin_unlock_irqrestore(&bp->lock, flags);
1649 
1650 	return 0;
1651 }
1652 
1653 static int
1654 ptp_ocp_null_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm)
1655 {
1656 	if (scaled_ppm == 0)
1657 		return 0;
1658 
1659 	return -EOPNOTSUPP;
1660 }
1661 
1662 static s32
1663 ptp_ocp_null_getmaxphase(struct ptp_clock_info *ptp_info)
1664 {
1665 	return 0;
1666 }
1667 
1668 static int
1669 ptp_ocp_null_adjphase(struct ptp_clock_info *ptp_info, s32 phase_ns)
1670 {
1671 	return -EOPNOTSUPP;
1672 }
1673 
1674 static int
1675 ptp_ocp_enable(struct ptp_clock_info *ptp_info, struct ptp_clock_request *rq,
1676 	       int on)
1677 {
1678 	struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1679 	struct ptp_ocp_ext_src *ext = NULL;
1680 	u32 req;
1681 	int err;
1682 
1683 	switch (rq->type) {
1684 	case PTP_CLK_REQ_EXTTS:
1685 		req = OCP_REQ_TIMESTAMP;
1686 		switch (rq->extts.index) {
1687 		case 0:
1688 			ext = bp->ts0;
1689 			break;
1690 		case 1:
1691 			ext = bp->ts1;
1692 			break;
1693 		case 2:
1694 			ext = bp->ts2;
1695 			break;
1696 		case 3:
1697 			ext = bp->ts3;
1698 			break;
1699 		case 4:
1700 			ext = bp->ts4;
1701 			break;
1702 		case 5:
1703 			ext = bp->pps;
1704 			break;
1705 		}
1706 		break;
1707 	case PTP_CLK_REQ_PPS:
1708 		req = OCP_REQ_PPS;
1709 		ext = bp->pps;
1710 		break;
1711 	case PTP_CLK_REQ_PEROUT:
1712 		switch (rq->perout.index) {
1713 		case 0:
1714 			/* This is a request for 1PPS on an output SMA.
1715 			 * Allow, but assume manual configuration.
1716 			 */
1717 			if (on && (rq->perout.period.sec != 1 ||
1718 				   rq->perout.period.nsec != 0))
1719 				return -EINVAL;
1720 			return 0;
1721 		case 1:
1722 		case 2:
1723 		case 3:
1724 		case 4:
1725 			req = rq->perout.index - 1;
1726 			ext = bp->signal_out[req];
1727 			err = ptp_ocp_signal_from_perout(bp, req, &rq->perout);
1728 			if (err)
1729 				return err;
1730 			break;
1731 		}
1732 		break;
1733 	default:
1734 		return -EOPNOTSUPP;
1735 	}
1736 
1737 	err = -ENXIO;
1738 	if (ext)
1739 		err = ext->info->enable(ext, req, on);
1740 
1741 	return err;
1742 }
1743 
1744 static int
1745 ptp_ocp_verify(struct ptp_clock_info *ptp_info, unsigned pin,
1746 	       enum ptp_pin_function func, unsigned chan)
1747 {
1748 	struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1749 	char buf[16];
1750 
1751 	switch (func) {
1752 	case PTP_PF_NONE:
1753 		snprintf(buf, sizeof(buf), "IN: None");
1754 		break;
1755 	case PTP_PF_EXTTS:
1756 		/* Allow timestamps, but require sysfs configuration. */
1757 		return 0;
1758 	case PTP_PF_PEROUT:
1759 		/* channel 0 is 1PPS from PHC.
1760 		 * channels 1..4 are the frequency generators.
1761 		 */
1762 		if (chan)
1763 			snprintf(buf, sizeof(buf), "OUT: GEN%d", chan);
1764 		else
1765 			snprintf(buf, sizeof(buf), "OUT: PHC");
1766 		break;
1767 	default:
1768 		return -EOPNOTSUPP;
1769 	}
1770 
1771 	return ptp_ocp_sma_store(bp, buf, pin + 1);
1772 }
1773 
1774 static const struct ptp_clock_info ptp_ocp_clock_info = {
1775 	.owner		= THIS_MODULE,
1776 	.name		= KBUILD_MODNAME,
1777 	.max_adj	= 100000000,
1778 	.gettimex64	= ptp_ocp_gettimex,
1779 	.settime64	= ptp_ocp_settime,
1780 	.adjtime	= ptp_ocp_adjtime,
1781 	.adjfine	= ptp_ocp_null_adjfine,
1782 	.adjphase	= ptp_ocp_null_adjphase,
1783 	.getmaxphase	= ptp_ocp_null_getmaxphase,
1784 	.enable		= ptp_ocp_enable,
1785 	.verify		= ptp_ocp_verify,
1786 	.pps		= true,
1787 	.n_ext_ts	= 6,
1788 	.n_per_out	= 5,
1789 	.supported_extts_flags = PTP_STRICT_FLAGS | PTP_RISING_EDGE,
1790 	.supported_perout_flags = PTP_PEROUT_DUTY_CYCLE | PTP_PEROUT_PHASE,
1791 };
1792 
1793 static void
1794 __ptp_ocp_clear_drift_locked(struct ptp_ocp *bp)
1795 {
1796 	u32 ctrl, select;
1797 
1798 	select = ioread32(&bp->reg->select);
1799 	iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1800 
1801 	iowrite32(0, &bp->reg->drift_ns);
1802 
1803 	ctrl = OCP_CTRL_ADJUST_DRIFT | OCP_CTRL_ENABLE;
1804 	iowrite32(ctrl, &bp->reg->ctrl);
1805 
1806 	/* restore clock selection */
1807 	iowrite32(select >> 16, &bp->reg->select);
1808 }
1809 
1810 static void
1811 ptp_ocp_utc_distribute(struct ptp_ocp *bp, u32 val)
1812 {
1813 	unsigned long flags;
1814 
1815 	spin_lock_irqsave(&bp->lock, flags);
1816 
1817 	bp->utc_tai_offset = val;
1818 
1819 	if (bp->irig_out)
1820 		iowrite32(val, &bp->irig_out->adj_sec);
1821 	if (bp->dcf_out)
1822 		iowrite32(val, &bp->dcf_out->adj_sec);
1823 	if (bp->nmea_out)
1824 		iowrite32(val, &bp->nmea_out->adj_sec);
1825 
1826 	spin_unlock_irqrestore(&bp->lock, flags);
1827 }
1828 
1829 static void
1830 ptp_ocp_watchdog(struct timer_list *t)
1831 {
1832 	struct ptp_ocp *bp = timer_container_of(bp, t, watchdog);
1833 	unsigned long flags;
1834 	u32 status, utc_offset;
1835 
1836 	status = ioread32(&bp->pps_to_clk->status);
1837 
1838 	if (status & PPS_STATUS_SUPERV_ERR) {
1839 		iowrite32(status, &bp->pps_to_clk->status);
1840 		if (!bp->gnss_lost) {
1841 			spin_lock_irqsave(&bp->lock, flags);
1842 			__ptp_ocp_clear_drift_locked(bp);
1843 			spin_unlock_irqrestore(&bp->lock, flags);
1844 			bp->gnss_lost = ktime_get_real_seconds();
1845 		}
1846 
1847 	} else if (bp->gnss_lost) {
1848 		bp->gnss_lost = 0;
1849 	}
1850 
1851 	/* if GNSS provides correct data we can rely on
1852 	 * it to get leap second information
1853 	 */
1854 	if (bp->tod) {
1855 		status = ioread32(&bp->tod->utc_status);
1856 		utc_offset = status & TOD_STATUS_UTC_MASK;
1857 		if (status & TOD_STATUS_UTC_VALID &&
1858 		    utc_offset != bp->utc_tai_offset)
1859 			ptp_ocp_utc_distribute(bp, utc_offset);
1860 	}
1861 
1862 	mod_timer(&bp->watchdog, jiffies + HZ);
1863 }
1864 
1865 static void
1866 ptp_ocp_estimate_pci_timing(struct ptp_ocp *bp)
1867 {
1868 	ktime_t start, end, delay = KTIME_MAX;
1869 	u32 ctrl;
1870 	int i;
1871 
1872 	for (i = 0; i < 3; i++) {
1873 		ctrl = ioread32(&bp->reg->ctrl);
1874 		ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
1875 
1876 		iowrite32(ctrl, &bp->reg->ctrl);
1877 
1878 		start = ktime_get_raw_ns();
1879 
1880 		ctrl = ioread32(&bp->reg->ctrl);
1881 
1882 		end = ktime_get_raw_ns();
1883 
1884 		delay = min(delay, end - start);
1885 	}
1886 	bp->ts_window_adjust = (delay >> 5) * 3;
1887 }
1888 
1889 static int
1890 ptp_ocp_init_clock(struct ptp_ocp *bp, struct ptp_ocp_servo_conf *servo_conf)
1891 {
1892 	struct timespec64 ts;
1893 	u32 ctrl;
1894 
1895 	ctrl = OCP_CTRL_ENABLE;
1896 	iowrite32(ctrl, &bp->reg->ctrl);
1897 
1898 	/* servo configuration */
1899 	iowrite32(servo_conf->servo_offset_p, &bp->reg->servo_offset_p);
1900 	iowrite32(servo_conf->servo_offset_i, &bp->reg->servo_offset_i);
1901 	iowrite32(servo_conf->servo_drift_p, &bp->reg->servo_drift_p);
1902 	iowrite32(servo_conf->servo_drift_p, &bp->reg->servo_drift_i);
1903 
1904 	/* latch servo values */
1905 	ctrl |= OCP_CTRL_ADJUST_SERVO;
1906 	iowrite32(ctrl, &bp->reg->ctrl);
1907 
1908 	if ((ioread32(&bp->reg->ctrl) & OCP_CTRL_ENABLE) == 0) {
1909 		dev_err(&bp->pdev->dev, "clock not enabled\n");
1910 		return -ENODEV;
1911 	}
1912 
1913 	ptp_ocp_estimate_pci_timing(bp);
1914 
1915 	bp->sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC;
1916 	if (!bp->sync) {
1917 		ktime_get_clocktai_ts64(&ts);
1918 		ptp_ocp_settime(&bp->ptp_info, &ts);
1919 	}
1920 
1921 	/* If there is a clock supervisor, then enable the watchdog */
1922 	if (bp->pps_to_clk) {
1923 		timer_setup(&bp->watchdog, ptp_ocp_watchdog, 0);
1924 		mod_timer(&bp->watchdog, jiffies + HZ);
1925 	}
1926 
1927 	return 0;
1928 }
1929 
1930 static void
1931 ptp_ocp_tod_init(struct ptp_ocp *bp)
1932 {
1933 	u32 ctrl, reg;
1934 
1935 	ctrl = ioread32(&bp->tod->ctrl);
1936 	ctrl |= TOD_CTRL_PROTOCOL | TOD_CTRL_ENABLE;
1937 	ctrl &= ~(TOD_CTRL_DISABLE_FMT_A | TOD_CTRL_DISABLE_FMT_B);
1938 	iowrite32(ctrl, &bp->tod->ctrl);
1939 
1940 	reg = ioread32(&bp->tod->utc_status);
1941 	if (reg & TOD_STATUS_UTC_VALID)
1942 		ptp_ocp_utc_distribute(bp, reg & TOD_STATUS_UTC_MASK);
1943 }
1944 
1945 static const char *
1946 ptp_ocp_tod_proto_name(const int idx)
1947 {
1948 	static const char * const proto_name[] = {
1949 		"NMEA", "NMEA_ZDA", "NMEA_RMC", "NMEA_none",
1950 		"UBX", "UBX_UTC", "UBX_LS", "UBX_none"
1951 	};
1952 	return proto_name[idx];
1953 }
1954 
1955 static const char *
1956 ptp_ocp_tod_gnss_name(int idx)
1957 {
1958 	static const char * const gnss_name[] = {
1959 		"ALL", "COMBINED", "GPS", "GLONASS", "GALILEO", "BEIDOU",
1960 		"Unknown"
1961 	};
1962 	if (idx >= ARRAY_SIZE(gnss_name))
1963 		idx = ARRAY_SIZE(gnss_name) - 1;
1964 	return gnss_name[idx];
1965 }
1966 
1967 static const char *
1968 ptp_ocp_tty_port_name(int idx)
1969 {
1970 	static const char * const tty_name[] = {
1971 		"GNSS", "GNSS2", "MAC", "NMEA"
1972 	};
1973 	return tty_name[idx];
1974 }
1975 
1976 struct ptp_ocp_nvmem_match_info {
1977 	struct ptp_ocp *bp;
1978 	const void * const tag;
1979 };
1980 
1981 static int
1982 ptp_ocp_nvmem_match(struct device *dev, const void *data)
1983 {
1984 	const struct ptp_ocp_nvmem_match_info *info = data;
1985 
1986 	dev = dev->parent;
1987 	if (!i2c_verify_client(dev) || info->tag != dev->platform_data)
1988 		return 0;
1989 
1990 	while ((dev = dev->parent))
1991 		if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
1992 			return info->bp == dev_get_drvdata(dev);
1993 	return 0;
1994 }
1995 
1996 static inline struct nvmem_device *
1997 ptp_ocp_nvmem_device_get(struct ptp_ocp *bp, const void * const tag)
1998 {
1999 	struct ptp_ocp_nvmem_match_info info = { .bp = bp, .tag = tag };
2000 
2001 	return nvmem_device_find(&info, ptp_ocp_nvmem_match);
2002 }
2003 
2004 static inline void
2005 ptp_ocp_nvmem_device_put(struct nvmem_device **nvmemp)
2006 {
2007 	if (!IS_ERR_OR_NULL(*nvmemp))
2008 		nvmem_device_put(*nvmemp);
2009 	*nvmemp = NULL;
2010 }
2011 
2012 static void
2013 ptp_ocp_read_eeprom(struct ptp_ocp *bp)
2014 {
2015 	const struct ptp_ocp_eeprom_map *map;
2016 	struct nvmem_device *nvmem;
2017 	const void *tag;
2018 	int ret;
2019 
2020 	if (!bp->i2c_ctrl)
2021 		return;
2022 
2023 	tag = NULL;
2024 	nvmem = NULL;
2025 
2026 	for (map = bp->eeprom_map; map->len; map++) {
2027 		if (map->tag != tag) {
2028 			tag = map->tag;
2029 			ptp_ocp_nvmem_device_put(&nvmem);
2030 		}
2031 		if (!nvmem) {
2032 			nvmem = ptp_ocp_nvmem_device_get(bp, tag);
2033 			if (IS_ERR(nvmem)) {
2034 				ret = PTR_ERR(nvmem);
2035 				goto fail;
2036 			}
2037 		}
2038 		ret = nvmem_device_read(nvmem, map->off, map->len,
2039 					BP_MAP_ENTRY_ADDR(bp, map));
2040 		if (ret != map->len)
2041 			goto fail;
2042 	}
2043 
2044 	bp->has_eeprom_data = true;
2045 
2046 out:
2047 	ptp_ocp_nvmem_device_put(&nvmem);
2048 	return;
2049 
2050 fail:
2051 	dev_err(&bp->pdev->dev, "could not read eeprom: %d\n", ret);
2052 	goto out;
2053 }
2054 
2055 static struct device *
2056 ptp_ocp_find_flash(struct ptp_ocp *bp)
2057 {
2058 	struct device *dev, *last;
2059 
2060 	last = NULL;
2061 	dev = &bp->spi_flash->dev;
2062 
2063 	while ((dev = device_find_any_child(dev))) {
2064 		if (!strcmp("mtd", dev_bus_name(dev)))
2065 			break;
2066 		put_device(last);
2067 		last = dev;
2068 	}
2069 	put_device(last);
2070 
2071 	return dev;
2072 }
2073 
2074 static int
2075 ptp_ocp_devlink_fw_image(struct devlink *devlink, const struct firmware *fw,
2076 			 const u8 **data, size_t *size)
2077 {
2078 	struct ptp_ocp *bp = devlink_priv(devlink);
2079 	const struct ptp_ocp_firmware_header *hdr;
2080 	size_t offset, length;
2081 	u16 crc;
2082 
2083 	hdr = (const struct ptp_ocp_firmware_header *)fw->data;
2084 	if (memcmp(hdr->magic, OCP_FIRMWARE_MAGIC_HEADER, 4)) {
2085 		devlink_flash_update_status_notify(devlink,
2086 			"No firmware header found, cancel firmware upgrade",
2087 			NULL, 0, 0);
2088 		return -EINVAL;
2089 	}
2090 
2091 	if (be16_to_cpu(hdr->pci_vendor_id) != bp->pdev->vendor ||
2092 	    be16_to_cpu(hdr->pci_device_id) != bp->pdev->device) {
2093 		devlink_flash_update_status_notify(devlink,
2094 			"Firmware image compatibility check failed",
2095 			NULL, 0, 0);
2096 		return -EINVAL;
2097 	}
2098 
2099 	offset = sizeof(*hdr);
2100 	length = be32_to_cpu(hdr->image_size);
2101 	if (length != (fw->size - offset)) {
2102 		devlink_flash_update_status_notify(devlink,
2103 			"Firmware image size check failed",
2104 			NULL, 0, 0);
2105 		return -EINVAL;
2106 	}
2107 
2108 	crc = crc16(0xffff, &fw->data[offset], length);
2109 	if (be16_to_cpu(hdr->crc) != crc) {
2110 		devlink_flash_update_status_notify(devlink,
2111 			"Firmware image CRC check failed",
2112 			NULL, 0, 0);
2113 		return -EINVAL;
2114 	}
2115 
2116 	*data = &fw->data[offset];
2117 	*size = length;
2118 
2119 	return 0;
2120 }
2121 
2122 static int
2123 ptp_ocp_devlink_flash(struct devlink *devlink, struct device *dev,
2124 		      const struct firmware *fw)
2125 {
2126 	struct mtd_info *mtd = dev_get_drvdata(dev);
2127 	struct ptp_ocp *bp = devlink_priv(devlink);
2128 	size_t off, len, size, resid, wrote;
2129 	struct erase_info erase;
2130 	size_t base, blksz;
2131 	const u8 *data;
2132 	int err;
2133 
2134 	err = ptp_ocp_devlink_fw_image(devlink, fw, &data, &size);
2135 	if (err)
2136 		goto out;
2137 
2138 	off = 0;
2139 	base = bp->flash_start;
2140 	blksz = 4096;
2141 	resid = size;
2142 
2143 	while (resid) {
2144 		devlink_flash_update_status_notify(devlink, "Flashing",
2145 						   NULL, off, size);
2146 
2147 		len = min_t(size_t, resid, blksz);
2148 		erase.addr = base + off;
2149 		erase.len = blksz;
2150 
2151 		err = mtd_erase(mtd, &erase);
2152 		if (err)
2153 			goto out;
2154 
2155 		err = mtd_write(mtd, base + off, len, &wrote, data + off);
2156 		if (err)
2157 			goto out;
2158 
2159 		off += blksz;
2160 		resid -= len;
2161 	}
2162 out:
2163 	return err;
2164 }
2165 
2166 static int
2167 ptp_ocp_devlink_flash_update(struct devlink *devlink,
2168 			     struct devlink_flash_update_params *params,
2169 			     struct netlink_ext_ack *extack)
2170 {
2171 	struct ptp_ocp *bp = devlink_priv(devlink);
2172 	struct device *dev;
2173 	const char *msg;
2174 	int err;
2175 
2176 	if (params->component) {
2177 		if (!bp->has_cpld ||
2178 		    strcmp(params->component, ADVA_CPLD_COMPONENT)) {
2179 			NL_SET_ERR_MSG_MOD(extack,
2180 					   "unsupported flash component");
2181 			return -EOPNOTSUPP;
2182 		}
2183 
2184 		err = adva_x1_cpld_flash(bp, devlink, params->fw, extack);
2185 		msg = err ? "Flash error" : "Flash complete";
2186 		devlink_flash_update_status_notify(devlink, msg,
2187 						   ADVA_CPLD_COMPONENT, 0, 0);
2188 		return err;
2189 	}
2190 
2191 	dev = ptp_ocp_find_flash(bp);
2192 	if (!dev) {
2193 		dev_err(&bp->pdev->dev, "Can't find Flash SPI adapter\n");
2194 		return -ENODEV;
2195 	}
2196 
2197 	devlink_flash_update_status_notify(devlink, "Preparing to flash",
2198 					   NULL, 0, 0);
2199 
2200 	err = ptp_ocp_devlink_flash(devlink, dev, params->fw);
2201 
2202 	msg = err ? "Flash error" : "Flash complete";
2203 	devlink_flash_update_status_notify(devlink, msg, NULL, 0, 0);
2204 
2205 	put_device(dev);
2206 	return err;
2207 }
2208 
2209 static int
2210 ptp_ocp_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req,
2211 			 struct netlink_ext_ack *extack)
2212 {
2213 	enum devlink_info_version_type ver_type =
2214 					DEVLINK_INFO_VERSION_TYPE_COMPONENT;
2215 	struct ptp_ocp *bp = devlink_priv(devlink);
2216 	const char *fw_image;
2217 	char buf[32];
2218 	int err;
2219 	u32 id;
2220 
2221 	fw_image = bp->fw_loader ? "loader" : "fw";
2222 	sprintf(buf, "%d.%d", bp->fw_tag, bp->fw_version);
2223 	err = devlink_info_version_running_put(req, fw_image, buf);
2224 	if (err)
2225 		return err;
2226 
2227 	if (bp->has_cpld) {
2228 		/* Read by the worker, not here: this command is unprivileged
2229 		 * and reading the ID claims the I2C bus.  0 means unread -
2230 		 * skip it rather than fail, devlink discards the whole reply
2231 		 * on error.
2232 		 */
2233 		id = READ_ONCE(bp->cpld_id);
2234 		if (id) {
2235 			sprintf(buf, "0x%08x", id);
2236 			err = devlink_info_version_fixed_put(req, "cpld.id",
2237 							     buf);
2238 			if (err)
2239 				return err;
2240 		}
2241 
2242 		/* The flashable component.  Naming it here is what lets
2243 		 * "devlink dev flash ... component fw.cpld" through, as the
2244 		 * core matches the name against the versions reported here,
2245 		 * so it is reported for every board that has the part and not
2246 		 * only once its USERCODE has been read: a part left holding a
2247 		 * bad image answers neither, and gating the component on the
2248 		 * read would make that state unrecoverable.
2249 		 */
2250 		if (smp_load_acquire(&bp->cpld_usercode_ok))
2251 			sprintf(buf, "0x%08x", READ_ONCE(bp->cpld_usercode));
2252 		else
2253 			strscpy(buf, "unknown", sizeof(buf));
2254 		err = devlink_info_version_running_put_ext(req, "fw.cpld", buf,
2255 							   ver_type);
2256 		if (err)
2257 			return err;
2258 	}
2259 
2260 	if (!bp->has_eeprom_data) {
2261 		ptp_ocp_read_eeprom(bp);
2262 		if (!bp->has_eeprom_data)
2263 			return 0;
2264 	}
2265 
2266 	sprintf(buf, "%pM", bp->serial);
2267 	err = devlink_info_serial_number_put(req, buf);
2268 	if (err)
2269 		return err;
2270 
2271 	snprintf(buf, sizeof(buf), "%.*s", OCP_BOARD_ID_LEN,
2272 		 (const char *)bp->board_id);
2273 	err = devlink_info_version_fixed_put(req,
2274 			DEVLINK_INFO_VERSION_GENERIC_BOARD_ID,
2275 			buf);
2276 	if (err)
2277 		return err;
2278 
2279 	return 0;
2280 }
2281 
2282 static const struct devlink_ops ptp_ocp_devlink_ops = {
2283 	.flash_update = ptp_ocp_devlink_flash_update,
2284 	.info_get = ptp_ocp_devlink_info_get,
2285 };
2286 
2287 static void __iomem *
2288 __ptp_ocp_get_mem(struct ptp_ocp *bp, resource_size_t start, int size)
2289 {
2290 	struct resource res = DEFINE_RES_MEM_NAMED(start, size, "ptp_ocp");
2291 
2292 	return devm_ioremap_resource(&bp->pdev->dev, &res);
2293 }
2294 
2295 static void __iomem *
2296 ptp_ocp_get_mem(struct ptp_ocp *bp, struct ocp_resource *r)
2297 {
2298 	resource_size_t start;
2299 
2300 	start = pci_resource_start(bp->pdev, 0) + r->offset;
2301 	return __ptp_ocp_get_mem(bp, start, r->size);
2302 }
2303 
2304 static int
2305 ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r)
2306 {
2307 	struct ptp_ocp_flash_info *info;
2308 	struct pci_dev *pdev = bp->pdev;
2309 	struct platform_device *p;
2310 	struct resource res[2];
2311 	resource_size_t start;
2312 	int id;
2313 
2314 	start = pci_resource_start(pdev, 0) + r->offset;
2315 	res[0] = DEFINE_RES_MEM(start, r->size);
2316 	res[1] = DEFINE_RES_IRQ(pci_irq_vector(pdev, r->irq_vec));
2317 
2318 	info = r->extra;
2319 	id = pci_dev_id(pdev) << 1;
2320 	id += info->pci_offset;
2321 
2322 	p = platform_device_register_resndata(&pdev->dev, info->name, id,
2323 					      res, ARRAY_SIZE(res), info->data,
2324 					      info->data_size);
2325 	if (IS_ERR(p))
2326 		return PTR_ERR(p);
2327 
2328 	bp_assign_entry(bp, r, p);
2329 
2330 	return 0;
2331 }
2332 
2333 static struct platform_device *
2334 ptp_ocp_i2c_bus(struct pci_dev *pdev, struct ocp_resource *r, int id)
2335 {
2336 	struct ptp_ocp_i2c_info *info;
2337 	struct resource res[2];
2338 	resource_size_t start;
2339 
2340 	info = r->extra;
2341 	start = pci_resource_start(pdev, 0) + r->offset;
2342 	res[0] = DEFINE_RES_MEM(start, r->size);
2343 	res[1] = DEFINE_RES_IRQ(pci_irq_vector(pdev, r->irq_vec));
2344 
2345 	return platform_device_register_resndata(&pdev->dev, info->name,
2346 						 id, res, ARRAY_SIZE(res),
2347 						 info->data, info->data_size);
2348 }
2349 
2350 static int
2351 ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r)
2352 {
2353 	struct pci_dev *pdev = bp->pdev;
2354 	struct ptp_ocp_i2c_info *info;
2355 	struct platform_device *p;
2356 	struct clk_hw *clk;
2357 	char buf[32];
2358 	int id;
2359 
2360 	info = r->extra;
2361 	id = pci_dev_id(bp->pdev);
2362 
2363 	sprintf(buf, "AXI.%d", id);
2364 	clk = clk_hw_register_fixed_rate(&pdev->dev, buf, NULL, 0,
2365 					 info->fixed_rate);
2366 	if (IS_ERR(clk))
2367 		return PTR_ERR(clk);
2368 	bp->i2c_clk = clk;
2369 
2370 	sprintf(buf, "%s.%d", info->name, id);
2371 	devm_clk_hw_register_clkdev(&pdev->dev, clk, NULL, buf);
2372 	p = ptp_ocp_i2c_bus(bp->pdev, r, id);
2373 	if (IS_ERR(p))
2374 		return PTR_ERR(p);
2375 
2376 	bp_assign_entry(bp, r, p);
2377 
2378 	return 0;
2379 }
2380 
2381 /* The expectation is that this is triggered only on error. */
2382 static irqreturn_t
2383 ptp_ocp_signal_irq(int irq, void *priv)
2384 {
2385 	struct ptp_ocp_ext_src *ext = priv;
2386 	struct signal_reg __iomem *reg = ext->mem;
2387 	struct ptp_ocp *bp = ext->bp;
2388 	u32 enable, status;
2389 	int gen;
2390 
2391 	gen = ext->info->index - 1;
2392 
2393 	enable = ioread32(&reg->enable);
2394 	status = ioread32(&reg->status);
2395 
2396 	/* disable generator on error */
2397 	if (status || !enable) {
2398 		iowrite32(0, &reg->intr_mask);
2399 		iowrite32(0, &reg->enable);
2400 		bp->signal[gen].running = false;
2401 	}
2402 
2403 	iowrite32(0, &reg->intr);	/* ack interrupt */
2404 
2405 	return IRQ_HANDLED;
2406 }
2407 
2408 static int
2409 ptp_ocp_signal_set(struct ptp_ocp *bp, int gen, struct ptp_ocp_signal *s)
2410 {
2411 	struct ptp_system_timestamp sts;
2412 	struct timespec64 ts;
2413 	ktime_t start_ns;
2414 	int err;
2415 
2416 	if (!s->period)
2417 		return 0;
2418 
2419 	if (!s->pulse)
2420 		s->pulse = ktime_divns(s->period * s->duty, 100);
2421 
2422 	err = ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts);
2423 	if (err)
2424 		return err;
2425 
2426 	start_ns = ktime_set(ts.tv_sec, ts.tv_nsec) + NSEC_PER_MSEC;
2427 	if (!s->start) {
2428 		/* roundup() does not work on 32-bit systems */
2429 		s->start = DIV64_U64_ROUND_UP(start_ns, s->period);
2430 		s->start *= s->period;
2431 		s->start = ktime_add(s->start, s->phase);
2432 	}
2433 
2434 	if (s->duty < 1 || s->duty > 99)
2435 		return -EINVAL;
2436 
2437 	if (s->pulse < 1 || s->pulse > s->period)
2438 		return -EINVAL;
2439 
2440 	if (s->start < start_ns)
2441 		return -EINVAL;
2442 
2443 	bp->signal[gen] = *s;
2444 
2445 	return 0;
2446 }
2447 
2448 static int
2449 ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,
2450 			   struct ptp_perout_request *req)
2451 {
2452 	struct ptp_ocp_signal s = { };
2453 
2454 	s.polarity = bp->signal[gen].polarity;
2455 	s.period = ktime_set(req->period.sec, req->period.nsec);
2456 	if (!s.period)
2457 		return 0;
2458 
2459 	if (req->flags & PTP_PEROUT_DUTY_CYCLE) {
2460 		s.pulse = ktime_set(req->on.sec, req->on.nsec);
2461 		s.duty = ktime_divns(s.pulse * 100, s.period);
2462 	}
2463 
2464 	if (req->flags & PTP_PEROUT_PHASE)
2465 		s.phase = ktime_set(req->phase.sec, req->phase.nsec);
2466 	else
2467 		s.start = ktime_set(req->start.sec, req->start.nsec);
2468 
2469 	return ptp_ocp_signal_set(bp, gen, &s);
2470 }
2471 
2472 static int
2473 ptp_ocp_signal_enable(void *priv, u32 req, bool enable)
2474 {
2475 	struct ptp_ocp_ext_src *ext = priv;
2476 	struct signal_reg __iomem *reg = ext->mem;
2477 	struct ptp_ocp *bp = ext->bp;
2478 	struct timespec64 ts;
2479 	int gen;
2480 
2481 	gen = ext->info->index - 1;
2482 
2483 	iowrite32(0, &reg->intr_mask);
2484 	iowrite32(0, &reg->enable);
2485 	bp->signal[gen].running = false;
2486 	if (!enable)
2487 		return 0;
2488 
2489 	ts = ktime_to_timespec64(bp->signal[gen].start);
2490 	iowrite32(ts.tv_sec, &reg->start_sec);
2491 	iowrite32(ts.tv_nsec, &reg->start_ns);
2492 
2493 	ts = ktime_to_timespec64(bp->signal[gen].period);
2494 	iowrite32(ts.tv_sec, &reg->period_sec);
2495 	iowrite32(ts.tv_nsec, &reg->period_ns);
2496 
2497 	ts = ktime_to_timespec64(bp->signal[gen].pulse);
2498 	iowrite32(ts.tv_sec, &reg->pulse_sec);
2499 	iowrite32(ts.tv_nsec, &reg->pulse_ns);
2500 
2501 	iowrite32(bp->signal[gen].polarity, &reg->polarity);
2502 	iowrite32(0, &reg->repeat_count);
2503 
2504 	iowrite32(0, &reg->intr);		/* clear interrupt state */
2505 	iowrite32(1, &reg->intr_mask);		/* enable interrupt */
2506 	iowrite32(3, &reg->enable);		/* valid & enable */
2507 
2508 	bp->signal[gen].running = true;
2509 
2510 	return 0;
2511 }
2512 
2513 static irqreturn_t
2514 ptp_ocp_ts_irq(int irq, void *priv)
2515 {
2516 	struct ptp_ocp_ext_src *ext = priv;
2517 	struct ts_reg __iomem *reg = ext->mem;
2518 	struct ptp_clock_event ev;
2519 	u32 sec, nsec;
2520 
2521 	if (ext == ext->bp->pps) {
2522 		if (ext->bp->pps_req_map & OCP_REQ_PPS) {
2523 			ev.type = PTP_CLOCK_PPS;
2524 			ptp_clock_event(ext->bp->ptp, &ev);
2525 		}
2526 
2527 		if ((ext->bp->pps_req_map & ~OCP_REQ_PPS) == 0)
2528 			goto out;
2529 	}
2530 
2531 	/* XXX should fix API - this converts s/ns -> ts -> s/ns */
2532 	sec = ioread32(&reg->time_sec);
2533 	nsec = ioread32(&reg->time_ns);
2534 
2535 	ev.type = PTP_CLOCK_EXTTS;
2536 	ev.index = ext->info->index;
2537 	ev.timestamp = sec * NSEC_PER_SEC + nsec;
2538 
2539 	ptp_clock_event(ext->bp->ptp, &ev);
2540 
2541 out:
2542 	iowrite32(1, &reg->intr);	/* write 1 to ack */
2543 
2544 	return IRQ_HANDLED;
2545 }
2546 
2547 static int
2548 ptp_ocp_ts_enable(void *priv, u32 req, bool enable)
2549 {
2550 	struct ptp_ocp_ext_src *ext = priv;
2551 	struct ts_reg __iomem *reg = ext->mem;
2552 	struct ptp_ocp *bp = ext->bp;
2553 
2554 	if (ext == bp->pps) {
2555 		u32 old_map = bp->pps_req_map;
2556 
2557 		if (enable)
2558 			bp->pps_req_map |= req;
2559 		else
2560 			bp->pps_req_map &= ~req;
2561 
2562 		/* if no state change, just return */
2563 		if ((!!old_map ^ !!bp->pps_req_map) == 0)
2564 			return 0;
2565 	}
2566 
2567 	if (enable) {
2568 		iowrite32(1, &reg->enable);
2569 		iowrite32(1, &reg->intr_mask);
2570 		iowrite32(1, &reg->intr);
2571 	} else {
2572 		int irq_vec = pci_irq_vector(bp->pdev, ext->irq_vec);
2573 
2574 		iowrite32(0, &reg->intr_mask);
2575 		iowrite32(0, &reg->enable);
2576 		ioread32(&reg->intr_mask);
2577 		if (irq_vec > 0)
2578 			synchronize_irq(irq_vec);
2579 	}
2580 
2581 	return 0;
2582 }
2583 
2584 static void
2585 ptp_ocp_unregister_ext(struct ptp_ocp_ext_src *ext)
2586 {
2587 	if (!ext)
2588 		return;
2589 
2590 	ext->info->enable(ext, ~0, false);
2591 	pci_free_irq(ext->bp->pdev, ext->irq_vec, ext);
2592 	kfree(ext);
2593 }
2594 
2595 static int
2596 ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r)
2597 {
2598 	struct pci_dev *pdev = bp->pdev;
2599 	struct ptp_ocp_ext_src *ext;
2600 	int err;
2601 
2602 	ext = kzalloc_obj(*ext);
2603 	if (!ext)
2604 		return -ENOMEM;
2605 
2606 	ext->mem = ptp_ocp_get_mem(bp, r);
2607 	if (IS_ERR(ext->mem)) {
2608 		err = PTR_ERR(ext->mem);
2609 		goto out;
2610 	}
2611 
2612 	ext->bp = bp;
2613 	ext->info = r->extra;
2614 	ext->irq_vec = r->irq_vec;
2615 
2616 	err = pci_request_irq(pdev, r->irq_vec, ext->info->irq_fcn, NULL,
2617 			      ext, "ocp%d.%s", bp->id, r->name);
2618 	if (err) {
2619 		dev_err(&pdev->dev, "Could not get irq %d\n", r->irq_vec);
2620 		goto out;
2621 	}
2622 
2623 	bp_assign_entry(bp, r, ext);
2624 
2625 	return 0;
2626 
2627 out:
2628 	kfree(ext);
2629 	return err;
2630 }
2631 
2632 static int
2633 ptp_ocp_serial_line(struct ptp_ocp *bp, struct ocp_resource *r)
2634 {
2635 	struct pci_dev *pdev = bp->pdev;
2636 	struct uart_8250_port uart;
2637 
2638 	/* Setting UPF_IOREMAP and leaving port.membase unspecified lets
2639 	 * the serial port device claim and release the pci resource.
2640 	 */
2641 	memset(&uart, 0, sizeof(uart));
2642 	uart.port.dev = &pdev->dev;
2643 	uart.port.iotype = UPIO_MEM;
2644 	uart.port.regshift = 2;
2645 	uart.port.mapbase = pci_resource_start(pdev, 0) + r->offset;
2646 	uart.port.irq = pci_irq_vector(pdev, r->irq_vec);
2647 	uart.port.uartclk = 50000000;
2648 	uart.port.flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_NO_THRE_TEST;
2649 	uart.port.type = PORT_16550A;
2650 
2651 	return serial8250_register_8250_port(&uart);
2652 }
2653 
2654 static int
2655 ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r)
2656 {
2657 	struct ptp_ocp_serial_port *p = (struct ptp_ocp_serial_port *)r->extra;
2658 	struct ptp_ocp_serial_port port = {};
2659 
2660 	port.line = ptp_ocp_serial_line(bp, r);
2661 	if (port.line < 0)
2662 		return port.line;
2663 
2664 	if (p)
2665 		port.baud = p->baud;
2666 
2667 	bp_assign_entry(bp, r, port);
2668 
2669 	return 0;
2670 }
2671 
2672 static int
2673 ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r)
2674 {
2675 	void __iomem *mem;
2676 
2677 	mem = ptp_ocp_get_mem(bp, r);
2678 	if (IS_ERR(mem))
2679 		return PTR_ERR(mem);
2680 
2681 	bp_assign_entry(bp, r, mem);
2682 
2683 	return 0;
2684 }
2685 
2686 static void
2687 ptp_ocp_nmea_out_init(struct ptp_ocp *bp)
2688 {
2689 	if (!bp->nmea_out)
2690 		return;
2691 
2692 	iowrite32(0, &bp->nmea_out->ctrl);		/* disable */
2693 	iowrite32(7, &bp->nmea_out->uart_baud);		/* 115200 */
2694 	iowrite32(1, &bp->nmea_out->ctrl);		/* enable */
2695 }
2696 
2697 static void
2698 _ptp_ocp_signal_init(struct ptp_ocp_signal *s, struct signal_reg __iomem *reg)
2699 {
2700 	u32 val;
2701 
2702 	iowrite32(0, &reg->enable);		/* disable */
2703 
2704 	val = ioread32(&reg->polarity);
2705 	s->polarity = val ? true : false;
2706 	s->duty = 50;
2707 }
2708 
2709 static void
2710 ptp_ocp_signal_init(struct ptp_ocp *bp)
2711 {
2712 	int i;
2713 
2714 	for (i = 0; i < 4; i++)
2715 		if (bp->signal_out[i])
2716 			_ptp_ocp_signal_init(&bp->signal[i],
2717 					     bp->signal_out[i]->mem);
2718 }
2719 
2720 static void
2721 ptp_ocp_attr_group_del(struct ptp_ocp *bp)
2722 {
2723 	sysfs_remove_groups(&bp->dev.kobj, bp->attr_group);
2724 	kfree(bp->attr_group);
2725 }
2726 
2727 static int
2728 ptp_ocp_attr_group_add(struct ptp_ocp *bp,
2729 		       const struct ocp_attr_group *attr_tbl)
2730 {
2731 	int count, i;
2732 	int err;
2733 
2734 	count = 0;
2735 	for (i = 0; attr_tbl[i].cap; i++)
2736 		if (attr_tbl[i].cap & bp->fw_cap)
2737 			count++;
2738 
2739 	bp->attr_group = kzalloc_objs(*bp->attr_group, count + 1);
2740 	if (!bp->attr_group)
2741 		return -ENOMEM;
2742 
2743 	count = 0;
2744 	for (i = 0; attr_tbl[i].cap; i++)
2745 		if (attr_tbl[i].cap & bp->fw_cap)
2746 			bp->attr_group[count++] = attr_tbl[i].group;
2747 
2748 	err = sysfs_create_groups(&bp->dev.kobj, bp->attr_group);
2749 	if (err)
2750 		bp->attr_group[0] = NULL;
2751 
2752 	return err;
2753 }
2754 
2755 static void
2756 ptp_ocp_enable_fpga(u32 __iomem *reg, u32 bit, bool enable)
2757 {
2758 	u32 ctrl;
2759 	bool on;
2760 
2761 	ctrl = ioread32(reg);
2762 	on = ctrl & bit;
2763 	if (on ^ enable) {
2764 		ctrl &= ~bit;
2765 		ctrl |= enable ? bit : 0;
2766 		iowrite32(ctrl, reg);
2767 	}
2768 }
2769 
2770 static void
2771 ptp_ocp_irig_out(struct ptp_ocp *bp, bool enable)
2772 {
2773 	return ptp_ocp_enable_fpga(&bp->irig_out->ctrl,
2774 				   IRIG_M_CTRL_ENABLE, enable);
2775 }
2776 
2777 static void
2778 ptp_ocp_irig_in(struct ptp_ocp *bp, bool enable)
2779 {
2780 	return ptp_ocp_enable_fpga(&bp->irig_in->ctrl,
2781 				   IRIG_S_CTRL_ENABLE, enable);
2782 }
2783 
2784 static void
2785 ptp_ocp_dcf_out(struct ptp_ocp *bp, bool enable)
2786 {
2787 	return ptp_ocp_enable_fpga(&bp->dcf_out->ctrl,
2788 				   DCF_M_CTRL_ENABLE, enable);
2789 }
2790 
2791 static void
2792 ptp_ocp_dcf_in(struct ptp_ocp *bp, bool enable)
2793 {
2794 	return ptp_ocp_enable_fpga(&bp->dcf_in->ctrl,
2795 				   DCF_S_CTRL_ENABLE, enable);
2796 }
2797 
2798 static void
2799 __handle_signal_outputs(struct ptp_ocp *bp, u32 val)
2800 {
2801 	ptp_ocp_irig_out(bp, val & 0x00100010);
2802 	ptp_ocp_dcf_out(bp, val & 0x00200020);
2803 }
2804 
2805 static void
2806 __handle_signal_inputs(struct ptp_ocp *bp, u32 val)
2807 {
2808 	ptp_ocp_irig_in(bp, val & 0x00100010);
2809 	ptp_ocp_dcf_in(bp, val & 0x00200020);
2810 }
2811 
2812 static u32
2813 ptp_ocp_sma_fb_get(struct ptp_ocp *bp, int sma_nr)
2814 {
2815 	u32 __iomem *gpio;
2816 	u32 shift;
2817 
2818 	if (bp->sma[sma_nr - 1].fixed_fcn)
2819 		return (sma_nr - 1) & 1;
2820 
2821 	if (bp->sma[sma_nr - 1].mode == SMA_MODE_IN)
2822 		gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2823 	else
2824 		gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2825 	shift = sma_nr & 1 ? 0 : 16;
2826 
2827 	return (ioread32(gpio) >> shift) & 0xffff;
2828 }
2829 
2830 static int
2831 ptp_ocp_sma_fb_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
2832 {
2833 	u32 reg, mask, shift;
2834 	unsigned long flags;
2835 	u32 __iomem *gpio;
2836 
2837 	gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2838 	shift = sma_nr & 1 ? 0 : 16;
2839 
2840 	mask = 0xffff << (16 - shift);
2841 
2842 	spin_lock_irqsave(&bp->lock, flags);
2843 
2844 	reg = ioread32(gpio);
2845 	reg = (reg & mask) | (val << shift);
2846 
2847 	__handle_signal_outputs(bp, reg);
2848 
2849 	iowrite32(reg, gpio);
2850 
2851 	spin_unlock_irqrestore(&bp->lock, flags);
2852 
2853 	return 0;
2854 }
2855 
2856 static int
2857 ptp_ocp_sma_fb_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
2858 {
2859 	u32 reg, mask, shift;
2860 	unsigned long flags;
2861 	u32 __iomem *gpio;
2862 
2863 	gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2864 	shift = sma_nr & 1 ? 0 : 16;
2865 
2866 	mask = 0xffff << (16 - shift);
2867 
2868 	spin_lock_irqsave(&bp->lock, flags);
2869 
2870 	reg = ioread32(gpio);
2871 	reg = (reg & mask) | (val << shift);
2872 
2873 	__handle_signal_inputs(bp, reg);
2874 
2875 	iowrite32(reg, gpio);
2876 
2877 	spin_unlock_irqrestore(&bp->lock, flags);
2878 
2879 	return 0;
2880 }
2881 
2882 static void
2883 ptp_ocp_sma_fb_init(struct ptp_ocp *bp)
2884 {
2885 	struct dpll_pin_properties prop = {
2886 		.board_label = NULL,
2887 		.type = DPLL_PIN_TYPE_EXT,
2888 		.capabilities = DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE,
2889 		.freq_supported_num = ARRAY_SIZE(ptp_ocp_sma_freq),
2890 		.freq_supported = ptp_ocp_sma_freq,
2891 
2892 	};
2893 	u32 reg;
2894 	int i;
2895 
2896 	/* defaults */
2897 	for (i = 0; i < OCP_SMA_NUM; i++) {
2898 		bp->sma[i].default_fcn = i & 1;
2899 		bp->sma[i].dpll_prop = prop;
2900 		bp->sma[i].dpll_prop.board_label =
2901 			bp->ptp_info.pin_config[i].name;
2902 	}
2903 	bp->sma[0].mode = SMA_MODE_IN;
2904 	bp->sma[1].mode = SMA_MODE_IN;
2905 	bp->sma[2].mode = SMA_MODE_OUT;
2906 	bp->sma[3].mode = SMA_MODE_OUT;
2907 	/* If no SMA1 map, the pin functions and directions are fixed. */
2908 	if (!bp->sma_map1) {
2909 		for (i = 0; i < OCP_SMA_NUM; i++) {
2910 			bp->sma[i].fixed_fcn = true;
2911 			bp->sma[i].fixed_dir = true;
2912 			bp->sma[i].dpll_prop.capabilities &=
2913 				~DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;
2914 		}
2915 		return;
2916 	}
2917 
2918 	/* If SMA2 GPIO output map is all 1, it is not present.
2919 	 * This indicates the firmware has fixed direction SMA pins.
2920 	 */
2921 	reg = ioread32(&bp->sma_map2->gpio2);
2922 	if (reg == 0xffffffff) {
2923 		for (i = 0; i < OCP_SMA_NUM; i++)
2924 			bp->sma[i].fixed_dir = true;
2925 	} else {
2926 		reg = ioread32(&bp->sma_map1->gpio1);
2927 		bp->sma[0].mode = reg & BIT(15) ? SMA_MODE_IN : SMA_MODE_OUT;
2928 		bp->sma[1].mode = reg & BIT(31) ? SMA_MODE_IN : SMA_MODE_OUT;
2929 
2930 		reg = ioread32(&bp->sma_map1->gpio2);
2931 		bp->sma[2].mode = reg & BIT(15) ? SMA_MODE_OUT : SMA_MODE_IN;
2932 		bp->sma[3].mode = reg & BIT(31) ? SMA_MODE_OUT : SMA_MODE_IN;
2933 	}
2934 }
2935 
2936 static const struct ocp_sma_op ocp_fb_sma_op = {
2937 	.tbl		= { ptp_ocp_sma_in, ptp_ocp_sma_out },
2938 	.init		= ptp_ocp_sma_fb_init,
2939 	.get		= ptp_ocp_sma_fb_get,
2940 	.set_inputs	= ptp_ocp_sma_fb_set_inputs,
2941 	.set_output	= ptp_ocp_sma_fb_set_output,
2942 };
2943 
2944 static int
2945 ptp_ocp_sma_adva_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
2946 {
2947 	u32 reg, mask, shift;
2948 	unsigned long flags;
2949 	u32 __iomem *gpio;
2950 
2951 	gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2952 	shift = sma_nr & 1 ? 0 : 16;
2953 
2954 	mask = 0xffff << (16 - shift);
2955 
2956 	spin_lock_irqsave(&bp->lock, flags);
2957 
2958 	reg = ioread32(gpio);
2959 	reg = (reg & mask) | (val << shift);
2960 
2961 	iowrite32(reg, gpio);
2962 
2963 	spin_unlock_irqrestore(&bp->lock, flags);
2964 
2965 	return 0;
2966 }
2967 
2968 static int
2969 ptp_ocp_sma_adva_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
2970 {
2971 	u32 reg, mask, shift;
2972 	unsigned long flags;
2973 	u32 __iomem *gpio;
2974 
2975 	gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2976 	shift = sma_nr & 1 ? 0 : 16;
2977 
2978 	mask = 0xffff << (16 - shift);
2979 
2980 	spin_lock_irqsave(&bp->lock, flags);
2981 
2982 	reg = ioread32(gpio);
2983 	reg = (reg & mask) | (val << shift);
2984 
2985 	iowrite32(reg, gpio);
2986 
2987 	spin_unlock_irqrestore(&bp->lock, flags);
2988 
2989 	return 0;
2990 }
2991 
2992 static const struct ocp_sma_op ocp_adva_sma_op = {
2993 	.tbl		= { ptp_ocp_adva_sma_in, ptp_ocp_adva_sma_out },
2994 	.init		= ptp_ocp_sma_fb_init,
2995 	.get		= ptp_ocp_sma_fb_get,
2996 	.set_inputs	= ptp_ocp_sma_adva_set_inputs,
2997 	.set_output	= ptp_ocp_sma_adva_set_output,
2998 };
2999 
3000 static const struct ocp_sma_op ocp_adva_x1_sma_op = {
3001 	.tbl		= { ptp_ocp_adva_x1_sma_in, ptp_ocp_adva_x1_sma_out },
3002 	.init		= ptp_ocp_sma_fb_init,
3003 	.get		= ptp_ocp_sma_fb_get,
3004 	.set_inputs	= ptp_ocp_sma_adva_set_inputs,
3005 	.set_output	= ptp_ocp_sma_adva_set_output,
3006 };
3007 
3008 static int
3009 ptp_ocp_set_pins(struct ptp_ocp *bp)
3010 {
3011 	struct ptp_pin_desc *config;
3012 	int i;
3013 
3014 	config = kzalloc_objs(*config, 4);
3015 	if (!config)
3016 		return -ENOMEM;
3017 
3018 	for (i = 0; i < 4; i++) {
3019 		sprintf(config[i].name, "sma%d", i + 1);
3020 		config[i].index = i;
3021 	}
3022 
3023 	bp->ptp_info.n_pins = 4;
3024 	bp->ptp_info.pin_config = config;
3025 
3026 	return 0;
3027 }
3028 
3029 static void
3030 ptp_ocp_fb_set_version(struct ptp_ocp *bp)
3031 {
3032 	u64 cap = OCP_CAP_BASIC;
3033 	u32 version;
3034 
3035 	version = ioread32(&bp->image->version);
3036 
3037 	/* if lower 16 bits are empty, this is the fw loader. */
3038 	if ((version & 0xffff) == 0) {
3039 		version = version >> 16;
3040 		bp->fw_loader = true;
3041 	}
3042 
3043 	bp->fw_tag = version >> 15;
3044 	bp->fw_version = version & 0x7fff;
3045 
3046 	if (bp->fw_tag) {
3047 		/* FPGA firmware */
3048 		if (version >= 5)
3049 			cap |= OCP_CAP_SIGNAL | OCP_CAP_FREQ;
3050 	} else {
3051 		/* SOM firmware */
3052 		if (version >= 19)
3053 			cap |= OCP_CAP_SIGNAL;
3054 		if (version >= 20)
3055 			cap |= OCP_CAP_FREQ;
3056 	}
3057 
3058 	bp->fw_cap = cap;
3059 }
3060 
3061 /* FB specific board initializers; last "resource" registered. */
3062 static int
3063 ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
3064 {
3065 	int err;
3066 
3067 	bp->flash_start = 1024 * 4096;
3068 	bp->eeprom_map = fb_eeprom_map;
3069 	bp->fw_version = ioread32(&bp->image->version);
3070 	bp->sma_op = &ocp_fb_sma_op;
3071 	bp->signals_nr = 4;
3072 	bp->freq_in_nr = 4;
3073 
3074 	ptp_ocp_fb_set_version(bp);
3075 
3076 	ptp_ocp_tod_init(bp);
3077 	ptp_ocp_nmea_out_init(bp);
3078 	ptp_ocp_signal_init(bp);
3079 
3080 	err = ptp_ocp_attr_group_add(bp, fb_timecard_groups);
3081 	if (err)
3082 		return err;
3083 
3084 	err = ptp_ocp_set_pins(bp);
3085 	if (err)
3086 		return err;
3087 	ptp_ocp_sma_init(bp);
3088 
3089 	return ptp_ocp_init_clock(bp, r->extra);
3090 }
3091 
3092 static bool
3093 ptp_ocp_allow_irq(struct ptp_ocp *bp, struct ocp_resource *r)
3094 {
3095 	bool allow = !r->irq_vec || r->irq_vec < bp->n_irqs;
3096 
3097 	if (!allow)
3098 		dev_err(&bp->pdev->dev, "irq %d out of range, skipping %s\n",
3099 			r->irq_vec, r->name);
3100 	return allow;
3101 }
3102 
3103 static int
3104 ptp_ocp_register_resources(struct ptp_ocp *bp, kernel_ulong_t driver_data)
3105 {
3106 	struct ocp_resource *r, *table;
3107 	int err = 0;
3108 
3109 	table = (struct ocp_resource *)driver_data;
3110 	for (r = table; r->setup; r++) {
3111 		if (!ptp_ocp_allow_irq(bp, r))
3112 			continue;
3113 		err = r->setup(bp, r);
3114 		if (err) {
3115 			dev_err(&bp->pdev->dev,
3116 				"Could not register %s: err %d\n",
3117 				r->name, err);
3118 			break;
3119 		}
3120 	}
3121 	return err;
3122 }
3123 
3124 static void
3125 ptp_ocp_art_sma_init(struct ptp_ocp *bp)
3126 {
3127 	struct dpll_pin_properties prop = {
3128 		.board_label = NULL,
3129 		.type = DPLL_PIN_TYPE_EXT,
3130 		.capabilities = 0,
3131 		.freq_supported_num = ARRAY_SIZE(ptp_ocp_sma_freq),
3132 		.freq_supported = ptp_ocp_sma_freq,
3133 
3134 	};
3135 	u32 reg;
3136 	int i;
3137 
3138 	/* defaults */
3139 	bp->sma[0].mode = SMA_MODE_IN;
3140 	bp->sma[1].mode = SMA_MODE_IN;
3141 	bp->sma[2].mode = SMA_MODE_OUT;
3142 	bp->sma[3].mode = SMA_MODE_OUT;
3143 
3144 	bp->sma[0].default_fcn = 0x08;	/* IN: 10Mhz */
3145 	bp->sma[1].default_fcn = 0x01;	/* IN: PPS1 */
3146 	bp->sma[2].default_fcn = 0x10;	/* OUT: 10Mhz */
3147 	bp->sma[3].default_fcn = 0x02;	/* OUT: PHC */
3148 
3149 	for (i = 0; i < OCP_SMA_NUM; i++) {
3150 		/* If no SMA map, the pin functions and directions are fixed. */
3151 		bp->sma[i].dpll_prop = prop;
3152 		bp->sma[i].dpll_prop.board_label =
3153 			bp->ptp_info.pin_config[i].name;
3154 		if (!bp->art_sma) {
3155 			bp->sma[i].fixed_fcn = true;
3156 			bp->sma[i].fixed_dir = true;
3157 			continue;
3158 		}
3159 		reg = ioread32(&bp->art_sma->map[i].gpio);
3160 
3161 		switch (reg & 0xff) {
3162 		case 0:
3163 			bp->sma[i].fixed_fcn = true;
3164 			bp->sma[i].fixed_dir = true;
3165 			break;
3166 		case 1:
3167 		case 8:
3168 			bp->sma[i].mode = SMA_MODE_IN;
3169 			bp->sma[i].dpll_prop.capabilities =
3170 				DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;
3171 			break;
3172 		default:
3173 			bp->sma[i].mode = SMA_MODE_OUT;
3174 			bp->sma[i].dpll_prop.capabilities =
3175 				DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;
3176 			break;
3177 		}
3178 	}
3179 }
3180 
3181 static u32
3182 ptp_ocp_art_sma_get(struct ptp_ocp *bp, int sma_nr)
3183 {
3184 	if (bp->sma[sma_nr - 1].fixed_fcn)
3185 		return bp->sma[sma_nr - 1].default_fcn;
3186 
3187 	return ioread32(&bp->art_sma->map[sma_nr - 1].gpio) & 0xff;
3188 }
3189 
3190 /* note: store 0 is considered invalid. */
3191 static int
3192 ptp_ocp_art_sma_set(struct ptp_ocp *bp, int sma_nr, u32 val)
3193 {
3194 	unsigned long flags;
3195 	u32 __iomem *gpio;
3196 	int err = 0;
3197 	u32 reg;
3198 
3199 	val &= SMA_SELECT_MASK;
3200 	if (hweight32(val) > 1)
3201 		return -EINVAL;
3202 
3203 	gpio = &bp->art_sma->map[sma_nr - 1].gpio;
3204 
3205 	spin_lock_irqsave(&bp->lock, flags);
3206 	reg = ioread32(gpio);
3207 	if (((reg >> 16) & val) == 0) {
3208 		err = -EOPNOTSUPP;
3209 	} else {
3210 		reg = (reg & 0xff00) | (val & 0xff);
3211 		iowrite32(reg, gpio);
3212 	}
3213 	spin_unlock_irqrestore(&bp->lock, flags);
3214 
3215 	return err;
3216 }
3217 
3218 static const struct ocp_sma_op ocp_art_sma_op = {
3219 	.tbl		= { ptp_ocp_art_sma_in, ptp_ocp_art_sma_out },
3220 	.init		= ptp_ocp_art_sma_init,
3221 	.get		= ptp_ocp_art_sma_get,
3222 	.set_inputs	= ptp_ocp_art_sma_set,
3223 	.set_output	= ptp_ocp_art_sma_set,
3224 };
3225 
3226 /* ART specific board initializers; last "resource" registered. */
3227 static int
3228 ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
3229 {
3230 	int err;
3231 
3232 	bp->flash_start = 0x1000000;
3233 	bp->eeprom_map = art_eeprom_map;
3234 	bp->fw_cap = OCP_CAP_BASIC;
3235 	bp->fw_version = ioread32(&bp->reg->version);
3236 	bp->fw_tag = 2;
3237 	bp->sma_op = &ocp_art_sma_op;
3238 	bp->signals_nr = 4;
3239 	bp->freq_in_nr = 4;
3240 
3241 	/* Enable MAC serial port during initialisation */
3242 	iowrite32(1, &bp->board_config->mro50_serial_activate);
3243 
3244 	err = ptp_ocp_set_pins(bp);
3245 	if (err)
3246 		return err;
3247 	ptp_ocp_sma_init(bp);
3248 
3249 	err = ptp_ocp_attr_group_add(bp, art_timecard_groups);
3250 	if (err)
3251 		return err;
3252 
3253 	return ptp_ocp_init_clock(bp, r->extra);
3254 }
3255 
3256 /* ADVA board initializer; variant differences come from r->extra. */
3257 static int
3258 ptp_ocp_adva_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
3259 {
3260 	struct ptp_ocp_adva_info *info = r->extra;
3261 	u32 version;
3262 	int err;
3263 
3264 	bp->flash_start = info->flash_start;
3265 	bp->eeprom_map  = fb_eeprom_map;
3266 	bp->sma_op      = info->sma_op;
3267 	bp->signals_nr  = info->signals_nr;
3268 	bp->freq_in_nr  = info->freq_in_nr;
3269 
3270 	version = ioread32(&bp->image->version);
3271 	/* if lower 16 bits are empty, this is the fw loader. */
3272 	if ((version & 0xffff) == 0) {
3273 		version = version >> 16;
3274 		bp->fw_loader = true;
3275 	}
3276 	bp->fw_tag     = 3;
3277 	bp->fw_version = version & 0xffff;
3278 	bp->fw_cap     = OCP_CAP_BASIC | OCP_CAP_SIGNAL | OCP_CAP_FREQ;
3279 
3280 	ptp_ocp_tod_init(bp);
3281 	ptp_ocp_nmea_out_init(bp);
3282 	ptp_ocp_signal_init(bp);
3283 
3284 	err = ptp_ocp_attr_group_add(bp, info->attr_groups);
3285 	if (err)
3286 		return err;
3287 
3288 	err = ptp_ocp_set_pins(bp);
3289 	if (err)
3290 		return err;
3291 	ptp_ocp_sma_init(bp);
3292 
3293 	bp->has_cpld = info->has_cpld;
3294 
3295 	return ptp_ocp_init_clock(bp, &info->servo);
3296 }
3297 
3298 static ssize_t
3299 ptp_ocp_show_output(const struct ocp_selector *tbl, u32 val, char *buf,
3300 		    int def_val)
3301 {
3302 	const char *name;
3303 	ssize_t count;
3304 
3305 	count = sysfs_emit(buf, "OUT: ");
3306 	name = ptp_ocp_select_name_from_val(tbl, val);
3307 	if (!name)
3308 		name = ptp_ocp_select_name_from_val(tbl, def_val);
3309 	count += sysfs_emit_at(buf, count, "%s\n", name);
3310 	return count;
3311 }
3312 
3313 static ssize_t
3314 ptp_ocp_show_inputs(const struct ocp_selector *tbl, u32 val, char *buf,
3315 		    int def_val)
3316 {
3317 	const char *name;
3318 	ssize_t count;
3319 	int i;
3320 
3321 	count = sysfs_emit(buf, "IN: ");
3322 	for (i = 0; tbl[i].name; i++) {
3323 		if (val & tbl[i].value) {
3324 			name = tbl[i].name;
3325 			count += sysfs_emit_at(buf, count, "%s ", name);
3326 		}
3327 	}
3328 	if (!val && def_val >= 0) {
3329 		name = ptp_ocp_select_name_from_val(tbl, def_val);
3330 		count += sysfs_emit_at(buf, count, "%s ", name);
3331 	}
3332 	if (count)
3333 		count--;
3334 	count += sysfs_emit_at(buf, count, "\n");
3335 	return count;
3336 }
3337 
3338 static int
3339 sma_parse_inputs(const struct ocp_selector * const tbl[], const char *buf,
3340 		 enum ptp_ocp_sma_mode *mode)
3341 {
3342 	int idx, count, dir;
3343 	char **argv;
3344 	int ret;
3345 
3346 	argv = argv_split(GFP_KERNEL, buf, &count);
3347 	if (!argv)
3348 		return -ENOMEM;
3349 
3350 	ret = -EINVAL;
3351 	if (!count)
3352 		goto out;
3353 
3354 	idx = 0;
3355 	dir = *mode == SMA_MODE_IN ? 0 : 1;
3356 	if (!strcasecmp("IN:", argv[0])) {
3357 		dir = 0;
3358 		idx++;
3359 	}
3360 	if (!strcasecmp("OUT:", argv[0])) {
3361 		dir = 1;
3362 		idx++;
3363 	}
3364 	*mode = dir == 0 ? SMA_MODE_IN : SMA_MODE_OUT;
3365 
3366 	ret = 0;
3367 	for (; idx < count; idx++)
3368 		ret |= ptp_ocp_select_val_from_name(tbl[dir], argv[idx]);
3369 	if (ret < 0)
3370 		ret = -EINVAL;
3371 
3372 out:
3373 	argv_free(argv);
3374 	return ret;
3375 }
3376 
3377 static ssize_t
3378 ptp_ocp_sma_show(struct ptp_ocp *bp, int sma_nr, char *buf,
3379 		 int default_in_val, int default_out_val)
3380 {
3381 	struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
3382 	const struct ocp_selector * const *tbl;
3383 	u32 val;
3384 
3385 	tbl = bp->sma_op->tbl;
3386 	val = ptp_ocp_sma_get(bp, sma_nr) & SMA_SELECT_MASK;
3387 
3388 	if (sma->mode == SMA_MODE_IN) {
3389 		if (sma->disabled)
3390 			val = SMA_DISABLE;
3391 		return ptp_ocp_show_inputs(tbl[0], val, buf, default_in_val);
3392 	}
3393 
3394 	return ptp_ocp_show_output(tbl[1], val, buf, default_out_val);
3395 }
3396 
3397 static ssize_t
3398 sma1_show(struct device *dev, struct device_attribute *attr, char *buf)
3399 {
3400 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3401 
3402 	return ptp_ocp_sma_show(bp, 1, buf, 0, 1);
3403 }
3404 
3405 static ssize_t
3406 sma2_show(struct device *dev, struct device_attribute *attr, char *buf)
3407 {
3408 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3409 
3410 	return ptp_ocp_sma_show(bp, 2, buf, -1, 1);
3411 }
3412 
3413 static ssize_t
3414 sma3_show(struct device *dev, struct device_attribute *attr, char *buf)
3415 {
3416 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3417 
3418 	return ptp_ocp_sma_show(bp, 3, buf, -1, 0);
3419 }
3420 
3421 static ssize_t
3422 sma4_show(struct device *dev, struct device_attribute *attr, char *buf)
3423 {
3424 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3425 
3426 	return ptp_ocp_sma_show(bp, 4, buf, -1, 1);
3427 }
3428 
3429 static int
3430 ptp_ocp_sma_store_val(struct ptp_ocp *bp, int val, enum ptp_ocp_sma_mode mode, int sma_nr)
3431 {
3432 	struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
3433 
3434 	if (sma->fixed_dir && (mode != sma->mode || val & SMA_DISABLE))
3435 		return -EOPNOTSUPP;
3436 
3437 	if (sma->fixed_fcn) {
3438 		if (val != sma->default_fcn)
3439 			return -EOPNOTSUPP;
3440 		return 0;
3441 	}
3442 
3443 	sma->disabled = !!(val & SMA_DISABLE);
3444 
3445 	if (mode != sma->mode) {
3446 		if (mode == SMA_MODE_IN)
3447 			ptp_ocp_sma_set_output(bp, sma_nr, 0);
3448 		else
3449 			ptp_ocp_sma_set_inputs(bp, sma_nr, 0);
3450 		sma->mode = mode;
3451 	}
3452 
3453 	if (!sma->fixed_dir)
3454 		val |= SMA_ENABLE;		/* add enable bit */
3455 
3456 	if (sma->disabled)
3457 		val = 0;
3458 
3459 	if (mode == SMA_MODE_IN)
3460 		val = ptp_ocp_sma_set_inputs(bp, sma_nr, val);
3461 	else
3462 		val = ptp_ocp_sma_set_output(bp, sma_nr, val);
3463 
3464 	return val;
3465 }
3466 
3467 static int
3468 ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr)
3469 {
3470 	struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
3471 	enum ptp_ocp_sma_mode mode;
3472 	int val;
3473 
3474 	mode = sma->mode;
3475 	val = sma_parse_inputs(bp->sma_op->tbl, buf, &mode);
3476 	if (val < 0)
3477 		return val;
3478 	return ptp_ocp_sma_store_val(bp, val, mode, sma_nr);
3479 }
3480 
3481 static ssize_t
3482 sma1_store(struct device *dev, struct device_attribute *attr,
3483 	   const char *buf, size_t count)
3484 {
3485 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3486 	int err;
3487 
3488 	err = ptp_ocp_sma_store(bp, buf, 1);
3489 	return err ? err : count;
3490 }
3491 
3492 static ssize_t
3493 sma2_store(struct device *dev, struct device_attribute *attr,
3494 	   const char *buf, size_t count)
3495 {
3496 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3497 	int err;
3498 
3499 	err = ptp_ocp_sma_store(bp, buf, 2);
3500 	return err ? err : count;
3501 }
3502 
3503 static ssize_t
3504 sma3_store(struct device *dev, struct device_attribute *attr,
3505 	   const char *buf, size_t count)
3506 {
3507 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3508 	int err;
3509 
3510 	err = ptp_ocp_sma_store(bp, buf, 3);
3511 	return err ? err : count;
3512 }
3513 
3514 static ssize_t
3515 sma4_store(struct device *dev, struct device_attribute *attr,
3516 	   const char *buf, size_t count)
3517 {
3518 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3519 	int err;
3520 
3521 	err = ptp_ocp_sma_store(bp, buf, 4);
3522 	return err ? err : count;
3523 }
3524 static DEVICE_ATTR_RW(sma1);
3525 static DEVICE_ATTR_RW(sma2);
3526 static DEVICE_ATTR_RW(sma3);
3527 static DEVICE_ATTR_RW(sma4);
3528 
3529 static ssize_t
3530 available_sma_inputs_show(struct device *dev,
3531 			  struct device_attribute *attr, char *buf)
3532 {
3533 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3534 
3535 	return ptp_ocp_select_table_show(bp->sma_op->tbl[0], buf);
3536 }
3537 static DEVICE_ATTR_RO(available_sma_inputs);
3538 
3539 static ssize_t
3540 available_sma_outputs_show(struct device *dev,
3541 			   struct device_attribute *attr, char *buf)
3542 {
3543 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3544 
3545 	return ptp_ocp_select_table_show(bp->sma_op->tbl[1], buf);
3546 }
3547 static DEVICE_ATTR_RO(available_sma_outputs);
3548 
3549 #define EXT_ATTR_RO(_group, _name, _val)				\
3550 	struct dev_ext_attribute dev_attr_##_group##_val##_##_name =	\
3551 		{ __ATTR_RO(_name), (void *)_val }
3552 #define EXT_ATTR_RW(_group, _name, _val)				\
3553 	struct dev_ext_attribute dev_attr_##_group##_val##_##_name =	\
3554 		{ __ATTR_RW(_name), (void *)_val }
3555 #define to_ext_attr(x) container_of(x, struct dev_ext_attribute, attr)
3556 
3557 /* period [duty [phase [polarity]]] */
3558 static ssize_t
3559 signal_store(struct device *dev, struct device_attribute *attr,
3560 	     const char *buf, size_t count)
3561 {
3562 	struct dev_ext_attribute *ea = to_ext_attr(attr);
3563 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3564 	struct ptp_ocp_signal s = { };
3565 	int gen = (uintptr_t)ea->var;
3566 	int argc, err;
3567 	char **argv;
3568 
3569 	argv = argv_split(GFP_KERNEL, buf, &argc);
3570 	if (!argv)
3571 		return -ENOMEM;
3572 
3573 	err = -EINVAL;
3574 	s.duty = bp->signal[gen].duty;
3575 	s.phase = bp->signal[gen].phase;
3576 	s.period = bp->signal[gen].period;
3577 	s.polarity = bp->signal[gen].polarity;
3578 
3579 	switch (argc) {
3580 	case 4:
3581 		argc--;
3582 		err = kstrtobool(argv[argc], &s.polarity);
3583 		if (err)
3584 			goto out;
3585 		fallthrough;
3586 	case 3:
3587 		argc--;
3588 		err = kstrtou64(argv[argc], 0, &s.phase);
3589 		if (err)
3590 			goto out;
3591 		fallthrough;
3592 	case 2:
3593 		argc--;
3594 		err = kstrtoint(argv[argc], 0, &s.duty);
3595 		if (err)
3596 			goto out;
3597 		fallthrough;
3598 	case 1:
3599 		argc--;
3600 		err = kstrtou64(argv[argc], 0, &s.period);
3601 		if (err)
3602 			goto out;
3603 		break;
3604 	default:
3605 		goto out;
3606 	}
3607 
3608 	err = ptp_ocp_signal_set(bp, gen, &s);
3609 	if (err)
3610 		goto out;
3611 
3612 	err = ptp_ocp_signal_enable(bp->signal_out[gen], gen, s.period != 0);
3613 
3614 out:
3615 	argv_free(argv);
3616 	return err ? err : count;
3617 }
3618 
3619 static ssize_t
3620 signal_show(struct device *dev, struct device_attribute *attr, char *buf)
3621 {
3622 	struct dev_ext_attribute *ea = to_ext_attr(attr);
3623 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3624 	struct ptp_ocp_signal *signal;
3625 	int gen = (uintptr_t)ea->var;
3626 	struct timespec64 ts;
3627 
3628 	signal = &bp->signal[gen];
3629 
3630 	ts = ktime_to_timespec64(signal->start);
3631 
3632 	return sysfs_emit(buf, "%llu %d %llu %d %ptT TAI\n",
3633 			  signal->period, signal->duty, signal->phase, signal->polarity,
3634 			  &ts.tv_sec);
3635 }
3636 static EXT_ATTR_RW(signal, signal, 0);
3637 static EXT_ATTR_RW(signal, signal, 1);
3638 static EXT_ATTR_RW(signal, signal, 2);
3639 static EXT_ATTR_RW(signal, signal, 3);
3640 
3641 static ssize_t
3642 duty_show(struct device *dev, struct device_attribute *attr, char *buf)
3643 {
3644 	struct dev_ext_attribute *ea = to_ext_attr(attr);
3645 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3646 	int i = (uintptr_t)ea->var;
3647 
3648 	return sysfs_emit(buf, "%d\n", bp->signal[i].duty);
3649 }
3650 static EXT_ATTR_RO(signal, duty, 0);
3651 static EXT_ATTR_RO(signal, duty, 1);
3652 static EXT_ATTR_RO(signal, duty, 2);
3653 static EXT_ATTR_RO(signal, duty, 3);
3654 
3655 static ssize_t
3656 period_show(struct device *dev, struct device_attribute *attr, char *buf)
3657 {
3658 	struct dev_ext_attribute *ea = to_ext_attr(attr);
3659 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3660 	int i = (uintptr_t)ea->var;
3661 
3662 	return sysfs_emit(buf, "%llu\n", bp->signal[i].period);
3663 }
3664 static EXT_ATTR_RO(signal, period, 0);
3665 static EXT_ATTR_RO(signal, period, 1);
3666 static EXT_ATTR_RO(signal, period, 2);
3667 static EXT_ATTR_RO(signal, period, 3);
3668 
3669 static ssize_t
3670 phase_show(struct device *dev, struct device_attribute *attr, char *buf)
3671 {
3672 	struct dev_ext_attribute *ea = to_ext_attr(attr);
3673 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3674 	int i = (uintptr_t)ea->var;
3675 
3676 	return sysfs_emit(buf, "%llu\n", bp->signal[i].phase);
3677 }
3678 static EXT_ATTR_RO(signal, phase, 0);
3679 static EXT_ATTR_RO(signal, phase, 1);
3680 static EXT_ATTR_RO(signal, phase, 2);
3681 static EXT_ATTR_RO(signal, phase, 3);
3682 
3683 static ssize_t
3684 polarity_show(struct device *dev, struct device_attribute *attr,
3685 	      char *buf)
3686 {
3687 	struct dev_ext_attribute *ea = to_ext_attr(attr);
3688 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3689 	int i = (uintptr_t)ea->var;
3690 
3691 	return sysfs_emit(buf, "%d\n", bp->signal[i].polarity);
3692 }
3693 static EXT_ATTR_RO(signal, polarity, 0);
3694 static EXT_ATTR_RO(signal, polarity, 1);
3695 static EXT_ATTR_RO(signal, polarity, 2);
3696 static EXT_ATTR_RO(signal, polarity, 3);
3697 
3698 static ssize_t
3699 running_show(struct device *dev, struct device_attribute *attr, char *buf)
3700 {
3701 	struct dev_ext_attribute *ea = to_ext_attr(attr);
3702 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3703 	int i = (uintptr_t)ea->var;
3704 
3705 	return sysfs_emit(buf, "%d\n", bp->signal[i].running);
3706 }
3707 static EXT_ATTR_RO(signal, running, 0);
3708 static EXT_ATTR_RO(signal, running, 1);
3709 static EXT_ATTR_RO(signal, running, 2);
3710 static EXT_ATTR_RO(signal, running, 3);
3711 
3712 static ssize_t
3713 start_show(struct device *dev, struct device_attribute *attr, char *buf)
3714 {
3715 	struct dev_ext_attribute *ea = to_ext_attr(attr);
3716 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3717 	int i = (uintptr_t)ea->var;
3718 	struct timespec64 ts;
3719 
3720 	ts = ktime_to_timespec64(bp->signal[i].start);
3721 	return sysfs_emit(buf, "%llu.%lu\n", ts.tv_sec, ts.tv_nsec);
3722 }
3723 static EXT_ATTR_RO(signal, start, 0);
3724 static EXT_ATTR_RO(signal, start, 1);
3725 static EXT_ATTR_RO(signal, start, 2);
3726 static EXT_ATTR_RO(signal, start, 3);
3727 
3728 static ssize_t
3729 seconds_store(struct device *dev, struct device_attribute *attr,
3730 	      const char *buf, size_t count)
3731 {
3732 	struct dev_ext_attribute *ea = to_ext_attr(attr);
3733 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3734 	int idx = (uintptr_t)ea->var;
3735 	u32 val;
3736 	int err;
3737 
3738 	err = kstrtou32(buf, 0, &val);
3739 	if (err)
3740 		return err;
3741 	if (val > 0xff)
3742 		return -EINVAL;
3743 
3744 	if (val)
3745 		val = (val << 8) | 0x1;
3746 
3747 	iowrite32(val, &bp->freq_in[idx]->ctrl);
3748 
3749 	return count;
3750 }
3751 
3752 static ssize_t
3753 seconds_show(struct device *dev, struct device_attribute *attr, char *buf)
3754 {
3755 	struct dev_ext_attribute *ea = to_ext_attr(attr);
3756 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3757 	int idx = (uintptr_t)ea->var;
3758 	u32 val;
3759 
3760 	val = ioread32(&bp->freq_in[idx]->ctrl);
3761 	if (val & 1)
3762 		val = (val >> 8) & 0xff;
3763 	else
3764 		val = 0;
3765 
3766 	return sysfs_emit(buf, "%u\n", val);
3767 }
3768 static EXT_ATTR_RW(freq, seconds, 0);
3769 static EXT_ATTR_RW(freq, seconds, 1);
3770 static EXT_ATTR_RW(freq, seconds, 2);
3771 static EXT_ATTR_RW(freq, seconds, 3);
3772 
3773 static ssize_t
3774 frequency_show(struct device *dev, struct device_attribute *attr, char *buf)
3775 {
3776 	struct dev_ext_attribute *ea = to_ext_attr(attr);
3777 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3778 	int idx = (uintptr_t)ea->var;
3779 	u32 val;
3780 
3781 	val = ioread32(&bp->freq_in[idx]->status);
3782 	if (val & FREQ_STATUS_ERROR)
3783 		return sysfs_emit(buf, "error\n");
3784 	if (val & FREQ_STATUS_OVERRUN)
3785 		return sysfs_emit(buf, "overrun\n");
3786 	if (val & FREQ_STATUS_VALID)
3787 		return sysfs_emit(buf, "%lu\n", val & FREQ_STATUS_MASK);
3788 	return 0;
3789 }
3790 static EXT_ATTR_RO(freq, frequency, 0);
3791 static EXT_ATTR_RO(freq, frequency, 1);
3792 static EXT_ATTR_RO(freq, frequency, 2);
3793 static EXT_ATTR_RO(freq, frequency, 3);
3794 
3795 static ssize_t
3796 ptp_ocp_tty_show(struct device *dev, struct device_attribute *attr, char *buf)
3797 {
3798 	struct dev_ext_attribute *ea = to_ext_attr(attr);
3799 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3800 
3801 	/*
3802 	 * NOTE: This output does not include a trailing newline for backward
3803 	 * compatibility. Existing userspace software uses this value directly
3804 	 * as a device path (e.g., "/dev/ttyS4"), and adding a newline would
3805 	 * break those applications. Do not add a newline to this output.
3806 	 */
3807 	return sysfs_emit(buf, "ttyS%d", bp->port[(uintptr_t)ea->var].line);
3808 }
3809 
3810 static umode_t
3811 ptp_ocp_timecard_tty_is_visible(struct kobject *kobj, struct attribute *attr, int n)
3812 {
3813 	struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3814 	struct ptp_ocp_serial_port *port;
3815 	struct device_attribute *dattr;
3816 	struct dev_ext_attribute *ea;
3817 
3818 	if (strncmp(attr->name, "tty", 3))
3819 		return attr->mode;
3820 
3821 	dattr = container_of(attr, struct device_attribute, attr);
3822 	ea = container_of(dattr, struct dev_ext_attribute, attr);
3823 	port = &bp->port[(uintptr_t)ea->var];
3824 	return port->line == -1 ? 0 : 0444;
3825 }
3826 
3827 #define EXT_TTY_ATTR_RO(_name, _val)			\
3828 	struct dev_ext_attribute dev_attr_tty##_name =	\
3829 		{ __ATTR(tty##_name, 0444, ptp_ocp_tty_show, NULL), (void *)_val }
3830 
3831 static EXT_TTY_ATTR_RO(GNSS, PORT_GNSS);
3832 static EXT_TTY_ATTR_RO(GNSS2, PORT_GNSS2);
3833 static EXT_TTY_ATTR_RO(MAC, PORT_MAC);
3834 static EXT_TTY_ATTR_RO(NMEA, PORT_NMEA);
3835 static struct attribute *ptp_ocp_timecard_tty_attrs[] = {
3836 	&dev_attr_ttyGNSS.attr.attr,
3837 	&dev_attr_ttyGNSS2.attr.attr,
3838 	&dev_attr_ttyMAC.attr.attr,
3839 	&dev_attr_ttyNMEA.attr.attr,
3840 	NULL,
3841 };
3842 
3843 static const struct attribute_group ptp_ocp_timecard_tty_group = {
3844 	.name = "tty",
3845 	.attrs = ptp_ocp_timecard_tty_attrs,
3846 	.is_visible = ptp_ocp_timecard_tty_is_visible,
3847 };
3848 
3849 static ssize_t
3850 serialnum_show(struct device *dev, struct device_attribute *attr, char *buf)
3851 {
3852 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3853 
3854 	if (!bp->has_eeprom_data)
3855 		ptp_ocp_read_eeprom(bp);
3856 
3857 	return sysfs_emit(buf, "%pM\n", bp->serial);
3858 }
3859 static DEVICE_ATTR_RO(serialnum);
3860 
3861 static ssize_t
3862 gnss_sync_show(struct device *dev, struct device_attribute *attr, char *buf)
3863 {
3864 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3865 	ssize_t ret;
3866 
3867 	if (bp->gnss_lost)
3868 		ret = sysfs_emit(buf, "LOST @ %ptT\n", &bp->gnss_lost);
3869 	else
3870 		ret = sysfs_emit(buf, "SYNC\n");
3871 
3872 	return ret;
3873 }
3874 static DEVICE_ATTR_RO(gnss_sync);
3875 
3876 static ssize_t
3877 utc_tai_offset_show(struct device *dev,
3878 		    struct device_attribute *attr, char *buf)
3879 {
3880 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3881 
3882 	return sysfs_emit(buf, "%d\n", bp->utc_tai_offset);
3883 }
3884 
3885 static ssize_t
3886 utc_tai_offset_store(struct device *dev,
3887 		     struct device_attribute *attr,
3888 		     const char *buf, size_t count)
3889 {
3890 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3891 	int err;
3892 	u32 val;
3893 
3894 	err = kstrtou32(buf, 0, &val);
3895 	if (err)
3896 		return err;
3897 
3898 	ptp_ocp_utc_distribute(bp, val);
3899 
3900 	return count;
3901 }
3902 static DEVICE_ATTR_RW(utc_tai_offset);
3903 
3904 static ssize_t
3905 ts_window_adjust_show(struct device *dev,
3906 		      struct device_attribute *attr, char *buf)
3907 {
3908 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3909 
3910 	return sysfs_emit(buf, "%d\n", bp->ts_window_adjust);
3911 }
3912 
3913 static ssize_t
3914 ts_window_adjust_store(struct device *dev,
3915 		       struct device_attribute *attr,
3916 		       const char *buf, size_t count)
3917 {
3918 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3919 	int err;
3920 	u32 val;
3921 
3922 	err = kstrtou32(buf, 0, &val);
3923 	if (err)
3924 		return err;
3925 
3926 	bp->ts_window_adjust = val;
3927 
3928 	return count;
3929 }
3930 static DEVICE_ATTR_RW(ts_window_adjust);
3931 
3932 static ssize_t
3933 irig_b_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
3934 {
3935 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3936 	u32 val;
3937 
3938 	val = ioread32(&bp->irig_out->ctrl);
3939 	val = (val >> 16) & 0x07;
3940 	return sysfs_emit(buf, "%d\n", val);
3941 }
3942 
3943 static ssize_t
3944 irig_b_mode_store(struct device *dev,
3945 		  struct device_attribute *attr,
3946 		  const char *buf, size_t count)
3947 {
3948 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3949 	unsigned long flags;
3950 	int err;
3951 	u32 reg;
3952 	u8 val;
3953 
3954 	err = kstrtou8(buf, 0, &val);
3955 	if (err)
3956 		return err;
3957 	if (val > 7)
3958 		return -EINVAL;
3959 
3960 	reg = ((val & 0x7) << 16);
3961 
3962 	spin_lock_irqsave(&bp->lock, flags);
3963 	iowrite32(0, &bp->irig_out->ctrl);		/* disable */
3964 	iowrite32(reg, &bp->irig_out->ctrl);		/* change mode */
3965 	iowrite32(reg | IRIG_M_CTRL_ENABLE, &bp->irig_out->ctrl);
3966 	spin_unlock_irqrestore(&bp->lock, flags);
3967 
3968 	return count;
3969 }
3970 static DEVICE_ATTR_RW(irig_b_mode);
3971 
3972 static ssize_t
3973 clock_source_show(struct device *dev, struct device_attribute *attr, char *buf)
3974 {
3975 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3976 	const char *p;
3977 	u32 select;
3978 
3979 	select = ioread32(&bp->reg->select);
3980 	p = ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16);
3981 
3982 	return sysfs_emit(buf, "%s\n", p);
3983 }
3984 
3985 static ssize_t
3986 clock_source_store(struct device *dev, struct device_attribute *attr,
3987 		   const char *buf, size_t count)
3988 {
3989 	struct ptp_ocp *bp = dev_get_drvdata(dev);
3990 	unsigned long flags;
3991 	int val;
3992 
3993 	val = ptp_ocp_select_val_from_name(ptp_ocp_clock, buf);
3994 	if (val < 0)
3995 		return val;
3996 
3997 	spin_lock_irqsave(&bp->lock, flags);
3998 	iowrite32(val, &bp->reg->select);
3999 	spin_unlock_irqrestore(&bp->lock, flags);
4000 
4001 	return count;
4002 }
4003 static DEVICE_ATTR_RW(clock_source);
4004 
4005 static ssize_t
4006 available_clock_sources_show(struct device *dev,
4007 			     struct device_attribute *attr, char *buf)
4008 {
4009 	return ptp_ocp_select_table_show(ptp_ocp_clock, buf);
4010 }
4011 static DEVICE_ATTR_RO(available_clock_sources);
4012 
4013 static ssize_t
4014 clock_status_drift_show(struct device *dev,
4015 			struct device_attribute *attr, char *buf)
4016 {
4017 	struct ptp_ocp *bp = dev_get_drvdata(dev);
4018 	u32 val;
4019 	int res;
4020 
4021 	val = ioread32(&bp->reg->status_drift);
4022 	res = (val & ~INT_MAX) ? -1 : 1;
4023 	res *= (val & INT_MAX);
4024 	return sysfs_emit(buf, "%d\n", res);
4025 }
4026 static DEVICE_ATTR_RO(clock_status_drift);
4027 
4028 static ssize_t
4029 clock_status_offset_show(struct device *dev,
4030 			 struct device_attribute *attr, char *buf)
4031 {
4032 	struct ptp_ocp *bp = dev_get_drvdata(dev);
4033 	u32 val;
4034 	int res;
4035 
4036 	val = ioread32(&bp->reg->status_offset);
4037 	res = (val & ~INT_MAX) ? -1 : 1;
4038 	res *= (val & INT_MAX);
4039 	return sysfs_emit(buf, "%d\n", res);
4040 }
4041 static DEVICE_ATTR_RO(clock_status_offset);
4042 
4043 static ssize_t
4044 tod_correction_show(struct device *dev,
4045 		    struct device_attribute *attr, char *buf)
4046 {
4047 	struct ptp_ocp *bp = dev_get_drvdata(dev);
4048 	u32 val;
4049 	int res;
4050 
4051 	val = ioread32(&bp->tod->adj_sec);
4052 	res = (val & ~INT_MAX) ? -1 : 1;
4053 	res *= (val & INT_MAX);
4054 	return sysfs_emit(buf, "%d\n", res);
4055 }
4056 
4057 static ssize_t
4058 tod_correction_store(struct device *dev, struct device_attribute *attr,
4059 		     const char *buf, size_t count)
4060 {
4061 	struct ptp_ocp *bp = dev_get_drvdata(dev);
4062 	unsigned long flags;
4063 	int err, res;
4064 	u32 val = 0;
4065 
4066 	err = kstrtos32(buf, 0, &res);
4067 	if (err)
4068 		return err;
4069 	if (res < 0) {
4070 		res *= -1;
4071 		val |= BIT(31);
4072 	}
4073 	val |= res;
4074 
4075 	spin_lock_irqsave(&bp->lock, flags);
4076 	iowrite32(val, &bp->tod->adj_sec);
4077 	spin_unlock_irqrestore(&bp->lock, flags);
4078 
4079 	return count;
4080 }
4081 static DEVICE_ATTR_RW(tod_correction);
4082 
4083 #define _DEVICE_SIGNAL_GROUP_ATTRS(_nr)					\
4084 	static struct attribute *fb_timecard_signal##_nr##_attrs[] = {	\
4085 		&dev_attr_signal##_nr##_signal.attr.attr,		\
4086 		&dev_attr_signal##_nr##_duty.attr.attr,			\
4087 		&dev_attr_signal##_nr##_phase.attr.attr,		\
4088 		&dev_attr_signal##_nr##_period.attr.attr,		\
4089 		&dev_attr_signal##_nr##_polarity.attr.attr,		\
4090 		&dev_attr_signal##_nr##_running.attr.attr,		\
4091 		&dev_attr_signal##_nr##_start.attr.attr,		\
4092 		NULL,							\
4093 	}
4094 
4095 #define DEVICE_SIGNAL_GROUP(_name, _nr)					\
4096 	_DEVICE_SIGNAL_GROUP_ATTRS(_nr);				\
4097 	static const struct attribute_group				\
4098 			fb_timecard_signal##_nr##_group = {		\
4099 		.name = #_name,						\
4100 		.attrs = fb_timecard_signal##_nr##_attrs,		\
4101 }
4102 
4103 DEVICE_SIGNAL_GROUP(gen1, 0);
4104 DEVICE_SIGNAL_GROUP(gen2, 1);
4105 DEVICE_SIGNAL_GROUP(gen3, 2);
4106 DEVICE_SIGNAL_GROUP(gen4, 3);
4107 
4108 #define _DEVICE_FREQ_GROUP_ATTRS(_nr)					\
4109 	static struct attribute *fb_timecard_freq##_nr##_attrs[] = {	\
4110 		&dev_attr_freq##_nr##_seconds.attr.attr,		\
4111 		&dev_attr_freq##_nr##_frequency.attr.attr,		\
4112 		NULL,							\
4113 	}
4114 
4115 #define DEVICE_FREQ_GROUP(_name, _nr)					\
4116 	_DEVICE_FREQ_GROUP_ATTRS(_nr);					\
4117 	static const struct attribute_group				\
4118 			fb_timecard_freq##_nr##_group = {		\
4119 		.name = #_name,						\
4120 		.attrs = fb_timecard_freq##_nr##_attrs,			\
4121 }
4122 
4123 DEVICE_FREQ_GROUP(freq1, 0);
4124 DEVICE_FREQ_GROUP(freq2, 1);
4125 DEVICE_FREQ_GROUP(freq3, 2);
4126 DEVICE_FREQ_GROUP(freq4, 3);
4127 
4128 static ssize_t
4129 disciplining_config_read(struct file *filp, struct kobject *kobj,
4130 			 const struct bin_attribute *bin_attr, char *buf,
4131 			 loff_t off, size_t count)
4132 {
4133 	struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
4134 	size_t size = OCP_ART_CONFIG_SIZE;
4135 	struct nvmem_device *nvmem;
4136 	ssize_t err;
4137 
4138 	nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
4139 	if (IS_ERR(nvmem))
4140 		return PTR_ERR(nvmem);
4141 
4142 	if (off > size) {
4143 		err = 0;
4144 		goto out;
4145 	}
4146 
4147 	if (off + count > size)
4148 		count = size - off;
4149 
4150 	// the configuration is in the very beginning of the EEPROM
4151 	err = nvmem_device_read(nvmem, off, count, buf);
4152 	if (err != count) {
4153 		err = -EFAULT;
4154 		goto out;
4155 	}
4156 
4157 out:
4158 	ptp_ocp_nvmem_device_put(&nvmem);
4159 
4160 	return err;
4161 }
4162 
4163 static ssize_t
4164 disciplining_config_write(struct file *filp, struct kobject *kobj,
4165 			  const struct bin_attribute *bin_attr, char *buf,
4166 			  loff_t off, size_t count)
4167 {
4168 	struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
4169 	struct nvmem_device *nvmem;
4170 	ssize_t err;
4171 
4172 	/* Allow write of the whole area only */
4173 	if (off || count != OCP_ART_CONFIG_SIZE)
4174 		return -EFAULT;
4175 
4176 	nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
4177 	if (IS_ERR(nvmem))
4178 		return PTR_ERR(nvmem);
4179 
4180 	err = nvmem_device_write(nvmem, 0x00, count, buf);
4181 	if (err != count)
4182 		err = -EFAULT;
4183 
4184 	ptp_ocp_nvmem_device_put(&nvmem);
4185 
4186 	return err;
4187 }
4188 static const BIN_ATTR_RW(disciplining_config, OCP_ART_CONFIG_SIZE);
4189 
4190 static ssize_t
4191 temperature_table_read(struct file *filp, struct kobject *kobj,
4192 		       const struct bin_attribute *bin_attr, char *buf,
4193 		       loff_t off, size_t count)
4194 {
4195 	struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
4196 	size_t size = OCP_ART_TEMP_TABLE_SIZE;
4197 	struct nvmem_device *nvmem;
4198 	ssize_t err;
4199 
4200 	nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
4201 	if (IS_ERR(nvmem))
4202 		return PTR_ERR(nvmem);
4203 
4204 	if (off > size) {
4205 		err = 0;
4206 		goto out;
4207 	}
4208 
4209 	if (off + count > size)
4210 		count = size - off;
4211 
4212 	// the configuration is in the very beginning of the EEPROM
4213 	err = nvmem_device_read(nvmem, 0x90 + off, count, buf);
4214 	if (err != count) {
4215 		err = -EFAULT;
4216 		goto out;
4217 	}
4218 
4219 out:
4220 	ptp_ocp_nvmem_device_put(&nvmem);
4221 
4222 	return err;
4223 }
4224 
4225 static ssize_t
4226 temperature_table_write(struct file *filp, struct kobject *kobj,
4227 			const struct bin_attribute *bin_attr, char *buf,
4228 			loff_t off, size_t count)
4229 {
4230 	struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
4231 	struct nvmem_device *nvmem;
4232 	ssize_t err;
4233 
4234 	/* Allow write of the whole area only */
4235 	if (off || count != OCP_ART_TEMP_TABLE_SIZE)
4236 		return -EFAULT;
4237 
4238 	nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
4239 	if (IS_ERR(nvmem))
4240 		return PTR_ERR(nvmem);
4241 
4242 	err = nvmem_device_write(nvmem, 0x90, count, buf);
4243 	if (err != count)
4244 		err = -EFAULT;
4245 
4246 	ptp_ocp_nvmem_device_put(&nvmem);
4247 
4248 	return err;
4249 }
4250 static const BIN_ATTR_RW(temperature_table, OCP_ART_TEMP_TABLE_SIZE);
4251 
4252 static struct attribute *fb_timecard_attrs[] = {
4253 	&dev_attr_serialnum.attr,
4254 	&dev_attr_gnss_sync.attr,
4255 	&dev_attr_clock_source.attr,
4256 	&dev_attr_available_clock_sources.attr,
4257 	&dev_attr_sma1.attr,
4258 	&dev_attr_sma2.attr,
4259 	&dev_attr_sma3.attr,
4260 	&dev_attr_sma4.attr,
4261 	&dev_attr_available_sma_inputs.attr,
4262 	&dev_attr_available_sma_outputs.attr,
4263 	&dev_attr_clock_status_drift.attr,
4264 	&dev_attr_clock_status_offset.attr,
4265 	&dev_attr_irig_b_mode.attr,
4266 	&dev_attr_utc_tai_offset.attr,
4267 	&dev_attr_ts_window_adjust.attr,
4268 	&dev_attr_tod_correction.attr,
4269 	NULL,
4270 };
4271 
4272 static const struct attribute_group fb_timecard_group = {
4273 	.attrs = fb_timecard_attrs,
4274 };
4275 
4276 static const struct ocp_attr_group fb_timecard_groups[] = {
4277 	{ .cap = OCP_CAP_BASIC,	    .group = &fb_timecard_group },
4278 	{ .cap = OCP_CAP_BASIC,	    .group = &ptp_ocp_timecard_tty_group },
4279 	{ .cap = OCP_CAP_SIGNAL,    .group = &fb_timecard_signal0_group },
4280 	{ .cap = OCP_CAP_SIGNAL,    .group = &fb_timecard_signal1_group },
4281 	{ .cap = OCP_CAP_SIGNAL,    .group = &fb_timecard_signal2_group },
4282 	{ .cap = OCP_CAP_SIGNAL,    .group = &fb_timecard_signal3_group },
4283 	{ .cap = OCP_CAP_FREQ,	    .group = &fb_timecard_freq0_group },
4284 	{ .cap = OCP_CAP_FREQ,	    .group = &fb_timecard_freq1_group },
4285 	{ .cap = OCP_CAP_FREQ,	    .group = &fb_timecard_freq2_group },
4286 	{ .cap = OCP_CAP_FREQ,	    .group = &fb_timecard_freq3_group },
4287 	{ },
4288 };
4289 
4290 static struct attribute *art_timecard_attrs[] = {
4291 	&dev_attr_serialnum.attr,
4292 	&dev_attr_clock_source.attr,
4293 	&dev_attr_available_clock_sources.attr,
4294 	&dev_attr_utc_tai_offset.attr,
4295 	&dev_attr_ts_window_adjust.attr,
4296 	&dev_attr_sma1.attr,
4297 	&dev_attr_sma2.attr,
4298 	&dev_attr_sma3.attr,
4299 	&dev_attr_sma4.attr,
4300 	&dev_attr_available_sma_inputs.attr,
4301 	&dev_attr_available_sma_outputs.attr,
4302 	NULL,
4303 };
4304 
4305 static const struct bin_attribute *const bin_art_timecard_attrs[] = {
4306 	&bin_attr_disciplining_config,
4307 	&bin_attr_temperature_table,
4308 	NULL,
4309 };
4310 
4311 static const struct attribute_group art_timecard_group = {
4312 	.attrs = art_timecard_attrs,
4313 	.bin_attrs = bin_art_timecard_attrs,
4314 };
4315 
4316 static const struct ocp_attr_group art_timecard_groups[] = {
4317 	{ .cap = OCP_CAP_BASIC,	    .group = &art_timecard_group },
4318 	{ .cap = OCP_CAP_BASIC,	    .group = &ptp_ocp_timecard_tty_group },
4319 	{ },
4320 };
4321 
4322 /*
4323  * adva_x1 TAP CPLD (Lattice LCMXO3LF-2100) helpers.
4324  *
4325  * The card has two I2C controllers; Linux registers only 0x00150000.
4326  * The i2c_bus_ctrl handshake re-routes what each is wired to:
4327  *
4328  *   grant 0:  0x150000 -> EEPROMs     0x120000 -> TMC or M.2, MB's choice
4329  *   grant 1:  0x150000 -> TMC bus     0x120000 -> M.2
4330  *
4331  * The PCA9548 at 0x74 and the CPLD at 0x40 behind its channel 0 are on the
4332  * TMC bus, reachable only while the grant is held.  The EEPROMs are not
4333  * behind the adapter for that window, so a CPLD operation holds cpld_lock
4334  * and the adapter lock to keep the EEPROM and nvmem paths off it.
4335  */
4336 
4337 #define ADVA_MUX_ADDR     0x74
4338 #define ADVA_CPLD_ADDR    0x40
4339 #define ADVA_MUX_CHANNEL  0
4340 
4341 /* Longest command or reply; bounds each half of the per-claim scratch. */
4342 #define ADVA_CPLD_XFER_MAX 32
4343 
4344 /* i2c_bus_ctrl carries a host-written request half and a firmware-written
4345  * grant half.  MBLAZE_GRANTED is what a granted register reads while our
4346  * request still stands; the release write clears the request half, so from
4347  * then on only the grant field can be tested.  Measured on an ADVA
4348  * TimeCard X1: the register reads 0x00000012 once the firmware has handed
4349  * the segment back, about 670 ms after the release write, so the low half
4350  * is not zero then and only the grant field is a valid test.
4351  */
4352 #define MBLAZE_REQUEST    0x0000aaaaU
4353 #define MBLAZE_GRANTED    0x5555aaaaU
4354 #define MBLAZE_RELEASE    0x55550000U
4355 #define MBLAZE_GRANT_MASK 0xffff0000U
4356 #define MBLAZE_GRANT      0x55550000U
4357 #define MBLAZE_RETRIES    200
4358 #define MBLAZE_RETRY_US   10000
4359 
4360 /* Lattice LCMXO3LF ISC command codes */
4361 #define CPLD_CMD_READ_ID      0xE0000000UL
4362 /* The USERCODE lives in the configuration flash that ERASE wipes, and the
4363  * page writes carry it: after programming an image whose JEDEC UH field is
4364  * 0x00000004 the part reads back 0x00000004, not an erased value.  So there
4365  * is no separate ISC_PROGRAM_USERCODE step here.
4366  */
4367 #define CPLD_CMD_READ_USERCODE 0xC0000000UL
4368 #define CPLD_CMD_READ_STATUS  0x3C000000UL
4369 #define CPLD_CMD_EN_CFG_TP    0x74   /* enable config, transparent mode */
4370 #define CPLD_CMD_DIS_CFG      0x26
4371 #define CPLD_CMD_ERASE        0x0E
4372 #define CPLD_CMD_RESET_ADDR   0x46
4373 #define CPLD_CMD_WRITE_PAGE   0x70
4374 #define CPLD_CMD_SET_DONE     0x5E
4375 #define CPLD_CMD_REFRESH      0x79
4376 #define CPLD_PAGE_SIZE        16
4377 #define CPLD_POLL_US          10000  /* status poll interval while busy */
4378 /* Bounds how long a claim can hold the i2c root lock, not image validity:
4379  * far above any bitstream this part takes.
4380  */
4381 #define CPLD_MAX_IMAGE_SZ     (256 * 1024)
4382 #define CPLD_EXIT_CFG_TRIES   3
4383 #define CPLD_ERASE_MS         15000  /* config sector erase, datasheet max */
4384 #define CPLD_ID_MAX_ATTEMPTS  10     /* one per sync_work tick */
4385 
4386 /* Status register bit positions (Lattice LCMXO3LF datasheet) */
4387 #define CPLD_STATUS_DONE   BIT(8)
4388 #define CPLD_STATUS_ENAB   BIT(9)
4389 #define CPLD_STATUS_BUSY   BIT(12)
4390 #define CPLD_STATUS_FAILED BIT(13)
4391 #define CPLD_STATUS_ERR    GENMASK(25, 23)
4392 
4393 /*
4394  * Issue one I2C transaction on the TMC bus: @cmd if not negative, then
4395  * @wlen bytes of @wdata (NULL sends zeros), then @rlen bytes read back.
4396  * The message is built in the scratch buffer from adva_x1_bus_claim(), so
4397  * a run of transfers costs one allocation, not one each.  I2C_M_DMA_SAFE
4398  * is not set: the two halves are not separately aligned, so let the core
4399  * bounce.  Caller holds the claim, hence __i2c_transfer().
4400  */
4401 static int adva_x1_i2c_xfer(struct ptp_ocp *bp, u8 addr, int cmd,
4402 			    const void *wdata, u8 wlen,
4403 			    void *rdata, u8 rlen)
4404 {
4405 	u8 *wbuf, *rbuf;
4406 	struct i2c_adapter *adap;
4407 	struct i2c_msg msgs[2];
4408 	int nmsgs = 0, ret;
4409 	u16 hdr = cmd >= 0;
4410 
4411 	lockdep_assert_held(&bp->cpld_lock);
4412 
4413 	adap = bp->cpld_adap;
4414 	if (!adap || !bp->cpld_buf)
4415 		return -ENODEV;
4416 
4417 	if (hdr + wlen > ADVA_CPLD_XFER_MAX || rlen > ADVA_CPLD_XFER_MAX)
4418 		return -EINVAL;
4419 
4420 	wbuf = bp->cpld_buf;
4421 	rbuf = bp->cpld_buf + ADVA_CPLD_XFER_MAX;
4422 
4423 	if (hdr + wlen) {
4424 		if (hdr)
4425 			wbuf[0] = cmd;
4426 		if (wdata)
4427 			memcpy(wbuf + hdr, wdata, wlen);
4428 		else
4429 			memset(wbuf + hdr, 0, wlen);
4430 		msgs[nmsgs++] = (struct i2c_msg){
4431 			.addr  = addr,
4432 			.flags = 0,
4433 			.len   = hdr + wlen,
4434 			.buf   = wbuf,
4435 		};
4436 	}
4437 	if (rlen) {
4438 		msgs[nmsgs++] = (struct i2c_msg){
4439 			.addr  = addr,
4440 			.flags = I2C_M_RD,
4441 			.len   = rlen,
4442 			.buf   = rbuf,
4443 		};
4444 	}
4445 
4446 	ret = __i2c_transfer(adap, msgs, nmsgs);
4447 	if (ret != nmsgs)
4448 		return (ret < 0) ? ret : -EIO;
4449 
4450 	if (rdata && rlen)
4451 		memcpy(rdata, rbuf, rlen);
4452 
4453 	return 0;
4454 }
4455 
4456 /* Hand the segment back, and wait for the firmware to drop the grant before
4457  * the caller unlocks the adapter: a transfer queued behind us would
4458  * otherwise be clocked out while the controller is still on the TMC bus,
4459  * which is what holding the adapter lock across the grant exists to stop.
4460  */
4461 static int adva_x1_mblaze_release(struct ptp_ocp *bp)
4462 {
4463 	u32 val = 0;
4464 	int i;
4465 
4466 	if (!bp->pps_select)
4467 		return 0;
4468 
4469 	iowrite32(MBLAZE_RELEASE, &bp->pps_select->i2c_bus_ctrl);
4470 	/* Flush the posted write, as the acquire path does. */
4471 	ioread32(&bp->pps_select->i2c_bus_ctrl);
4472 
4473 	for (i = 0; i < MBLAZE_RETRIES; i++) {
4474 		val = ioread32(&bp->pps_select->i2c_bus_ctrl);
4475 		if ((val & MBLAZE_GRANT_MASK) != MBLAZE_GRANT)
4476 			return 0;
4477 		usleep_range(MBLAZE_RETRY_US, MBLAZE_RETRY_US + 1000);
4478 	}
4479 
4480 	dev_err(&bp->pdev->dev,
4481 		"TMC bus still granted after release, i2c_bus_ctrl 0x%08x\n",
4482 		val);
4483 
4484 	return -ETIMEDOUT;
4485 }
4486 
4487 /* Acquire the shared I2C bus from the MicroBlaze firmware.  Returns with no
4488  * request outstanding on failure, so the firmware is never left granting a
4489  * segment to a host that has given up waiting for it.
4490  */
4491 static int adva_x1_mblaze_acquire(struct ptp_ocp *bp)
4492 {
4493 	u32 val;
4494 	int i;
4495 
4496 	if (!bp->pps_select)
4497 		return -ENODEV;
4498 
4499 	/* Drop a request left by a caller that died mid-sequence; cpld_lock
4500 	 * keeps live ones out.  The read back only flushes the posted write.
4501 	 */
4502 	iowrite32(0, &bp->pps_select->i2c_bus_ctrl);
4503 	ioread32(&bp->pps_select->i2c_bus_ctrl);
4504 
4505 	iowrite32(MBLAZE_REQUEST, &bp->pps_select->i2c_bus_ctrl);
4506 	for (i = 0; i < MBLAZE_RETRIES; i++) {
4507 		usleep_range(MBLAZE_RETRY_US, MBLAZE_RETRY_US + 1000);
4508 		val = ioread32(&bp->pps_select->i2c_bus_ctrl);
4509 		if (val == MBLAZE_GRANTED)
4510 			return 0;
4511 	}
4512 
4513 	/* Drop the request we gave up on.  Any error from the hand-back is
4514 	 * subsumed by the -ETIMEDOUT we are already returning.
4515 	 */
4516 	adva_x1_mblaze_release(bp);
4517 	return -ETIMEDOUT;
4518 }
4519 
4520 /* Route the host controller back to the EEPROMs and release the adapter.
4521  * Safe after a failed claim: it also clears a request that was never granted.
4522  *
4523  * The adapter is unlocked even when the hand-back timed out: keeping the
4524  * root lock would stall every other user of the controller for good, with
4525  * no way to recover it.  The error is returned instead, so the operation
4526  * that held the claim fails rather than reporting success over a bus that
4527  * may still be routed to the TMC segment.
4528  */
4529 static int adva_x1_bus_release(struct ptp_ocp *bp)
4530 {
4531 	struct i2c_adapter *adap = bp->cpld_adap;
4532 	int err;
4533 
4534 	if (!adap)
4535 		return 0;
4536 
4537 	err = adva_x1_mblaze_release(bp);
4538 	bp->cpld_adap = NULL;
4539 	kfree(bp->cpld_buf);
4540 	bp->cpld_buf = NULL;
4541 	i2c_unlock_bus(adap, I2C_LOCK_ROOT_ADAPTER);
4542 	i2c_put_adapter(adap);
4543 
4544 	return err;
4545 }
4546 
4547 static int adva_x1_i2c_adap_match(struct device *dev, const void *data)
4548 {
4549 	return !!i2c_verify_adapter(dev);
4550 }
4551 
4552 /*
4553  * Cache the adapter the CPLD hangs off.  ptp_ocp_i2c_notifier_call() misses
4554  * it when the i2c controller driver is already loaded: the adapter is then
4555  * added from inside platform_device_register(), before bp->i2c_ctrl is set.
4556  * Only direct children are searched, so a mux adapter cannot match.
4557  *
4558  * Called from the worker rather than once from probe: device_add() notifies
4559  * before it links the device to its parent, so with asynchronous probing
4560  * both the notifier and a single lookup here can miss the same adapter.
4561  * Retrying costs a short klist walk per tick until one of them succeeds.
4562  */
4563 static void adva_x1_cache_i2c_adap(struct ptp_ocp *bp)
4564 {
4565 	struct device *child;
4566 
4567 	if (!bp->has_cpld || !bp->i2c_ctrl ||
4568 	    READ_ONCE(bp->cpld_i2c_adap_nr) >= 0)
4569 		return;
4570 
4571 	child = device_find_child(&bp->i2c_ctrl->dev, NULL,
4572 				  adva_x1_i2c_adap_match);
4573 	if (!child)
4574 		return;
4575 
4576 	/* Re-test under the lock so this does not overwrite a number the
4577 	 * notifier published meanwhile.  It cannot tell that apart from a
4578 	 * number the notifier has just invalidated, so an adapter removed in
4579 	 * this window can still be cached; adva_x1_bus_claim() rejects it on
4580 	 * the parent check and forgets it, and the next tick looks again.
4581 	 */
4582 	scoped_guard(spinlock, &bp->cpld_adap_lock) {
4583 		if (bp->cpld_i2c_adap_nr < 0)
4584 			bp->cpld_i2c_adap_nr = i2c_verify_adapter(child)->nr;
4585 	}
4586 
4587 	put_device(child);
4588 }
4589 
4590 /*
4591  * Claim the TMC bus.  The adapter lock is held across the handshake to keep
4592  * the EEPROM, nvmem and at24 paths off the controller while it is routed
4593  * away from the EEPROMs; an EEPROM read blocks until the claim is dropped.
4594  */
4595 static int adva_x1_bus_claim(struct ptp_ocp *bp)
4596 {
4597 	struct i2c_adapter *adap;
4598 	int ret;
4599 
4600 	lockdep_assert_held(&bp->cpld_lock);
4601 
4602 	adap = i2c_get_adapter(READ_ONCE(bp->cpld_i2c_adap_nr));
4603 	if (!adap)
4604 		return -ENODEV;
4605 
4606 	/* The number is freed before the notifier clears it, so it can
4607 	 * already be another adapter's.  Check this is still ours, and drop
4608 	 * a number that is not: otherwise every later claim fails the same
4609 	 * way, where forgetting it lets the worker look the adapter up again.
4610 	 */
4611 	if (!bp->i2c_ctrl || adap->dev.parent != &bp->i2c_ctrl->dev) {
4612 		scoped_guard(spinlock, &bp->cpld_adap_lock) {
4613 			if (bp->cpld_i2c_adap_nr == adap->nr)
4614 				bp->cpld_i2c_adap_nr = -1;
4615 		}
4616 		i2c_put_adapter(adap);
4617 		return -ENODEV;
4618 	}
4619 
4620 	/* One scratch buffer per claim rather than per transfer: a claim can
4621 	 * cover many transfers.
4622 	 */
4623 	bp->cpld_buf = kzalloc(2 * ADVA_CPLD_XFER_MAX, GFP_KERNEL);
4624 	if (!bp->cpld_buf) {
4625 		i2c_put_adapter(adap);
4626 		return -ENOMEM;
4627 	}
4628 
4629 	i2c_lock_bus(adap, I2C_LOCK_ROOT_ADAPTER);
4630 	bp->cpld_adap = adap;
4631 
4632 	ret = adva_x1_mblaze_acquire(bp);
4633 	if (ret)
4634 		adva_x1_bus_release(bp);	/* keeps the acquire error */
4635 
4636 	return ret;
4637 }
4638 
4639 /* Select a mux channel, or deselect all with ch < 0 - the power-on state.
4640  * The mux is on the TMC bus, so what it is left set to never affects the
4641  * EEPROM paths.
4642  */
4643 static int adva_x1_mux_select(struct ptp_ocp *bp, int ch)
4644 {
4645 	u8 val = (ch >= 0) ? BIT(ch) : 0;
4646 
4647 	return adva_x1_i2c_xfer(bp, ADVA_MUX_ADDR, val, NULL, 0, NULL, 0);
4648 }
4649 
4650 /*
4651  * Argument bytes that follow an ISC opcode.  Returns NULL with @nargs set
4652  * when the arguments are all zero: adva_x1_i2c_xfer() zeroes the buffer.
4653  *
4654  * EN_CFG_TP, DIS_CFG and REFRESH take two operand bytes here where the SPI
4655  * drivers in drivers/fpga send three.  These are the frames the part on this
4656  * board answers: the sequence below has programmed and refreshed it
4657  * successfully over I2C, so the counts are kept as validated rather than
4658  * aligned with the SPI framing.
4659  */
4660 static const u8 *adva_x1_cpld_args(u8 cmd, u8 *nargs)
4661 {
4662 	static const u8 en_cfg_tp[] = { 0x08, 0x00 };
4663 	/* cfg sector only */
4664 	static const u8 erase_cfg[] = { 0x04, 0x00, 0x00 };
4665 
4666 	switch (cmd) {
4667 	case CPLD_CMD_EN_CFG_TP:
4668 		*nargs = sizeof(en_cfg_tp);
4669 		return en_cfg_tp;
4670 	case CPLD_CMD_ERASE:
4671 		*nargs = sizeof(erase_cfg);
4672 		return erase_cfg;
4673 	case CPLD_CMD_RESET_ADDR:
4674 	case CPLD_CMD_SET_DONE:
4675 		*nargs = 3;
4676 		return NULL;
4677 	case CPLD_CMD_DIS_CFG:
4678 	case CPLD_CMD_REFRESH:
4679 		*nargs = 2;
4680 		return NULL;
4681 	default:
4682 		*nargs = 0;
4683 		return NULL;
4684 	}
4685 }
4686 
4687 /* Send an ISC command with the fixed arguments that belong to it. */
4688 static int adva_x1_cpld_write(struct ptp_ocp *bp, u8 cmd)
4689 {
4690 	const u8 *args;
4691 	u8 nargs;
4692 
4693 	args = adva_x1_cpld_args(cmd, &nargs);
4694 
4695 	return adva_x1_i2c_xfer(bp, ADVA_CPLD_ADDR, cmd, args, nargs, NULL, 0);
4696 }
4697 
4698 /*
4699  * Send a 4-byte command and read back without an intermediate STOP: two
4700  * messages in one transfer is the Lattice write -> repeated START -> read,
4701  * so no protocol-mangling flag is needed.
4702  */
4703 static int adva_x1_cpld_cmd_read(struct ptp_ocp *bp,
4704 				 u32 cmd_be, u8 *out, u8 out_len)
4705 {
4706 	__be32 cmd = cpu_to_be32(cmd_be);
4707 
4708 	return adva_x1_i2c_xfer(bp, ADVA_CPLD_ADDR, -1, &cmd, 4, out, out_len);
4709 }
4710 
4711 static int adva_x1_cpld_read_status(struct ptp_ocp *bp, u32 *status)
4712 {
4713 	u8 buf[4];
4714 	int ret;
4715 
4716 	ret = adva_x1_cpld_cmd_read(bp, CPLD_CMD_READ_STATUS, buf, 4);
4717 	if (ret)
4718 		return ret;
4719 	*status = get_unaligned_be32(buf);
4720 	return 0;
4721 }
4722 
4723 /* Poll the status register until the CPLD goes idle, or @max_ms elapses.
4724  * The deadline is on wall time, so the I2C transactions count against it,
4725  * and the status is read once more after it expires before giving up.
4726  */
4727 static int adva_x1_cpld_wait_ready(struct ptp_ocp *bp, unsigned int max_ms)
4728 {
4729 	u32 status = 0;
4730 	int err = 0, ret;
4731 
4732 	ret = read_poll_timeout(adva_x1_cpld_read_status, err,
4733 				err || (status & CPLD_STATUS_FAILED) ||
4734 				!(status & CPLD_STATUS_BUSY),
4735 				CPLD_POLL_US, max_ms * USEC_PER_MSEC, false,
4736 				bp, &status);
4737 	if (ret)
4738 		return ret;
4739 	/* Keep the transport errno so it reaches userspace as-is; -EIO is
4740 	 * reserved for the CPLD itself reporting FAILED.
4741 	 */
4742 	if (err)
4743 		return err;
4744 	if (status & CPLD_STATUS_FAILED)
4745 		return -EIO;
4746 
4747 	return 0;
4748 }
4749 
4750 /* Wait for BUSY to clear.  Unlike adva_x1_cpld_wait_ready() a latched FAILED
4751  * status is not an error here: this is used on the exit path, where an ISC
4752  * command issued while the part is still erasing or programming may not
4753  * latch, so the operation has to be waited out whatever its outcome.
4754  */
4755 static int adva_x1_cpld_wait_idle(struct ptp_ocp *bp, unsigned int max_ms)
4756 {
4757 	u32 status = 0;
4758 	int err = 0, ret;
4759 
4760 	ret = read_poll_timeout(adva_x1_cpld_read_status, err,
4761 				err || !(status & CPLD_STATUS_BUSY),
4762 				CPLD_POLL_US, max_ms * USEC_PER_MSEC, false,
4763 				bp, &status);
4764 	if (ret)
4765 		return ret;
4766 
4767 	return err;
4768 }
4769 
4770 /* Leave transparent configuration mode.
4771  *
4772  * A DIS_CFG issued while the part is still busy may not latch, so the wait
4773  * has to succeed before the write is believed - an ACKed write after a
4774  * timed-out wait says nothing about whether the part left the mode.  Retry
4775  * a few times rather than leaving it latched on one bad attempt; there is
4776  * no other caller that would try again.
4777  */
4778 static void adva_x1_cpld_exit_config(struct ptp_ocp *bp)
4779 {
4780 	int err, i;
4781 
4782 	if (!bp->cpld_in_config_mode)
4783 		return;
4784 
4785 	for (i = 0; i < CPLD_EXIT_CFG_TRIES; i++) {
4786 		err = adva_x1_cpld_wait_idle(bp, CPLD_ERASE_MS);
4787 		if (!err)
4788 			err = adva_x1_cpld_write(bp, CPLD_CMD_DIS_CFG);
4789 		if (!err) {
4790 			bp->cpld_in_config_mode = false;
4791 			return;
4792 		}
4793 	}
4794 
4795 	dev_err(&bp->pdev->dev, "CPLD left in configuration mode: %d\n", err);
4796 }
4797 
4798 /*
4799  * Read the Lattice device ID and the image USERCODE under one bus claim.
4800  * Done once, off the unprivileged devlink path, which reports the cached
4801  * values.  -EBUSY means cpld_lock is held, so the caller can retry rather
4802  * than wait behind a long CPLD operation.
4803  */
4804 static int adva_x1_cpld_read_id(struct ptp_ocp *bp)
4805 {
4806 	u8 data[4];
4807 	int err, ret;
4808 
4809 	if (!mutex_trylock(&bp->cpld_lock))
4810 		return -EBUSY;
4811 
4812 	ret = adva_x1_bus_claim(bp);
4813 	if (ret)
4814 		goto out;
4815 	/* A select reported as failed may still have been ACKed, so the
4816 	 * deselect runs either way rather than handing the mux back with a
4817 	 * channel possibly left open.
4818 	 */
4819 	ret = adva_x1_mux_select(bp, ADVA_MUX_CHANNEL);
4820 	if (ret)
4821 		goto deselect;
4822 	ret = adva_x1_cpld_cmd_read(bp, CPLD_CMD_READ_ID, data, 4);
4823 	if (ret)
4824 		goto deselect;
4825 	/* Publish the ID before the USERCODE is attempted: a part that does
4826 	 * not answer 0xC0 must not cost us the device ID as well.
4827 	 */
4828 	WRITE_ONCE(bp->cpld_id, get_unaligned_be32(data));
4829 
4830 	ret = adva_x1_cpld_cmd_read(bp, CPLD_CMD_READ_USERCODE, data, 4);
4831 	if (ret)
4832 		goto deselect;
4833 	WRITE_ONCE(bp->cpld_usercode, get_unaligned_be32(data));
4834 	/* Pairs with the acquire in ptp_ocp_devlink_info_get(): the value has
4835 	 * to be visible before the flag that declares it valid.
4836 	 */
4837 	smp_store_release(&bp->cpld_usercode_ok, true);
4838 deselect:
4839 	err = adva_x1_mux_select(bp, -1);
4840 	if (!ret)
4841 		ret = err;
4842 	err = adva_x1_bus_release(bp);
4843 	if (!ret)
4844 		ret = err;
4845 out:
4846 	/* Under cpld_lock, so an operation that resets this bookkeeping
4847 	 * while holding the lock cannot have it overwritten afterwards by a
4848 	 * worker that had already finished reading.
4849 	 */
4850 	if (!ret || ++bp->cpld_id_attempts >= CPLD_ID_MAX_ATTEMPTS)
4851 		bp->cpld_id_tried = true;
4852 	mutex_unlock(&bp->cpld_lock);
4853 	if (ret)
4854 		dev_dbg(&bp->pdev->dev,
4855 			"CPLD device ID unavailable: %d\n", ret);
4856 
4857 	return ret;
4858 }
4859 
4860 /* cpld_status - show the flags set in the TAP CPLD status register. */
4861 static ssize_t
4862 cpld_status_show(struct device *dev, struct device_attribute *attr,
4863 		 char *buf)
4864 {
4865 	struct ptp_ocp *bp = dev_get_drvdata(dev);
4866 	int count = 0;
4867 	u32 st = 0;
4868 	int err, ret;
4869 
4870 	/* A CPLD operation can hold cpld_lock a long time; stay killable. */
4871 	ret = mutex_lock_interruptible(&bp->cpld_lock);
4872 	if (ret)
4873 		return ret;
4874 
4875 	ret = adva_x1_bus_claim(bp);
4876 	if (ret)
4877 		goto out;
4878 	ret = adva_x1_mux_select(bp, ADVA_MUX_CHANNEL);
4879 	if (ret)
4880 		goto deselect;
4881 	ret = adva_x1_cpld_read_status(bp, &st);
4882 deselect:
4883 	err = adva_x1_mux_select(bp, -1);
4884 	if (!ret)
4885 		ret = err;
4886 	err = adva_x1_bus_release(bp);
4887 	if (!ret)
4888 		ret = err;
4889 out:
4890 	mutex_unlock(&bp->cpld_lock);
4891 	if (ret)
4892 		return ret;
4893 
4894 	/* Flags: the names of the bits that are set, nothing when none is,
4895 	 * rather than a value per bit in one file.
4896 	 */
4897 	if (st & CPLD_STATUS_DONE)
4898 		count += sysfs_emit_at(buf, count, "done");
4899 	if (st & CPLD_STATUS_BUSY)
4900 		count += sysfs_emit_at(buf, count, "%sbusy", count ? " " : "");
4901 	if (st & CPLD_STATUS_FAILED)
4902 		count += sysfs_emit_at(buf, count, "%sfailed",
4903 				       count ? " " : "");
4904 
4905 	return count + sysfs_emit_at(buf, count, "\n");
4906 }
4907 static DEVICE_ATTR_ADMIN_RO(cpld_status);
4908 
4909 /*
4910  * Program the CPLD configuration flash from @fw and activate it.  Selected
4911  * by the "fw.cpld" flash component; the SPI flash keeps the default path.
4912  * Runs under cpld_lock with the i2c adapter lock held, so an EEPROM read
4913  * blocks for as long as programming takes.
4914  */
4915 static int adva_x1_cpld_flash(struct ptp_ocp *bp, struct devlink *devlink,
4916 			      const struct firmware *fw,
4917 			      struct netlink_ext_ack *extack)
4918 {
4919 	size_t offset;
4920 	int err, ret;
4921 	u32 st;
4922 
4923 	if (!fw->size || fw->size % CPLD_PAGE_SIZE) {
4924 		NL_SET_ERR_MSG_MOD(extack,
4925 				   "image must be a whole number of 16-byte pages");
4926 		return -EINVAL;
4927 	}
4928 	if (fw->size > CPLD_MAX_IMAGE_SZ) {
4929 		NL_SET_ERR_MSG_MOD(extack, "image too large for this part");
4930 		return -EINVAL;
4931 	}
4932 
4933 	mutex_lock(&bp->cpld_lock);
4934 
4935 	err = adva_x1_bus_claim(bp);
4936 	if (err)
4937 		goto unlock;
4938 	/* A select reported as failed may still have been ACKed, so hand the
4939 	 * mux back deselected either way.
4940 	 */
4941 	err = adva_x1_mux_select(bp, ADVA_MUX_CHANNEL);
4942 	if (err)
4943 		goto deselect;
4944 
4945 	/* A previous flash may have failed to leave configuration mode.  Now
4946 	 * that the bus is claimed again, retry the exit before re-entering;
4947 	 * a no-op when the flag is already clear.
4948 	 */
4949 	adva_x1_cpld_exit_config(bp);
4950 
4951 	/* Set before EN_CFG_TP, not after: the CPLD may have entered config
4952 	 * mode even if the write errors or the wait times out, and only this
4953 	 * makes the exit path send DIS_CFG.  A stray DIS_CFG is harmless;
4954 	 * leaving config mode enabled is not.
4955 	 */
4956 	bp->cpld_in_config_mode = true;
4957 
4958 	err = adva_x1_cpld_write(bp, CPLD_CMD_EN_CFG_TP);
4959 	if (!err)
4960 		err = adva_x1_cpld_wait_ready(bp, 5000);
4961 	if (err)
4962 		goto exit_config;
4963 
4964 	/* Confirm the part really entered configuration mode.  An enable
4965 	 * frame that did not latch leaves an idle part reporting neither
4966 	 * BUSY nor FAILED, the erase and page writes are ignored, and DONE
4967 	 * is still set from the old image - so every later check passes and
4968 	 * the update would be reported successful with the flash untouched.
4969 	 */
4970 	err = adva_x1_cpld_read_status(bp, &st);
4971 	if (err)
4972 		goto exit_config;
4973 	if (!(st & CPLD_STATUS_ENAB)) {
4974 		dev_err(&bp->pdev->dev,
4975 			"CPLD did not enter configuration mode, status 0x%08x\n",
4976 			st);
4977 		NL_SET_ERR_MSG_MOD(extack,
4978 				   "CPLD did not enter configuration mode");
4979 		err = -EIO;
4980 		goto exit_config;
4981 	}
4982 
4983 	devlink_flash_update_status_notify(devlink, "Erasing",
4984 					   ADVA_CPLD_COMPONENT, 0, 0);
4985 	err = adva_x1_cpld_write(bp, CPLD_CMD_ERASE);
4986 	if (!err)
4987 		err = adva_x1_cpld_wait_ready(bp, CPLD_ERASE_MS);
4988 	if (err)
4989 		goto exit_config;
4990 
4991 	/* The old image is gone from here on, so stop reporting its
4992 	 * identity even if the rest of the sequence fails.  Written under
4993 	 * cpld_lock, which adva_x1_cpld_read_id() also holds across its own
4994 	 * bookkeeping, so the worker cannot resurrect any of it.
4995 	 */
4996 	WRITE_ONCE(bp->cpld_id, 0);
4997 	WRITE_ONCE(bp->cpld_usercode_ok, false);
4998 	bp->cpld_id_tried = false;
4999 	bp->cpld_id_attempts = 0;
5000 
5001 	err = adva_x1_cpld_write(bp, CPLD_CMD_RESET_ADDR);
5002 	if (err)
5003 		goto exit_config;
5004 
5005 	for (offset = 0; offset < fw->size; offset += CPLD_PAGE_SIZE) {
5006 		u8 args[3 + CPLD_PAGE_SIZE] = { 0x00, 0x00, 0x01 };
5007 
5008 		/* The loop holds cpld_lock and the i2c root lock for the
5009 		 * whole image, so give a dying task a way out.  The part is
5010 		 * left unconfigured, which is recoverable: fw.cpld stays
5011 		 * advertised so the image can be written again.
5012 		 */
5013 		if (fatal_signal_pending(current)) {
5014 			err = -EINTR;
5015 			goto exit_config;
5016 		}
5017 
5018 		memcpy(&args[3], fw->data + offset, CPLD_PAGE_SIZE);
5019 		err = adva_x1_i2c_xfer(bp, ADVA_CPLD_ADDR, CPLD_CMD_WRITE_PAGE,
5020 				       args, sizeof(args), NULL, 0);
5021 		if (!err)
5022 			err = adva_x1_cpld_wait_ready(bp, 100);
5023 		if (err)
5024 			goto exit_config;
5025 
5026 		if (!(offset % (CPLD_PAGE_SIZE * 64)))
5027 			devlink_flash_update_status_notify(devlink,
5028 							   "Programming",
5029 							   ADVA_CPLD_COMPONENT,
5030 							   offset, fw->size);
5031 	}
5032 	devlink_flash_update_status_notify(devlink, "Programming",
5033 					   ADVA_CPLD_COMPONENT,
5034 					   fw->size, fw->size);
5035 
5036 	err = adva_x1_cpld_write(bp, CPLD_CMD_SET_DONE);
5037 	if (!err)
5038 		err = adva_x1_cpld_wait_ready(bp, 1000);
5039 	if (err)
5040 		goto exit_config;
5041 
5042 	err = adva_x1_cpld_read_status(bp, &st);
5043 	if (err)
5044 		goto exit_config;
5045 	if (!(st & CPLD_STATUS_DONE)) {
5046 		dev_err(&bp->pdev->dev,
5047 			"CPLD SET_DONE left status 0x%08x\n", st);
5048 		NL_SET_ERR_MSG_MOD(extack, "CPLD did not accept the image");
5049 		err = -EIO;
5050 		goto exit_config;
5051 	}
5052 
5053 	devlink_flash_update_status_notify(devlink, "Activating",
5054 					   ADVA_CPLD_COMPONENT, 0, 0);
5055 	err = adva_x1_cpld_write(bp, CPLD_CMD_REFRESH);
5056 	if (err)
5057 		goto exit_config;
5058 
5059 	/* REFRESH reboots the CPLD out of configuration mode, so the exit
5060 	 * path must not send DIS_CFG afterwards even if a check below fails.
5061 	 */
5062 	bp->cpld_in_config_mode = false;
5063 
5064 	/* The new image is already running, so a segment that is not back
5065 	 * yet must not be reported as a failed update: retry the reselect
5066 	 * rather than sampling the mux once at a fixed delay.
5067 	 */
5068 	msleep(1500);
5069 	err = read_poll_timeout(adva_x1_mux_select, err, !err, CPLD_POLL_US,
5070 				3000 * USEC_PER_MSEC, false,
5071 				bp, ADVA_MUX_CHANNEL);
5072 	if (err)
5073 		goto deselect;
5074 
5075 	err = adva_x1_cpld_wait_ready(bp, 3000);
5076 	if (err)
5077 		goto deselect;
5078 
5079 	/* Require DONE set, not busy and no error code, as machxo2-spi.c does
5080 	 * after a refresh: without it a CRC or preamble error reads back as a
5081 	 * successful update.
5082 	 */
5083 	err = adva_x1_cpld_read_status(bp, &st);
5084 	if (err)
5085 		goto deselect;
5086 	if (!(st & CPLD_STATUS_DONE) || (st & CPLD_STATUS_BUSY) ||
5087 	    (st & CPLD_STATUS_ERR)) {
5088 		dev_err(&bp->pdev->dev,
5089 			"CPLD refresh left status 0x%08x\n", st);
5090 		NL_SET_ERR_MSG_MOD(extack, "CPLD did not come back configured");
5091 		err = -EIO;
5092 		goto deselect;
5093 	}
5094 
5095 exit_config:
5096 	adva_x1_cpld_exit_config(bp);
5097 deselect:
5098 	ret = adva_x1_mux_select(bp, -1);
5099 	if (!err)
5100 		err = ret;
5101 	ret = adva_x1_bus_release(bp);
5102 	if (!err)
5103 		err = ret;
5104 unlock:
5105 	mutex_unlock(&bp->cpld_lock);
5106 
5107 	return err;
5108 }
5109 
5110 static struct attribute *adva_timecard_attrs[] = {
5111 	&dev_attr_serialnum.attr,
5112 	&dev_attr_gnss_sync.attr,
5113 	&dev_attr_clock_source.attr,
5114 	&dev_attr_available_clock_sources.attr,
5115 	&dev_attr_sma1.attr,
5116 	&dev_attr_sma2.attr,
5117 	&dev_attr_sma3.attr,
5118 	&dev_attr_sma4.attr,
5119 	&dev_attr_available_sma_inputs.attr,
5120 	&dev_attr_available_sma_outputs.attr,
5121 	&dev_attr_clock_status_drift.attr,
5122 	&dev_attr_clock_status_offset.attr,
5123 	&dev_attr_ts_window_adjust.attr,
5124 	&dev_attr_tod_correction.attr,
5125 	NULL,
5126 };
5127 
5128 static const struct attribute_group adva_timecard_group = {
5129 	.attrs = adva_timecard_attrs,
5130 };
5131 
5132 static const struct ocp_attr_group adva_timecard_groups[] = {
5133 	{ .cap = OCP_CAP_BASIC,	    .group = &adva_timecard_group },
5134 	{ .cap = OCP_CAP_BASIC,	    .group = &ptp_ocp_timecard_tty_group },
5135 	{ .cap = OCP_CAP_SIGNAL,    .group = &fb_timecard_signal0_group },
5136 	{ .cap = OCP_CAP_SIGNAL,    .group = &fb_timecard_signal1_group },
5137 	{ .cap = OCP_CAP_FREQ,	    .group = &fb_timecard_freq0_group },
5138 	{ .cap = OCP_CAP_FREQ,	    .group = &fb_timecard_freq1_group },
5139 	{ },
5140 };
5141 
5142 static struct attribute *adva_timecard_x1_attrs[] = {
5143 	&dev_attr_serialnum.attr,
5144 	&dev_attr_gnss_sync.attr,
5145 	&dev_attr_clock_source.attr,
5146 	&dev_attr_available_clock_sources.attr,
5147 	&dev_attr_sma1.attr,
5148 	&dev_attr_sma2.attr,
5149 	&dev_attr_sma3.attr,
5150 	&dev_attr_sma4.attr,
5151 	&dev_attr_available_sma_inputs.attr,
5152 	&dev_attr_available_sma_outputs.attr,
5153 	&dev_attr_clock_status_drift.attr,
5154 	&dev_attr_clock_status_offset.attr,
5155 	&dev_attr_ts_window_adjust.attr,
5156 	&dev_attr_utc_tai_offset.attr,
5157 	&dev_attr_tod_correction.attr,
5158 	&dev_attr_cpld_status.attr,
5159 	NULL,
5160 };
5161 
5162 static const struct attribute_group adva_timecard_x1_group = {
5163 	.attrs = adva_timecard_x1_attrs,
5164 };
5165 
5166 static const struct ocp_attr_group adva_timecard_x1_groups[] = {
5167 	{ .cap = OCP_CAP_BASIC,	    .group = &adva_timecard_x1_group },
5168 	{ .cap = OCP_CAP_BASIC,	    .group = &ptp_ocp_timecard_tty_group },
5169 	{ .cap = OCP_CAP_SIGNAL,    .group = &fb_timecard_signal0_group },
5170 	{ .cap = OCP_CAP_SIGNAL,    .group = &fb_timecard_signal1_group },
5171 	{ .cap = OCP_CAP_SIGNAL,    .group = &fb_timecard_signal2_group },
5172 	{ .cap = OCP_CAP_SIGNAL,    .group = &fb_timecard_signal3_group },
5173 	{ .cap = OCP_CAP_FREQ,	    .group = &fb_timecard_freq0_group },
5174 	{ .cap = OCP_CAP_FREQ,	    .group = &fb_timecard_freq1_group },
5175 	{ .cap = OCP_CAP_FREQ,	    .group = &fb_timecard_freq2_group },
5176 	{ .cap = OCP_CAP_FREQ,	    .group = &fb_timecard_freq3_group },
5177 	{ },
5178 };
5179 
5180 static void
5181 gpio_input_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit,
5182 	       const char *def)
5183 {
5184 	int i;
5185 
5186 	for (i = 0; i < 4; i++) {
5187 		if (bp->sma[i].mode != SMA_MODE_IN)
5188 			continue;
5189 		if (map[i][0] & (1 << bit)) {
5190 			sprintf(buf, "sma%d", i + 1);
5191 			return;
5192 		}
5193 	}
5194 	if (!def)
5195 		def = "----";
5196 	strcpy(buf, def);
5197 }
5198 
5199 static void
5200 gpio_output_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit)
5201 {
5202 	char *ans = buf;
5203 	int i;
5204 
5205 	strcpy(ans, "----");
5206 	for (i = 0; i < 4; i++) {
5207 		if (bp->sma[i].mode != SMA_MODE_OUT)
5208 			continue;
5209 		if (map[i][1] & (1 << bit))
5210 			ans += sprintf(ans, "sma%d ", i + 1);
5211 	}
5212 }
5213 
5214 static void
5215 _signal_summary_show(struct seq_file *s, struct ptp_ocp *bp, int nr)
5216 {
5217 	struct signal_reg __iomem *reg = bp->signal_out[nr]->mem;
5218 	struct ptp_ocp_signal *signal = &bp->signal[nr];
5219 	char label[16];
5220 	bool on;
5221 	u32 val;
5222 
5223 	on = signal->running;
5224 	sprintf(label, "GEN%d", nr + 1);
5225 	seq_printf(s, "%7s: %s, period:%llu duty:%d%% phase:%llu pol:%d",
5226 		   label, on ? " ON" : "OFF",
5227 		   signal->period, signal->duty, signal->phase,
5228 		   signal->polarity);
5229 
5230 	val = ioread32(&reg->enable);
5231 	seq_printf(s, " [%x", val);
5232 	val = ioread32(&reg->status);
5233 	seq_printf(s, " %x]", val);
5234 
5235 	seq_printf(s, " start:%llu\n", signal->start);
5236 }
5237 
5238 static void
5239 _frequency_summary_show(struct seq_file *s, int nr,
5240 			struct frequency_reg __iomem *reg)
5241 {
5242 	char label[16];
5243 	bool on;
5244 	u32 val;
5245 
5246 	if (!reg)
5247 		return;
5248 
5249 	sprintf(label, "FREQ%d", nr + 1);
5250 	val = ioread32(&reg->ctrl);
5251 	on = val & 1;
5252 	val = (val >> 8) & 0xff;
5253 	seq_printf(s, "%7s: %s, sec:%u",
5254 		   label,
5255 		   on ? " ON" : "OFF",
5256 		   val);
5257 
5258 	val = ioread32(&reg->status);
5259 	if (val & FREQ_STATUS_ERROR)
5260 		seq_printf(s, ", error");
5261 	if (val & FREQ_STATUS_OVERRUN)
5262 		seq_printf(s, ", overrun");
5263 	if (val & FREQ_STATUS_VALID)
5264 		seq_printf(s, ", freq %lu Hz", val & FREQ_STATUS_MASK);
5265 	seq_printf(s, "  reg:%x\n", val);
5266 }
5267 
5268 static int
5269 ptp_ocp_summary_show(struct seq_file *s, void *data)
5270 {
5271 	struct device *dev = s->private;
5272 	struct ptp_system_timestamp sts;
5273 	struct ts_reg __iomem *ts_reg;
5274 	char *buf, *src, *mac_src;
5275 	struct timespec64 ts;
5276 	struct ptp_ocp *bp;
5277 	u16 sma_val[4][2];
5278 	u32 ctrl, val;
5279 	bool on, map;
5280 	int i;
5281 
5282 	buf = (char *)__get_free_page(GFP_KERNEL);
5283 	if (!buf)
5284 		return -ENOMEM;
5285 
5286 	bp = dev_get_drvdata(dev);
5287 
5288 	seq_printf(s, "%7s: /dev/ptp%d\n", "PTP", ptp_clock_index(bp->ptp));
5289 	for (i = 0; i < __PORT_COUNT; i++) {
5290 		if (bp->port[i].line != -1)
5291 			seq_printf(s, "%7s: /dev/ttyS%d\n", ptp_ocp_tty_port_name(i),
5292 				   bp->port[i].line);
5293 	}
5294 
5295 	memset(sma_val, 0xff, sizeof(sma_val));
5296 	if (bp->sma_map1) {
5297 		u32 reg;
5298 
5299 		reg = ioread32(&bp->sma_map1->gpio1);
5300 		sma_val[0][0] = reg & 0xffff;
5301 		sma_val[1][0] = reg >> 16;
5302 
5303 		reg = ioread32(&bp->sma_map1->gpio2);
5304 		sma_val[2][1] = reg & 0xffff;
5305 		sma_val[3][1] = reg >> 16;
5306 
5307 		reg = ioread32(&bp->sma_map2->gpio1);
5308 		sma_val[2][0] = reg & 0xffff;
5309 		sma_val[3][0] = reg >> 16;
5310 
5311 		reg = ioread32(&bp->sma_map2->gpio2);
5312 		sma_val[0][1] = reg & 0xffff;
5313 		sma_val[1][1] = reg >> 16;
5314 	}
5315 
5316 	sma1_show(dev, NULL, buf);
5317 	seq_printf(s, "   sma1: %04x,%04x %s",
5318 		   sma_val[0][0], sma_val[0][1], buf);
5319 
5320 	sma2_show(dev, NULL, buf);
5321 	seq_printf(s, "   sma2: %04x,%04x %s",
5322 		   sma_val[1][0], sma_val[1][1], buf);
5323 
5324 	sma3_show(dev, NULL, buf);
5325 	seq_printf(s, "   sma3: %04x,%04x %s",
5326 		   sma_val[2][0], sma_val[2][1], buf);
5327 
5328 	sma4_show(dev, NULL, buf);
5329 	seq_printf(s, "   sma4: %04x,%04x %s",
5330 		   sma_val[3][0], sma_val[3][1], buf);
5331 
5332 	if (bp->ts0) {
5333 		ts_reg = bp->ts0->mem;
5334 		on = ioread32(&ts_reg->enable);
5335 		src = "GNSS1";
5336 		seq_printf(s, "%7s: %s, src: %s\n", "TS0",
5337 			   on ? " ON" : "OFF", src);
5338 	}
5339 
5340 	if (bp->ts1) {
5341 		ts_reg = bp->ts1->mem;
5342 		on = ioread32(&ts_reg->enable);
5343 		gpio_input_map(buf, bp, sma_val, 2, NULL);
5344 		seq_printf(s, "%7s: %s, src: %s\n", "TS1",
5345 			   on ? " ON" : "OFF", buf);
5346 	}
5347 
5348 	if (bp->ts2) {
5349 		ts_reg = bp->ts2->mem;
5350 		on = ioread32(&ts_reg->enable);
5351 		gpio_input_map(buf, bp, sma_val, 3, NULL);
5352 		seq_printf(s, "%7s: %s, src: %s\n", "TS2",
5353 			   on ? " ON" : "OFF", buf);
5354 	}
5355 
5356 	if (bp->ts3) {
5357 		ts_reg = bp->ts3->mem;
5358 		on = ioread32(&ts_reg->enable);
5359 		gpio_input_map(buf, bp, sma_val, 6, NULL);
5360 		seq_printf(s, "%7s: %s, src: %s\n", "TS3",
5361 			   on ? " ON" : "OFF", buf);
5362 	}
5363 
5364 	if (bp->ts4) {
5365 		ts_reg = bp->ts4->mem;
5366 		on = ioread32(&ts_reg->enable);
5367 		gpio_input_map(buf, bp, sma_val, 7, NULL);
5368 		seq_printf(s, "%7s: %s, src: %s\n", "TS4",
5369 			   on ? " ON" : "OFF", buf);
5370 	}
5371 
5372 	if (bp->pps) {
5373 		ts_reg = bp->pps->mem;
5374 		src = "PHC";
5375 		on = ioread32(&ts_reg->enable);
5376 		map = !!(bp->pps_req_map & OCP_REQ_TIMESTAMP);
5377 		seq_printf(s, "%7s: %s, src: %s\n", "TS5",
5378 			   on && map ? " ON" : "OFF", src);
5379 
5380 		map = !!(bp->pps_req_map & OCP_REQ_PPS);
5381 		seq_printf(s, "%7s: %s, src: %s\n", "PPS",
5382 			   on && map ? " ON" : "OFF", src);
5383 	}
5384 
5385 	if (bp->fw_cap & OCP_CAP_SIGNAL)
5386 		for (i = 0; i < bp->signals_nr; i++)
5387 			_signal_summary_show(s, bp, i);
5388 
5389 	if (bp->fw_cap & OCP_CAP_FREQ)
5390 		for (i = 0; i < bp->freq_in_nr; i++)
5391 			_frequency_summary_show(s, i, bp->freq_in[i]);
5392 
5393 	if (bp->irig_out) {
5394 		ctrl = ioread32(&bp->irig_out->ctrl);
5395 		on = ctrl & IRIG_M_CTRL_ENABLE;
5396 		val = ioread32(&bp->irig_out->status);
5397 		gpio_output_map(buf, bp, sma_val, 4);
5398 		seq_printf(s, "%7s: %s, error: %d, mode %d, out: %s\n", "IRIG",
5399 			   on ? " ON" : "OFF", val, (ctrl >> 16), buf);
5400 	}
5401 
5402 	if (bp->irig_in) {
5403 		on = ioread32(&bp->irig_in->ctrl) & IRIG_S_CTRL_ENABLE;
5404 		val = ioread32(&bp->irig_in->status);
5405 		gpio_input_map(buf, bp, sma_val, 4, NULL);
5406 		seq_printf(s, "%7s: %s, error: %d, src: %s\n", "IRIG in",
5407 			   on ? " ON" : "OFF", val, buf);
5408 	}
5409 
5410 	if (bp->dcf_out) {
5411 		on = ioread32(&bp->dcf_out->ctrl) & DCF_M_CTRL_ENABLE;
5412 		val = ioread32(&bp->dcf_out->status);
5413 		gpio_output_map(buf, bp, sma_val, 5);
5414 		seq_printf(s, "%7s: %s, error: %d, out: %s\n", "DCF",
5415 			   on ? " ON" : "OFF", val, buf);
5416 	}
5417 
5418 	if (bp->dcf_in) {
5419 		on = ioread32(&bp->dcf_in->ctrl) & DCF_S_CTRL_ENABLE;
5420 		val = ioread32(&bp->dcf_in->status);
5421 		gpio_input_map(buf, bp, sma_val, 5, NULL);
5422 		seq_printf(s, "%7s: %s, error: %d, src: %s\n", "DCF in",
5423 			   on ? " ON" : "OFF", val, buf);
5424 	}
5425 
5426 	if (bp->nmea_out) {
5427 		on = ioread32(&bp->nmea_out->ctrl) & 1;
5428 		val = ioread32(&bp->nmea_out->status);
5429 		seq_printf(s, "%7s: %s, error: %d\n", "NMEA",
5430 			   on ? " ON" : "OFF", val);
5431 	}
5432 
5433 	/* compute src for PPS1, used below. */
5434 	if (bp->pps_select) {
5435 		val = ioread32(&bp->pps_select->gpio1);
5436 		src = &buf[80];
5437 		mac_src = "GNSS1";
5438 		if (val & 0x01) {
5439 			gpio_input_map(src, bp, sma_val, 0, NULL);
5440 			mac_src = src;
5441 		} else if (val & 0x02) {
5442 			src = "MAC";
5443 		} else if (val & 0x04) {
5444 			src = "GNSS1";
5445 		} else {
5446 			src = "----";
5447 			mac_src = src;
5448 		}
5449 	} else {
5450 		src = "?";
5451 		mac_src = src;
5452 	}
5453 	seq_printf(s, "MAC PPS1 src: %s\n", mac_src);
5454 
5455 	gpio_input_map(buf, bp, sma_val, 1, "GNSS2");
5456 	seq_printf(s, "MAC PPS2 src: %s\n", buf);
5457 
5458 	/* assumes automatic switchover/selection */
5459 	val = ioread32(&bp->reg->select);
5460 	switch (val >> 16) {
5461 	case 0:
5462 		sprintf(buf, "----");
5463 		break;
5464 	case 2:
5465 		sprintf(buf, "IRIG");
5466 		break;
5467 	case 3:
5468 		sprintf(buf, "%s via PPS1", src);
5469 		break;
5470 	case 6:
5471 		sprintf(buf, "DCF");
5472 		break;
5473 	default:
5474 		strcpy(buf, "unknown");
5475 		break;
5476 	}
5477 	seq_printf(s, "%7s: %s, state: %s\n", "PHC src", buf,
5478 		   bp->sync ? "sync" : "unsynced");
5479 
5480 	if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts)) {
5481 		struct timespec64 sys_ts;
5482 		s64 pre_ns, post_ns, ns;
5483 
5484 		pre_ns = ktime_to_ns(sts.pre_sts.systime);
5485 		post_ns = ktime_to_ns(sts.post_sts.systime);
5486 		ns = (pre_ns + post_ns) / 2;
5487 		ns += (s64)bp->utc_tai_offset * NSEC_PER_SEC;
5488 		sys_ts = ns_to_timespec64(ns);
5489 
5490 		seq_printf(s, "%7s: %ptSp == %ptS TAI\n", "PHC", &ts, &ts);
5491 		seq_printf(s, "%7s: %ptSp == %ptS UTC offset %d\n", "SYS",
5492 			   &sys_ts, &sys_ts, bp->utc_tai_offset);
5493 		seq_printf(s, "%7s: PHC:SYS offset: %lld  window: %lld\n", "",
5494 			   timespec64_to_ns(&ts) - ns,
5495 			   post_ns - pre_ns);
5496 	}
5497 
5498 	free_page((unsigned long)buf);
5499 	return 0;
5500 }
5501 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_summary);
5502 
5503 static int
5504 ptp_ocp_tod_status_show(struct seq_file *s, void *data)
5505 {
5506 	struct device *dev = s->private;
5507 	struct ptp_ocp *bp;
5508 	u32 val;
5509 	int idx;
5510 
5511 	bp = dev_get_drvdata(dev);
5512 
5513 	val = ioread32(&bp->tod->ctrl);
5514 	if (!(val & TOD_CTRL_ENABLE)) {
5515 		seq_printf(s, "TOD Slave disabled\n");
5516 		return 0;
5517 	}
5518 	seq_printf(s, "TOD Slave enabled, Control Register 0x%08X\n", val);
5519 
5520 	idx = val & TOD_CTRL_PROTOCOL ? 4 : 0;
5521 	idx += (val >> 16) & 3;
5522 	seq_printf(s, "Protocol %s\n", ptp_ocp_tod_proto_name(idx));
5523 
5524 	idx = (val >> TOD_CTRL_GNSS_SHIFT) & TOD_CTRL_GNSS_MASK;
5525 	seq_printf(s, "GNSS %s\n", ptp_ocp_tod_gnss_name(idx));
5526 
5527 	val = ioread32(&bp->tod->version);
5528 	seq_printf(s, "TOD Version %d.%d.%d\n",
5529 		val >> 24, (val >> 16) & 0xff, val & 0xffff);
5530 
5531 	val = ioread32(&bp->tod->status);
5532 	seq_printf(s, "Status register: 0x%08X\n", val);
5533 
5534 	val = ioread32(&bp->tod->adj_sec);
5535 	idx = (val & ~INT_MAX) ? -1 : 1;
5536 	idx *= (val & INT_MAX);
5537 	seq_printf(s, "Correction seconds: %d\n", idx);
5538 
5539 	val = ioread32(&bp->tod->utc_status);
5540 	seq_printf(s, "UTC status register: 0x%08X\n", val);
5541 	seq_printf(s, "UTC offset: %ld  valid:%d\n",
5542 		val & TOD_STATUS_UTC_MASK, val & TOD_STATUS_UTC_VALID ? 1 : 0);
5543 	seq_printf(s, "Leap second info valid:%d, Leap second announce %d\n",
5544 		val & TOD_STATUS_LEAP_VALID ? 1 : 0,
5545 		val & TOD_STATUS_LEAP_ANNOUNCE ? 1 : 0);
5546 
5547 	val = ioread32(&bp->tod->leap);
5548 	seq_printf(s, "Time to next leap second (in sec): %d\n", (s32) val);
5549 
5550 	return 0;
5551 }
5552 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_tod_status);
5553 
5554 static struct dentry *ptp_ocp_debugfs_root;
5555 
5556 static void
5557 ptp_ocp_debugfs_add_device(struct ptp_ocp *bp)
5558 {
5559 	struct dentry *d;
5560 
5561 	d = debugfs_create_dir(dev_name(&bp->dev), ptp_ocp_debugfs_root);
5562 	bp->debug_root = d;
5563 	debugfs_create_file("summary", 0444, bp->debug_root,
5564 			    &bp->dev, &ptp_ocp_summary_fops);
5565 	if (bp->tod)
5566 		debugfs_create_file("tod_status", 0444, bp->debug_root,
5567 				    &bp->dev, &ptp_ocp_tod_status_fops);
5568 }
5569 
5570 static void
5571 ptp_ocp_debugfs_remove_device(struct ptp_ocp *bp)
5572 {
5573 	debugfs_remove_recursive(bp->debug_root);
5574 }
5575 
5576 static void
5577 ptp_ocp_debugfs_init(void)
5578 {
5579 	ptp_ocp_debugfs_root = debugfs_create_dir("timecard", NULL);
5580 }
5581 
5582 static void
5583 ptp_ocp_debugfs_fini(void)
5584 {
5585 	debugfs_remove_recursive(ptp_ocp_debugfs_root);
5586 }
5587 
5588 static void
5589 ptp_ocp_dev_release(struct device *dev)
5590 {
5591 	struct ptp_ocp *bp = dev_get_drvdata(dev);
5592 
5593 	mutex_lock(&ptp_ocp_lock);
5594 	idr_remove(&ptp_ocp_idr, bp->id);
5595 	mutex_unlock(&ptp_ocp_lock);
5596 }
5597 
5598 static int
5599 ptp_ocp_device_init(struct ptp_ocp *bp, struct pci_dev *pdev)
5600 {
5601 	int i, err;
5602 
5603 	mutex_lock(&ptp_ocp_lock);
5604 	err = idr_alloc(&ptp_ocp_idr, bp, 0, 0, GFP_KERNEL);
5605 	mutex_unlock(&ptp_ocp_lock);
5606 	if (err < 0) {
5607 		dev_err(&pdev->dev, "idr_alloc failed: %d\n", err);
5608 		return err;
5609 	}
5610 	bp->id = err;
5611 
5612 	bp->ptp_info = ptp_ocp_clock_info;
5613 	spin_lock_init(&bp->lock);
5614 
5615 	for (i = 0; i < __PORT_COUNT; i++)
5616 		bp->port[i].line = -1;
5617 
5618 	bp->pdev = pdev;
5619 
5620 	device_initialize(&bp->dev);
5621 	dev_set_name(&bp->dev, "ocp%d", bp->id);
5622 	bp->dev.class = &timecard_class;
5623 	bp->dev.parent = &pdev->dev;
5624 	bp->dev.release = ptp_ocp_dev_release;
5625 	dev_set_drvdata(&bp->dev, bp);
5626 
5627 	err = device_add(&bp->dev);
5628 	if (err) {
5629 		dev_err(&bp->dev, "device add failed: %d\n", err);
5630 		goto out;
5631 	}
5632 
5633 	pci_set_drvdata(pdev, bp);
5634 
5635 	return 0;
5636 
5637 out:
5638 	put_device(&bp->dev);
5639 	return err;
5640 }
5641 
5642 static void
5643 ptp_ocp_symlink(struct ptp_ocp *bp, struct device *child, const char *link)
5644 {
5645 	struct device *dev = &bp->dev;
5646 
5647 	if (sysfs_create_link(&dev->kobj, &child->kobj, link))
5648 		dev_err(dev, "%s symlink failed\n", link);
5649 }
5650 
5651 static void
5652 ptp_ocp_link_child(struct ptp_ocp *bp, const char *name, const char *link)
5653 {
5654 	struct device *dev, *child;
5655 
5656 	dev = &bp->pdev->dev;
5657 
5658 	child = device_find_child_by_name(dev, name);
5659 	if (!child) {
5660 		dev_err(dev, "Could not find device %s\n", name);
5661 		return;
5662 	}
5663 
5664 	ptp_ocp_symlink(bp, child, link);
5665 	put_device(child);
5666 }
5667 
5668 static int
5669 ptp_ocp_complete(struct ptp_ocp *bp)
5670 {
5671 	struct pps_device *pps;
5672 	char buf[32];
5673 
5674 	sprintf(buf, "ptp%d", ptp_clock_index(bp->ptp));
5675 	ptp_ocp_link_child(bp, buf, "ptp");
5676 
5677 	pps = pps_lookup_dev(bp->ptp);
5678 	if (pps)
5679 		ptp_ocp_symlink(bp, &pps->dev, "pps");
5680 
5681 	ptp_ocp_debugfs_add_device(bp);
5682 
5683 	return 0;
5684 }
5685 
5686 static void
5687 ptp_ocp_phc_info(struct ptp_ocp *bp)
5688 {
5689 	struct timespec64 ts;
5690 	u32 version, select;
5691 
5692 	version = ioread32(&bp->reg->version);
5693 	select = ioread32(&bp->reg->select);
5694 	dev_info(&bp->pdev->dev, "Version %d.%d.%d, clock %s, device ptp%d\n",
5695 		 version >> 24, (version >> 16) & 0xff, version & 0xffff,
5696 		 ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16),
5697 		 ptp_clock_index(bp->ptp));
5698 
5699 	if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, NULL))
5700 		dev_info(&bp->pdev->dev, "Time: %ptSp, %s\n",
5701 			 &ts, bp->sync ? "in-sync" : "UNSYNCED");
5702 }
5703 
5704 static void
5705 ptp_ocp_serial_info(struct device *dev, const char *name, int port, int baud)
5706 {
5707 	if (port != -1)
5708 		dev_info(dev, "%5s: /dev/ttyS%-2d @ %6d\n", name, port, baud);
5709 }
5710 
5711 static void
5712 ptp_ocp_info(struct ptp_ocp *bp)
5713 {
5714 	static int nmea_baud[] = {
5715 		1200, 2400, 4800, 9600, 19200, 38400,
5716 		57600, 115200, 230400, 460800, 921600,
5717 		1000000, 2000000
5718 	};
5719 	struct device *dev = &bp->pdev->dev;
5720 	u32 reg;
5721 	int i;
5722 
5723 	ptp_ocp_phc_info(bp);
5724 
5725 	for (i = 0; i < __PORT_COUNT; i++) {
5726 		if (i == PORT_NMEA && bp->nmea_out && bp->port[PORT_NMEA].line != -1) {
5727 			bp->port[PORT_NMEA].baud = -1;
5728 
5729 			reg = ioread32(&bp->nmea_out->uart_baud);
5730 			if (reg < ARRAY_SIZE(nmea_baud))
5731 				bp->port[PORT_NMEA].baud = nmea_baud[reg];
5732 		}
5733 		ptp_ocp_serial_info(dev, ptp_ocp_tty_port_name(i), bp->port[i].line,
5734 				    bp->port[i].baud);
5735 	}
5736 }
5737 
5738 static void
5739 ptp_ocp_detach_sysfs(struct ptp_ocp *bp)
5740 {
5741 	struct device *dev = &bp->dev;
5742 
5743 	sysfs_remove_link(&dev->kobj, "ptp");
5744 	sysfs_remove_link(&dev->kobj, "pps");
5745 }
5746 
5747 static void
5748 ptp_ocp_detach(struct ptp_ocp *bp)
5749 {
5750 	int i;
5751 
5752 	ptp_ocp_debugfs_remove_device(bp);
5753 	ptp_ocp_detach_sysfs(bp);
5754 	ptp_ocp_attr_group_del(bp);
5755 	timer_delete_sync(&bp->watchdog);
5756 	/* Disable interrupts on all timestampers */
5757 	if (bp->ts0)
5758 		ptp_ocp_ts_enable(bp->ts0, 0, false);
5759 	if (bp->ts1)
5760 		ptp_ocp_ts_enable(bp->ts1, 0, false);
5761 	if (bp->ts2)
5762 		ptp_ocp_ts_enable(bp->ts2, 0, false);
5763 	if (bp->ts3)
5764 		ptp_ocp_ts_enable(bp->ts3, 0, false);
5765 	if (bp->ts4)
5766 		ptp_ocp_ts_enable(bp->ts4, 0, false);
5767 	if (bp->pps)
5768 		ptp_ocp_ts_enable(bp->pps, ~0, false);
5769 	if (bp->ptp)
5770 		ptp_clock_unregister(bp->ptp);
5771 	kfree(bp->ptp_info.pin_config);
5772 	ptp_ocp_unregister_ext(bp->ts0);
5773 	ptp_ocp_unregister_ext(bp->ts1);
5774 	ptp_ocp_unregister_ext(bp->ts2);
5775 	ptp_ocp_unregister_ext(bp->ts3);
5776 	ptp_ocp_unregister_ext(bp->ts4);
5777 	ptp_ocp_unregister_ext(bp->pps);
5778 	for (i = 0; i < 4; i++)
5779 		ptp_ocp_unregister_ext(bp->signal_out[i]);
5780 	for (i = 0; i < __PORT_COUNT; i++)
5781 		if (bp->port[i].line != -1)
5782 			serial8250_unregister_port(bp->port[i].line);
5783 	platform_device_unregister(bp->spi_flash);
5784 	platform_device_unregister(bp->i2c_ctrl);
5785 	if (bp->i2c_clk)
5786 		clk_hw_unregister_fixed_rate(bp->i2c_clk);
5787 	if (bp->n_irqs)
5788 		pci_free_irq_vectors(bp->pdev);
5789 	mutex_destroy(&bp->cpld_lock);
5790 	device_unregister(&bp->dev);
5791 }
5792 
5793 static int
5794 ptp_ocp_dpll_lock_status_get(const struct dpll_device *dpll, void *priv,
5795 			     enum dpll_lock_status *status,
5796 			     enum dpll_lock_status_error *status_error,
5797 			     struct netlink_ext_ack *extack)
5798 {
5799 	struct ptp_ocp *bp = priv;
5800 
5801 	*status = bp->sync ? DPLL_LOCK_STATUS_LOCKED : DPLL_LOCK_STATUS_UNLOCKED;
5802 
5803 	return 0;
5804 }
5805 
5806 static int ptp_ocp_dpll_state_get(const struct dpll_pin *pin, void *pin_priv,
5807 				  const struct dpll_device *dpll, void *priv,
5808 				  enum dpll_pin_state *state,
5809 				  struct netlink_ext_ack *extack)
5810 {
5811 	struct ptp_ocp *bp = priv;
5812 	int idx;
5813 
5814 	if (bp->pps_select) {
5815 		idx = ioread32(&bp->pps_select->gpio1);
5816 		*state = (&bp->sma[idx] == pin_priv) ? DPLL_PIN_STATE_CONNECTED :
5817 						      DPLL_PIN_STATE_SELECTABLE;
5818 		return 0;
5819 	}
5820 	NL_SET_ERR_MSG(extack, "pin selection is not supported on current HW");
5821 	return -EINVAL;
5822 }
5823 
5824 static int ptp_ocp_dpll_mode_get(const struct dpll_device *dpll, void *priv,
5825 				 enum dpll_mode *mode, struct netlink_ext_ack *extack)
5826 {
5827 	*mode = DPLL_MODE_AUTOMATIC;
5828 	return 0;
5829 }
5830 
5831 static int ptp_ocp_dpll_direction_get(const struct dpll_pin *pin,
5832 				      void *pin_priv,
5833 				      const struct dpll_device *dpll,
5834 				      void *priv,
5835 				      enum dpll_pin_direction *direction,
5836 				      struct netlink_ext_ack *extack)
5837 {
5838 	struct ptp_ocp_sma_connector *sma = pin_priv;
5839 
5840 	*direction = sma->mode == SMA_MODE_IN ?
5841 				  DPLL_PIN_DIRECTION_INPUT :
5842 				  DPLL_PIN_DIRECTION_OUTPUT;
5843 	return 0;
5844 }
5845 
5846 static int ptp_ocp_dpll_direction_set(const struct dpll_pin *pin,
5847 				      void *pin_priv,
5848 				      const struct dpll_device *dpll,
5849 				      void *dpll_priv,
5850 				      enum dpll_pin_direction direction,
5851 				      struct netlink_ext_ack *extack)
5852 {
5853 	struct ptp_ocp_sma_connector *sma = pin_priv;
5854 	struct ptp_ocp *bp = dpll_priv;
5855 	enum ptp_ocp_sma_mode mode;
5856 	int sma_nr = (sma - bp->sma);
5857 
5858 	if (sma->fixed_dir)
5859 		return -EOPNOTSUPP;
5860 	mode = direction == DPLL_PIN_DIRECTION_INPUT ?
5861 			    SMA_MODE_IN : SMA_MODE_OUT;
5862 	return ptp_ocp_sma_store_val(bp, 0, mode, sma_nr + 1);
5863 }
5864 
5865 static int ptp_ocp_dpll_frequency_set(const struct dpll_pin *pin,
5866 				      void *pin_priv,
5867 				      const struct dpll_device *dpll,
5868 				      void *dpll_priv, u64 frequency,
5869 				      struct netlink_ext_ack *extack)
5870 {
5871 	struct ptp_ocp_sma_connector *sma = pin_priv;
5872 	struct ptp_ocp *bp = dpll_priv;
5873 	const struct ocp_selector *tbl;
5874 	int sma_nr = (sma - bp->sma);
5875 	int i;
5876 
5877 	if (sma->fixed_fcn)
5878 		return -EOPNOTSUPP;
5879 
5880 	tbl = bp->sma_op->tbl[sma->mode];
5881 	for (i = 0; tbl[i].name; i++)
5882 		if (tbl[i].frequency == frequency)
5883 			return ptp_ocp_sma_store_val(bp, i, sma->mode, sma_nr + 1);
5884 	return -EINVAL;
5885 }
5886 
5887 static int ptp_ocp_dpll_frequency_get(const struct dpll_pin *pin,
5888 				      void *pin_priv,
5889 				      const struct dpll_device *dpll,
5890 				      void *dpll_priv, u64 *frequency,
5891 				      struct netlink_ext_ack *extack)
5892 {
5893 	struct ptp_ocp_sma_connector *sma = pin_priv;
5894 	struct ptp_ocp *bp = dpll_priv;
5895 	const struct ocp_selector *tbl;
5896 	int sma_nr = (sma - bp->sma);
5897 	u32 val;
5898 	int i;
5899 
5900 	val = bp->sma_op->get(bp, sma_nr + 1);
5901 	tbl = bp->sma_op->tbl[sma->mode];
5902 	for (i = 0; tbl[i].name; i++)
5903 		if (val == tbl[i].value) {
5904 			*frequency = tbl[i].frequency;
5905 			return 0;
5906 		}
5907 
5908 	return -EINVAL;
5909 }
5910 
5911 static const struct dpll_device_ops dpll_ops = {
5912 	.lock_status_get = ptp_ocp_dpll_lock_status_get,
5913 	.mode_get = ptp_ocp_dpll_mode_get,
5914 };
5915 
5916 static const struct dpll_pin_ops dpll_pins_ops = {
5917 	.frequency_get = ptp_ocp_dpll_frequency_get,
5918 	.frequency_set = ptp_ocp_dpll_frequency_set,
5919 	.direction_get = ptp_ocp_dpll_direction_get,
5920 	.direction_set = ptp_ocp_dpll_direction_set,
5921 	.state_on_dpll_get = ptp_ocp_dpll_state_get,
5922 };
5923 
5924 static void
5925 ptp_ocp_sync_work(struct work_struct *work)
5926 {
5927 	struct ptp_ocp *bp;
5928 	bool sync;
5929 
5930 	bp = container_of(work, struct ptp_ocp, sync_work.work);
5931 	sync = !!(ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC);
5932 
5933 	if (bp->sync != sync)
5934 		dpll_device_change_ntf(bp->dpll);
5935 
5936 	bp->sync = sync;
5937 
5938 	/* Resolve the adapter here rather than once in probe, where it can
5939 	 * race the adapter's own registration, and read the ID as soon as it
5940 	 * turns up.  A claim can fail transiently - the firmware may not
5941 	 * grant the segment straight after power-up - so adva_x1_cpld_read_id()
5942 	 * retries a bounded number of times before giving up.
5943 	 */
5944 	adva_x1_cache_i2c_adap(bp);
5945 	if (bp->has_cpld && !READ_ONCE(bp->cpld_id_tried) &&
5946 	    READ_ONCE(bp->cpld_i2c_adap_nr) >= 0)
5947 		adva_x1_cpld_read_id(bp);
5948 
5949 	queue_delayed_work(system_power_efficient_wq, &bp->sync_work, HZ);
5950 }
5951 
5952 static int
5953 ptp_ocp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
5954 {
5955 	struct devlink *devlink;
5956 	struct ptp_ocp *bp;
5957 	int err, i;
5958 	u64 clkid;
5959 
5960 	devlink = devlink_alloc(&ptp_ocp_devlink_ops, sizeof(*bp), &pdev->dev);
5961 	if (!devlink) {
5962 		dev_err(&pdev->dev, "devlink_alloc failed\n");
5963 		return -ENOMEM;
5964 	}
5965 
5966 	err = pci_enable_device(pdev);
5967 	if (err) {
5968 		dev_err(&pdev->dev, "pci_enable_device\n");
5969 		goto out_free;
5970 	}
5971 
5972 	bp = devlink_priv(devlink);
5973 	err = ptp_ocp_device_init(bp, pdev);
5974 	if (err)
5975 		goto out_disable;
5976 
5977 	/* Before the first error path that calls ptp_ocp_detach(), so
5978 	 * mutex_destroy() runs on an initialised mutex, and before
5979 	 * ptp_ocp_register_resources(), so this sentinel cannot overwrite an
5980 	 * adapter number the i2c notifier stores during registration.
5981 	 */
5982 	mutex_init(&bp->cpld_lock);
5983 	spin_lock_init(&bp->cpld_adap_lock);
5984 	bp->cpld_i2c_adap_nr = -1;
5985 
5986 	INIT_DELAYED_WORK(&bp->sync_work, ptp_ocp_sync_work);
5987 
5988 	/* compat mode.
5989 	 * Older FPGA firmware only returns 2 irq's.
5990 	 * allow this - if not all of the IRQ's are returned, skip the
5991 	 * extra devices and just register the clock.
5992 	 */
5993 	err = pci_alloc_irq_vectors(pdev, 1, 17, PCI_IRQ_MSI | PCI_IRQ_MSIX);
5994 	if (err < 0) {
5995 		dev_err(&pdev->dev, "alloc_irq_vectors err: %d\n", err);
5996 		goto out;
5997 	}
5998 	bp->n_irqs = err;
5999 	pci_set_master(pdev);
6000 
6001 	err = ptp_ocp_register_resources(bp, id->driver_data);
6002 	if (err)
6003 		goto out;
6004 
6005 	bp->ptp = ptp_clock_register(&bp->ptp_info, &pdev->dev);
6006 	if (IS_ERR(bp->ptp)) {
6007 		err = PTR_ERR(bp->ptp);
6008 		dev_err(&pdev->dev, "ptp_clock_register: %d\n", err);
6009 		bp->ptp = NULL;
6010 		goto out;
6011 	}
6012 
6013 	err = ptp_ocp_complete(bp);
6014 	if (err)
6015 		goto out;
6016 
6017 	ptp_ocp_info(bp);
6018 	devlink_register(devlink);
6019 
6020 	clkid = pci_get_dsn(pdev);
6021 	bp->dpll = dpll_device_get(clkid, 0, THIS_MODULE, &bp->tracker);
6022 	if (IS_ERR(bp->dpll)) {
6023 		err = PTR_ERR(bp->dpll);
6024 		dev_err(&pdev->dev, "dpll_device_alloc failed\n");
6025 		goto out_devlink;
6026 	}
6027 
6028 	err = dpll_device_register(bp->dpll, DPLL_TYPE_PPS, &dpll_ops, bp);
6029 	if (err)
6030 		goto out_dpll_put;
6031 
6032 	for (i = 0; i < OCP_SMA_NUM; i++) {
6033 		bp->sma[i].dpll_pin = dpll_pin_get(clkid, i, THIS_MODULE,
6034 						   &bp->sma[i].dpll_prop,
6035 						   &bp->sma[i].tracker);
6036 		if (IS_ERR(bp->sma[i].dpll_pin)) {
6037 			err = PTR_ERR(bp->sma[i].dpll_pin);
6038 			goto out_dpll;
6039 		}
6040 
6041 		err = dpll_pin_register(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops,
6042 					&bp->sma[i]);
6043 		if (err) {
6044 			dpll_pin_put(bp->sma[i].dpll_pin, &bp->sma[i].tracker);
6045 			goto out_dpll;
6046 		}
6047 	}
6048 	queue_delayed_work(system_power_efficient_wq, &bp->sync_work, HZ);
6049 
6050 	return 0;
6051 out_dpll:
6052 	while (i--) {
6053 		dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]);
6054 		dpll_pin_put(bp->sma[i].dpll_pin, &bp->sma[i].tracker);
6055 	}
6056 	/* dpll_device_register() takes a second reference and stores bp; only
6057 	 * dpll_device_unregister() drops it.  Without this the device stays
6058 	 * visible with a priv pointer into storage devlink_free() will release.
6059 	 */
6060 	dpll_device_unregister(bp->dpll, &dpll_ops, bp);
6061 out_dpll_put:
6062 	dpll_device_put(bp->dpll, &bp->tracker);
6063 out_devlink:
6064 	/* detach() destroys cpld_lock; no devlink op may still reach it */
6065 	devlink_unregister(devlink);
6066 out:
6067 	ptp_ocp_detach(bp);
6068 out_disable:
6069 	pci_disable_device(pdev);
6070 out_free:
6071 	devlink_free(devlink);
6072 	return err;
6073 }
6074 
6075 static void
6076 ptp_ocp_remove(struct pci_dev *pdev)
6077 {
6078 	struct ptp_ocp *bp = pci_get_drvdata(pdev);
6079 	struct devlink *devlink = priv_to_devlink(bp);
6080 	int i;
6081 
6082 	cancel_delayed_work_sync(&bp->sync_work);
6083 	for (i = 0; i < OCP_SMA_NUM; i++) {
6084 		if (bp->sma[i].dpll_pin) {
6085 			dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]);
6086 			dpll_pin_put(bp->sma[i].dpll_pin, &bp->sma[i].tracker);
6087 		}
6088 	}
6089 	dpll_device_unregister(bp->dpll, &dpll_ops, bp);
6090 	dpll_device_put(bp->dpll, &bp->tracker);
6091 	devlink_unregister(devlink);
6092 	ptp_ocp_detach(bp);
6093 	pci_disable_device(pdev);
6094 
6095 	devlink_free(devlink);
6096 }
6097 
6098 static struct pci_driver ptp_ocp_driver = {
6099 	.name		= KBUILD_MODNAME,
6100 	.id_table	= ptp_ocp_pcidev_id,
6101 	.probe		= ptp_ocp_probe,
6102 	.remove		= ptp_ocp_remove,
6103 	.shutdown	= ptp_ocp_remove,
6104 };
6105 
6106 static int
6107 ptp_ocp_i2c_notifier_call(struct notifier_block *nb,
6108 			  unsigned long action, void *data)
6109 {
6110 	struct device *dev, *child = data;
6111 	struct i2c_adapter *adap;
6112 	struct ptp_ocp *bp;
6113 	bool add;
6114 
6115 	switch (action) {
6116 	case BUS_NOTIFY_ADD_DEVICE:
6117 	case BUS_NOTIFY_DEL_DEVICE:
6118 		add = action == BUS_NOTIFY_ADD_DEVICE;
6119 		break;
6120 	default:
6121 		return 0;
6122 	}
6123 
6124 	if (!i2c_verify_adapter(child))
6125 		return 0;
6126 
6127 	dev = child;
6128 	while ((dev = dev->parent))
6129 		if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
6130 			goto found;
6131 	return 0;
6132 
6133 found:
6134 	bp = dev_get_drvdata(dev);
6135 	adap = i2c_verify_adapter(child);
6136 	if (add) {
6137 		ptp_ocp_symlink(bp, child, "i2c");
6138 		/* Only the card's own controller: a mux child added on it
6139 		 * reaches ptp_ocp through the same walk.  Numbers are
6140 		 * recycled, so the claim re-checks the parent itself.
6141 		 */
6142 		if (bp->i2c_ctrl && adap->dev.parent == &bp->i2c_ctrl->dev) {
6143 			scoped_guard(spinlock, &bp->cpld_adap_lock)
6144 				bp->cpld_i2c_adap_nr = adap->nr;
6145 		}
6146 	} else {
6147 		/* invalidate before free, but only for the cached adapter */
6148 		scoped_guard(spinlock, &bp->cpld_adap_lock) {
6149 			if (bp->cpld_i2c_adap_nr == adap->nr)
6150 				bp->cpld_i2c_adap_nr = -1;
6151 		}
6152 		sysfs_remove_link(&bp->dev.kobj, "i2c");
6153 	}
6154 	return 0;
6155 }
6156 
6157 static struct notifier_block ptp_ocp_i2c_notifier = {
6158 	.notifier_call = ptp_ocp_i2c_notifier_call,
6159 };
6160 
6161 static int __init
6162 ptp_ocp_init(void)
6163 {
6164 	const char *what;
6165 	int err;
6166 
6167 	ptp_ocp_debugfs_init();
6168 
6169 	what = "timecard class";
6170 	err = class_register(&timecard_class);
6171 	if (err)
6172 		goto out;
6173 
6174 	what = "i2c notifier";
6175 	err = bus_register_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
6176 	if (err)
6177 		goto out_notifier;
6178 
6179 	what = "ptp_ocp driver";
6180 	err = pci_register_driver(&ptp_ocp_driver);
6181 	if (err)
6182 		goto out_register;
6183 
6184 	return 0;
6185 
6186 out_register:
6187 	bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
6188 out_notifier:
6189 	class_unregister(&timecard_class);
6190 out:
6191 	ptp_ocp_debugfs_fini();
6192 	pr_err(KBUILD_MODNAME ": failed to register %s: %d\n", what, err);
6193 	return err;
6194 }
6195 
6196 static void __exit
6197 ptp_ocp_fini(void)
6198 {
6199 	bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
6200 	pci_unregister_driver(&ptp_ocp_driver);
6201 	class_unregister(&timecard_class);
6202 	ptp_ocp_debugfs_fini();
6203 }
6204 
6205 module_init(ptp_ocp_init);
6206 module_exit(ptp_ocp_fini);
6207 
6208 MODULE_DESCRIPTION("OpenCompute TimeCard driver");
6209 MODULE_LICENSE("GPL v2");
6210