Home
last modified time | relevance | path

Searched refs:slice_mask (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/gpu/drm/i915/gt/
H A Dintel_sseu.c156 sseu->slice_mask |= BIT(0); in gen11_compute_sseu_info()
172 sseu->slice_mask |= BIT(0); in xehp_compute_sseu_info()
333 sseu->slice_mask = BIT(0); in cherryview_sseu_info_init()
388 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; in gen9_sseu_info_init()
407 if (!(sseu->slice_mask & BIT(s))) in gen9_sseu_info_init()
462 !IS_GEN9_LP(i915) && hweight8(sseu->slice_mask) > 1; in gen9_sseu_info_init()
493 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; in bdw_sseu_info_init()
519 if (!(sseu->slice_mask & BIT(s))) in bdw_sseu_info_init()
564 sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1; in bdw_sseu_info_init()
586 sseu->slice_mask = BIT(0); in hsw_sseu_info_init()
[all …]
H A Dintel_sseu_debugfs.c36 sseu->slice_mask = BIT(0); in cherryview_sseu_device_status()
87 sseu->slice_mask |= BIT(s); in gen11_sseu_device_status()
140 sseu->slice_mask |= BIT(s); in gen9_sseu_device_status()
175 sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK; in bdw_sseu_device_status()
177 if (sseu->slice_mask) { in bdw_sseu_device_status()
179 for (s = 0; s < fls(sseu->slice_mask); s++) in bdw_sseu_device_status()
185 for (s = 0; s < fls(sseu->slice_mask); s++) { in bdw_sseu_device_status()
201 sseu->slice_mask); in i915_print_sseu_info()
203 hweight8(sseu->slice_mask)); in i915_print_sseu_info()
H A Dintel_sseu.h69 u8 slice_mask; member
102 u8 slice_mask; member
112 .slice_mask = sseu->slice_mask, in intel_sseu_from_device_info()
H A Dintel_workarounds.c1127 slice = ffs(sseu->slice_mask) - 1; in gen9_wa_init_mcr()
1276 GEM_BUG_ON(hweight8(sseu->slice_mask) > 1); in icl_wa_init_mcr()
1304 unsigned long slice, subslice = 0, slice_mask = 0; in xehp_init_mcr() local
1335 slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask, in xehp_init_mcr()
1349 if (slice_mask & lncf_mask) { in xehp_init_mcr()
1350 slice_mask &= lncf_mask; in xehp_init_mcr()
1355 if (slice_mask & gt->info.mslice_mask) { in xehp_init_mcr()
1356 slice_mask &= gt->info.mslice_mask; in xehp_init_mcr()
1360 slice = __ffs(slice_mask); in xehp_init_mcr()
/linux/arch/powerpc/include/asm/book3s/64/
H A Dmmu-hash.h708 struct slice_mask { struct
721 struct slice_mask mask_64k; argument
723 struct slice_mask mask_4k;
725 struct slice_mask mask_16m;
726 struct slice_mask mask_16g;
H A Dmmu.h169 static inline struct slice_mask *slice_mask_for_size(mm_context_t *ctx, int psize) in slice_mask_for_size()
/linux/drivers/gpu/drm/i915/gem/
H A Di915_gem_context.c1002 if (sseu.slice_mask && !WARN_ON(ce->engine->class != RENDER_CLASS)) in intel_context_set_gem()
1917 if (!user->slice_mask || !user->subslice_mask || in i915_gem_user_to_context_sseu()
1929 if (overflows_type(user->slice_mask, context->slice_mask) || in i915_gem_user_to_context_sseu()
1938 if (user->slice_mask & ~device->slice_mask) in i915_gem_user_to_context_sseu()
1947 context->slice_mask = user->slice_mask; in i915_gem_user_to_context_sseu()
1954 unsigned int hw_s = hweight8(device->slice_mask); in i915_gem_user_to_context_sseu()
1956 unsigned int req_s = hweight8(context->slice_mask); in i915_gem_user_to_context_sseu()
2517 user_sseu.slice_mask = ce->sseu.slice_mask; in get_sseu()
/linux/drivers/crypto/intel/qat/qat_common/
H A Dicp_qat_fw_loader_handle.h19 unsigned int slice_mask; member
/linux/drivers/gpu/drm/i915/
H A Di915_query.c42 BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask)); in fill_topology_info()
47 slice_length = sizeof(sseu->slice_mask); in fill_topology_info()
73 &sseu->slice_mask, slice_length)) in fill_topology_info()
H A Di915_getparam.c173 value = sseu->slice_mask; in i915_getparam_ioctl()
H A Di915_perf.c3168 out_sseu->slice_mask = 0x1; in get_default_sseu_config()
/linux/drivers/gpu/drm/i915/display/
H A Dskl_watermark.c536 hweight8(DISPLAY_INFO(i915)->dbuf.slice_mask); in intel_dbuf_slice_size()
540 skl_ddb_entry_for_slices(struct drm_i915_private *i915, u8 slice_mask, in skl_ddb_entry_for_slices() argument
545 if (!slice_mask) { in skl_ddb_entry_for_slices()
551 ddb->start = (ffs(slice_mask) - 1) * slice_size; in skl_ddb_entry_for_slices()
552 ddb->end = fls(slice_mask) * slice_size; in skl_ddb_entry_for_slices()
558 static unsigned int mbus_ddb_offset(struct drm_i915_private *i915, u8 slice_mask) in mbus_ddb_offset() argument
562 if (slice_mask & (BIT(DBUF_S1) | BIT(DBUF_S2))) in mbus_ddb_offset()
563 slice_mask = BIT(DBUF_S1); in mbus_ddb_offset()
564 else if (slice_mask & (BIT(DBUF_S3) | BIT(DBUF_S4))) in mbus_ddb_offset()
565 slice_mask = BIT(DBUF_S3); in mbus_ddb_offset()
[all …]
H A Dintel_display_device.c660 .dbuf.slice_mask = BIT(DBUF_S1),
810 .dbuf.slice_mask = BIT(DBUF_S1), \
869 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
959 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
1126 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
1304 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
H A Dintel_display_device.h270 u8 slice_mask; member
H A Dintel_display_power.c1069 u8 slice_mask = DISPLAY_INFO(display)->dbuf.slice_mask; in gen9_dbuf_slices_update() local
1072 drm_WARN(display->drm, req_slices & ~slice_mask, in gen9_dbuf_slices_update()
1074 req_slices, slice_mask); in gen9_dbuf_slices_update()
H A Dintel_display.h105 for_each_if(DISPLAY_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice))
/linux/include/uapi/drm/
H A Di915_drm.h2218 __u64 slice_mask; member
/linux/tools/include/uapi/drm/
H A Di915_drm.h2218 __u64 slice_mask; member
/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_ads.c900 hweight8(gt->info.sseu.slice_mask)); in __guc_ads_init()