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Searched refs:shader (Results 1 – 25 of 33) sorted by relevance

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/linux/drivers/gpu/drm/vmwgfx/
H A Dvmwgfx_shader.c45 struct vmw_shader shader; member
167 struct vmw_shader *shader = vmw_res_to_shader(res); in vmw_gb_shader_init() local
186 shader->size = size; in vmw_gb_shader_init()
187 shader->type = type; in vmw_gb_shader_init()
188 shader->num_input_sig = num_input_sig; in vmw_gb_shader_init()
189 shader->num_output_sig = num_output_sig; in vmw_gb_shader_init()
202 struct vmw_shader *shader = vmw_res_to_shader(res); in vmw_gb_shader_create() local
232 cmd->body.type = shader->type; in vmw_gb_shader_create()
233 cmd->body.sizeInBytes = shader->size; in vmw_gb_shader_create()
357 struct vmw_dx_shader *shader = vmw_res_to_dx_shader(res); in vmw_dx_shader_commit_notify() local
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H A Dvmwgfx_binding.h190 struct vmw_ctx_bindinfo_shader shader; member
/linux/drivers/gpu/drm/vc4/
H A Dvc4_validate_shaders.c58 uint64_t *shader; member
189 uint64_t inst = validation_state->shader[validation_state->ip]; in check_tmu_write()
313 uint64_t inst = validation_state->shader[validation_state->ip]; in validate_uniform_address_write()
392 uint64_t inst = validation_state->shader[validation_state->ip]; in check_reg_write()
483 uint64_t inst = validation_state->shader[validation_state->ip]; in track_live_clamps()
558 uint64_t inst = validation_state->shader[validation_state->ip]; in check_instruction_writes()
605 uint64_t inst = validation_state->shader[validation_state->ip]; in check_instruction_reads()
644 uint64_t inst = validation_state->shader[ip]; in vc4_validate_branches()
795 validation_state.shader = shader_obj->vaddr; in vc4_validate_shader()
814 uint64_t inst = validation_state.shader[ip]; in vc4_validate_shader()
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dmcp77.c203 const int shader = cstate->domain[nv_clk_src_shader]; in mcp77_clk_calc() local
239 if (shader == nvkm_clk_read(&clk->base, nv_clk_src_href)) { in mcp77_clk_calc()
242 clock = calc_pll(clk, 0x4020, shader, &N, &M, &P1); in mcp77_clk_calc()
244 out = calc_P((core << 1), shader, &divs); in mcp77_clk_calc()
246 if (abs(shader - out) <= in mcp77_clk_calc()
247 abs(shader - clock) && in mcp77_clk_calc()
H A Dnv50.c375 const int shader = cstate->domain[nv_clk_src_shader]; in nv50_clk_calc() local
474 if (P1-- && shader == (core << 1)) { in nv50_clk_calc()
478 freq = calc_pll(clk, 0x4020, shader, &N, &M, &P1); in nv50_clk_calc()
H A Dbase.c432 cstate->domain[nv_clk_src_shader] = perfE.shader; in nvkm_pstate_new()
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
H A Dperf.c116 info->shader = nvbios_rd16(bios, perf + 0x06) * 1000; in nvbios_perfEp()
117 info->core = info->shader + (signed char) in nvbios_perfEp()
133 info->shader = nvbios_rd16(bios, perf + 0x0a) * 1000; in nvbios_perfEp()
143 info->shader = nvbios_rd16(bios, perf + 0x0a) * 1000; in nvbios_perfEp()
/linux/arch/arm64/boot/dts/qcom/
H A Dsc7180-el2.dtso10 /* We can't and don't need to use zap shader in EL2 as linux can zap the gpu on it's own. */
H A Dsc8280xp-el2.dtso10 /* We can't and don't need to use zap shader in EL2 as linux can zap the gpu on it's own. */
H A Dsc7180-acer-aspire1.dts34 gpu_mem: zap-shader@80840000 {
H A Dmsm8996.dtsi1336 gpu_zap_shader: zap-shader {
H A Dsm8350.dtsi2054 gpu_zap_shader: zap-shader {
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8-ss-gpu0.dtsi21 clock-names = "core", "shader";
H A Dimx8mp.dtsi2308 clock-names = "core", "shader", "bus", "reg";
2383 clock-names = "core", "shader", "bus", "reg";
H A Dfsl-ls1028a.dtsi889 clock-names = "core", "shader", "bus";
/linux/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/
H A Dperf.h12 u32 shader; member
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v10_3_0_cleaner_shader.asm39 shader main label
H A Dgfx_v10_1_10_cleaner_shader.asm38 shader main label
H A Dgfx_v9_4_3_cleaner_shader.asm47 shader main label
/linux/arch/arc/boot/dts/
H A Dhsdk.dts323 clock-names = "bus", "reg", "core", "shader";
/linux/arch/mips/boot/dts/ingenic/
H A Djz4770.dtsi393 clock-names = "bus", "core", "shader";
/linux/Documentation/gpu/rfc/
H A Dcolor_pipeline.rst26 transformations with no, or minimal CPU or shader load. The switch between HW
42 When fixed-function HW is not available the compositor will assemble a shader to
/linux/drivers/gpu/drm/amd/amdkfd/
H A Dcwsr_trap_handler_gfx8.asm152 shader main label
H A Dcwsr_trap_handler_gfx9.asm205 shader main label
H A Dcwsr_trap_handler_gfx10.asm205 shader main label

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