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Searched refs:set_mask (Results 1 – 22 of 22) sorted by relevance

/linux/arch/arm/mm/
H A Dpageattr.c12 pgprot_t set_mask; member
22 pte = set_pte_bit(pte, cdata->set_mask); in change_page_range()
39 pgprot_t set_mask, pgprot_t clear_mask) in __change_memory_common() argument
44 data.set_mask = set_mask; in __change_memory_common()
55 pgprot_t set_mask, pgprot_t clear_mask) in change_memory_common() argument
70 return __change_memory_common(start, size, set_mask, clear_mask); in change_memory_common()
/linux/drivers/hwmon/
H A Dlm75.c88 u16 set_mask; member
139 .set_mask = 0x94C0, /* 8 sample/s, 4 CF, positive polarity */
147 .set_mask = 3 << 5, /* 12-bit mode*/
156 .set_mask = 2 << 5, /* 11-bit mode */
165 .set_mask = 2 << 5, /* 11-bit mode */
174 .set_mask = 2 << 5, /* 11-bit mode */
186 .set_mask = 3 << 5, /* 12-bit mode*/
250 .set_mask = 3 << 5, /* 12-bit mode */
260 .set_mask = 3 << 5, /* 12-bit mode */
269 .set_mask = 3 << 5, /* 12-bit mode */
[all …]
H A Dmax31730.c60 static int max31730_write_config(struct max31730_data *data, u8 set_mask, in max31730_write_config() argument
67 value |= set_mask; in max31730_write_config()
/linux/drivers/gpio/
H A Dgpio-mmio.c156 unsigned long get_mask = 0, set_mask = 0; in gpio_mmio_get_set_multiple() local
161 set_mask = *mask & chip->sdir; in gpio_mmio_get_set_multiple()
164 if (set_mask) in gpio_mmio_get_set_multiple()
165 *bits |= chip->read_reg(chip->reg_set) & set_mask; in gpio_mmio_get_set_multiple()
280 unsigned long *set_mask, in gpio_mmio_multiple_get_masks() argument
286 *set_mask = 0; in gpio_mmio_multiple_get_masks()
291 *set_mask |= gpio_mmio_line2mask(gc, i); in gpio_mmio_multiple_get_masks()
303 unsigned long set_mask, clear_mask; in gpio_mmio_set_multiple_single_reg() local
307 gpio_mmio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); in gpio_mmio_set_multiple_single_reg()
309 chip->sdata |= set_mask; in gpio_mmio_set_multiple_single_reg()
[all …]
H A Dgpio-graniterapids.c76 u32 clear_mask, u32 set_mask) in gnr_gpio_configure_line() argument
89 dw |= set_mask; in gnr_gpio_configure_line()
H A Dgpiolib.c3739 ret = gpiochip_set_multiple(gc, array_info->set_mask, in gpiod_set_array_value_complex()
3744 i = find_first_zero_bit(array_info->set_mask, array_size); in gpiod_set_array_value_complex()
3817 i = find_next_zero_bit(array_info->set_mask, in gpiod_set_array_value_complex()
5125 array_info->set_mask = array_info->get_mask + in gpiod_get_array()
5133 bitmap_set(array_info->set_mask, descs->ndescs, in gpiod_get_array()
5145 __clear_bit(descs->ndescs, array_info->set_mask); in gpiod_get_array()
5163 array_info->set_mask); in gpiod_get_array()
5171 array_info->set_mask); in gpiod_get_array()
5182 *array_info->get_mask, *array_info->set_mask, in gpiod_get_array()
/linux/drivers/net/ethernet/microchip/
H A Dencx24j600-regmap.c195 unsigned int set_mask = mask & val; in regmap_encx24j600_reg_update_bits() local
201 if (set_mask & 0xff) in regmap_encx24j600_reg_update_bits()
202 ret = regmap_encx24j600_sfr_set_bits(ctx, reg, set_mask); in regmap_encx24j600_reg_update_bits()
204 set_mask = (set_mask & 0xff00) >> 8; in regmap_encx24j600_reg_update_bits()
206 if ((set_mask & 0xff) && (ret == 0)) in regmap_encx24j600_reg_update_bits()
207 ret = regmap_encx24j600_sfr_set_bits(ctx, reg + 1, set_mask); in regmap_encx24j600_reg_update_bits()
/linux/drivers/gpib/common/
H A Diblib.c523 int clear_mask, int set_mask, struct gpib_descriptor *desc) in general_ibstatus() argument
550 if (set_mask & CMPL) in general_ibstatus()
639 int ibwait(struct gpib_board *board, int wait_mask, int clear_mask, int set_mask, in ibwait() argument
652 *status = general_ibstatus(board, status_queue, clear_mask, set_mask, desc); in ibwait()
676 if (*status & clear_mask || set_mask) in ibwait()
677 general_ibstatus(board, status_queue, *status & clear_mask, set_mask, NULL); in ibwait()
H A Dgpib_os.c1339 wait_cmd.set_mask, &wait_cmd.ibsta, wait_cmd.usec_timeout, desc); in wait_ioctl()
/linux/drivers/gpib/include/
H A Dgpib_proto.h40 int ibwait(struct gpib_board *board, int wait_mask, int clear_mask, int set_mask,
45 int clear_mask, int set_mask, struct gpib_descriptor *desc);
/linux/drivers/mfd/
H A Dssbi.c93 static int ssbi_wait_mask(struct ssbi *ssbi, u32 set_mask, u32 clr_mask) in ssbi_wait_mask() argument
100 if (((val & set_mask) == set_mask) && ((val & clr_mask) == 0)) in ssbi_wait_mask()
/linux/drivers/mailbox/
H A Dpcc.c79 u64 set_mask; member
206 val |= reg->set_mask; in pcc_chan_reg_read_modify_write()
611 u64 preserve_mask, u64 set_mask, u64 status_mask, char *name) in pcc_chan_reg_init() argument
629 reg->set_mask = set_mask; in pcc_chan_reg_init()
/linux/drivers/net/ethernet/ibm/
H A Dibmveth.h92 unsigned long reset_mask, unsigned long set_mask, in h_illan_attributes() argument
99 reset_mask, set_mask); in h_illan_attributes()
/linux/sound/pci/ice1712/
H A Dice1712.h354 void (*set_mask)(struct snd_ice1712 *ice, unsigned int data); member
407 ice->gpio.set_mask(ice, bits); in snd_ice1712_gpio_set_mask()
435 ice->gpio.set_mask(ice, ice->gpio.saved[1]); in snd_ice1712_restore_gpio_status()
/linux/arch/arm/mach-omap2/
H A Dcommon.h245 extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
/linux/include/uapi/linux/
H A Dgpib_ioctl.h55 __s32 set_mask; member
/linux/net/iucv/
H A Diucv.c306 struct iucv_cmd_set_mask set_mask;
415 parm->set_mask.ipmask = 0xf8; in iucv_allow_cpu()
428 parm->set_mask.ipmask = 0xf8; in iucv_allow_cpu()
307 struct iucv_cmd_set_mask set_mask; global() member
/linux/drivers/infiniband/hw/mlx5/
H A Dfs.c114 static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask) in check_mpls_supp_fields() argument
116 if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) && in check_mpls_supp_fields()
120 if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) && in check_mpls_supp_fields()
124 if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) && in check_mpls_supp_fields()
128 if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) && in check_mpls_supp_fields()
H A Dqp.c70 u32 set_mask; /* raw_qp_set_mask_map */ member
3819 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { in modify_raw_packet_qp_rq()
3866 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) { in modify_raw_packet_qp_sq()
3945 if (raw_qp_param->set_mask & ~MLX5_RAW_QP_RATE_LIMIT) in modify_raw_packet_qp()
3953 if (raw_qp_param->set_mask) in modify_raw_packet_qp()
4372 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; in __mlx5_ib_modify_qp()
4403 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT; in __mlx5_ib_modify_qp()
/linux/drivers/pinctrl/
H A Dpinctrl-at91.c1471 uint32_t set_mask = (*mask & *bits) & BITS_MASK(chip->ngpio); in at91_gpio_set_multiple() local
1474 writel_relaxed(set_mask, pio + PIO_SODR); in at91_gpio_set_multiple()
/linux/drivers/net/ethernet/intel/i40e/
H A Di40e_adminq_cmd.h2259 __le32 set_mask; member
/linux/fs/btrfs/
H A Dioctl.c4179 u64 set_mask = flags & change_mask; in check_feature_bits() local
4182 unsupported = set_mask & ~supported_flags; in check_feature_bits()
4196 disallowed = set_mask & ~safe_set; in check_feature_bits()