| /linux/drivers/net/ethernet/intel/idpf/ |
| H A D | idpf_vf_dev.c | 19 struct libie_ctlq_reg *rx_reg = &cci[LIBIE_CTLQ_TYPE_RX].reg; in idpf_vf_ctlq_reg_init() local
30 rx_reg->head = libie_pci_get_mmio_addr(mmio, VF_ARQH); in idpf_vf_ctlq_reg_init()
31 rx_reg->tail = libie_pci_get_mmio_addr(mmio, VF_ARQT); in idpf_vf_ctlq_reg_init()
32 rx_reg->len = libie_pci_get_mmio_addr(mmio, VF_ARQLEN); in idpf_vf_ctlq_reg_init()
33 rx_reg->addr_high = libie_pci_get_mmio_addr(mmio, VF_ARQBAH); in idpf_vf_ctlq_reg_init()
34 rx_reg->addr_low = libie_pci_get_mmio_addr(mmio, VF_ARQBAL); in idpf_vf_ctlq_reg_init()
35 rx_reg->len_mask = VF_ARQLEN_ARQLEN_M; in idpf_vf_ctlq_reg_init()
36 rx_reg->len_ena_mask = VF_ARQLEN_ARQENABLE_M; in idpf_vf_ctlq_reg_init()
37 rx_reg->head_mask = VF_ARQH_ARQH_M; in idpf_vf_ctlq_reg_init()
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| H A D | idpf_dev.c | 20 struct libie_ctlq_reg *rx_reg = &cci[LIBIE_CTLQ_TYPE_RX].reg; in idpf_ctlq_reg_init() local
31 rx_reg->head = libie_pci_get_mmio_addr(mmio, PF_FW_ARQH); in idpf_ctlq_reg_init()
32 rx_reg->tail = libie_pci_get_mmio_addr(mmio, PF_FW_ARQT); in idpf_ctlq_reg_init()
33 rx_reg->len = libie_pci_get_mmio_addr(mmio, PF_FW_ARQLEN); in idpf_ctlq_reg_init()
34 rx_reg->addr_high = libie_pci_get_mmio_addr(mmio, PF_FW_ARQBAH); in idpf_ctlq_reg_init()
35 rx_reg->addr_low = libie_pci_get_mmio_addr(mmio, PF_FW_ARQBAL); in idpf_ctlq_reg_init()
36 rx_reg->len_mask = PF_FW_ARQLEN_ARQLEN_M; in idpf_ctlq_reg_init()
37 rx_reg->len_ena_mask = PF_FW_ARQLEN_ARQENABLE_M; in idpf_ctlq_reg_init()
38 rx_reg->head_mask = PF_FW_ARQH_ARQH_M; in idpf_ctlq_reg_init()
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| /linux/drivers/mailbox/ |
| H A D | platform_mhu.c | 36 void __iomem *rx_reg; member
52 val = readl_relaxed(mlink->rx_reg + INTR_STAT_OFS); in platform_mhu_rx_interrupt()
58 writel_relaxed(val, mlink->rx_reg + INTR_CLR_OFS); in platform_mhu_rx_interrupt()
140 mhu->mlink[i].rx_reg = mhu->base + platform_mhu_reg[i]; in platform_mhu_probe()
141 mhu->mlink[i].tx_reg = mhu->mlink[i].rx_reg + TX_REG_OFFSET; in platform_mhu_probe()
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| H A D | arm_mhu_db.c | 35 void __iomem *rx_reg; member
78 void __iomem *base = chan_info->mhu->mlink[chan_info->pchan].rx_reg; in mhu_db_mbox_clear_irq()
100 void __iomem *base = mhu->mlink[pchan].rx_reg; in mhu_db_mbox_irq_to_channel()
314 mhu->mlink[i].rx_reg = mhu->base + mhu_reg[i]; in mhu_db_probe()
315 mhu->mlink[i].tx_reg = mhu->mlink[i].rx_reg + TX_REG_OFFSET; in mhu_db_probe()
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| /linux/include/linux/ |
| H A D | pch_dma.h | 21 dma_addr_t rx_reg; member
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| /linux/arch/mips/include/asm/txx9/ |
| H A D | dmac.h | 41 u64 rx_reg; member
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| /linux/drivers/net/ethernet/intel/ice/ |
| H A D | ice_base.c | 845 u32 rx_reg; in ice_vsi_ctrl_one_rx_ring() local
847 rx_reg = rd32(hw, QRX_CTRL(pf_q)); in ice_vsi_ctrl_one_rx_ring()
850 if (ena == !!(rx_reg & QRX_CTRL_QENA_STAT_M)) in ice_vsi_ctrl_one_rx_ring()
855 rx_reg |= QRX_CTRL_QENA_REQ_M; in ice_vsi_ctrl_one_rx_ring()
857 rx_reg &= ~QRX_CTRL_QENA_REQ_M; in ice_vsi_ctrl_one_rx_ring()
858 wr32(hw, QRX_CTRL(pf_q), rx_reg); in ice_vsi_ctrl_one_rx_ring()
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| H A D | ice_lib.c | 2045 u32 rx_reg; in ice_vsi_is_rx_queue_active() local
2049 rx_reg = rd32(hw, QRX_CTRL(pf_q)); in ice_vsi_is_rx_queue_active()
2050 if (rx_reg & QRX_CTRL_QENA_STAT_M) in ice_vsi_is_rx_queue_active()
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| /linux/drivers/dma/ |
| H A D | txx9dmac.c | 845 desc->hwdesc.SAR = ds->rx_reg; in txx9dmac_prep_slave_sg()
854 desc->hwdesc32.SAR = ds->rx_reg; in txx9dmac_prep_slave_sg()
1011 (ds->tx_reg && ds->rx_reg) || (!ds->tx_reg && !ds->rx_reg)) in txx9dmac_alloc_chan_resources()
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| /linux/drivers/net/phy/ |
| H A D | motorcomm.c | 895 u32 rx_reg, tx_reg; in ytphy_rgmii_clk_delay_config() local
899 rx_reg = ytphy_get_delay_reg_value(phydev, "rx-internal-delay-ps", in ytphy_rgmii_clk_delay_config()
912 val |= FIELD_PREP(YT8521_RC1R_RX_DELAY_MASK, rx_reg); in ytphy_rgmii_clk_delay_config()
919 val |= FIELD_PREP(YT8521_RC1R_RX_DELAY_MASK, rx_reg) | in ytphy_rgmii_clk_delay_config()
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| /linux/drivers/net/ethernet/marvell/ |
| H A D | sky2.c | 902 u32 rx_reg; in sky2_mac_init() local
986 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON; in sky2_mac_init()
989 rx_reg |= GMF_RX_OVER_ON; in sky2_mac_init()
991 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg); in sky2_mac_init()
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| /linux/drivers/net/ethernet/intel/i40e/ |
| H A D | i40e_main.c | 4803 u32 rx_reg; in i40e_pf_rxq_wait() local
4806 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q)); in i40e_pf_rxq_wait()
4807 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK)) in i40e_pf_rxq_wait()
4831 u32 rx_reg; in i40e_control_rx_q() local
4835 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q)); in i40e_control_rx_q()
4836 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) == in i40e_control_rx_q()
4837 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1)) in i40e_control_rx_q()
4843 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK)) in i40e_control_rx_q()
4848 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK; in i40e_control_rx_q()
4850 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK; in i40e_control_rx_q()
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