1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #include <linux/vmalloc.h>
6
7 #include "coex.h"
8 #include "debug.h"
9 #include "fw.h"
10 #include "mac.h"
11 #include "pci.h"
12 #include "ps.h"
13 #include "reg.h"
14 #include "sar.h"
15
16 #ifdef CONFIG_RTW89_DEBUGMSG
17 unsigned int rtw89_debug_mask;
18 EXPORT_SYMBOL(rtw89_debug_mask);
19 module_param_named(debug_mask, rtw89_debug_mask, uint, 0644);
20 MODULE_PARM_DESC(debug_mask, "Debugging mask");
21 #endif
22
23 #ifdef CONFIG_RTW89_DEBUGFS
24 struct rtw89_debugfs_priv {
25 struct rtw89_dev *rtwdev;
26 int (*cb_read)(struct seq_file *m, void *v);
27 ssize_t (*cb_write)(struct file *filp, const char __user *buffer,
28 size_t count, loff_t *loff);
29 union {
30 u32 cb_data;
31 struct {
32 u32 addr;
33 u32 len;
34 } read_reg;
35 struct {
36 u32 addr;
37 u32 mask;
38 u8 path;
39 } read_rf;
40 struct {
41 u8 ss_dbg:1;
42 u8 dle_dbg:1;
43 u8 dmac_dbg:1;
44 u8 cmac_dbg:1;
45 u8 dbg_port:1;
46 } dbgpkg_en;
47 struct {
48 u32 start;
49 u32 len;
50 u8 sel;
51 } mac_mem;
52 };
53 };
54
55 struct rtw89_debugfs {
56 struct rtw89_debugfs_priv read_reg;
57 struct rtw89_debugfs_priv write_reg;
58 struct rtw89_debugfs_priv read_rf;
59 struct rtw89_debugfs_priv write_rf;
60 struct rtw89_debugfs_priv rf_reg_dump;
61 struct rtw89_debugfs_priv txpwr_table;
62 struct rtw89_debugfs_priv mac_reg_dump;
63 struct rtw89_debugfs_priv mac_mem_dump;
64 struct rtw89_debugfs_priv mac_dbg_port_dump;
65 struct rtw89_debugfs_priv send_h2c;
66 struct rtw89_debugfs_priv early_h2c;
67 struct rtw89_debugfs_priv fw_crash;
68 struct rtw89_debugfs_priv btc_info;
69 struct rtw89_debugfs_priv btc_manual;
70 struct rtw89_debugfs_priv fw_log_manual;
71 struct rtw89_debugfs_priv phy_info;
72 struct rtw89_debugfs_priv stations;
73 struct rtw89_debugfs_priv disable_dm;
74 };
75
76 static const u16 rtw89_rate_info_bw_to_mhz_map[] = {
77 [RATE_INFO_BW_20] = 20,
78 [RATE_INFO_BW_40] = 40,
79 [RATE_INFO_BW_80] = 80,
80 [RATE_INFO_BW_160] = 160,
81 [RATE_INFO_BW_320] = 320,
82 };
83
rtw89_rate_info_bw_to_mhz(enum rate_info_bw bw)84 static u16 rtw89_rate_info_bw_to_mhz(enum rate_info_bw bw)
85 {
86 if (bw < ARRAY_SIZE(rtw89_rate_info_bw_to_mhz_map))
87 return rtw89_rate_info_bw_to_mhz_map[bw];
88
89 return 0;
90 }
91
rtw89_debugfs_single_show(struct seq_file * m,void * v)92 static int rtw89_debugfs_single_show(struct seq_file *m, void *v)
93 {
94 struct rtw89_debugfs_priv *debugfs_priv = m->private;
95
96 return debugfs_priv->cb_read(m, v);
97 }
98
rtw89_debugfs_single_write(struct file * filp,const char __user * buffer,size_t count,loff_t * loff)99 static ssize_t rtw89_debugfs_single_write(struct file *filp,
100 const char __user *buffer,
101 size_t count, loff_t *loff)
102 {
103 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data;
104
105 return debugfs_priv->cb_write(filp, buffer, count, loff);
106 }
107
rtw89_debugfs_seq_file_write(struct file * filp,const char __user * buffer,size_t count,loff_t * loff)108 static ssize_t rtw89_debugfs_seq_file_write(struct file *filp,
109 const char __user *buffer,
110 size_t count, loff_t *loff)
111 {
112 struct seq_file *seqpriv = (struct seq_file *)filp->private_data;
113 struct rtw89_debugfs_priv *debugfs_priv = seqpriv->private;
114
115 return debugfs_priv->cb_write(filp, buffer, count, loff);
116 }
117
rtw89_debugfs_single_open(struct inode * inode,struct file * filp)118 static int rtw89_debugfs_single_open(struct inode *inode, struct file *filp)
119 {
120 return single_open(filp, rtw89_debugfs_single_show, inode->i_private);
121 }
122
rtw89_debugfs_close(struct inode * inode,struct file * filp)123 static int rtw89_debugfs_close(struct inode *inode, struct file *filp)
124 {
125 return 0;
126 }
127
128 static const struct file_operations file_ops_single_r = {
129 .owner = THIS_MODULE,
130 .open = rtw89_debugfs_single_open,
131 .read = seq_read,
132 .llseek = seq_lseek,
133 .release = single_release,
134 };
135
136 static const struct file_operations file_ops_common_rw = {
137 .owner = THIS_MODULE,
138 .open = rtw89_debugfs_single_open,
139 .release = single_release,
140 .read = seq_read,
141 .llseek = seq_lseek,
142 .write = rtw89_debugfs_seq_file_write,
143 };
144
145 static const struct file_operations file_ops_single_w = {
146 .owner = THIS_MODULE,
147 .write = rtw89_debugfs_single_write,
148 .open = simple_open,
149 .release = rtw89_debugfs_close,
150 };
151
152 static ssize_t
rtw89_debug_priv_read_reg_select(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)153 rtw89_debug_priv_read_reg_select(struct file *filp,
154 const char __user *user_buf,
155 size_t count, loff_t *loff)
156 {
157 struct seq_file *m = (struct seq_file *)filp->private_data;
158 struct rtw89_debugfs_priv *debugfs_priv = m->private;
159 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
160 char buf[32];
161 size_t buf_size;
162 u32 addr, len;
163 int num;
164
165 buf_size = min(count, sizeof(buf) - 1);
166 if (copy_from_user(buf, user_buf, buf_size))
167 return -EFAULT;
168
169 buf[buf_size] = '\0';
170 num = sscanf(buf, "%x %x", &addr, &len);
171 if (num != 2) {
172 rtw89_info(rtwdev, "invalid format: <addr> <len>\n");
173 return -EINVAL;
174 }
175
176 debugfs_priv->read_reg.addr = addr;
177 debugfs_priv->read_reg.len = len;
178
179 rtw89_info(rtwdev, "select read %d bytes from 0x%08x\n", len, addr);
180
181 return count;
182 }
183
rtw89_debug_priv_read_reg_get(struct seq_file * m,void * v)184 static int rtw89_debug_priv_read_reg_get(struct seq_file *m, void *v)
185 {
186 struct rtw89_debugfs_priv *debugfs_priv = m->private;
187 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
188 u32 addr, end, data, k;
189 u32 len;
190
191 len = debugfs_priv->read_reg.len;
192 addr = debugfs_priv->read_reg.addr;
193
194 if (len > 4)
195 goto ndata;
196
197 switch (len) {
198 case 1:
199 data = rtw89_read8(rtwdev, addr);
200 break;
201 case 2:
202 data = rtw89_read16(rtwdev, addr);
203 break;
204 case 4:
205 data = rtw89_read32(rtwdev, addr);
206 break;
207 default:
208 rtw89_info(rtwdev, "invalid read reg len %d\n", len);
209 return -EINVAL;
210 }
211
212 seq_printf(m, "get %d bytes at 0x%08x=0x%08x\n", len, addr, data);
213
214 return 0;
215
216 ndata:
217 end = addr + len;
218
219 for (; addr < end; addr += 16) {
220 seq_printf(m, "%08xh : ", 0x18600000 + addr);
221 for (k = 0; k < 16; k += 4) {
222 data = rtw89_read32(rtwdev, addr + k);
223 seq_printf(m, "%08x ", data);
224 }
225 seq_puts(m, "\n");
226 }
227
228 return 0;
229 }
230
rtw89_debug_priv_write_reg_set(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)231 static ssize_t rtw89_debug_priv_write_reg_set(struct file *filp,
232 const char __user *user_buf,
233 size_t count, loff_t *loff)
234 {
235 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data;
236 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
237 char buf[32];
238 size_t buf_size;
239 u32 addr, val, len;
240 int num;
241
242 buf_size = min(count, sizeof(buf) - 1);
243 if (copy_from_user(buf, user_buf, buf_size))
244 return -EFAULT;
245
246 buf[buf_size] = '\0';
247 num = sscanf(buf, "%x %x %x", &addr, &val, &len);
248 if (num != 3) {
249 rtw89_info(rtwdev, "invalid format: <addr> <val> <len>\n");
250 return -EINVAL;
251 }
252
253 switch (len) {
254 case 1:
255 rtw89_info(rtwdev, "reg write8 0x%08x: 0x%02x\n", addr, val);
256 rtw89_write8(rtwdev, addr, (u8)val);
257 break;
258 case 2:
259 rtw89_info(rtwdev, "reg write16 0x%08x: 0x%04x\n", addr, val);
260 rtw89_write16(rtwdev, addr, (u16)val);
261 break;
262 case 4:
263 rtw89_info(rtwdev, "reg write32 0x%08x: 0x%08x\n", addr, val);
264 rtw89_write32(rtwdev, addr, (u32)val);
265 break;
266 default:
267 rtw89_info(rtwdev, "invalid read write len %d\n", len);
268 break;
269 }
270
271 return count;
272 }
273
274 static ssize_t
rtw89_debug_priv_read_rf_select(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)275 rtw89_debug_priv_read_rf_select(struct file *filp,
276 const char __user *user_buf,
277 size_t count, loff_t *loff)
278 {
279 struct seq_file *m = (struct seq_file *)filp->private_data;
280 struct rtw89_debugfs_priv *debugfs_priv = m->private;
281 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
282 char buf[32];
283 size_t buf_size;
284 u32 addr, mask;
285 u8 path;
286 int num;
287
288 buf_size = min(count, sizeof(buf) - 1);
289 if (copy_from_user(buf, user_buf, buf_size))
290 return -EFAULT;
291
292 buf[buf_size] = '\0';
293 num = sscanf(buf, "%hhd %x %x", &path, &addr, &mask);
294 if (num != 3) {
295 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask>\n");
296 return -EINVAL;
297 }
298
299 if (path >= rtwdev->chip->rf_path_num) {
300 rtw89_info(rtwdev, "wrong rf path\n");
301 return -EINVAL;
302 }
303 debugfs_priv->read_rf.addr = addr;
304 debugfs_priv->read_rf.mask = mask;
305 debugfs_priv->read_rf.path = path;
306
307 rtw89_info(rtwdev, "select read rf path %d from 0x%08x\n", path, addr);
308
309 return count;
310 }
311
rtw89_debug_priv_read_rf_get(struct seq_file * m,void * v)312 static int rtw89_debug_priv_read_rf_get(struct seq_file *m, void *v)
313 {
314 struct rtw89_debugfs_priv *debugfs_priv = m->private;
315 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
316 u32 addr, data, mask;
317 u8 path;
318
319 addr = debugfs_priv->read_rf.addr;
320 mask = debugfs_priv->read_rf.mask;
321 path = debugfs_priv->read_rf.path;
322
323 data = rtw89_read_rf(rtwdev, path, addr, mask);
324
325 seq_printf(m, "path %d, rf register 0x%08x=0x%08x\n", path, addr, data);
326
327 return 0;
328 }
329
rtw89_debug_priv_write_rf_set(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)330 static ssize_t rtw89_debug_priv_write_rf_set(struct file *filp,
331 const char __user *user_buf,
332 size_t count, loff_t *loff)
333 {
334 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data;
335 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
336 char buf[32];
337 size_t buf_size;
338 u32 addr, val, mask;
339 u8 path;
340 int num;
341
342 buf_size = min(count, sizeof(buf) - 1);
343 if (copy_from_user(buf, user_buf, buf_size))
344 return -EFAULT;
345
346 buf[buf_size] = '\0';
347 num = sscanf(buf, "%hhd %x %x %x", &path, &addr, &mask, &val);
348 if (num != 4) {
349 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask> <val>\n");
350 return -EINVAL;
351 }
352
353 if (path >= rtwdev->chip->rf_path_num) {
354 rtw89_info(rtwdev, "wrong rf path\n");
355 return -EINVAL;
356 }
357
358 rtw89_info(rtwdev, "path %d, rf register write 0x%08x=0x%08x (mask = 0x%08x)\n",
359 path, addr, val, mask);
360 rtw89_write_rf(rtwdev, path, addr, mask, val);
361
362 return count;
363 }
364
rtw89_debug_priv_rf_reg_dump_get(struct seq_file * m,void * v)365 static int rtw89_debug_priv_rf_reg_dump_get(struct seq_file *m, void *v)
366 {
367 struct rtw89_debugfs_priv *debugfs_priv = m->private;
368 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
369 const struct rtw89_chip_info *chip = rtwdev->chip;
370 u32 addr, offset, data;
371 u8 path;
372
373 for (path = 0; path < chip->rf_path_num; path++) {
374 seq_printf(m, "RF path %d:\n\n", path);
375 for (addr = 0; addr < 0x100; addr += 4) {
376 seq_printf(m, "0x%08x: ", addr);
377 for (offset = 0; offset < 4; offset++) {
378 data = rtw89_read_rf(rtwdev, path,
379 addr + offset, RFREG_MASK);
380 seq_printf(m, "0x%05x ", data);
381 }
382 seq_puts(m, "\n");
383 }
384 seq_puts(m, "\n");
385 }
386
387 return 0;
388 }
389
390 struct txpwr_ent {
391 bool nested;
392 union {
393 const char *txt;
394 const struct txpwr_ent *ptr;
395 };
396 u8 len;
397 };
398
399 struct txpwr_map {
400 const struct txpwr_ent *ent;
401 u8 size;
402 u32 addr_from;
403 u32 addr_to;
404 u32 addr_to_1ss;
405 };
406
407 #define __GEN_TXPWR_ENT_NESTED(_e) \
408 { .nested = true, .ptr = __txpwr_ent_##_e, \
409 .len = ARRAY_SIZE(__txpwr_ent_##_e) }
410
411 #define __GEN_TXPWR_ENT0(_t) { .len = 0, .txt = _t }
412
413 #define __GEN_TXPWR_ENT2(_t, _e0, _e1) \
414 { .len = 2, .txt = _t "\t- " _e0 " " _e1 }
415
416 #define __GEN_TXPWR_ENT4(_t, _e0, _e1, _e2, _e3) \
417 { .len = 4, .txt = _t "\t- " _e0 " " _e1 " " _e2 " " _e3 }
418
419 #define __GEN_TXPWR_ENT8(_t, _e0, _e1, _e2, _e3, _e4, _e5, _e6, _e7) \
420 { .len = 8, .txt = _t "\t- " \
421 _e0 " " _e1 " " _e2 " " _e3 " " \
422 _e4 " " _e5 " " _e6 " " _e7 }
423
424 static const struct txpwr_ent __txpwr_ent_byr_ax[] = {
425 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "),
426 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "),
427 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "),
428 /* 1NSS */
429 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "),
430 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "),
431 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"),
432 __GEN_TXPWR_ENT4("HEDCM_1NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "),
433 /* 2NSS */
434 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "),
435 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "),
436 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"),
437 __GEN_TXPWR_ENT4("HEDCM_2NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "),
438 };
439
440 static_assert((ARRAY_SIZE(__txpwr_ent_byr_ax) * 4) ==
441 (R_AX_PWR_BY_RATE_MAX - R_AX_PWR_BY_RATE + 4));
442
443 static const struct txpwr_map __txpwr_map_byr_ax = {
444 .ent = __txpwr_ent_byr_ax,
445 .size = ARRAY_SIZE(__txpwr_ent_byr_ax),
446 .addr_from = R_AX_PWR_BY_RATE,
447 .addr_to = R_AX_PWR_BY_RATE_MAX,
448 .addr_to_1ss = R_AX_PWR_BY_RATE_1SS_MAX,
449 };
450
451 static const struct txpwr_ent __txpwr_ent_lmt_ax[] = {
452 /* 1TX */
453 __GEN_TXPWR_ENT2("CCK_1TX_20M ", "NON_BF", "BF"),
454 __GEN_TXPWR_ENT2("CCK_1TX_40M ", "NON_BF", "BF"),
455 __GEN_TXPWR_ENT2("OFDM_1TX ", "NON_BF", "BF"),
456 __GEN_TXPWR_ENT2("MCS_1TX_20M_0 ", "NON_BF", "BF"),
457 __GEN_TXPWR_ENT2("MCS_1TX_20M_1 ", "NON_BF", "BF"),
458 __GEN_TXPWR_ENT2("MCS_1TX_20M_2 ", "NON_BF", "BF"),
459 __GEN_TXPWR_ENT2("MCS_1TX_20M_3 ", "NON_BF", "BF"),
460 __GEN_TXPWR_ENT2("MCS_1TX_20M_4 ", "NON_BF", "BF"),
461 __GEN_TXPWR_ENT2("MCS_1TX_20M_5 ", "NON_BF", "BF"),
462 __GEN_TXPWR_ENT2("MCS_1TX_20M_6 ", "NON_BF", "BF"),
463 __GEN_TXPWR_ENT2("MCS_1TX_20M_7 ", "NON_BF", "BF"),
464 __GEN_TXPWR_ENT2("MCS_1TX_40M_0 ", "NON_BF", "BF"),
465 __GEN_TXPWR_ENT2("MCS_1TX_40M_1 ", "NON_BF", "BF"),
466 __GEN_TXPWR_ENT2("MCS_1TX_40M_2 ", "NON_BF", "BF"),
467 __GEN_TXPWR_ENT2("MCS_1TX_40M_3 ", "NON_BF", "BF"),
468 __GEN_TXPWR_ENT2("MCS_1TX_80M_0 ", "NON_BF", "BF"),
469 __GEN_TXPWR_ENT2("MCS_1TX_80M_1 ", "NON_BF", "BF"),
470 __GEN_TXPWR_ENT2("MCS_1TX_160M ", "NON_BF", "BF"),
471 __GEN_TXPWR_ENT2("MCS_1TX_40M_0p5", "NON_BF", "BF"),
472 __GEN_TXPWR_ENT2("MCS_1TX_40M_2p5", "NON_BF", "BF"),
473 /* 2TX */
474 __GEN_TXPWR_ENT2("CCK_2TX_20M ", "NON_BF", "BF"),
475 __GEN_TXPWR_ENT2("CCK_2TX_40M ", "NON_BF", "BF"),
476 __GEN_TXPWR_ENT2("OFDM_2TX ", "NON_BF", "BF"),
477 __GEN_TXPWR_ENT2("MCS_2TX_20M_0 ", "NON_BF", "BF"),
478 __GEN_TXPWR_ENT2("MCS_2TX_20M_1 ", "NON_BF", "BF"),
479 __GEN_TXPWR_ENT2("MCS_2TX_20M_2 ", "NON_BF", "BF"),
480 __GEN_TXPWR_ENT2("MCS_2TX_20M_3 ", "NON_BF", "BF"),
481 __GEN_TXPWR_ENT2("MCS_2TX_20M_4 ", "NON_BF", "BF"),
482 __GEN_TXPWR_ENT2("MCS_2TX_20M_5 ", "NON_BF", "BF"),
483 __GEN_TXPWR_ENT2("MCS_2TX_20M_6 ", "NON_BF", "BF"),
484 __GEN_TXPWR_ENT2("MCS_2TX_20M_7 ", "NON_BF", "BF"),
485 __GEN_TXPWR_ENT2("MCS_2TX_40M_0 ", "NON_BF", "BF"),
486 __GEN_TXPWR_ENT2("MCS_2TX_40M_1 ", "NON_BF", "BF"),
487 __GEN_TXPWR_ENT2("MCS_2TX_40M_2 ", "NON_BF", "BF"),
488 __GEN_TXPWR_ENT2("MCS_2TX_40M_3 ", "NON_BF", "BF"),
489 __GEN_TXPWR_ENT2("MCS_2TX_80M_0 ", "NON_BF", "BF"),
490 __GEN_TXPWR_ENT2("MCS_2TX_80M_1 ", "NON_BF", "BF"),
491 __GEN_TXPWR_ENT2("MCS_2TX_160M ", "NON_BF", "BF"),
492 __GEN_TXPWR_ENT2("MCS_2TX_40M_0p5", "NON_BF", "BF"),
493 __GEN_TXPWR_ENT2("MCS_2TX_40M_2p5", "NON_BF", "BF"),
494 };
495
496 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ax) * 2) ==
497 (R_AX_PWR_LMT_MAX - R_AX_PWR_LMT + 4));
498
499 static const struct txpwr_map __txpwr_map_lmt_ax = {
500 .ent = __txpwr_ent_lmt_ax,
501 .size = ARRAY_SIZE(__txpwr_ent_lmt_ax),
502 .addr_from = R_AX_PWR_LMT,
503 .addr_to = R_AX_PWR_LMT_MAX,
504 .addr_to_1ss = R_AX_PWR_LMT_1SS_MAX,
505 };
506
507 static const struct txpwr_ent __txpwr_ent_lmt_ru_ax[] = {
508 /* 1TX */
509 __GEN_TXPWR_ENT8("1TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3",
510 "RU26__4", "RU26__5", "RU26__6", "RU26__7"),
511 __GEN_TXPWR_ENT8("1TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3",
512 "RU52__4", "RU52__5", "RU52__6", "RU52__7"),
513 __GEN_TXPWR_ENT8("1TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3",
514 "RU106_4", "RU106_5", "RU106_6", "RU106_7"),
515 /* 2TX */
516 __GEN_TXPWR_ENT8("2TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3",
517 "RU26__4", "RU26__5", "RU26__6", "RU26__7"),
518 __GEN_TXPWR_ENT8("2TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3",
519 "RU52__4", "RU52__5", "RU52__6", "RU52__7"),
520 __GEN_TXPWR_ENT8("2TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3",
521 "RU106_4", "RU106_5", "RU106_6", "RU106_7"),
522 };
523
524 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ru_ax) * 8) ==
525 (R_AX_PWR_RU_LMT_MAX - R_AX_PWR_RU_LMT + 4));
526
527 static const struct txpwr_map __txpwr_map_lmt_ru_ax = {
528 .ent = __txpwr_ent_lmt_ru_ax,
529 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru_ax),
530 .addr_from = R_AX_PWR_RU_LMT,
531 .addr_to = R_AX_PWR_RU_LMT_MAX,
532 .addr_to_1ss = R_AX_PWR_RU_LMT_1SS_MAX,
533 };
534
535 static const struct txpwr_ent __txpwr_ent_byr_mcs_be[] = {
536 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "),
537 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "),
538 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"),
539 __GEN_TXPWR_ENT2("MCS_1SS ", "MCS12 ", "MCS13 \t"),
540 __GEN_TXPWR_ENT4("HEDCM_1SS ", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "),
541 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "),
542 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "),
543 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"),
544 __GEN_TXPWR_ENT2("DLRU_MCS_1SS ", "MCS12 ", "MCS13 \t"),
545 __GEN_TXPWR_ENT4("DLRU_HEDCM_1SS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "),
546 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "),
547 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "),
548 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"),
549 __GEN_TXPWR_ENT2("MCS_2SS ", "MCS12 ", "MCS13 \t"),
550 __GEN_TXPWR_ENT4("HEDCM_2SS ", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "),
551 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "),
552 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "),
553 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"),
554 __GEN_TXPWR_ENT2("DLRU_MCS_2SS ", "MCS12 ", "MCS13 \t"),
555 __GEN_TXPWR_ENT4("DLRU_HEDCM_2SS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "),
556 };
557
558 static const struct txpwr_ent __txpwr_ent_byr_be[] = {
559 __GEN_TXPWR_ENT0("BW20"),
560 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "),
561 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "),
562 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "),
563 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"),
564 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"),
565 __GEN_TXPWR_ENT_NESTED(byr_mcs_be),
566
567 __GEN_TXPWR_ENT0("BW40"),
568 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "),
569 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "),
570 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "),
571 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"),
572 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"),
573 __GEN_TXPWR_ENT_NESTED(byr_mcs_be),
574
575 /* there is no CCK section after BW80 */
576 __GEN_TXPWR_ENT0("BW80"),
577 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "),
578 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "),
579 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"),
580 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"),
581 __GEN_TXPWR_ENT_NESTED(byr_mcs_be),
582
583 __GEN_TXPWR_ENT0("BW160"),
584 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "),
585 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "),
586 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"),
587 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"),
588 __GEN_TXPWR_ENT_NESTED(byr_mcs_be),
589
590 __GEN_TXPWR_ENT0("BW320"),
591 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "),
592 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "),
593 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"),
594 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"),
595 __GEN_TXPWR_ENT_NESTED(byr_mcs_be),
596 };
597
598 static const struct txpwr_map __txpwr_map_byr_be = {
599 .ent = __txpwr_ent_byr_be,
600 .size = ARRAY_SIZE(__txpwr_ent_byr_be),
601 .addr_from = R_BE_PWR_BY_RATE,
602 .addr_to = R_BE_PWR_BY_RATE_MAX,
603 .addr_to_1ss = 0, /* not support */
604 };
605
606 static const struct txpwr_ent __txpwr_ent_lmt_mcs_be[] = {
607 __GEN_TXPWR_ENT2("MCS_20M_0 ", "NON_BF", "BF"),
608 __GEN_TXPWR_ENT2("MCS_20M_1 ", "NON_BF", "BF"),
609 __GEN_TXPWR_ENT2("MCS_20M_2 ", "NON_BF", "BF"),
610 __GEN_TXPWR_ENT2("MCS_20M_3 ", "NON_BF", "BF"),
611 __GEN_TXPWR_ENT2("MCS_20M_4 ", "NON_BF", "BF"),
612 __GEN_TXPWR_ENT2("MCS_20M_5 ", "NON_BF", "BF"),
613 __GEN_TXPWR_ENT2("MCS_20M_6 ", "NON_BF", "BF"),
614 __GEN_TXPWR_ENT2("MCS_20M_7 ", "NON_BF", "BF"),
615 __GEN_TXPWR_ENT2("MCS_20M_8 ", "NON_BF", "BF"),
616 __GEN_TXPWR_ENT2("MCS_20M_9 ", "NON_BF", "BF"),
617 __GEN_TXPWR_ENT2("MCS_20M_10 ", "NON_BF", "BF"),
618 __GEN_TXPWR_ENT2("MCS_20M_11 ", "NON_BF", "BF"),
619 __GEN_TXPWR_ENT2("MCS_20M_12 ", "NON_BF", "BF"),
620 __GEN_TXPWR_ENT2("MCS_20M_13 ", "NON_BF", "BF"),
621 __GEN_TXPWR_ENT2("MCS_20M_14 ", "NON_BF", "BF"),
622 __GEN_TXPWR_ENT2("MCS_20M_15 ", "NON_BF", "BF"),
623 __GEN_TXPWR_ENT2("MCS_40M_0 ", "NON_BF", "BF"),
624 __GEN_TXPWR_ENT2("MCS_40M_1 ", "NON_BF", "BF"),
625 __GEN_TXPWR_ENT2("MCS_40M_2 ", "NON_BF", "BF"),
626 __GEN_TXPWR_ENT2("MCS_40M_3 ", "NON_BF", "BF"),
627 __GEN_TXPWR_ENT2("MCS_40M_4 ", "NON_BF", "BF"),
628 __GEN_TXPWR_ENT2("MCS_40M_5 ", "NON_BF", "BF"),
629 __GEN_TXPWR_ENT2("MCS_40M_6 ", "NON_BF", "BF"),
630 __GEN_TXPWR_ENT2("MCS_40M_7 ", "NON_BF", "BF"),
631 __GEN_TXPWR_ENT2("MCS_80M_0 ", "NON_BF", "BF"),
632 __GEN_TXPWR_ENT2("MCS_80M_1 ", "NON_BF", "BF"),
633 __GEN_TXPWR_ENT2("MCS_80M_2 ", "NON_BF", "BF"),
634 __GEN_TXPWR_ENT2("MCS_80M_3 ", "NON_BF", "BF"),
635 __GEN_TXPWR_ENT2("MCS_160M_0 ", "NON_BF", "BF"),
636 __GEN_TXPWR_ENT2("MCS_160M_1 ", "NON_BF", "BF"),
637 __GEN_TXPWR_ENT2("MCS_320M ", "NON_BF", "BF"),
638 __GEN_TXPWR_ENT2("MCS_40M_0p5", "NON_BF", "BF"),
639 __GEN_TXPWR_ENT2("MCS_40M_2p5", "NON_BF", "BF"),
640 __GEN_TXPWR_ENT2("MCS_40M_4p5", "NON_BF", "BF"),
641 __GEN_TXPWR_ENT2("MCS_40M_6p5", "NON_BF", "BF"),
642 };
643
644 static const struct txpwr_ent __txpwr_ent_lmt_be[] = {
645 __GEN_TXPWR_ENT0("1TX"),
646 __GEN_TXPWR_ENT2("CCK_20M ", "NON_BF", "BF"),
647 __GEN_TXPWR_ENT2("CCK_40M ", "NON_BF", "BF"),
648 __GEN_TXPWR_ENT2("OFDM ", "NON_BF", "BF"),
649 __GEN_TXPWR_ENT_NESTED(lmt_mcs_be),
650
651 __GEN_TXPWR_ENT0("2TX"),
652 __GEN_TXPWR_ENT2("CCK_20M ", "NON_BF", "BF"),
653 __GEN_TXPWR_ENT2("CCK_40M ", "NON_BF", "BF"),
654 __GEN_TXPWR_ENT2("OFDM ", "NON_BF", "BF"),
655 __GEN_TXPWR_ENT_NESTED(lmt_mcs_be),
656 };
657
658 static const struct txpwr_map __txpwr_map_lmt_be = {
659 .ent = __txpwr_ent_lmt_be,
660 .size = ARRAY_SIZE(__txpwr_ent_lmt_be),
661 .addr_from = R_BE_PWR_LMT,
662 .addr_to = R_BE_PWR_LMT_MAX,
663 .addr_to_1ss = 0, /* not support */
664 };
665
666 static const struct txpwr_ent __txpwr_ent_lmt_ru_indexes_be[] = {
667 __GEN_TXPWR_ENT8("RU26 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ",
668 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "),
669 __GEN_TXPWR_ENT8("RU26 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11",
670 "IDX_12", "IDX_13", "IDX_14", "IDX_15"),
671 __GEN_TXPWR_ENT8("RU52 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ",
672 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "),
673 __GEN_TXPWR_ENT8("RU52 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11",
674 "IDX_12", "IDX_13", "IDX_14", "IDX_15"),
675 __GEN_TXPWR_ENT8("RU106 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ",
676 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "),
677 __GEN_TXPWR_ENT8("RU106 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11",
678 "IDX_12", "IDX_13", "IDX_14", "IDX_15"),
679 __GEN_TXPWR_ENT8("RU52_26 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ",
680 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "),
681 __GEN_TXPWR_ENT8("RU52_26 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11",
682 "IDX_12", "IDX_13", "IDX_14", "IDX_15"),
683 __GEN_TXPWR_ENT8("RU106_26", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ",
684 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "),
685 __GEN_TXPWR_ENT8("RU106_26", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11",
686 "IDX_12", "IDX_13", "IDX_14", "IDX_15"),
687 };
688
689 static const struct txpwr_ent __txpwr_ent_lmt_ru_be[] = {
690 __GEN_TXPWR_ENT0("1TX"),
691 __GEN_TXPWR_ENT_NESTED(lmt_ru_indexes_be),
692
693 __GEN_TXPWR_ENT0("2TX"),
694 __GEN_TXPWR_ENT_NESTED(lmt_ru_indexes_be),
695 };
696
697 static const struct txpwr_map __txpwr_map_lmt_ru_be = {
698 .ent = __txpwr_ent_lmt_ru_be,
699 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru_be),
700 .addr_from = R_BE_PWR_RU_LMT,
701 .addr_to = R_BE_PWR_RU_LMT_MAX,
702 .addr_to_1ss = 0, /* not support */
703 };
704
705 static unsigned int
__print_txpwr_ent(struct seq_file * m,const struct txpwr_ent * ent,const s8 * buf,const unsigned int cur)706 __print_txpwr_ent(struct seq_file *m, const struct txpwr_ent *ent,
707 const s8 *buf, const unsigned int cur)
708 {
709 unsigned int cnt, i;
710 char *fmt;
711
712 if (ent->nested) {
713 for (cnt = 0, i = 0; i < ent->len; i++)
714 cnt += __print_txpwr_ent(m, ent->ptr + i, buf,
715 cur + cnt);
716 return cnt;
717 }
718
719 switch (ent->len) {
720 case 0:
721 seq_printf(m, "\t<< %s >>\n", ent->txt);
722 return 0;
723 case 2:
724 fmt = "%s\t| %3d, %3d,\t\tdBm\n";
725 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1]);
726 return 2;
727 case 4:
728 fmt = "%s\t| %3d, %3d, %3d, %3d,\tdBm\n";
729 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1],
730 buf[cur + 2], buf[cur + 3]);
731 return 4;
732 case 8:
733 fmt = "%s\t| %3d, %3d, %3d, %3d, %3d, %3d, %3d, %3d,\tdBm\n";
734 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1],
735 buf[cur + 2], buf[cur + 3], buf[cur + 4],
736 buf[cur + 5], buf[cur + 6], buf[cur + 7]);
737 return 8;
738 default:
739 return 0;
740 }
741 }
742
__print_txpwr_map(struct seq_file * m,struct rtw89_dev * rtwdev,const struct txpwr_map * map)743 static int __print_txpwr_map(struct seq_file *m, struct rtw89_dev *rtwdev,
744 const struct txpwr_map *map)
745 {
746 u8 fct = rtwdev->chip->txpwr_factor_mac;
747 u8 path_num = rtwdev->chip->rf_path_num;
748 unsigned int cur, i;
749 u32 max_valid_addr;
750 u32 val, addr;
751 s8 *buf, tmp;
752 int ret;
753
754 buf = vzalloc(map->addr_to - map->addr_from + 4);
755 if (!buf)
756 return -ENOMEM;
757
758 if (path_num == 1)
759 max_valid_addr = map->addr_to_1ss;
760 else
761 max_valid_addr = map->addr_to;
762
763 if (max_valid_addr == 0)
764 return -EOPNOTSUPP;
765
766 for (addr = map->addr_from; addr <= max_valid_addr; addr += 4) {
767 ret = rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, addr, &val);
768 if (ret)
769 val = MASKDWORD;
770
771 cur = addr - map->addr_from;
772 for (i = 0; i < 4; i++, val >>= 8) {
773 /* signed 7 bits, and reserved BIT(7) */
774 tmp = sign_extend32(val, 6);
775 buf[cur + i] = tmp >> fct;
776 }
777 }
778
779 for (cur = 0, i = 0; i < map->size; i++)
780 cur += __print_txpwr_ent(m, &map->ent[i], buf, cur);
781
782 vfree(buf);
783 return 0;
784 }
785
786 #define case_REGD(_regd) \
787 case RTW89_ ## _regd: \
788 seq_puts(m, #_regd "\n"); \
789 break
790
__print_regd(struct seq_file * m,struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)791 static void __print_regd(struct seq_file *m, struct rtw89_dev *rtwdev,
792 const struct rtw89_chan *chan)
793 {
794 u8 band = chan->band_type;
795 u8 regd = rtw89_regd_get(rtwdev, band);
796
797 switch (regd) {
798 default:
799 seq_printf(m, "UNKNOWN: %d\n", regd);
800 break;
801 case_REGD(WW);
802 case_REGD(ETSI);
803 case_REGD(FCC);
804 case_REGD(MKK);
805 case_REGD(NA);
806 case_REGD(IC);
807 case_REGD(KCC);
808 case_REGD(NCC);
809 case_REGD(CHILE);
810 case_REGD(ACMA);
811 case_REGD(MEXICO);
812 case_REGD(UKRAINE);
813 case_REGD(CN);
814 }
815 }
816
817 #undef case_REGD
818
819 struct dbgfs_txpwr_table {
820 const struct txpwr_map *byr;
821 const struct txpwr_map *lmt;
822 const struct txpwr_map *lmt_ru;
823 };
824
825 static const struct dbgfs_txpwr_table dbgfs_txpwr_table_ax = {
826 .byr = &__txpwr_map_byr_ax,
827 .lmt = &__txpwr_map_lmt_ax,
828 .lmt_ru = &__txpwr_map_lmt_ru_ax,
829 };
830
831 static const struct dbgfs_txpwr_table dbgfs_txpwr_table_be = {
832 .byr = &__txpwr_map_byr_be,
833 .lmt = &__txpwr_map_lmt_be,
834 .lmt_ru = &__txpwr_map_lmt_ru_be,
835 };
836
837 static const struct dbgfs_txpwr_table *dbgfs_txpwr_tables[RTW89_CHIP_GEN_NUM] = {
838 [RTW89_CHIP_AX] = &dbgfs_txpwr_table_ax,
839 [RTW89_CHIP_BE] = &dbgfs_txpwr_table_be,
840 };
841
842 static
rtw89_debug_priv_txpwr_table_get_regd(struct seq_file * m,struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)843 void rtw89_debug_priv_txpwr_table_get_regd(struct seq_file *m,
844 struct rtw89_dev *rtwdev,
845 const struct rtw89_chan *chan)
846 {
847 const struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
848 const struct rtw89_reg_6ghz_tpe *tpe6 = ®ulatory->reg_6ghz_tpe;
849
850 seq_printf(m, "[Chanctx] band %u, ch %u, bw %u\n",
851 chan->band_type, chan->channel, chan->band_width);
852
853 seq_puts(m, "[Regulatory] ");
854 __print_regd(m, rtwdev, chan);
855
856 if (chan->band_type == RTW89_BAND_6G) {
857 seq_printf(m, "[reg6_pwr_type] %u\n", regulatory->reg_6ghz_power);
858
859 if (tpe6->valid)
860 seq_printf(m, "[TPE] %d dBm\n", tpe6->constraint);
861 }
862 }
863
rtw89_debug_priv_txpwr_table_get(struct seq_file * m,void * v)864 static int rtw89_debug_priv_txpwr_table_get(struct seq_file *m, void *v)
865 {
866 struct rtw89_debugfs_priv *debugfs_priv = m->private;
867 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
868 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen;
869 const struct dbgfs_txpwr_table *tbl;
870 const struct rtw89_chan *chan;
871 int ret = 0;
872
873 mutex_lock(&rtwdev->mutex);
874 rtw89_leave_ps_mode(rtwdev);
875 chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
876
877 rtw89_debug_priv_txpwr_table_get_regd(m, rtwdev, chan);
878
879 seq_puts(m, "[SAR]\n");
880 rtw89_print_sar(m, rtwdev, chan->freq);
881
882 seq_puts(m, "[TAS]\n");
883 rtw89_print_tas(m, rtwdev);
884
885 tbl = dbgfs_txpwr_tables[chip_gen];
886 if (!tbl) {
887 ret = -EOPNOTSUPP;
888 goto err;
889 }
890
891 seq_puts(m, "\n[TX power byrate]\n");
892 ret = __print_txpwr_map(m, rtwdev, tbl->byr);
893 if (ret)
894 goto err;
895
896 seq_puts(m, "\n[TX power limit]\n");
897 ret = __print_txpwr_map(m, rtwdev, tbl->lmt);
898 if (ret)
899 goto err;
900
901 seq_puts(m, "\n[TX power limit_ru]\n");
902 ret = __print_txpwr_map(m, rtwdev, tbl->lmt_ru);
903 if (ret)
904 goto err;
905
906 err:
907 mutex_unlock(&rtwdev->mutex);
908 return ret;
909 }
910
911 static ssize_t
rtw89_debug_priv_mac_reg_dump_select(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)912 rtw89_debug_priv_mac_reg_dump_select(struct file *filp,
913 const char __user *user_buf,
914 size_t count, loff_t *loff)
915 {
916 struct seq_file *m = (struct seq_file *)filp->private_data;
917 struct rtw89_debugfs_priv *debugfs_priv = m->private;
918 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
919 const struct rtw89_chip_info *chip = rtwdev->chip;
920 char buf[32];
921 size_t buf_size;
922 int sel;
923 int ret;
924
925 buf_size = min(count, sizeof(buf) - 1);
926 if (copy_from_user(buf, user_buf, buf_size))
927 return -EFAULT;
928
929 buf[buf_size] = '\0';
930 ret = kstrtoint(buf, 0, &sel);
931 if (ret)
932 return ret;
933
934 if (sel < RTW89_DBG_SEL_MAC_00 || sel > RTW89_DBG_SEL_RFC) {
935 rtw89_info(rtwdev, "invalid args: %d\n", sel);
936 return -EINVAL;
937 }
938
939 if (sel == RTW89_DBG_SEL_MAC_30 && chip->chip_id != RTL8852C) {
940 rtw89_info(rtwdev, "sel %d is address hole on chip %d\n", sel,
941 chip->chip_id);
942 return -EINVAL;
943 }
944
945 debugfs_priv->cb_data = sel;
946 rtw89_info(rtwdev, "select mac page dump %d\n", debugfs_priv->cb_data);
947
948 return count;
949 }
950
951 #define RTW89_MAC_PAGE_SIZE 0x100
952
rtw89_debug_priv_mac_reg_dump_get(struct seq_file * m,void * v)953 static int rtw89_debug_priv_mac_reg_dump_get(struct seq_file *m, void *v)
954 {
955 struct rtw89_debugfs_priv *debugfs_priv = m->private;
956 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
957 enum rtw89_debug_mac_reg_sel reg_sel = debugfs_priv->cb_data;
958 u32 start, end;
959 u32 i, j, k, page;
960 u32 val;
961
962 switch (reg_sel) {
963 case RTW89_DBG_SEL_MAC_00:
964 seq_puts(m, "Debug selected MAC page 0x00\n");
965 start = 0x000;
966 end = 0x014;
967 break;
968 case RTW89_DBG_SEL_MAC_30:
969 seq_puts(m, "Debug selected MAC page 0x30\n");
970 start = 0x030;
971 end = 0x033;
972 break;
973 case RTW89_DBG_SEL_MAC_40:
974 seq_puts(m, "Debug selected MAC page 0x40\n");
975 start = 0x040;
976 end = 0x07f;
977 break;
978 case RTW89_DBG_SEL_MAC_80:
979 seq_puts(m, "Debug selected MAC page 0x80\n");
980 start = 0x080;
981 end = 0x09f;
982 break;
983 case RTW89_DBG_SEL_MAC_C0:
984 seq_puts(m, "Debug selected MAC page 0xc0\n");
985 start = 0x0c0;
986 end = 0x0df;
987 break;
988 case RTW89_DBG_SEL_MAC_E0:
989 seq_puts(m, "Debug selected MAC page 0xe0\n");
990 start = 0x0e0;
991 end = 0x0ff;
992 break;
993 case RTW89_DBG_SEL_BB:
994 seq_puts(m, "Debug selected BB register\n");
995 start = 0x100;
996 end = 0x17f;
997 break;
998 case RTW89_DBG_SEL_IQK:
999 seq_puts(m, "Debug selected IQK register\n");
1000 start = 0x180;
1001 end = 0x1bf;
1002 break;
1003 case RTW89_DBG_SEL_RFC:
1004 seq_puts(m, "Debug selected RFC register\n");
1005 start = 0x1c0;
1006 end = 0x1ff;
1007 break;
1008 default:
1009 seq_puts(m, "Selected invalid register page\n");
1010 return -EINVAL;
1011 }
1012
1013 for (i = start; i <= end; i++) {
1014 page = i << 8;
1015 for (j = page; j < page + RTW89_MAC_PAGE_SIZE; j += 16) {
1016 seq_printf(m, "%08xh : ", 0x18600000 + j);
1017 for (k = 0; k < 4; k++) {
1018 val = rtw89_read32(rtwdev, j + (k << 2));
1019 seq_printf(m, "%08x ", val);
1020 }
1021 seq_puts(m, "\n");
1022 }
1023 }
1024
1025 return 0;
1026 }
1027
1028 static ssize_t
rtw89_debug_priv_mac_mem_dump_select(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)1029 rtw89_debug_priv_mac_mem_dump_select(struct file *filp,
1030 const char __user *user_buf,
1031 size_t count, loff_t *loff)
1032 {
1033 struct seq_file *m = (struct seq_file *)filp->private_data;
1034 struct rtw89_debugfs_priv *debugfs_priv = m->private;
1035 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
1036 char buf[32];
1037 size_t buf_size;
1038 u32 sel, start_addr, len;
1039 int num;
1040
1041 buf_size = min(count, sizeof(buf) - 1);
1042 if (copy_from_user(buf, user_buf, buf_size))
1043 return -EFAULT;
1044
1045 buf[buf_size] = '\0';
1046 num = sscanf(buf, "%x %x %x", &sel, &start_addr, &len);
1047 if (num != 3) {
1048 rtw89_info(rtwdev, "invalid format: <sel> <start> <len>\n");
1049 return -EINVAL;
1050 }
1051
1052 debugfs_priv->mac_mem.sel = sel;
1053 debugfs_priv->mac_mem.start = start_addr;
1054 debugfs_priv->mac_mem.len = len;
1055
1056 rtw89_info(rtwdev, "select mem %d start %d len %d\n",
1057 sel, start_addr, len);
1058
1059 return count;
1060 }
1061
rtw89_debug_dump_mac_mem(struct seq_file * m,struct rtw89_dev * rtwdev,u8 sel,u32 start_addr,u32 len)1062 static void rtw89_debug_dump_mac_mem(struct seq_file *m,
1063 struct rtw89_dev *rtwdev,
1064 u8 sel, u32 start_addr, u32 len)
1065 {
1066 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1067 u32 filter_model_addr = mac->filter_model_addr;
1068 u32 indir_access_addr = mac->indir_access_addr;
1069 u32 base_addr, start_page, residue;
1070 u32 i, j, p, pages;
1071 u32 dump_len, remain;
1072 u32 val;
1073
1074 remain = len;
1075 pages = len / MAC_MEM_DUMP_PAGE_SIZE + 1;
1076 start_page = start_addr / MAC_MEM_DUMP_PAGE_SIZE;
1077 residue = start_addr % MAC_MEM_DUMP_PAGE_SIZE;
1078 base_addr = mac->mem_base_addrs[sel];
1079 base_addr += start_page * MAC_MEM_DUMP_PAGE_SIZE;
1080
1081 for (p = 0; p < pages; p++) {
1082 dump_len = min_t(u32, remain, MAC_MEM_DUMP_PAGE_SIZE);
1083 rtw89_write32(rtwdev, filter_model_addr, base_addr);
1084 for (i = indir_access_addr + residue;
1085 i < indir_access_addr + dump_len;) {
1086 seq_printf(m, "%08xh:", i);
1087 for (j = 0;
1088 j < 4 && i < indir_access_addr + dump_len;
1089 j++, i += 4) {
1090 val = rtw89_read32(rtwdev, i);
1091 seq_printf(m, " %08x", val);
1092 remain -= 4;
1093 }
1094 seq_puts(m, "\n");
1095 }
1096 base_addr += MAC_MEM_DUMP_PAGE_SIZE;
1097 }
1098 }
1099
1100 static int
rtw89_debug_priv_mac_mem_dump_get(struct seq_file * m,void * v)1101 rtw89_debug_priv_mac_mem_dump_get(struct seq_file *m, void *v)
1102 {
1103 struct rtw89_debugfs_priv *debugfs_priv = m->private;
1104 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
1105 bool grant_read = false;
1106
1107 if (debugfs_priv->mac_mem.sel >= RTW89_MAC_MEM_NUM)
1108 return -ENOENT;
1109
1110 if (rtwdev->chip->chip_id == RTL8852C) {
1111 switch (debugfs_priv->mac_mem.sel) {
1112 case RTW89_MAC_MEM_TXD_FIFO_0_V1:
1113 case RTW89_MAC_MEM_TXD_FIFO_1_V1:
1114 case RTW89_MAC_MEM_TXDATA_FIFO_0:
1115 case RTW89_MAC_MEM_TXDATA_FIFO_1:
1116 grant_read = true;
1117 break;
1118 default:
1119 break;
1120 }
1121 }
1122
1123 mutex_lock(&rtwdev->mutex);
1124 rtw89_leave_ps_mode(rtwdev);
1125 if (grant_read)
1126 rtw89_write32_set(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO);
1127 rtw89_debug_dump_mac_mem(m, rtwdev,
1128 debugfs_priv->mac_mem.sel,
1129 debugfs_priv->mac_mem.start,
1130 debugfs_priv->mac_mem.len);
1131 if (grant_read)
1132 rtw89_write32_clr(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO);
1133 mutex_unlock(&rtwdev->mutex);
1134
1135 return 0;
1136 }
1137
1138 static ssize_t
rtw89_debug_priv_mac_dbg_port_dump_select(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)1139 rtw89_debug_priv_mac_dbg_port_dump_select(struct file *filp,
1140 const char __user *user_buf,
1141 size_t count, loff_t *loff)
1142 {
1143 struct seq_file *m = (struct seq_file *)filp->private_data;
1144 struct rtw89_debugfs_priv *debugfs_priv = m->private;
1145 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
1146 char buf[32];
1147 size_t buf_size;
1148 int sel, set;
1149 int num;
1150 bool enable;
1151
1152 buf_size = min(count, sizeof(buf) - 1);
1153 if (copy_from_user(buf, user_buf, buf_size))
1154 return -EFAULT;
1155
1156 buf[buf_size] = '\0';
1157 num = sscanf(buf, "%d %d", &sel, &set);
1158 if (num != 2) {
1159 rtw89_info(rtwdev, "invalid format: <sel> <set>\n");
1160 return -EINVAL;
1161 }
1162
1163 enable = set != 0;
1164 switch (sel) {
1165 case 0:
1166 debugfs_priv->dbgpkg_en.ss_dbg = enable;
1167 break;
1168 case 1:
1169 debugfs_priv->dbgpkg_en.dle_dbg = enable;
1170 break;
1171 case 2:
1172 debugfs_priv->dbgpkg_en.dmac_dbg = enable;
1173 break;
1174 case 3:
1175 debugfs_priv->dbgpkg_en.cmac_dbg = enable;
1176 break;
1177 case 4:
1178 debugfs_priv->dbgpkg_en.dbg_port = enable;
1179 break;
1180 default:
1181 rtw89_info(rtwdev, "invalid args: sel %d set %d\n", sel, set);
1182 return -EINVAL;
1183 }
1184
1185 rtw89_info(rtwdev, "%s debug port dump %d\n",
1186 enable ? "Enable" : "Disable", sel);
1187
1188 return count;
1189 }
1190
rtw89_debug_mac_dump_ss_dbg(struct rtw89_dev * rtwdev,struct seq_file * m)1191 static int rtw89_debug_mac_dump_ss_dbg(struct rtw89_dev *rtwdev,
1192 struct seq_file *m)
1193 {
1194 return 0;
1195 }
1196
rtw89_debug_mac_dump_dle_dbg(struct rtw89_dev * rtwdev,struct seq_file * m)1197 static int rtw89_debug_mac_dump_dle_dbg(struct rtw89_dev *rtwdev,
1198 struct seq_file *m)
1199 {
1200 #define DLE_DFI_DUMP(__type, __target, __sel) \
1201 ({ \
1202 u32 __ctrl; \
1203 u32 __reg_ctrl = R_AX_##__type##_DBG_FUN_INTF_CTL; \
1204 u32 __reg_data = R_AX_##__type##_DBG_FUN_INTF_DATA; \
1205 u32 __data, __val32; \
1206 int __ret; \
1207 \
1208 __ctrl = FIELD_PREP(B_AX_##__type##_DFI_TRGSEL_MASK, \
1209 DLE_DFI_TYPE_##__target) | \
1210 FIELD_PREP(B_AX_##__type##_DFI_ADDR_MASK, __sel) | \
1211 B_AX_WDE_DFI_ACTIVE; \
1212 rtw89_write32(rtwdev, __reg_ctrl, __ctrl); \
1213 __ret = read_poll_timeout(rtw89_read32, __val32, \
1214 !(__val32 & B_AX_##__type##_DFI_ACTIVE), \
1215 1000, 50000, false, \
1216 rtwdev, __reg_ctrl); \
1217 if (__ret) { \
1218 rtw89_err(rtwdev, "failed to dump DLE %s %s %d\n", \
1219 #__type, #__target, __sel); \
1220 return __ret; \
1221 } \
1222 \
1223 __data = rtw89_read32(rtwdev, __reg_data); \
1224 __data; \
1225 })
1226
1227 #define DLE_DFI_FREE_PAGE_DUMP(__m, __type) \
1228 ({ \
1229 u32 __freepg, __pubpg; \
1230 u32 __freepg_head, __freepg_tail, __pubpg_num; \
1231 \
1232 __freepg = DLE_DFI_DUMP(__type, FREEPG, 0); \
1233 __pubpg = DLE_DFI_DUMP(__type, FREEPG, 1); \
1234 __freepg_head = FIELD_GET(B_AX_DLE_FREE_HEADPG, __freepg); \
1235 __freepg_tail = FIELD_GET(B_AX_DLE_FREE_TAILPG, __freepg); \
1236 __pubpg_num = FIELD_GET(B_AX_DLE_PUB_PGNUM, __pubpg); \
1237 seq_printf(__m, "[%s] freepg head: %d\n", \
1238 #__type, __freepg_head); \
1239 seq_printf(__m, "[%s] freepg tail: %d\n", \
1240 #__type, __freepg_tail); \
1241 seq_printf(__m, "[%s] pubpg num : %d\n", \
1242 #__type, __pubpg_num); \
1243 })
1244
1245 #define case_QUOTA(__m, __type, __id) \
1246 case __type##_QTAID_##__id: \
1247 val32 = DLE_DFI_DUMP(__type, QUOTA, __type##_QTAID_##__id); \
1248 rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, val32); \
1249 use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, val32); \
1250 seq_printf(__m, "[%s][%s] rsv_pgnum: %d\n", \
1251 #__type, #__id, rsv_pgnum); \
1252 seq_printf(__m, "[%s][%s] use_pgnum: %d\n", \
1253 #__type, #__id, use_pgnum); \
1254 break
1255 u32 quota_id;
1256 u32 val32;
1257 u16 rsv_pgnum, use_pgnum;
1258 int ret;
1259
1260 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL);
1261 if (ret) {
1262 seq_puts(m, "[DLE] : DMAC not enabled\n");
1263 return ret;
1264 }
1265
1266 DLE_DFI_FREE_PAGE_DUMP(m, WDE);
1267 DLE_DFI_FREE_PAGE_DUMP(m, PLE);
1268 for (quota_id = 0; quota_id <= WDE_QTAID_CPUIO; quota_id++) {
1269 switch (quota_id) {
1270 case_QUOTA(m, WDE, HOST_IF);
1271 case_QUOTA(m, WDE, WLAN_CPU);
1272 case_QUOTA(m, WDE, DATA_CPU);
1273 case_QUOTA(m, WDE, PKTIN);
1274 case_QUOTA(m, WDE, CPUIO);
1275 }
1276 }
1277 for (quota_id = 0; quota_id <= PLE_QTAID_CPUIO; quota_id++) {
1278 switch (quota_id) {
1279 case_QUOTA(m, PLE, B0_TXPL);
1280 case_QUOTA(m, PLE, B1_TXPL);
1281 case_QUOTA(m, PLE, C2H);
1282 case_QUOTA(m, PLE, H2C);
1283 case_QUOTA(m, PLE, WLAN_CPU);
1284 case_QUOTA(m, PLE, MPDU);
1285 case_QUOTA(m, PLE, CMAC0_RX);
1286 case_QUOTA(m, PLE, CMAC1_RX);
1287 case_QUOTA(m, PLE, CMAC1_BBRPT);
1288 case_QUOTA(m, PLE, WDRLS);
1289 case_QUOTA(m, PLE, CPUIO);
1290 }
1291 }
1292
1293 return 0;
1294
1295 #undef case_QUOTA
1296 #undef DLE_DFI_DUMP
1297 #undef DLE_DFI_FREE_PAGE_DUMP
1298 }
1299
rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev * rtwdev,struct seq_file * m)1300 static int rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev *rtwdev,
1301 struct seq_file *m)
1302 {
1303 const struct rtw89_chip_info *chip = rtwdev->chip;
1304 u32 dmac_err;
1305 int i, ret;
1306
1307 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL);
1308 if (ret) {
1309 seq_puts(m, "[DMAC] : DMAC not enabled\n");
1310 return ret;
1311 }
1312
1313 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR);
1314 seq_printf(m, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err);
1315 seq_printf(m, "R_AX_DMAC_ERR_IMR=0x%08x\n",
1316 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR));
1317
1318 if (dmac_err) {
1319 seq_printf(m, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n",
1320 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1));
1321 seq_printf(m, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n",
1322 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1));
1323 if (chip->chip_id == RTL8852C) {
1324 seq_printf(m, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n",
1325 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG));
1326 seq_printf(m, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n",
1327 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG));
1328 seq_printf(m, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n",
1329 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN));
1330 seq_printf(m, "R_AX_PLE_DBGERR_STS=0x%08x\n",
1331 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS));
1332 }
1333 }
1334
1335 if (dmac_err & B_AX_WDRLS_ERR_FLAG) {
1336 seq_printf(m, "R_AX_WDRLS_ERR_IMR=0x%08x\n",
1337 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR));
1338 seq_printf(m, "R_AX_WDRLS_ERR_ISR=0x%08x\n",
1339 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR));
1340 if (chip->chip_id == RTL8852C)
1341 seq_printf(m, "R_AX_RPQ_RXBD_IDX=0x%08x\n",
1342 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1));
1343 else
1344 seq_printf(m, "R_AX_RPQ_RXBD_IDX=0x%08x\n",
1345 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX));
1346 }
1347
1348 if (dmac_err & B_AX_WSEC_ERR_FLAG) {
1349 if (chip->chip_id == RTL8852C) {
1350 seq_printf(m, "R_AX_SEC_ERR_IMR=0x%08x\n",
1351 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR));
1352 seq_printf(m, "R_AX_SEC_ERR_ISR=0x%08x\n",
1353 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG));
1354 seq_printf(m, "R_AX_SEC_ENG_CTRL=0x%08x\n",
1355 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL));
1356 seq_printf(m, "R_AX_SEC_MPDU_PROC=0x%08x\n",
1357 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC));
1358 seq_printf(m, "R_AX_SEC_CAM_ACCESS=0x%08x\n",
1359 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS));
1360 seq_printf(m, "R_AX_SEC_CAM_RDATA=0x%08x\n",
1361 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA));
1362 seq_printf(m, "R_AX_SEC_DEBUG1=0x%08x\n",
1363 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1));
1364 seq_printf(m, "R_AX_SEC_TX_DEBUG=0x%08x\n",
1365 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG));
1366 seq_printf(m, "R_AX_SEC_RX_DEBUG=0x%08x\n",
1367 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG));
1368
1369 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL,
1370 B_AX_DBG_SEL0, 0x8B);
1371 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL,
1372 B_AX_DBG_SEL1, 0x8B);
1373 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1,
1374 B_AX_SEL_0XC0_MASK, 1);
1375 for (i = 0; i < 0x10; i++) {
1376 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL,
1377 B_AX_SEC_DBG_PORT_FIELD_MASK, i);
1378 seq_printf(m, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n",
1379 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2));
1380 }
1381 } else {
1382 seq_printf(m, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n",
1383 rtw89_read32(rtwdev, R_AX_SEC_DEBUG));
1384 seq_printf(m, "R_AX_SEC_ENG_CTRL=0x%08x\n",
1385 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL));
1386 seq_printf(m, "R_AX_SEC_MPDU_PROC=0x%08x\n",
1387 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC));
1388 seq_printf(m, "R_AX_SEC_CAM_ACCESS=0x%08x\n",
1389 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS));
1390 seq_printf(m, "R_AX_SEC_CAM_RDATA=0x%08x\n",
1391 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA));
1392 seq_printf(m, "R_AX_SEC_CAM_WDATA=0x%08x\n",
1393 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA));
1394 seq_printf(m, "R_AX_SEC_TX_DEBUG=0x%08x\n",
1395 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG));
1396 seq_printf(m, "R_AX_SEC_RX_DEBUG=0x%08x\n",
1397 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG));
1398 seq_printf(m, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n",
1399 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT));
1400 seq_printf(m, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n",
1401 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT));
1402 }
1403 }
1404
1405 if (dmac_err & B_AX_MPDU_ERR_FLAG) {
1406 seq_printf(m, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n",
1407 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR));
1408 seq_printf(m, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n",
1409 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR));
1410 seq_printf(m, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n",
1411 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR));
1412 seq_printf(m, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n",
1413 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR));
1414 }
1415
1416 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) {
1417 seq_printf(m, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n",
1418 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR));
1419 seq_printf(m, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n",
1420 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR));
1421 }
1422
1423 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) {
1424 seq_printf(m, "R_AX_WDE_ERR_IMR=0x%08x\n",
1425 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR));
1426 seq_printf(m, "R_AX_WDE_ERR_ISR=0x%08x\n",
1427 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR));
1428 seq_printf(m, "R_AX_PLE_ERR_IMR=0x%08x\n",
1429 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR));
1430 seq_printf(m, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
1431 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR));
1432 }
1433
1434 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) {
1435 if (chip->chip_id == RTL8852C) {
1436 seq_printf(m, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n",
1437 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR));
1438 seq_printf(m, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n",
1439 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR));
1440 seq_printf(m, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n",
1441 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR));
1442 seq_printf(m, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n",
1443 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR));
1444 } else {
1445 seq_printf(m, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n",
1446 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR));
1447 seq_printf(m, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n",
1448 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1));
1449 }
1450 }
1451
1452 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) {
1453 seq_printf(m, "R_AX_WDE_ERR_IMR=0x%08x\n",
1454 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR));
1455 seq_printf(m, "R_AX_WDE_ERR_ISR=0x%08x\n",
1456 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR));
1457 seq_printf(m, "R_AX_PLE_ERR_IMR=0x%08x\n",
1458 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR));
1459 seq_printf(m, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
1460 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR));
1461 seq_printf(m, "R_AX_WD_CPUQ_OP_0=0x%08x\n",
1462 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0));
1463 seq_printf(m, "R_AX_WD_CPUQ_OP_1=0x%08x\n",
1464 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1));
1465 seq_printf(m, "R_AX_WD_CPUQ_OP_2=0x%08x\n",
1466 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2));
1467 seq_printf(m, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n",
1468 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS));
1469 seq_printf(m, "R_AX_PL_CPUQ_OP_0=0x%08x\n",
1470 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0));
1471 seq_printf(m, "R_AX_PL_CPUQ_OP_1=0x%08x\n",
1472 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1));
1473 seq_printf(m, "R_AX_PL_CPUQ_OP_2=0x%08x\n",
1474 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2));
1475 seq_printf(m, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n",
1476 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS));
1477 if (chip->chip_id == RTL8852C) {
1478 seq_printf(m, "R_AX_RX_CTRL0=0x%08x\n",
1479 rtw89_read32(rtwdev, R_AX_RX_CTRL0));
1480 seq_printf(m, "R_AX_RX_CTRL1=0x%08x\n",
1481 rtw89_read32(rtwdev, R_AX_RX_CTRL1));
1482 seq_printf(m, "R_AX_RX_CTRL2=0x%08x\n",
1483 rtw89_read32(rtwdev, R_AX_RX_CTRL2));
1484 } else {
1485 seq_printf(m, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n",
1486 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0));
1487 seq_printf(m, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n",
1488 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1));
1489 seq_printf(m, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n",
1490 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2));
1491 }
1492 }
1493
1494 if (dmac_err & B_AX_PKTIN_ERR_FLAG) {
1495 seq_printf(m, "R_AX_PKTIN_ERR_IMR=0x%08x\n",
1496 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR));
1497 seq_printf(m, "R_AX_PKTIN_ERR_ISR=0x%08x\n",
1498 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR));
1499 }
1500
1501 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) {
1502 seq_printf(m, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n",
1503 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR));
1504 seq_printf(m, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n",
1505 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR));
1506 seq_printf(m, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n",
1507 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR));
1508 seq_printf(m, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n",
1509 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR));
1510 seq_printf(m, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n",
1511 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR));
1512 seq_printf(m, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n",
1513 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR));
1514 }
1515
1516 if (dmac_err & B_AX_BBRPT_ERR_FLAG) {
1517 if (chip->chip_id == RTL8852C) {
1518 seq_printf(m, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n",
1519 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR));
1520 seq_printf(m, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n",
1521 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR));
1522 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n",
1523 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR));
1524 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n",
1525 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR));
1526 seq_printf(m, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n",
1527 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR));
1528 seq_printf(m, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n",
1529 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR));
1530 } else {
1531 seq_printf(m, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n",
1532 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR));
1533 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n",
1534 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR));
1535 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n",
1536 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR));
1537 seq_printf(m, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n",
1538 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR));
1539 seq_printf(m, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n",
1540 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR));
1541 }
1542 }
1543
1544 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG && chip->chip_id == RTL8852C) {
1545 seq_printf(m, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n",
1546 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK));
1547 seq_printf(m, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n",
1548 rtw89_read32(rtwdev, R_AX_HAXI_IDCT));
1549 }
1550
1551 return 0;
1552 }
1553
rtw89_debug_mac_dump_cmac_err(struct rtw89_dev * rtwdev,struct seq_file * m,enum rtw89_mac_idx band)1554 static int rtw89_debug_mac_dump_cmac_err(struct rtw89_dev *rtwdev,
1555 struct seq_file *m,
1556 enum rtw89_mac_idx band)
1557 {
1558 const struct rtw89_chip_info *chip = rtwdev->chip;
1559 u32 offset = 0;
1560 u32 cmac_err;
1561 int ret;
1562
1563 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL);
1564 if (ret) {
1565 if (band)
1566 seq_puts(m, "[CMAC] : CMAC1 not enabled\n");
1567 else
1568 seq_puts(m, "[CMAC] : CMAC0 not enabled\n");
1569 return ret;
1570 }
1571
1572 if (band)
1573 offset = RTW89_MAC_AX_BAND_REG_OFFSET;
1574
1575 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset);
1576 seq_printf(m, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band,
1577 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset));
1578 seq_printf(m, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band,
1579 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset));
1580 seq_printf(m, "R_AX_CK_EN [%d]=0x%08x\n", band,
1581 rtw89_read32(rtwdev, R_AX_CK_EN + offset));
1582
1583 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) {
1584 seq_printf(m, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band,
1585 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset));
1586 seq_printf(m, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band,
1587 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset));
1588 }
1589
1590 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) {
1591 seq_printf(m, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band,
1592 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset));
1593 seq_printf(m, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band,
1594 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset));
1595 }
1596
1597 if (cmac_err & B_AX_DMA_TOP_ERR_IND) {
1598 if (chip->chip_id == RTL8852C) {
1599 seq_printf(m, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band,
1600 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset));
1601 seq_printf(m, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band,
1602 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset));
1603 } else {
1604 seq_printf(m, "R_AX_DLE_CTRL [%d]=0x%08x\n", band,
1605 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset));
1606 }
1607 }
1608
1609 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) {
1610 if (chip->chip_id == RTL8852C) {
1611 seq_printf(m, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band,
1612 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset));
1613 seq_printf(m, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band,
1614 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset));
1615 } else {
1616 seq_printf(m, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band,
1617 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset));
1618 }
1619 }
1620
1621 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) {
1622 seq_printf(m, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band,
1623 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset));
1624 seq_printf(m, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band,
1625 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset));
1626 }
1627
1628 if (cmac_err & B_AX_WMAC_TX_ERR_IND) {
1629 if (chip->chip_id == RTL8852C) {
1630 seq_printf(m, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band,
1631 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset));
1632 seq_printf(m, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band,
1633 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset));
1634 } else {
1635 seq_printf(m, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band,
1636 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset));
1637 }
1638 seq_printf(m, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band,
1639 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset));
1640 }
1641
1642 seq_printf(m, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band,
1643 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset));
1644
1645 return 0;
1646 }
1647
rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev * rtwdev,struct seq_file * m)1648 static int rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev *rtwdev,
1649 struct seq_file *m)
1650 {
1651 rtw89_debug_mac_dump_cmac_err(rtwdev, m, RTW89_MAC_0);
1652 if (rtwdev->dbcc_en)
1653 rtw89_debug_mac_dump_cmac_err(rtwdev, m, RTW89_MAC_1);
1654
1655 return 0;
1656 }
1657
1658 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c0 = {
1659 .sel_addr = R_AX_PTCL_DBG,
1660 .sel_byte = 1,
1661 .sel_msk = B_AX_PTCL_DBG_SEL_MASK,
1662 .srt = 0x00,
1663 .end = 0x3F,
1664 .rd_addr = R_AX_PTCL_DBG_INFO,
1665 .rd_byte = 4,
1666 .rd_msk = B_AX_PTCL_DBG_INFO_MASK
1667 };
1668
1669 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c1 = {
1670 .sel_addr = R_AX_PTCL_DBG_C1,
1671 .sel_byte = 1,
1672 .sel_msk = B_AX_PTCL_DBG_SEL_MASK,
1673 .srt = 0x00,
1674 .end = 0x3F,
1675 .rd_addr = R_AX_PTCL_DBG_INFO_C1,
1676 .rd_byte = 4,
1677 .rd_msk = B_AX_PTCL_DBG_INFO_MASK
1678 };
1679
1680 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx0_5 = {
1681 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1682 .sel_byte = 2,
1683 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1684 .srt = 0x0,
1685 .end = 0xD,
1686 .rd_addr = R_AX_DBG_PORT_SEL,
1687 .rd_byte = 4,
1688 .rd_msk = B_AX_DEBUG_ST_MASK
1689 };
1690
1691 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx6 = {
1692 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1693 .sel_byte = 2,
1694 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1695 .srt = 0x0,
1696 .end = 0x5,
1697 .rd_addr = R_AX_DBG_PORT_SEL,
1698 .rd_byte = 4,
1699 .rd_msk = B_AX_DEBUG_ST_MASK
1700 };
1701
1702 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx7 = {
1703 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1704 .sel_byte = 2,
1705 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1706 .srt = 0x0,
1707 .end = 0x9,
1708 .rd_addr = R_AX_DBG_PORT_SEL,
1709 .rd_byte = 4,
1710 .rd_msk = B_AX_DEBUG_ST_MASK
1711 };
1712
1713 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx8 = {
1714 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1715 .sel_byte = 2,
1716 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1717 .srt = 0x0,
1718 .end = 0x3,
1719 .rd_addr = R_AX_DBG_PORT_SEL,
1720 .rd_byte = 4,
1721 .rd_msk = B_AX_DEBUG_ST_MASK
1722 };
1723
1724 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx9_C = {
1725 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1726 .sel_byte = 2,
1727 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1728 .srt = 0x0,
1729 .end = 0x1,
1730 .rd_addr = R_AX_DBG_PORT_SEL,
1731 .rd_byte = 4,
1732 .rd_msk = B_AX_DEBUG_ST_MASK
1733 };
1734
1735 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_txD = {
1736 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1737 .sel_byte = 2,
1738 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1739 .srt = 0x0,
1740 .end = 0x0,
1741 .rd_addr = R_AX_DBG_PORT_SEL,
1742 .rd_byte = 4,
1743 .rd_msk = B_AX_DEBUG_ST_MASK
1744 };
1745
1746 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx0 = {
1747 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1748 .sel_byte = 2,
1749 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1750 .srt = 0x0,
1751 .end = 0xB,
1752 .rd_addr = R_AX_DBG_PORT_SEL,
1753 .rd_byte = 4,
1754 .rd_msk = B_AX_DEBUG_ST_MASK
1755 };
1756
1757 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx1 = {
1758 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1759 .sel_byte = 2,
1760 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1761 .srt = 0x0,
1762 .end = 0x4,
1763 .rd_addr = R_AX_DBG_PORT_SEL,
1764 .rd_byte = 4,
1765 .rd_msk = B_AX_DEBUG_ST_MASK
1766 };
1767
1768 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx3 = {
1769 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1770 .sel_byte = 2,
1771 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1772 .srt = 0x0,
1773 .end = 0x8,
1774 .rd_addr = R_AX_DBG_PORT_SEL,
1775 .rd_byte = 4,
1776 .rd_msk = B_AX_DEBUG_ST_MASK
1777 };
1778
1779 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx4 = {
1780 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1781 .sel_byte = 2,
1782 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1783 .srt = 0x0,
1784 .end = 0x7,
1785 .rd_addr = R_AX_DBG_PORT_SEL,
1786 .rd_byte = 4,
1787 .rd_msk = B_AX_DEBUG_ST_MASK
1788 };
1789
1790 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx5_8 = {
1791 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1792 .sel_byte = 2,
1793 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1794 .srt = 0x0,
1795 .end = 0x1,
1796 .rd_addr = R_AX_DBG_PORT_SEL,
1797 .rd_byte = 4,
1798 .rd_msk = B_AX_DEBUG_ST_MASK
1799 };
1800
1801 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx9 = {
1802 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1803 .sel_byte = 2,
1804 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1805 .srt = 0x0,
1806 .end = 0x3,
1807 .rd_addr = R_AX_DBG_PORT_SEL,
1808 .rd_byte = 4,
1809 .rd_msk = B_AX_DEBUG_ST_MASK
1810 };
1811
1812 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_txA_C = {
1813 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1814 .sel_byte = 2,
1815 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1816 .srt = 0x0,
1817 .end = 0x0,
1818 .rd_addr = R_AX_DBG_PORT_SEL,
1819 .rd_byte = 4,
1820 .rd_msk = B_AX_DEBUG_ST_MASK
1821 };
1822
1823 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx0 = {
1824 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1825 .sel_byte = 2,
1826 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1827 .srt = 0x0,
1828 .end = 0x8,
1829 .rd_addr = R_AX_DBG_PORT_SEL,
1830 .rd_byte = 4,
1831 .rd_msk = B_AX_DEBUG_ST_MASK
1832 };
1833
1834 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx1_2 = {
1835 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1836 .sel_byte = 2,
1837 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1838 .srt = 0x0,
1839 .end = 0x0,
1840 .rd_addr = R_AX_DBG_PORT_SEL,
1841 .rd_byte = 4,
1842 .rd_msk = B_AX_DEBUG_ST_MASK
1843 };
1844
1845 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx3 = {
1846 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1847 .sel_byte = 2,
1848 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1849 .srt = 0x0,
1850 .end = 0x6,
1851 .rd_addr = R_AX_DBG_PORT_SEL,
1852 .rd_byte = 4,
1853 .rd_msk = B_AX_DEBUG_ST_MASK
1854 };
1855
1856 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx4 = {
1857 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1858 .sel_byte = 2,
1859 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1860 .srt = 0x0,
1861 .end = 0x0,
1862 .rd_addr = R_AX_DBG_PORT_SEL,
1863 .rd_byte = 4,
1864 .rd_msk = B_AX_DEBUG_ST_MASK
1865 };
1866
1867 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx5 = {
1868 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1869 .sel_byte = 2,
1870 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1871 .srt = 0x0,
1872 .end = 0x0,
1873 .rd_addr = R_AX_DBG_PORT_SEL,
1874 .rd_byte = 4,
1875 .rd_msk = B_AX_DEBUG_ST_MASK
1876 };
1877
1878 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_0 = {
1879 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1880 .sel_byte = 1,
1881 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
1882 .srt = 0x0,
1883 .end = 0x3,
1884 .rd_addr = R_AX_DBG_PORT_SEL,
1885 .rd_byte = 4,
1886 .rd_msk = B_AX_DEBUG_ST_MASK
1887 };
1888
1889 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_1 = {
1890 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1891 .sel_byte = 1,
1892 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
1893 .srt = 0x0,
1894 .end = 0x6,
1895 .rd_addr = R_AX_DBG_PORT_SEL,
1896 .rd_byte = 4,
1897 .rd_msk = B_AX_DEBUG_ST_MASK
1898 };
1899
1900 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_2 = {
1901 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1902 .sel_byte = 1,
1903 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
1904 .srt = 0x0,
1905 .end = 0x0,
1906 .rd_addr = R_AX_DBG_PORT_SEL,
1907 .rd_byte = 4,
1908 .rd_msk = B_AX_DEBUG_ST_MASK
1909 };
1910
1911 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p1 = {
1912 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1913 .sel_byte = 1,
1914 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
1915 .srt = 0x8,
1916 .end = 0xE,
1917 .rd_addr = R_AX_DBG_PORT_SEL,
1918 .rd_byte = 4,
1919 .rd_msk = B_AX_DEBUG_ST_MASK
1920 };
1921
1922 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_stf_ctrl = {
1923 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1924 .sel_byte = 1,
1925 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
1926 .srt = 0x0,
1927 .end = 0x5,
1928 .rd_addr = R_AX_DBG_PORT_SEL,
1929 .rd_byte = 4,
1930 .rd_msk = B_AX_DEBUG_ST_MASK
1931 };
1932
1933 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_addr_ctrl = {
1934 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1935 .sel_byte = 1,
1936 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
1937 .srt = 0x0,
1938 .end = 0x6,
1939 .rd_addr = R_AX_DBG_PORT_SEL,
1940 .rd_byte = 4,
1941 .rd_msk = B_AX_DEBUG_ST_MASK
1942 };
1943
1944 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_wde_intf = {
1945 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1946 .sel_byte = 1,
1947 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
1948 .srt = 0x0,
1949 .end = 0xF,
1950 .rd_addr = R_AX_DBG_PORT_SEL,
1951 .rd_byte = 4,
1952 .rd_msk = B_AX_DEBUG_ST_MASK
1953 };
1954
1955 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_ple_intf = {
1956 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1957 .sel_byte = 1,
1958 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
1959 .srt = 0x0,
1960 .end = 0x9,
1961 .rd_addr = R_AX_DBG_PORT_SEL,
1962 .rd_byte = 4,
1963 .rd_msk = B_AX_DEBUG_ST_MASK
1964 };
1965
1966 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_flow_ctrl = {
1967 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1968 .sel_byte = 1,
1969 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
1970 .srt = 0x0,
1971 .end = 0x3,
1972 .rd_addr = R_AX_DBG_PORT_SEL,
1973 .rd_byte = 4,
1974 .rd_msk = B_AX_DEBUG_ST_MASK
1975 };
1976
1977 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c0 = {
1978 .sel_addr = R_AX_SCH_DBG_SEL,
1979 .sel_byte = 1,
1980 .sel_msk = B_AX_SCH_DBG_SEL_MASK,
1981 .srt = 0x00,
1982 .end = 0x2F,
1983 .rd_addr = R_AX_SCH_DBG,
1984 .rd_byte = 4,
1985 .rd_msk = B_AX_SCHEDULER_DBG_MASK
1986 };
1987
1988 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c1 = {
1989 .sel_addr = R_AX_SCH_DBG_SEL_C1,
1990 .sel_byte = 1,
1991 .sel_msk = B_AX_SCH_DBG_SEL_MASK,
1992 .srt = 0x00,
1993 .end = 0x2F,
1994 .rd_addr = R_AX_SCH_DBG_C1,
1995 .rd_byte = 4,
1996 .rd_msk = B_AX_SCHEDULER_DBG_MASK
1997 };
1998
1999 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c0 = {
2000 .sel_addr = R_AX_MACTX_DBG_SEL_CNT,
2001 .sel_byte = 1,
2002 .sel_msk = B_AX_DBGSEL_MACTX_MASK,
2003 .srt = 0x00,
2004 .end = 0x19,
2005 .rd_addr = R_AX_DBG_PORT_SEL,
2006 .rd_byte = 4,
2007 .rd_msk = B_AX_DEBUG_ST_MASK
2008 };
2009
2010 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c1 = {
2011 .sel_addr = R_AX_MACTX_DBG_SEL_CNT_C1,
2012 .sel_byte = 1,
2013 .sel_msk = B_AX_DBGSEL_MACTX_MASK,
2014 .srt = 0x00,
2015 .end = 0x19,
2016 .rd_addr = R_AX_DBG_PORT_SEL,
2017 .rd_byte = 4,
2018 .rd_msk = B_AX_DEBUG_ST_MASK
2019 };
2020
2021 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c0 = {
2022 .sel_addr = R_AX_RX_DEBUG_SELECT,
2023 .sel_byte = 1,
2024 .sel_msk = B_AX_DEBUG_SEL_MASK,
2025 .srt = 0x00,
2026 .end = 0x58,
2027 .rd_addr = R_AX_DBG_PORT_SEL,
2028 .rd_byte = 4,
2029 .rd_msk = B_AX_DEBUG_ST_MASK
2030 };
2031
2032 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c1 = {
2033 .sel_addr = R_AX_RX_DEBUG_SELECT_C1,
2034 .sel_byte = 1,
2035 .sel_msk = B_AX_DEBUG_SEL_MASK,
2036 .srt = 0x00,
2037 .end = 0x58,
2038 .rd_addr = R_AX_DBG_PORT_SEL,
2039 .rd_byte = 4,
2040 .rd_msk = B_AX_DEBUG_ST_MASK
2041 };
2042
2043 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c0 = {
2044 .sel_addr = R_AX_RX_STATE_MONITOR,
2045 .sel_byte = 1,
2046 .sel_msk = B_AX_STATE_SEL_MASK,
2047 .srt = 0x00,
2048 .end = 0x17,
2049 .rd_addr = R_AX_RX_STATE_MONITOR,
2050 .rd_byte = 4,
2051 .rd_msk = B_AX_RX_STATE_MONITOR_MASK
2052 };
2053
2054 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c1 = {
2055 .sel_addr = R_AX_RX_STATE_MONITOR_C1,
2056 .sel_byte = 1,
2057 .sel_msk = B_AX_STATE_SEL_MASK,
2058 .srt = 0x00,
2059 .end = 0x17,
2060 .rd_addr = R_AX_RX_STATE_MONITOR_C1,
2061 .rd_byte = 4,
2062 .rd_msk = B_AX_RX_STATE_MONITOR_MASK
2063 };
2064
2065 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c0 = {
2066 .sel_addr = R_AX_RMAC_PLCP_MON,
2067 .sel_byte = 4,
2068 .sel_msk = B_AX_PCLP_MON_SEL_MASK,
2069 .srt = 0x0,
2070 .end = 0xF,
2071 .rd_addr = R_AX_RMAC_PLCP_MON,
2072 .rd_byte = 4,
2073 .rd_msk = B_AX_RMAC_PLCP_MON_MASK
2074 };
2075
2076 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c1 = {
2077 .sel_addr = R_AX_RMAC_PLCP_MON_C1,
2078 .sel_byte = 4,
2079 .sel_msk = B_AX_PCLP_MON_SEL_MASK,
2080 .srt = 0x0,
2081 .end = 0xF,
2082 .rd_addr = R_AX_RMAC_PLCP_MON_C1,
2083 .rd_byte = 4,
2084 .rd_msk = B_AX_RMAC_PLCP_MON_MASK
2085 };
2086
2087 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c0 = {
2088 .sel_addr = R_AX_DBGSEL_TRXPTCL,
2089 .sel_byte = 1,
2090 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK,
2091 .srt = 0x08,
2092 .end = 0x10,
2093 .rd_addr = R_AX_DBG_PORT_SEL,
2094 .rd_byte = 4,
2095 .rd_msk = B_AX_DEBUG_ST_MASK
2096 };
2097
2098 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c1 = {
2099 .sel_addr = R_AX_DBGSEL_TRXPTCL_C1,
2100 .sel_byte = 1,
2101 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK,
2102 .srt = 0x08,
2103 .end = 0x10,
2104 .rd_addr = R_AX_DBG_PORT_SEL,
2105 .rd_byte = 4,
2106 .rd_msk = B_AX_DEBUG_ST_MASK
2107 };
2108
2109 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c0 = {
2110 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG,
2111 .sel_byte = 1,
2112 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK,
2113 .srt = 0x00,
2114 .end = 0x07,
2115 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG,
2116 .rd_byte = 4,
2117 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK
2118 };
2119
2120 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c0 = {
2121 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG,
2122 .sel_byte = 1,
2123 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK,
2124 .srt = 0x00,
2125 .end = 0x07,
2126 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG,
2127 .rd_byte = 4,
2128 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK
2129 };
2130
2131 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c1 = {
2132 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1,
2133 .sel_byte = 1,
2134 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK,
2135 .srt = 0x00,
2136 .end = 0x07,
2137 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG_C1,
2138 .rd_byte = 4,
2139 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK
2140 };
2141
2142 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c1 = {
2143 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1,
2144 .sel_byte = 1,
2145 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK,
2146 .srt = 0x00,
2147 .end = 0x07,
2148 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG_C1,
2149 .rd_byte = 4,
2150 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK
2151 };
2152
2153 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c0 = {
2154 .sel_addr = R_AX_WMAC_TX_TF_INFO_0,
2155 .sel_byte = 1,
2156 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK,
2157 .srt = 0x00,
2158 .end = 0x04,
2159 .rd_addr = R_AX_WMAC_TX_TF_INFO_1,
2160 .rd_byte = 4,
2161 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK
2162 };
2163
2164 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c0 = {
2165 .sel_addr = R_AX_WMAC_TX_TF_INFO_0,
2166 .sel_byte = 1,
2167 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK,
2168 .srt = 0x00,
2169 .end = 0x04,
2170 .rd_addr = R_AX_WMAC_TX_TF_INFO_2,
2171 .rd_byte = 4,
2172 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK
2173 };
2174
2175 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c1 = {
2176 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1,
2177 .sel_byte = 1,
2178 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK,
2179 .srt = 0x00,
2180 .end = 0x04,
2181 .rd_addr = R_AX_WMAC_TX_TF_INFO_1_C1,
2182 .rd_byte = 4,
2183 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK
2184 };
2185
2186 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c1 = {
2187 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1,
2188 .sel_byte = 1,
2189 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK,
2190 .srt = 0x00,
2191 .end = 0x04,
2192 .rd_addr = R_AX_WMAC_TX_TF_INFO_2_C1,
2193 .rd_byte = 4,
2194 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK
2195 };
2196
2197 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_freepg = {
2198 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
2199 .sel_byte = 4,
2200 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
2201 .srt = 0x80000000,
2202 .end = 0x80000001,
2203 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
2204 .rd_byte = 4,
2205 .rd_msk = B_AX_WDE_DFI_DATA_MASK
2206 };
2207
2208 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_quota = {
2209 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
2210 .sel_byte = 4,
2211 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
2212 .srt = 0x80010000,
2213 .end = 0x80010004,
2214 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
2215 .rd_byte = 4,
2216 .rd_msk = B_AX_WDE_DFI_DATA_MASK
2217 };
2218
2219 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pagellt = {
2220 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
2221 .sel_byte = 4,
2222 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
2223 .srt = 0x80020000,
2224 .end = 0x80020FFF,
2225 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
2226 .rd_byte = 4,
2227 .rd_msk = B_AX_WDE_DFI_DATA_MASK
2228 };
2229
2230 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pktinfo = {
2231 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
2232 .sel_byte = 4,
2233 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
2234 .srt = 0x80030000,
2235 .end = 0x80030FFF,
2236 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
2237 .rd_byte = 4,
2238 .rd_msk = B_AX_WDE_DFI_DATA_MASK
2239 };
2240
2241 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_prepkt = {
2242 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
2243 .sel_byte = 4,
2244 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
2245 .srt = 0x80040000,
2246 .end = 0x80040FFF,
2247 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
2248 .rd_byte = 4,
2249 .rd_msk = B_AX_WDE_DFI_DATA_MASK
2250 };
2251
2252 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_nxtpkt = {
2253 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
2254 .sel_byte = 4,
2255 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
2256 .srt = 0x80050000,
2257 .end = 0x80050FFF,
2258 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
2259 .rd_byte = 4,
2260 .rd_msk = B_AX_WDE_DFI_DATA_MASK
2261 };
2262
2263 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qlnktbl = {
2264 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
2265 .sel_byte = 4,
2266 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
2267 .srt = 0x80060000,
2268 .end = 0x80060453,
2269 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
2270 .rd_byte = 4,
2271 .rd_msk = B_AX_WDE_DFI_DATA_MASK
2272 };
2273
2274 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qempty = {
2275 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
2276 .sel_byte = 4,
2277 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
2278 .srt = 0x80070000,
2279 .end = 0x80070011,
2280 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
2281 .rd_byte = 4,
2282 .rd_msk = B_AX_WDE_DFI_DATA_MASK
2283 };
2284
2285 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_freepg = {
2286 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
2287 .sel_byte = 4,
2288 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
2289 .srt = 0x80000000,
2290 .end = 0x80000001,
2291 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
2292 .rd_byte = 4,
2293 .rd_msk = B_AX_PLE_DFI_DATA_MASK
2294 };
2295
2296 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_quota = {
2297 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
2298 .sel_byte = 4,
2299 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
2300 .srt = 0x80010000,
2301 .end = 0x8001000A,
2302 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
2303 .rd_byte = 4,
2304 .rd_msk = B_AX_PLE_DFI_DATA_MASK
2305 };
2306
2307 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pagellt = {
2308 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
2309 .sel_byte = 4,
2310 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
2311 .srt = 0x80020000,
2312 .end = 0x80020DBF,
2313 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
2314 .rd_byte = 4,
2315 .rd_msk = B_AX_PLE_DFI_DATA_MASK
2316 };
2317
2318 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pktinfo = {
2319 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
2320 .sel_byte = 4,
2321 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
2322 .srt = 0x80030000,
2323 .end = 0x80030DBF,
2324 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
2325 .rd_byte = 4,
2326 .rd_msk = B_AX_PLE_DFI_DATA_MASK
2327 };
2328
2329 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_prepkt = {
2330 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
2331 .sel_byte = 4,
2332 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
2333 .srt = 0x80040000,
2334 .end = 0x80040DBF,
2335 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
2336 .rd_byte = 4,
2337 .rd_msk = B_AX_PLE_DFI_DATA_MASK
2338 };
2339
2340 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_nxtpkt = {
2341 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
2342 .sel_byte = 4,
2343 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
2344 .srt = 0x80050000,
2345 .end = 0x80050DBF,
2346 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
2347 .rd_byte = 4,
2348 .rd_msk = B_AX_PLE_DFI_DATA_MASK
2349 };
2350
2351 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qlnktbl = {
2352 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
2353 .sel_byte = 4,
2354 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
2355 .srt = 0x80060000,
2356 .end = 0x80060041,
2357 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
2358 .rd_byte = 4,
2359 .rd_msk = B_AX_PLE_DFI_DATA_MASK
2360 };
2361
2362 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qempty = {
2363 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
2364 .sel_byte = 4,
2365 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
2366 .srt = 0x80070000,
2367 .end = 0x80070001,
2368 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
2369 .rd_byte = 4,
2370 .rd_msk = B_AX_PLE_DFI_DATA_MASK
2371 };
2372
2373 static const struct rtw89_mac_dbg_port_info dbg_port_pktinfo = {
2374 .sel_addr = R_AX_DBG_FUN_INTF_CTL,
2375 .sel_byte = 4,
2376 .sel_msk = B_AX_DFI_DATA_MASK,
2377 .srt = 0x80000000,
2378 .end = 0x8000017f,
2379 .rd_addr = R_AX_DBG_FUN_INTF_DATA,
2380 .rd_byte = 4,
2381 .rd_msk = B_AX_DFI_DATA_MASK
2382 };
2383
2384 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_txdma = {
2385 .sel_addr = R_AX_PCIE_DBG_CTRL,
2386 .sel_byte = 2,
2387 .sel_msk = B_AX_PCIE_DBG_SEL_MASK,
2388 .srt = 0x00,
2389 .end = 0x03,
2390 .rd_addr = R_AX_DBG_PORT_SEL,
2391 .rd_byte = 4,
2392 .rd_msk = B_AX_DEBUG_ST_MASK
2393 };
2394
2395 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_rxdma = {
2396 .sel_addr = R_AX_PCIE_DBG_CTRL,
2397 .sel_byte = 2,
2398 .sel_msk = B_AX_PCIE_DBG_SEL_MASK,
2399 .srt = 0x00,
2400 .end = 0x04,
2401 .rd_addr = R_AX_DBG_PORT_SEL,
2402 .rd_byte = 4,
2403 .rd_msk = B_AX_DEBUG_ST_MASK
2404 };
2405
2406 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cvt = {
2407 .sel_addr = R_AX_PCIE_DBG_CTRL,
2408 .sel_byte = 2,
2409 .sel_msk = B_AX_PCIE_DBG_SEL_MASK,
2410 .srt = 0x00,
2411 .end = 0x01,
2412 .rd_addr = R_AX_DBG_PORT_SEL,
2413 .rd_byte = 4,
2414 .rd_msk = B_AX_DEBUG_ST_MASK
2415 };
2416
2417 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cxpl = {
2418 .sel_addr = R_AX_PCIE_DBG_CTRL,
2419 .sel_byte = 2,
2420 .sel_msk = B_AX_PCIE_DBG_SEL_MASK,
2421 .srt = 0x00,
2422 .end = 0x05,
2423 .rd_addr = R_AX_DBG_PORT_SEL,
2424 .rd_byte = 4,
2425 .rd_msk = B_AX_DEBUG_ST_MASK
2426 };
2427
2428 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_io = {
2429 .sel_addr = R_AX_PCIE_DBG_CTRL,
2430 .sel_byte = 2,
2431 .sel_msk = B_AX_PCIE_DBG_SEL_MASK,
2432 .srt = 0x00,
2433 .end = 0x05,
2434 .rd_addr = R_AX_DBG_PORT_SEL,
2435 .rd_byte = 4,
2436 .rd_msk = B_AX_DEBUG_ST_MASK
2437 };
2438
2439 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc = {
2440 .sel_addr = R_AX_PCIE_DBG_CTRL,
2441 .sel_byte = 2,
2442 .sel_msk = B_AX_PCIE_DBG_SEL_MASK,
2443 .srt = 0x00,
2444 .end = 0x06,
2445 .rd_addr = R_AX_DBG_PORT_SEL,
2446 .rd_byte = 4,
2447 .rd_msk = B_AX_DEBUG_ST_MASK
2448 };
2449
2450 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc2 = {
2451 .sel_addr = R_AX_DBG_CTRL,
2452 .sel_byte = 1,
2453 .sel_msk = B_AX_DBG_SEL0,
2454 .srt = 0x34,
2455 .end = 0x3C,
2456 .rd_addr = R_AX_DBG_PORT_SEL,
2457 .rd_byte = 4,
2458 .rd_msk = B_AX_DEBUG_ST_MASK
2459 };
2460
2461 static const struct rtw89_mac_dbg_port_info *
rtw89_debug_mac_dbg_port_sel(struct seq_file * m,struct rtw89_dev * rtwdev,u32 sel)2462 rtw89_debug_mac_dbg_port_sel(struct seq_file *m,
2463 struct rtw89_dev *rtwdev, u32 sel)
2464 {
2465 const struct rtw89_mac_dbg_port_info *info;
2466 u32 index;
2467 u32 val32;
2468 u16 val16;
2469 u8 val8;
2470
2471 switch (sel) {
2472 case RTW89_DBG_PORT_SEL_PTCL_C0:
2473 info = &dbg_port_ptcl_c0;
2474 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG);
2475 val16 |= B_AX_PTCL_DBG_EN;
2476 rtw89_write16(rtwdev, R_AX_PTCL_DBG, val16);
2477 seq_puts(m, "Enable PTCL C0 dbgport.\n");
2478 break;
2479 case RTW89_DBG_PORT_SEL_PTCL_C1:
2480 info = &dbg_port_ptcl_c1;
2481 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG_C1);
2482 val16 |= B_AX_PTCL_DBG_EN;
2483 rtw89_write16(rtwdev, R_AX_PTCL_DBG_C1, val16);
2484 seq_puts(m, "Enable PTCL C1 dbgport.\n");
2485 break;
2486 case RTW89_DBG_PORT_SEL_SCH_C0:
2487 info = &dbg_port_sch_c0;
2488 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL);
2489 val32 |= B_AX_SCH_DBG_EN;
2490 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL, val32);
2491 seq_puts(m, "Enable SCH C0 dbgport.\n");
2492 break;
2493 case RTW89_DBG_PORT_SEL_SCH_C1:
2494 info = &dbg_port_sch_c1;
2495 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL_C1);
2496 val32 |= B_AX_SCH_DBG_EN;
2497 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL_C1, val32);
2498 seq_puts(m, "Enable SCH C1 dbgport.\n");
2499 break;
2500 case RTW89_DBG_PORT_SEL_TMAC_C0:
2501 info = &dbg_port_tmac_c0;
2502 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL);
2503 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC,
2504 B_AX_DBGSEL_TRXPTCL_MASK);
2505 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32);
2506
2507 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
2508 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL0);
2509 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL1);
2510 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
2511
2512 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
2513 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
2514 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
2515 seq_puts(m, "Enable TMAC C0 dbgport.\n");
2516 break;
2517 case RTW89_DBG_PORT_SEL_TMAC_C1:
2518 info = &dbg_port_tmac_c1;
2519 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1);
2520 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC,
2521 B_AX_DBGSEL_TRXPTCL_MASK);
2522 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32);
2523
2524 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
2525 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL0);
2526 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL1);
2527 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
2528
2529 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
2530 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
2531 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
2532 seq_puts(m, "Enable TMAC C1 dbgport.\n");
2533 break;
2534 case RTW89_DBG_PORT_SEL_RMAC_C0:
2535 info = &dbg_port_rmac_c0;
2536 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL);
2537 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC,
2538 B_AX_DBGSEL_TRXPTCL_MASK);
2539 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32);
2540
2541 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
2542 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL0);
2543 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL1);
2544 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
2545
2546 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
2547 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
2548 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
2549
2550 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL);
2551 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL,
2552 B_AX_DBGSEL_TRXPTCL_MASK);
2553 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL, val8);
2554 seq_puts(m, "Enable RMAC C0 dbgport.\n");
2555 break;
2556 case RTW89_DBG_PORT_SEL_RMAC_C1:
2557 info = &dbg_port_rmac_c1;
2558 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1);
2559 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC,
2560 B_AX_DBGSEL_TRXPTCL_MASK);
2561 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32);
2562
2563 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
2564 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL0);
2565 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL1);
2566 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
2567
2568 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
2569 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
2570 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
2571
2572 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1);
2573 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL,
2574 B_AX_DBGSEL_TRXPTCL_MASK);
2575 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val8);
2576 seq_puts(m, "Enable RMAC C1 dbgport.\n");
2577 break;
2578 case RTW89_DBG_PORT_SEL_RMACST_C0:
2579 info = &dbg_port_rmacst_c0;
2580 seq_puts(m, "Enable RMAC state C0 dbgport.\n");
2581 break;
2582 case RTW89_DBG_PORT_SEL_RMACST_C1:
2583 info = &dbg_port_rmacst_c1;
2584 seq_puts(m, "Enable RMAC state C1 dbgport.\n");
2585 break;
2586 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C0:
2587 info = &dbg_port_rmac_plcp_c0;
2588 seq_puts(m, "Enable RMAC PLCP C0 dbgport.\n");
2589 break;
2590 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C1:
2591 info = &dbg_port_rmac_plcp_c1;
2592 seq_puts(m, "Enable RMAC PLCP C1 dbgport.\n");
2593 break;
2594 case RTW89_DBG_PORT_SEL_TRXPTCL_C0:
2595 info = &dbg_port_trxptcl_c0;
2596 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
2597 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL0);
2598 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL1);
2599 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
2600
2601 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
2602 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
2603 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
2604 seq_puts(m, "Enable TRXPTCL C0 dbgport.\n");
2605 break;
2606 case RTW89_DBG_PORT_SEL_TRXPTCL_C1:
2607 info = &dbg_port_trxptcl_c1;
2608 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
2609 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL0);
2610 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL1);
2611 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
2612
2613 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
2614 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
2615 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
2616 seq_puts(m, "Enable TRXPTCL C1 dbgport.\n");
2617 break;
2618 case RTW89_DBG_PORT_SEL_TX_INFOL_C0:
2619 info = &dbg_port_tx_infol_c0;
2620 val32 = rtw89_read32(rtwdev, R_AX_TCR1);
2621 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
2622 rtw89_write32(rtwdev, R_AX_TCR1, val32);
2623 seq_puts(m, "Enable tx infol dump.\n");
2624 break;
2625 case RTW89_DBG_PORT_SEL_TX_INFOH_C0:
2626 info = &dbg_port_tx_infoh_c0;
2627 val32 = rtw89_read32(rtwdev, R_AX_TCR1);
2628 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
2629 rtw89_write32(rtwdev, R_AX_TCR1, val32);
2630 seq_puts(m, "Enable tx infoh dump.\n");
2631 break;
2632 case RTW89_DBG_PORT_SEL_TX_INFOL_C1:
2633 info = &dbg_port_tx_infol_c1;
2634 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1);
2635 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
2636 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32);
2637 seq_puts(m, "Enable tx infol dump.\n");
2638 break;
2639 case RTW89_DBG_PORT_SEL_TX_INFOH_C1:
2640 info = &dbg_port_tx_infoh_c1;
2641 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1);
2642 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
2643 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32);
2644 seq_puts(m, "Enable tx infoh dump.\n");
2645 break;
2646 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C0:
2647 info = &dbg_port_txtf_infol_c0;
2648 val32 = rtw89_read32(rtwdev, R_AX_TCR1);
2649 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
2650 rtw89_write32(rtwdev, R_AX_TCR1, val32);
2651 seq_puts(m, "Enable tx tf infol dump.\n");
2652 break;
2653 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C0:
2654 info = &dbg_port_txtf_infoh_c0;
2655 val32 = rtw89_read32(rtwdev, R_AX_TCR1);
2656 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
2657 rtw89_write32(rtwdev, R_AX_TCR1, val32);
2658 seq_puts(m, "Enable tx tf infoh dump.\n");
2659 break;
2660 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C1:
2661 info = &dbg_port_txtf_infol_c1;
2662 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1);
2663 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
2664 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32);
2665 seq_puts(m, "Enable tx tf infol dump.\n");
2666 break;
2667 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C1:
2668 info = &dbg_port_txtf_infoh_c1;
2669 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1);
2670 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
2671 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32);
2672 seq_puts(m, "Enable tx tf infoh dump.\n");
2673 break;
2674 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG:
2675 info = &dbg_port_wde_bufmgn_freepg;
2676 seq_puts(m, "Enable wde bufmgn freepg dump.\n");
2677 break;
2678 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA:
2679 info = &dbg_port_wde_bufmgn_quota;
2680 seq_puts(m, "Enable wde bufmgn quota dump.\n");
2681 break;
2682 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT:
2683 info = &dbg_port_wde_bufmgn_pagellt;
2684 seq_puts(m, "Enable wde bufmgn pagellt dump.\n");
2685 break;
2686 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO:
2687 info = &dbg_port_wde_bufmgn_pktinfo;
2688 seq_puts(m, "Enable wde bufmgn pktinfo dump.\n");
2689 break;
2690 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT:
2691 info = &dbg_port_wde_quemgn_prepkt;
2692 seq_puts(m, "Enable wde quemgn prepkt dump.\n");
2693 break;
2694 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT:
2695 info = &dbg_port_wde_quemgn_nxtpkt;
2696 seq_puts(m, "Enable wde quemgn nxtpkt dump.\n");
2697 break;
2698 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL:
2699 info = &dbg_port_wde_quemgn_qlnktbl;
2700 seq_puts(m, "Enable wde quemgn qlnktbl dump.\n");
2701 break;
2702 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY:
2703 info = &dbg_port_wde_quemgn_qempty;
2704 seq_puts(m, "Enable wde quemgn qempty dump.\n");
2705 break;
2706 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG:
2707 info = &dbg_port_ple_bufmgn_freepg;
2708 seq_puts(m, "Enable ple bufmgn freepg dump.\n");
2709 break;
2710 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA:
2711 info = &dbg_port_ple_bufmgn_quota;
2712 seq_puts(m, "Enable ple bufmgn quota dump.\n");
2713 break;
2714 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT:
2715 info = &dbg_port_ple_bufmgn_pagellt;
2716 seq_puts(m, "Enable ple bufmgn pagellt dump.\n");
2717 break;
2718 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO:
2719 info = &dbg_port_ple_bufmgn_pktinfo;
2720 seq_puts(m, "Enable ple bufmgn pktinfo dump.\n");
2721 break;
2722 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT:
2723 info = &dbg_port_ple_quemgn_prepkt;
2724 seq_puts(m, "Enable ple quemgn prepkt dump.\n");
2725 break;
2726 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT:
2727 info = &dbg_port_ple_quemgn_nxtpkt;
2728 seq_puts(m, "Enable ple quemgn nxtpkt dump.\n");
2729 break;
2730 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL:
2731 info = &dbg_port_ple_quemgn_qlnktbl;
2732 seq_puts(m, "Enable ple quemgn qlnktbl dump.\n");
2733 break;
2734 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY:
2735 info = &dbg_port_ple_quemgn_qempty;
2736 seq_puts(m, "Enable ple quemgn qempty dump.\n");
2737 break;
2738 case RTW89_DBG_PORT_SEL_PKTINFO:
2739 info = &dbg_port_pktinfo;
2740 seq_puts(m, "Enable pktinfo dump.\n");
2741 break;
2742 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX0:
2743 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL,
2744 B_AX_DBG_SEL0, 0x80);
2745 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1,
2746 B_AX_SEL_0XC0_MASK, 1);
2747 fallthrough;
2748 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX1:
2749 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX2:
2750 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX3:
2751 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX4:
2752 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX5:
2753 info = &dbg_port_dspt_hdt_tx0_5;
2754 index = sel - RTW89_DBG_PORT_SEL_DSPT_HDT_TX0;
2755 rtw89_write16_mask(rtwdev, info->sel_addr,
2756 B_AX_DISPATCHER_INTN_SEL_MASK, 0);
2757 rtw89_write16_mask(rtwdev, info->sel_addr,
2758 B_AX_DISPATCHER_CH_SEL_MASK, index);
2759 seq_printf(m, "Enable Dispatcher hdt tx%x dump.\n", index);
2760 break;
2761 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX6:
2762 info = &dbg_port_dspt_hdt_tx6;
2763 rtw89_write16_mask(rtwdev, info->sel_addr,
2764 B_AX_DISPATCHER_INTN_SEL_MASK, 0);
2765 rtw89_write16_mask(rtwdev, info->sel_addr,
2766 B_AX_DISPATCHER_CH_SEL_MASK, 6);
2767 seq_puts(m, "Enable Dispatcher hdt tx6 dump.\n");
2768 break;
2769 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX7:
2770 info = &dbg_port_dspt_hdt_tx7;
2771 rtw89_write16_mask(rtwdev, info->sel_addr,
2772 B_AX_DISPATCHER_INTN_SEL_MASK, 0);
2773 rtw89_write16_mask(rtwdev, info->sel_addr,
2774 B_AX_DISPATCHER_CH_SEL_MASK, 7);
2775 seq_puts(m, "Enable Dispatcher hdt tx7 dump.\n");
2776 break;
2777 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX8:
2778 info = &dbg_port_dspt_hdt_tx8;
2779 rtw89_write16_mask(rtwdev, info->sel_addr,
2780 B_AX_DISPATCHER_INTN_SEL_MASK, 0);
2781 rtw89_write16_mask(rtwdev, info->sel_addr,
2782 B_AX_DISPATCHER_CH_SEL_MASK, 8);
2783 seq_puts(m, "Enable Dispatcher hdt tx8 dump.\n");
2784 break;
2785 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX9:
2786 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXA:
2787 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXB:
2788 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXC:
2789 info = &dbg_port_dspt_hdt_tx9_C;
2790 index = sel + 9 - RTW89_DBG_PORT_SEL_DSPT_HDT_TX9;
2791 rtw89_write16_mask(rtwdev, info->sel_addr,
2792 B_AX_DISPATCHER_INTN_SEL_MASK, 0);
2793 rtw89_write16_mask(rtwdev, info->sel_addr,
2794 B_AX_DISPATCHER_CH_SEL_MASK, index);
2795 seq_printf(m, "Enable Dispatcher hdt tx%x dump.\n", index);
2796 break;
2797 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXD:
2798 info = &dbg_port_dspt_hdt_txD;
2799 rtw89_write16_mask(rtwdev, info->sel_addr,
2800 B_AX_DISPATCHER_INTN_SEL_MASK, 0);
2801 rtw89_write16_mask(rtwdev, info->sel_addr,
2802 B_AX_DISPATCHER_CH_SEL_MASK, 0xD);
2803 seq_puts(m, "Enable Dispatcher hdt txD dump.\n");
2804 break;
2805 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX0:
2806 info = &dbg_port_dspt_cdt_tx0;
2807 rtw89_write16_mask(rtwdev, info->sel_addr,
2808 B_AX_DISPATCHER_INTN_SEL_MASK, 1);
2809 rtw89_write16_mask(rtwdev, info->sel_addr,
2810 B_AX_DISPATCHER_CH_SEL_MASK, 0);
2811 seq_puts(m, "Enable Dispatcher cdt tx0 dump.\n");
2812 break;
2813 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX1:
2814 info = &dbg_port_dspt_cdt_tx1;
2815 rtw89_write16_mask(rtwdev, info->sel_addr,
2816 B_AX_DISPATCHER_INTN_SEL_MASK, 1);
2817 rtw89_write16_mask(rtwdev, info->sel_addr,
2818 B_AX_DISPATCHER_CH_SEL_MASK, 1);
2819 seq_puts(m, "Enable Dispatcher cdt tx1 dump.\n");
2820 break;
2821 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX3:
2822 info = &dbg_port_dspt_cdt_tx3;
2823 rtw89_write16_mask(rtwdev, info->sel_addr,
2824 B_AX_DISPATCHER_INTN_SEL_MASK, 1);
2825 rtw89_write16_mask(rtwdev, info->sel_addr,
2826 B_AX_DISPATCHER_CH_SEL_MASK, 3);
2827 seq_puts(m, "Enable Dispatcher cdt tx3 dump.\n");
2828 break;
2829 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX4:
2830 info = &dbg_port_dspt_cdt_tx4;
2831 rtw89_write16_mask(rtwdev, info->sel_addr,
2832 B_AX_DISPATCHER_INTN_SEL_MASK, 1);
2833 rtw89_write16_mask(rtwdev, info->sel_addr,
2834 B_AX_DISPATCHER_CH_SEL_MASK, 4);
2835 seq_puts(m, "Enable Dispatcher cdt tx4 dump.\n");
2836 break;
2837 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX5:
2838 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX6:
2839 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX7:
2840 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX8:
2841 info = &dbg_port_dspt_cdt_tx5_8;
2842 index = sel + 5 - RTW89_DBG_PORT_SEL_DSPT_CDT_TX5;
2843 rtw89_write16_mask(rtwdev, info->sel_addr,
2844 B_AX_DISPATCHER_INTN_SEL_MASK, 1);
2845 rtw89_write16_mask(rtwdev, info->sel_addr,
2846 B_AX_DISPATCHER_CH_SEL_MASK, index);
2847 seq_printf(m, "Enable Dispatcher cdt tx%x dump.\n", index);
2848 break;
2849 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX9:
2850 info = &dbg_port_dspt_cdt_tx9;
2851 rtw89_write16_mask(rtwdev, info->sel_addr,
2852 B_AX_DISPATCHER_INTN_SEL_MASK, 1);
2853 rtw89_write16_mask(rtwdev, info->sel_addr,
2854 B_AX_DISPATCHER_CH_SEL_MASK, 9);
2855 seq_puts(m, "Enable Dispatcher cdt tx9 dump.\n");
2856 break;
2857 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXA:
2858 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXB:
2859 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXC:
2860 info = &dbg_port_dspt_cdt_txA_C;
2861 index = sel + 0xA - RTW89_DBG_PORT_SEL_DSPT_CDT_TXA;
2862 rtw89_write16_mask(rtwdev, info->sel_addr,
2863 B_AX_DISPATCHER_INTN_SEL_MASK, 1);
2864 rtw89_write16_mask(rtwdev, info->sel_addr,
2865 B_AX_DISPATCHER_CH_SEL_MASK, index);
2866 seq_printf(m, "Enable Dispatcher cdt tx%x dump.\n", index);
2867 break;
2868 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX0:
2869 info = &dbg_port_dspt_hdt_rx0;
2870 rtw89_write16_mask(rtwdev, info->sel_addr,
2871 B_AX_DISPATCHER_INTN_SEL_MASK, 2);
2872 rtw89_write16_mask(rtwdev, info->sel_addr,
2873 B_AX_DISPATCHER_CH_SEL_MASK, 0);
2874 seq_puts(m, "Enable Dispatcher hdt rx0 dump.\n");
2875 break;
2876 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX1:
2877 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX2:
2878 info = &dbg_port_dspt_hdt_rx1_2;
2879 index = sel + 1 - RTW89_DBG_PORT_SEL_DSPT_HDT_RX1;
2880 rtw89_write16_mask(rtwdev, info->sel_addr,
2881 B_AX_DISPATCHER_INTN_SEL_MASK, 2);
2882 rtw89_write16_mask(rtwdev, info->sel_addr,
2883 B_AX_DISPATCHER_CH_SEL_MASK, index);
2884 seq_printf(m, "Enable Dispatcher hdt rx%x dump.\n", index);
2885 break;
2886 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX3:
2887 info = &dbg_port_dspt_hdt_rx3;
2888 rtw89_write16_mask(rtwdev, info->sel_addr,
2889 B_AX_DISPATCHER_INTN_SEL_MASK, 2);
2890 rtw89_write16_mask(rtwdev, info->sel_addr,
2891 B_AX_DISPATCHER_CH_SEL_MASK, 3);
2892 seq_puts(m, "Enable Dispatcher hdt rx3 dump.\n");
2893 break;
2894 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX4:
2895 info = &dbg_port_dspt_hdt_rx4;
2896 rtw89_write16_mask(rtwdev, info->sel_addr,
2897 B_AX_DISPATCHER_INTN_SEL_MASK, 2);
2898 rtw89_write16_mask(rtwdev, info->sel_addr,
2899 B_AX_DISPATCHER_CH_SEL_MASK, 4);
2900 seq_puts(m, "Enable Dispatcher hdt rx4 dump.\n");
2901 break;
2902 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX5:
2903 info = &dbg_port_dspt_hdt_rx5;
2904 rtw89_write16_mask(rtwdev, info->sel_addr,
2905 B_AX_DISPATCHER_INTN_SEL_MASK, 2);
2906 rtw89_write16_mask(rtwdev, info->sel_addr,
2907 B_AX_DISPATCHER_CH_SEL_MASK, 5);
2908 seq_puts(m, "Enable Dispatcher hdt rx5 dump.\n");
2909 break;
2910 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0:
2911 info = &dbg_port_dspt_cdt_rx_p0_0;
2912 rtw89_write16_mask(rtwdev, info->sel_addr,
2913 B_AX_DISPATCHER_INTN_SEL_MASK, 3);
2914 rtw89_write16_mask(rtwdev, info->sel_addr,
2915 B_AX_DISPATCHER_CH_SEL_MASK, 0);
2916 seq_puts(m, "Enable Dispatcher cdt rx part0 0 dump.\n");
2917 break;
2918 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0:
2919 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1:
2920 info = &dbg_port_dspt_cdt_rx_p0_1;
2921 rtw89_write16_mask(rtwdev, info->sel_addr,
2922 B_AX_DISPATCHER_INTN_SEL_MASK, 3);
2923 rtw89_write16_mask(rtwdev, info->sel_addr,
2924 B_AX_DISPATCHER_CH_SEL_MASK, 1);
2925 seq_puts(m, "Enable Dispatcher cdt rx part0 1 dump.\n");
2926 break;
2927 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2:
2928 info = &dbg_port_dspt_cdt_rx_p0_2;
2929 rtw89_write16_mask(rtwdev, info->sel_addr,
2930 B_AX_DISPATCHER_INTN_SEL_MASK, 3);
2931 rtw89_write16_mask(rtwdev, info->sel_addr,
2932 B_AX_DISPATCHER_CH_SEL_MASK, 2);
2933 seq_puts(m, "Enable Dispatcher cdt rx part0 2 dump.\n");
2934 break;
2935 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1:
2936 info = &dbg_port_dspt_cdt_rx_p1;
2937 rtw89_write8_mask(rtwdev, info->sel_addr,
2938 B_AX_DISPATCHER_INTN_SEL_MASK, 3);
2939 seq_puts(m, "Enable Dispatcher cdt rx part1 dump.\n");
2940 break;
2941 case RTW89_DBG_PORT_SEL_DSPT_STF_CTRL:
2942 info = &dbg_port_dspt_stf_ctrl;
2943 rtw89_write8_mask(rtwdev, info->sel_addr,
2944 B_AX_DISPATCHER_INTN_SEL_MASK, 4);
2945 seq_puts(m, "Enable Dispatcher stf control dump.\n");
2946 break;
2947 case RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL:
2948 info = &dbg_port_dspt_addr_ctrl;
2949 rtw89_write8_mask(rtwdev, info->sel_addr,
2950 B_AX_DISPATCHER_INTN_SEL_MASK, 5);
2951 seq_puts(m, "Enable Dispatcher addr control dump.\n");
2952 break;
2953 case RTW89_DBG_PORT_SEL_DSPT_WDE_INTF:
2954 info = &dbg_port_dspt_wde_intf;
2955 rtw89_write8_mask(rtwdev, info->sel_addr,
2956 B_AX_DISPATCHER_INTN_SEL_MASK, 6);
2957 seq_puts(m, "Enable Dispatcher wde interface dump.\n");
2958 break;
2959 case RTW89_DBG_PORT_SEL_DSPT_PLE_INTF:
2960 info = &dbg_port_dspt_ple_intf;
2961 rtw89_write8_mask(rtwdev, info->sel_addr,
2962 B_AX_DISPATCHER_INTN_SEL_MASK, 7);
2963 seq_puts(m, "Enable Dispatcher ple interface dump.\n");
2964 break;
2965 case RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL:
2966 info = &dbg_port_dspt_flow_ctrl;
2967 rtw89_write8_mask(rtwdev, info->sel_addr,
2968 B_AX_DISPATCHER_INTN_SEL_MASK, 8);
2969 seq_puts(m, "Enable Dispatcher flow control dump.\n");
2970 break;
2971 case RTW89_DBG_PORT_SEL_PCIE_TXDMA:
2972 info = &dbg_port_pcie_txdma;
2973 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
2974 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL0);
2975 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL1);
2976 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
2977 seq_puts(m, "Enable pcie txdma dump.\n");
2978 break;
2979 case RTW89_DBG_PORT_SEL_PCIE_RXDMA:
2980 info = &dbg_port_pcie_rxdma;
2981 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
2982 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL0);
2983 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL1);
2984 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
2985 seq_puts(m, "Enable pcie rxdma dump.\n");
2986 break;
2987 case RTW89_DBG_PORT_SEL_PCIE_CVT:
2988 info = &dbg_port_pcie_cvt;
2989 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
2990 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL0);
2991 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL1);
2992 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
2993 seq_puts(m, "Enable pcie cvt dump.\n");
2994 break;
2995 case RTW89_DBG_PORT_SEL_PCIE_CXPL:
2996 info = &dbg_port_pcie_cxpl;
2997 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
2998 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL0);
2999 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL1);
3000 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
3001 seq_puts(m, "Enable pcie cxpl dump.\n");
3002 break;
3003 case RTW89_DBG_PORT_SEL_PCIE_IO:
3004 info = &dbg_port_pcie_io;
3005 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
3006 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL0);
3007 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL1);
3008 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
3009 seq_puts(m, "Enable pcie io dump.\n");
3010 break;
3011 case RTW89_DBG_PORT_SEL_PCIE_MISC:
3012 info = &dbg_port_pcie_misc;
3013 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
3014 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL0);
3015 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL1);
3016 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
3017 seq_puts(m, "Enable pcie misc dump.\n");
3018 break;
3019 case RTW89_DBG_PORT_SEL_PCIE_MISC2:
3020 info = &dbg_port_pcie_misc2;
3021 val16 = rtw89_read16(rtwdev, R_AX_PCIE_DBG_CTRL);
3022 val16 = u16_replace_bits(val16, PCIE_MISC2_DBG_SEL,
3023 B_AX_PCIE_DBG_SEL_MASK);
3024 rtw89_write16(rtwdev, R_AX_PCIE_DBG_CTRL, val16);
3025 seq_puts(m, "Enable pcie misc2 dump.\n");
3026 break;
3027 default:
3028 seq_puts(m, "Dbg port select err\n");
3029 return NULL;
3030 }
3031
3032 return info;
3033 }
3034
is_dbg_port_valid(struct rtw89_dev * rtwdev,u32 sel)3035 static bool is_dbg_port_valid(struct rtw89_dev *rtwdev, u32 sel)
3036 {
3037 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE &&
3038 sel >= RTW89_DBG_PORT_SEL_PCIE_TXDMA &&
3039 sel <= RTW89_DBG_PORT_SEL_PCIE_MISC2)
3040 return false;
3041 if (rtw89_is_rtl885xb(rtwdev) &&
3042 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 &&
3043 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1)
3044 return false;
3045 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) &&
3046 sel >= RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG &&
3047 sel <= RTW89_DBG_PORT_SEL_PKTINFO)
3048 return false;
3049 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) &&
3050 sel >= RTW89_DBG_PORT_SEL_DSPT_HDT_TX0 &&
3051 sel <= RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL)
3052 return false;
3053 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL) &&
3054 sel >= RTW89_DBG_PORT_SEL_PTCL_C0 &&
3055 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C0)
3056 return false;
3057 if (rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL) &&
3058 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 &&
3059 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1)
3060 return false;
3061
3062 return true;
3063 }
3064
rtw89_debug_mac_dbg_port_dump(struct rtw89_dev * rtwdev,struct seq_file * m,u32 sel)3065 static int rtw89_debug_mac_dbg_port_dump(struct rtw89_dev *rtwdev,
3066 struct seq_file *m, u32 sel)
3067 {
3068 const struct rtw89_mac_dbg_port_info *info;
3069 u8 val8;
3070 u16 val16;
3071 u32 val32;
3072 u32 i;
3073
3074 info = rtw89_debug_mac_dbg_port_sel(m, rtwdev, sel);
3075 if (!info) {
3076 rtw89_err(rtwdev, "failed to select debug port %d\n", sel);
3077 return -EINVAL;
3078 }
3079
3080 #define case_DBG_SEL(__sel) \
3081 case RTW89_DBG_PORT_SEL_##__sel: \
3082 seq_puts(m, "Dump debug port " #__sel ":\n"); \
3083 break
3084
3085 switch (sel) {
3086 case_DBG_SEL(PTCL_C0);
3087 case_DBG_SEL(PTCL_C1);
3088 case_DBG_SEL(SCH_C0);
3089 case_DBG_SEL(SCH_C1);
3090 case_DBG_SEL(TMAC_C0);
3091 case_DBG_SEL(TMAC_C1);
3092 case_DBG_SEL(RMAC_C0);
3093 case_DBG_SEL(RMAC_C1);
3094 case_DBG_SEL(RMACST_C0);
3095 case_DBG_SEL(RMACST_C1);
3096 case_DBG_SEL(TRXPTCL_C0);
3097 case_DBG_SEL(TRXPTCL_C1);
3098 case_DBG_SEL(TX_INFOL_C0);
3099 case_DBG_SEL(TX_INFOH_C0);
3100 case_DBG_SEL(TX_INFOL_C1);
3101 case_DBG_SEL(TX_INFOH_C1);
3102 case_DBG_SEL(TXTF_INFOL_C0);
3103 case_DBG_SEL(TXTF_INFOH_C0);
3104 case_DBG_SEL(TXTF_INFOL_C1);
3105 case_DBG_SEL(TXTF_INFOH_C1);
3106 case_DBG_SEL(WDE_BUFMGN_FREEPG);
3107 case_DBG_SEL(WDE_BUFMGN_QUOTA);
3108 case_DBG_SEL(WDE_BUFMGN_PAGELLT);
3109 case_DBG_SEL(WDE_BUFMGN_PKTINFO);
3110 case_DBG_SEL(WDE_QUEMGN_PREPKT);
3111 case_DBG_SEL(WDE_QUEMGN_NXTPKT);
3112 case_DBG_SEL(WDE_QUEMGN_QLNKTBL);
3113 case_DBG_SEL(WDE_QUEMGN_QEMPTY);
3114 case_DBG_SEL(PLE_BUFMGN_FREEPG);
3115 case_DBG_SEL(PLE_BUFMGN_QUOTA);
3116 case_DBG_SEL(PLE_BUFMGN_PAGELLT);
3117 case_DBG_SEL(PLE_BUFMGN_PKTINFO);
3118 case_DBG_SEL(PLE_QUEMGN_PREPKT);
3119 case_DBG_SEL(PLE_QUEMGN_NXTPKT);
3120 case_DBG_SEL(PLE_QUEMGN_QLNKTBL);
3121 case_DBG_SEL(PLE_QUEMGN_QEMPTY);
3122 case_DBG_SEL(PKTINFO);
3123 case_DBG_SEL(DSPT_HDT_TX0);
3124 case_DBG_SEL(DSPT_HDT_TX1);
3125 case_DBG_SEL(DSPT_HDT_TX2);
3126 case_DBG_SEL(DSPT_HDT_TX3);
3127 case_DBG_SEL(DSPT_HDT_TX4);
3128 case_DBG_SEL(DSPT_HDT_TX5);
3129 case_DBG_SEL(DSPT_HDT_TX6);
3130 case_DBG_SEL(DSPT_HDT_TX7);
3131 case_DBG_SEL(DSPT_HDT_TX8);
3132 case_DBG_SEL(DSPT_HDT_TX9);
3133 case_DBG_SEL(DSPT_HDT_TXA);
3134 case_DBG_SEL(DSPT_HDT_TXB);
3135 case_DBG_SEL(DSPT_HDT_TXC);
3136 case_DBG_SEL(DSPT_HDT_TXD);
3137 case_DBG_SEL(DSPT_HDT_TXE);
3138 case_DBG_SEL(DSPT_HDT_TXF);
3139 case_DBG_SEL(DSPT_CDT_TX0);
3140 case_DBG_SEL(DSPT_CDT_TX1);
3141 case_DBG_SEL(DSPT_CDT_TX3);
3142 case_DBG_SEL(DSPT_CDT_TX4);
3143 case_DBG_SEL(DSPT_CDT_TX5);
3144 case_DBG_SEL(DSPT_CDT_TX6);
3145 case_DBG_SEL(DSPT_CDT_TX7);
3146 case_DBG_SEL(DSPT_CDT_TX8);
3147 case_DBG_SEL(DSPT_CDT_TX9);
3148 case_DBG_SEL(DSPT_CDT_TXA);
3149 case_DBG_SEL(DSPT_CDT_TXB);
3150 case_DBG_SEL(DSPT_CDT_TXC);
3151 case_DBG_SEL(DSPT_HDT_RX0);
3152 case_DBG_SEL(DSPT_HDT_RX1);
3153 case_DBG_SEL(DSPT_HDT_RX2);
3154 case_DBG_SEL(DSPT_HDT_RX3);
3155 case_DBG_SEL(DSPT_HDT_RX4);
3156 case_DBG_SEL(DSPT_HDT_RX5);
3157 case_DBG_SEL(DSPT_CDT_RX_P0);
3158 case_DBG_SEL(DSPT_CDT_RX_P0_0);
3159 case_DBG_SEL(DSPT_CDT_RX_P0_1);
3160 case_DBG_SEL(DSPT_CDT_RX_P0_2);
3161 case_DBG_SEL(DSPT_CDT_RX_P1);
3162 case_DBG_SEL(DSPT_STF_CTRL);
3163 case_DBG_SEL(DSPT_ADDR_CTRL);
3164 case_DBG_SEL(DSPT_WDE_INTF);
3165 case_DBG_SEL(DSPT_PLE_INTF);
3166 case_DBG_SEL(DSPT_FLOW_CTRL);
3167 case_DBG_SEL(PCIE_TXDMA);
3168 case_DBG_SEL(PCIE_RXDMA);
3169 case_DBG_SEL(PCIE_CVT);
3170 case_DBG_SEL(PCIE_CXPL);
3171 case_DBG_SEL(PCIE_IO);
3172 case_DBG_SEL(PCIE_MISC);
3173 case_DBG_SEL(PCIE_MISC2);
3174 }
3175
3176 #undef case_DBG_SEL
3177
3178 seq_printf(m, "Sel addr = 0x%X\n", info->sel_addr);
3179 seq_printf(m, "Read addr = 0x%X\n", info->rd_addr);
3180
3181 for (i = info->srt; i <= info->end; i++) {
3182 switch (info->sel_byte) {
3183 case 1:
3184 default:
3185 rtw89_write8_mask(rtwdev, info->sel_addr,
3186 info->sel_msk, i);
3187 seq_printf(m, "0x%02X: ", i);
3188 break;
3189 case 2:
3190 rtw89_write16_mask(rtwdev, info->sel_addr,
3191 info->sel_msk, i);
3192 seq_printf(m, "0x%04X: ", i);
3193 break;
3194 case 4:
3195 rtw89_write32_mask(rtwdev, info->sel_addr,
3196 info->sel_msk, i);
3197 seq_printf(m, "0x%04X: ", i);
3198 break;
3199 }
3200
3201 udelay(10);
3202
3203 switch (info->rd_byte) {
3204 case 1:
3205 default:
3206 val8 = rtw89_read8_mask(rtwdev,
3207 info->rd_addr, info->rd_msk);
3208 seq_printf(m, "0x%02X\n", val8);
3209 break;
3210 case 2:
3211 val16 = rtw89_read16_mask(rtwdev,
3212 info->rd_addr, info->rd_msk);
3213 seq_printf(m, "0x%04X\n", val16);
3214 break;
3215 case 4:
3216 val32 = rtw89_read32_mask(rtwdev,
3217 info->rd_addr, info->rd_msk);
3218 seq_printf(m, "0x%08X\n", val32);
3219 break;
3220 }
3221 }
3222
3223 return 0;
3224 }
3225
rtw89_debug_mac_dump_dbg_port(struct rtw89_dev * rtwdev,struct seq_file * m)3226 static int rtw89_debug_mac_dump_dbg_port(struct rtw89_dev *rtwdev,
3227 struct seq_file *m)
3228 {
3229 u32 sel;
3230 int ret = 0;
3231
3232 for (sel = RTW89_DBG_PORT_SEL_PTCL_C0;
3233 sel < RTW89_DBG_PORT_SEL_LAST; sel++) {
3234 if (!is_dbg_port_valid(rtwdev, sel))
3235 continue;
3236 ret = rtw89_debug_mac_dbg_port_dump(rtwdev, m, sel);
3237 if (ret) {
3238 rtw89_err(rtwdev,
3239 "failed to dump debug port %d\n", sel);
3240 break;
3241 }
3242 }
3243
3244 return ret;
3245 }
3246
3247 static int
rtw89_debug_priv_mac_dbg_port_dump_get(struct seq_file * m,void * v)3248 rtw89_debug_priv_mac_dbg_port_dump_get(struct seq_file *m, void *v)
3249 {
3250 struct rtw89_debugfs_priv *debugfs_priv = m->private;
3251 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
3252
3253 if (debugfs_priv->dbgpkg_en.ss_dbg)
3254 rtw89_debug_mac_dump_ss_dbg(rtwdev, m);
3255 if (debugfs_priv->dbgpkg_en.dle_dbg)
3256 rtw89_debug_mac_dump_dle_dbg(rtwdev, m);
3257 if (debugfs_priv->dbgpkg_en.dmac_dbg)
3258 rtw89_debug_mac_dump_dmac_dbg(rtwdev, m);
3259 if (debugfs_priv->dbgpkg_en.cmac_dbg)
3260 rtw89_debug_mac_dump_cmac_dbg(rtwdev, m);
3261 if (debugfs_priv->dbgpkg_en.dbg_port)
3262 rtw89_debug_mac_dump_dbg_port(rtwdev, m);
3263
3264 return 0;
3265 };
3266
rtw89_hex2bin_user(struct rtw89_dev * rtwdev,const char __user * user_buf,size_t count)3267 static u8 *rtw89_hex2bin_user(struct rtw89_dev *rtwdev,
3268 const char __user *user_buf, size_t count)
3269 {
3270 char *buf;
3271 u8 *bin;
3272 int num;
3273 int err = 0;
3274
3275 buf = memdup_user(user_buf, count);
3276 if (IS_ERR(buf))
3277 return buf;
3278
3279 num = count / 2;
3280 bin = kmalloc(num, GFP_KERNEL);
3281 if (!bin) {
3282 err = -EFAULT;
3283 goto out;
3284 }
3285
3286 if (hex2bin(bin, buf, num)) {
3287 rtw89_info(rtwdev, "valid format: H1H2H3...\n");
3288 kfree(bin);
3289 err = -EINVAL;
3290 }
3291
3292 out:
3293 kfree(buf);
3294
3295 return err ? ERR_PTR(err) : bin;
3296 }
3297
rtw89_debug_priv_send_h2c_set(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)3298 static ssize_t rtw89_debug_priv_send_h2c_set(struct file *filp,
3299 const char __user *user_buf,
3300 size_t count, loff_t *loff)
3301 {
3302 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data;
3303 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
3304 u8 *h2c;
3305 int ret;
3306 u16 h2c_len = count / 2;
3307
3308 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count);
3309 if (IS_ERR(h2c))
3310 return -EFAULT;
3311
3312 ret = rtw89_fw_h2c_raw(rtwdev, h2c, h2c_len);
3313
3314 kfree(h2c);
3315
3316 return ret ? ret : count;
3317 }
3318
3319 static int
rtw89_debug_priv_early_h2c_get(struct seq_file * m,void * v)3320 rtw89_debug_priv_early_h2c_get(struct seq_file *m, void *v)
3321 {
3322 struct rtw89_debugfs_priv *debugfs_priv = m->private;
3323 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
3324 struct rtw89_early_h2c *early_h2c;
3325 int seq = 0;
3326
3327 mutex_lock(&rtwdev->mutex);
3328 list_for_each_entry(early_h2c, &rtwdev->early_h2c_list, list)
3329 seq_printf(m, "%d: %*ph\n", ++seq, early_h2c->h2c_len, early_h2c->h2c);
3330 mutex_unlock(&rtwdev->mutex);
3331
3332 return 0;
3333 }
3334
3335 static ssize_t
rtw89_debug_priv_early_h2c_set(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)3336 rtw89_debug_priv_early_h2c_set(struct file *filp, const char __user *user_buf,
3337 size_t count, loff_t *loff)
3338 {
3339 struct seq_file *m = (struct seq_file *)filp->private_data;
3340 struct rtw89_debugfs_priv *debugfs_priv = m->private;
3341 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
3342 struct rtw89_early_h2c *early_h2c;
3343 u8 *h2c;
3344 u16 h2c_len = count / 2;
3345
3346 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count);
3347 if (IS_ERR(h2c))
3348 return -EFAULT;
3349
3350 if (h2c_len >= 2 && h2c[0] == 0x00 && h2c[1] == 0x00) {
3351 kfree(h2c);
3352 rtw89_fw_free_all_early_h2c(rtwdev);
3353 goto out;
3354 }
3355
3356 early_h2c = kmalloc(sizeof(*early_h2c), GFP_KERNEL);
3357 if (!early_h2c) {
3358 kfree(h2c);
3359 return -EFAULT;
3360 }
3361
3362 early_h2c->h2c = h2c;
3363 early_h2c->h2c_len = h2c_len;
3364
3365 mutex_lock(&rtwdev->mutex);
3366 list_add_tail(&early_h2c->list, &rtwdev->early_h2c_list);
3367 mutex_unlock(&rtwdev->mutex);
3368
3369 out:
3370 return count;
3371 }
3372
rtw89_dbg_trigger_ctrl_error(struct rtw89_dev * rtwdev)3373 static int rtw89_dbg_trigger_ctrl_error(struct rtw89_dev *rtwdev)
3374 {
3375 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
3376 struct rtw89_cpuio_ctrl ctrl_para = {0};
3377 u16 pkt_id;
3378 int ret;
3379
3380 rtw89_leave_ps_mode(rtwdev);
3381
3382 ret = mac->dle_buf_req(rtwdev, 0x20, true, &pkt_id);
3383 if (ret)
3384 return ret;
3385
3386 /* intentionally, enqueue two pkt, but has only one pkt id */
3387 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD;
3388 ctrl_para.start_pktid = pkt_id;
3389 ctrl_para.end_pktid = pkt_id;
3390 ctrl_para.pkt_num = 1; /* start from 0 */
3391 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS;
3392 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT;
3393
3394 if (mac->set_cpuio(rtwdev, &ctrl_para, true))
3395 return -EFAULT;
3396
3397 return 0;
3398 }
3399
3400 static int
rtw89_debug_priv_fw_crash_get(struct seq_file * m,void * v)3401 rtw89_debug_priv_fw_crash_get(struct seq_file *m, void *v)
3402 {
3403 struct rtw89_debugfs_priv *debugfs_priv = m->private;
3404 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
3405
3406 seq_printf(m, "%d\n",
3407 test_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags));
3408 return 0;
3409 }
3410
3411 enum rtw89_dbg_crash_simulation_type {
3412 RTW89_DBG_SIM_CPU_EXCEPTION = 1,
3413 RTW89_DBG_SIM_CTRL_ERROR = 2,
3414 };
3415
3416 static ssize_t
rtw89_debug_priv_fw_crash_set(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)3417 rtw89_debug_priv_fw_crash_set(struct file *filp, const char __user *user_buf,
3418 size_t count, loff_t *loff)
3419 {
3420 struct seq_file *m = (struct seq_file *)filp->private_data;
3421 struct rtw89_debugfs_priv *debugfs_priv = m->private;
3422 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
3423 int (*sim)(struct rtw89_dev *rtwdev);
3424 u8 crash_type;
3425 int ret;
3426
3427 ret = kstrtou8_from_user(user_buf, count, 0, &crash_type);
3428 if (ret)
3429 return -EINVAL;
3430
3431 switch (crash_type) {
3432 case RTW89_DBG_SIM_CPU_EXCEPTION:
3433 if (!RTW89_CHK_FW_FEATURE(CRASH_TRIGGER, &rtwdev->fw))
3434 return -EOPNOTSUPP;
3435 sim = rtw89_fw_h2c_trigger_cpu_exception;
3436 break;
3437 case RTW89_DBG_SIM_CTRL_ERROR:
3438 sim = rtw89_dbg_trigger_ctrl_error;
3439 break;
3440 default:
3441 return -EINVAL;
3442 }
3443
3444 mutex_lock(&rtwdev->mutex);
3445 set_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags);
3446 ret = sim(rtwdev);
3447 mutex_unlock(&rtwdev->mutex);
3448
3449 if (ret)
3450 return ret;
3451
3452 return count;
3453 }
3454
rtw89_debug_priv_btc_info_get(struct seq_file * m,void * v)3455 static int rtw89_debug_priv_btc_info_get(struct seq_file *m, void *v)
3456 {
3457 struct rtw89_debugfs_priv *debugfs_priv = m->private;
3458 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
3459
3460 rtw89_btc_dump_info(rtwdev, m);
3461
3462 return 0;
3463 }
3464
rtw89_debug_priv_btc_manual_set(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)3465 static ssize_t rtw89_debug_priv_btc_manual_set(struct file *filp,
3466 const char __user *user_buf,
3467 size_t count, loff_t *loff)
3468 {
3469 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data;
3470 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
3471 struct rtw89_btc *btc = &rtwdev->btc;
3472 const struct rtw89_btc_ver *ver = btc->ver;
3473 int ret;
3474
3475 ret = kstrtobool_from_user(user_buf, count, &btc->manual_ctrl);
3476 if (ret)
3477 return ret;
3478
3479 if (ver->fcxctrl == 7)
3480 btc->ctrl.ctrl_v7.manual = btc->manual_ctrl;
3481 else
3482 btc->ctrl.ctrl.manual = btc->manual_ctrl;
3483
3484 return count;
3485 }
3486
rtw89_debug_priv_fw_log_manual_set(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)3487 static ssize_t rtw89_debug_priv_fw_log_manual_set(struct file *filp,
3488 const char __user *user_buf,
3489 size_t count, loff_t *loff)
3490 {
3491 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data;
3492 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
3493 struct rtw89_fw_log *log = &rtwdev->fw.log;
3494 bool fw_log_manual;
3495
3496 if (kstrtobool_from_user(user_buf, count, &fw_log_manual))
3497 goto out;
3498
3499 mutex_lock(&rtwdev->mutex);
3500 log->enable = fw_log_manual;
3501 if (log->enable)
3502 rtw89_fw_log_prepare(rtwdev);
3503 rtw89_fw_h2c_fw_log(rtwdev, fw_log_manual);
3504 mutex_unlock(&rtwdev->mutex);
3505 out:
3506 return count;
3507 }
3508
rtw89_sta_info_get_iter(void * data,struct ieee80211_sta * sta)3509 static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta)
3510 {
3511 static const char * const he_gi_str[] = {
3512 [NL80211_RATE_INFO_HE_GI_0_8] = "0.8",
3513 [NL80211_RATE_INFO_HE_GI_1_6] = "1.6",
3514 [NL80211_RATE_INFO_HE_GI_3_2] = "3.2",
3515 };
3516 static const char * const eht_gi_str[] = {
3517 [NL80211_RATE_INFO_EHT_GI_0_8] = "0.8",
3518 [NL80211_RATE_INFO_EHT_GI_1_6] = "1.6",
3519 [NL80211_RATE_INFO_EHT_GI_3_2] = "3.2",
3520 };
3521 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
3522 struct rate_info *rate = &rtwsta->ra_report.txrate;
3523 struct ieee80211_rx_status *status = &rtwsta->rx_status;
3524 struct seq_file *m = (struct seq_file *)data;
3525 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
3526 struct rtw89_hal *hal = &rtwdev->hal;
3527 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num;
3528 bool ant_asterisk = hal->tx_path_diversity || hal->ant_diversity;
3529 u8 evm_min, evm_max, evm_1ss;
3530 u8 rssi;
3531 u8 snr;
3532 int i;
3533
3534 seq_printf(m, "TX rate [%d]: ", rtwsta->mac_id);
3535
3536 if (rate->flags & RATE_INFO_FLAGS_MCS)
3537 seq_printf(m, "HT MCS-%d%s", rate->mcs,
3538 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : "");
3539 else if (rate->flags & RATE_INFO_FLAGS_VHT_MCS)
3540 seq_printf(m, "VHT %dSS MCS-%d%s", rate->nss, rate->mcs,
3541 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : "");
3542 else if (rate->flags & RATE_INFO_FLAGS_HE_MCS)
3543 seq_printf(m, "HE %dSS MCS-%d GI:%s", rate->nss, rate->mcs,
3544 rate->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ?
3545 he_gi_str[rate->he_gi] : "N/A");
3546 else if (rate->flags & RATE_INFO_FLAGS_EHT_MCS)
3547 seq_printf(m, "EHT %dSS MCS-%d GI:%s", rate->nss, rate->mcs,
3548 rate->eht_gi < ARRAY_SIZE(eht_gi_str) ?
3549 eht_gi_str[rate->eht_gi] : "N/A");
3550 else
3551 seq_printf(m, "Legacy %d", rate->legacy);
3552 seq_printf(m, "%s", rtwsta->ra_report.might_fallback_legacy ? " FB_G" : "");
3553 seq_printf(m, " BW:%u", rtw89_rate_info_bw_to_mhz(rate->bw));
3554 seq_printf(m, "\t(hw_rate=0x%x)", rtwsta->ra_report.hw_rate);
3555 seq_printf(m, "\t==> agg_wait=%d (%d)\n", rtwsta->max_agg_wait,
3556 sta->deflink.agg.max_rc_amsdu_len);
3557
3558 seq_printf(m, "RX rate [%d]: ", rtwsta->mac_id);
3559
3560 switch (status->encoding) {
3561 case RX_ENC_LEGACY:
3562 seq_printf(m, "Legacy %d", status->rate_idx +
3563 (status->band != NL80211_BAND_2GHZ ? 4 : 0));
3564 break;
3565 case RX_ENC_HT:
3566 seq_printf(m, "HT MCS-%d%s", status->rate_idx,
3567 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : "");
3568 break;
3569 case RX_ENC_VHT:
3570 seq_printf(m, "VHT %dSS MCS-%d%s", status->nss, status->rate_idx,
3571 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : "");
3572 break;
3573 case RX_ENC_HE:
3574 seq_printf(m, "HE %dSS MCS-%d GI:%s", status->nss, status->rate_idx,
3575 status->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ?
3576 he_gi_str[status->he_gi] : "N/A");
3577 break;
3578 case RX_ENC_EHT:
3579 seq_printf(m, "EHT %dSS MCS-%d GI:%s", status->nss, status->rate_idx,
3580 status->eht.gi < ARRAY_SIZE(eht_gi_str) ?
3581 eht_gi_str[status->eht.gi] : "N/A");
3582 break;
3583 }
3584 seq_printf(m, " BW:%u", rtw89_rate_info_bw_to_mhz(status->bw));
3585 seq_printf(m, "\t(hw_rate=0x%x)\n", rtwsta->rx_hw_rate);
3586
3587 rssi = ewma_rssi_read(&rtwsta->avg_rssi);
3588 seq_printf(m, "RSSI: %d dBm (raw=%d, prev=%d) [",
3589 RTW89_RSSI_RAW_TO_DBM(rssi), rssi, rtwsta->prev_rssi);
3590 for (i = 0; i < ant_num; i++) {
3591 rssi = ewma_rssi_read(&rtwsta->rssi[i]);
3592 seq_printf(m, "%d%s%s", RTW89_RSSI_RAW_TO_DBM(rssi),
3593 ant_asterisk && (hal->antenna_tx & BIT(i)) ? "*" : "",
3594 i + 1 == ant_num ? "" : ", ");
3595 }
3596 seq_puts(m, "]\n");
3597
3598 evm_1ss = ewma_evm_read(&rtwsta->evm_1ss);
3599 seq_printf(m, "EVM: [%2u.%02u, ", evm_1ss >> 2, (evm_1ss & 0x3) * 25);
3600 for (i = 0; i < (hal->ant_diversity ? 2 : 1); i++) {
3601 evm_min = ewma_evm_read(&rtwsta->evm_min[i]);
3602 evm_max = ewma_evm_read(&rtwsta->evm_max[i]);
3603
3604 seq_printf(m, "%s(%2u.%02u, %2u.%02u)", i == 0 ? "" : " ",
3605 evm_min >> 2, (evm_min & 0x3) * 25,
3606 evm_max >> 2, (evm_max & 0x3) * 25);
3607 }
3608 seq_puts(m, "]\t");
3609
3610 snr = ewma_snr_read(&rtwsta->avg_snr);
3611 seq_printf(m, "SNR: %u\n", snr);
3612 }
3613
3614 static void
rtw89_debug_append_rx_rate(struct seq_file * m,struct rtw89_pkt_stat * pkt_stat,enum rtw89_hw_rate first_rate,int len)3615 rtw89_debug_append_rx_rate(struct seq_file *m, struct rtw89_pkt_stat *pkt_stat,
3616 enum rtw89_hw_rate first_rate, int len)
3617 {
3618 int i;
3619
3620 for (i = 0; i < len; i++)
3621 seq_printf(m, "%s%u", i == 0 ? "" : ", ",
3622 pkt_stat->rx_rate_cnt[first_rate + i]);
3623 }
3624
3625 #define FIRST_RATE_SAME(rate) {RTW89_HW_RATE_ ## rate, RTW89_HW_RATE_ ## rate}
3626 #define FIRST_RATE_ENUM(rate) {RTW89_HW_RATE_ ## rate, RTW89_HW_RATE_V1_ ## rate}
3627 #define FIRST_RATE_GEV1(rate) {RTW89_HW_RATE_INVAL, RTW89_HW_RATE_V1_ ## rate}
3628
3629 static const struct rtw89_rx_rate_cnt_info {
3630 enum rtw89_hw_rate first_rate[RTW89_CHIP_GEN_NUM];
3631 int len;
3632 int ext;
3633 const char *rate_mode;
3634 } rtw89_rx_rate_cnt_infos[] = {
3635 {FIRST_RATE_SAME(CCK1), 4, 0, "Legacy:"},
3636 {FIRST_RATE_SAME(OFDM6), 8, 0, "OFDM:"},
3637 {FIRST_RATE_ENUM(MCS0), 8, 0, "HT 0:"},
3638 {FIRST_RATE_ENUM(MCS8), 8, 0, "HT 1:"},
3639 {FIRST_RATE_ENUM(VHT_NSS1_MCS0), 10, 2, "VHT 1SS:"},
3640 {FIRST_RATE_ENUM(VHT_NSS2_MCS0), 10, 2, "VHT 2SS:"},
3641 {FIRST_RATE_ENUM(HE_NSS1_MCS0), 12, 0, "HE 1SS:"},
3642 {FIRST_RATE_ENUM(HE_NSS2_MCS0), 12, 0, "HE 2SS:"},
3643 {FIRST_RATE_GEV1(EHT_NSS1_MCS0), 14, 2, "EHT 1SS:"},
3644 {FIRST_RATE_GEV1(EHT_NSS2_MCS0), 14, 0, "EHT 2SS:"},
3645 };
3646
rtw89_debug_priv_phy_info_get(struct seq_file * m,void * v)3647 static int rtw89_debug_priv_phy_info_get(struct seq_file *m, void *v)
3648 {
3649 struct rtw89_debugfs_priv *debugfs_priv = m->private;
3650 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
3651 struct rtw89_traffic_stats *stats = &rtwdev->stats;
3652 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.last_pkt_stat;
3653 const struct rtw89_chip_info *chip = rtwdev->chip;
3654 const struct rtw89_rx_rate_cnt_info *info;
3655 enum rtw89_hw_rate first_rate;
3656 int i;
3657
3658 seq_printf(m, "TP TX: %u [%u] Mbps (lv: %d), RX: %u [%u] Mbps (lv: %d)\n",
3659 stats->tx_throughput, stats->tx_throughput_raw, stats->tx_tfc_lv,
3660 stats->rx_throughput, stats->rx_throughput_raw, stats->rx_tfc_lv);
3661 seq_printf(m, "Beacon: %u, TF: %u\n", pkt_stat->beacon_nr,
3662 stats->rx_tf_periodic);
3663 seq_printf(m, "Avg packet length: TX=%u, RX=%u\n", stats->tx_avg_len,
3664 stats->rx_avg_len);
3665
3666 seq_puts(m, "RX count:\n");
3667
3668 for (i = 0; i < ARRAY_SIZE(rtw89_rx_rate_cnt_infos); i++) {
3669 info = &rtw89_rx_rate_cnt_infos[i];
3670 first_rate = info->first_rate[chip->chip_gen];
3671 if (first_rate >= RTW89_HW_RATE_NR)
3672 continue;
3673
3674 seq_printf(m, "%10s [", info->rate_mode);
3675 rtw89_debug_append_rx_rate(m, pkt_stat,
3676 first_rate, info->len);
3677 if (info->ext) {
3678 seq_puts(m, "][");
3679 rtw89_debug_append_rx_rate(m, pkt_stat,
3680 first_rate + info->len, info->ext);
3681 }
3682 seq_puts(m, "]\n");
3683 }
3684
3685 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_info_get_iter, m);
3686
3687 return 0;
3688 }
3689
rtw89_dump_addr_cam(struct seq_file * m,struct rtw89_dev * rtwdev,struct rtw89_addr_cam_entry * addr_cam)3690 static void rtw89_dump_addr_cam(struct seq_file *m,
3691 struct rtw89_dev *rtwdev,
3692 struct rtw89_addr_cam_entry *addr_cam)
3693 {
3694 struct rtw89_cam_info *cam_info = &rtwdev->cam_info;
3695 const struct rtw89_sec_cam_entry *sec_entry;
3696 u8 sec_cam_idx;
3697 int i;
3698
3699 seq_printf(m, "\taddr_cam_idx=%u\n", addr_cam->addr_cam_idx);
3700 seq_printf(m, "\t-> bssid_cam_idx=%u\n", addr_cam->bssid_cam_idx);
3701 seq_printf(m, "\tsec_cam_bitmap=%*ph\n", (int)sizeof(addr_cam->sec_cam_map),
3702 addr_cam->sec_cam_map);
3703 for_each_set_bit(i, addr_cam->sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM) {
3704 sec_cam_idx = addr_cam->sec_ent[i];
3705 sec_entry = cam_info->sec_entries[sec_cam_idx];
3706 if (!sec_entry)
3707 continue;
3708 seq_printf(m, "\tsec[%d]: sec_cam_idx %u", i, sec_entry->sec_cam_idx);
3709 if (sec_entry->ext_key)
3710 seq_printf(m, ", %u", sec_entry->sec_cam_idx + 1);
3711 seq_puts(m, "\n");
3712 }
3713 }
3714
3715 __printf(3, 4)
rtw89_dump_pkt_offload(struct seq_file * m,struct list_head * pkt_list,const char * fmt,...)3716 static void rtw89_dump_pkt_offload(struct seq_file *m, struct list_head *pkt_list,
3717 const char *fmt, ...)
3718 {
3719 struct rtw89_pktofld_info *info;
3720 struct va_format vaf;
3721 va_list args;
3722
3723 if (list_empty(pkt_list))
3724 return;
3725
3726 va_start(args, fmt);
3727 vaf.va = &args;
3728 vaf.fmt = fmt;
3729
3730 seq_printf(m, "%pV", &vaf);
3731
3732 va_end(args);
3733
3734 list_for_each_entry(info, pkt_list, list)
3735 seq_printf(m, "%d ", info->id);
3736
3737 seq_puts(m, "\n");
3738 }
3739
3740 static
rtw89_vif_ids_get_iter(void * data,u8 * mac,struct ieee80211_vif * vif)3741 void rtw89_vif_ids_get_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
3742 {
3743 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
3744 struct rtw89_dev *rtwdev = rtwvif->rtwdev;
3745 struct seq_file *m = (struct seq_file *)data;
3746 struct rtw89_bssid_cam_entry *bssid_cam = &rtwvif->bssid_cam;
3747
3748 seq_printf(m, "VIF [%d] %pM\n", rtwvif->mac_id, rtwvif->mac_addr);
3749 seq_printf(m, "\tbssid_cam_idx=%u\n", bssid_cam->bssid_cam_idx);
3750 rtw89_dump_addr_cam(m, rtwdev, &rtwvif->addr_cam);
3751 rtw89_dump_pkt_offload(m, &rtwvif->general_pkt_list, "\tpkt_ofld[GENERAL]: ");
3752 }
3753
rtw89_dump_ba_cam(struct seq_file * m,struct rtw89_sta * rtwsta)3754 static void rtw89_dump_ba_cam(struct seq_file *m, struct rtw89_sta *rtwsta)
3755 {
3756 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
3757 struct rtw89_dev *rtwdev = rtwvif->rtwdev;
3758 struct rtw89_ba_cam_entry *entry;
3759 bool first = true;
3760
3761 list_for_each_entry(entry, &rtwsta->ba_cam_list, list) {
3762 if (first) {
3763 seq_puts(m, "\tba_cam ");
3764 first = false;
3765 } else {
3766 seq_puts(m, ", ");
3767 }
3768 seq_printf(m, "tid[%u]=%d", entry->tid,
3769 (int)(entry - rtwdev->cam_info.ba_cam_entry));
3770 }
3771 seq_puts(m, "\n");
3772 }
3773
rtw89_sta_ids_get_iter(void * data,struct ieee80211_sta * sta)3774 static void rtw89_sta_ids_get_iter(void *data, struct ieee80211_sta *sta)
3775 {
3776 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
3777 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
3778 struct seq_file *m = (struct seq_file *)data;
3779
3780 seq_printf(m, "STA [%d] %pM %s\n", rtwsta->mac_id, sta->addr,
3781 sta->tdls ? "(TDLS)" : "");
3782 rtw89_dump_addr_cam(m, rtwdev, &rtwsta->addr_cam);
3783 rtw89_dump_ba_cam(m, rtwsta);
3784 }
3785
rtw89_debug_priv_stations_get(struct seq_file * m,void * v)3786 static int rtw89_debug_priv_stations_get(struct seq_file *m, void *v)
3787 {
3788 struct rtw89_debugfs_priv *debugfs_priv = m->private;
3789 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
3790 struct rtw89_cam_info *cam_info = &rtwdev->cam_info;
3791 u8 idx;
3792
3793 mutex_lock(&rtwdev->mutex);
3794
3795 seq_puts(m, "map:\n");
3796 seq_printf(m, "\tmac_id: %*ph\n", (int)sizeof(rtwdev->mac_id_map),
3797 rtwdev->mac_id_map);
3798 seq_printf(m, "\taddr_cam: %*ph\n", (int)sizeof(cam_info->addr_cam_map),
3799 cam_info->addr_cam_map);
3800 seq_printf(m, "\tbssid_cam: %*ph\n", (int)sizeof(cam_info->bssid_cam_map),
3801 cam_info->bssid_cam_map);
3802 seq_printf(m, "\tsec_cam: %*ph\n", (int)sizeof(cam_info->sec_cam_map),
3803 cam_info->sec_cam_map);
3804 seq_printf(m, "\tba_cam: %*ph\n", (int)sizeof(cam_info->ba_cam_map),
3805 cam_info->ba_cam_map);
3806 seq_printf(m, "\tpkt_ofld: %*ph\n", (int)sizeof(rtwdev->pkt_offload),
3807 rtwdev->pkt_offload);
3808
3809 for (idx = NL80211_BAND_2GHZ; idx < NUM_NL80211_BANDS; idx++) {
3810 if (!(rtwdev->chip->support_bands & BIT(idx)))
3811 continue;
3812 rtw89_dump_pkt_offload(m, &rtwdev->scan_info.pkt_list[idx],
3813 "\t\t[SCAN %u]: ", idx);
3814 }
3815
3816 ieee80211_iterate_active_interfaces_atomic(rtwdev->hw,
3817 IEEE80211_IFACE_ITER_NORMAL, rtw89_vif_ids_get_iter, m);
3818
3819 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_ids_get_iter, m);
3820
3821 mutex_unlock(&rtwdev->mutex);
3822
3823 return 0;
3824 }
3825
3826 #define DM_INFO(type) {RTW89_DM_ ## type, #type}
3827
3828 static const struct rtw89_disabled_dm_info {
3829 enum rtw89_dm_type type;
3830 const char *name;
3831 } rtw89_disabled_dm_infos[] = {
3832 DM_INFO(DYNAMIC_EDCCA),
3833 };
3834
3835 static int
rtw89_debug_priv_disable_dm_get(struct seq_file * m,void * v)3836 rtw89_debug_priv_disable_dm_get(struct seq_file *m, void *v)
3837 {
3838 struct rtw89_debugfs_priv *debugfs_priv = m->private;
3839 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
3840 const struct rtw89_disabled_dm_info *info;
3841 struct rtw89_hal *hal = &rtwdev->hal;
3842 u32 disabled;
3843 int i;
3844
3845 seq_printf(m, "Disabled DM: 0x%x\n", hal->disabled_dm_bitmap);
3846
3847 for (i = 0; i < ARRAY_SIZE(rtw89_disabled_dm_infos); i++) {
3848 info = &rtw89_disabled_dm_infos[i];
3849 disabled = BIT(info->type) & hal->disabled_dm_bitmap;
3850
3851 seq_printf(m, "[%d] %s: %c\n", info->type, info->name,
3852 disabled ? 'X' : 'O');
3853 }
3854
3855 return 0;
3856 }
3857
3858 static ssize_t
rtw89_debug_priv_disable_dm_set(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)3859 rtw89_debug_priv_disable_dm_set(struct file *filp, const char __user *user_buf,
3860 size_t count, loff_t *loff)
3861 {
3862 struct seq_file *m = (struct seq_file *)filp->private_data;
3863 struct rtw89_debugfs_priv *debugfs_priv = m->private;
3864 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
3865 struct rtw89_hal *hal = &rtwdev->hal;
3866 u32 conf;
3867 int ret;
3868
3869 ret = kstrtou32_from_user(user_buf, count, 0, &conf);
3870 if (ret)
3871 return -EINVAL;
3872
3873 hal->disabled_dm_bitmap = conf;
3874
3875 return count;
3876 }
3877
3878 #define rtw89_debug_priv_get(name) \
3879 { \
3880 .cb_read = rtw89_debug_priv_ ##name## _get, \
3881 }
3882
3883 #define rtw89_debug_priv_set(name) \
3884 { \
3885 .cb_write = rtw89_debug_priv_ ##name## _set, \
3886 }
3887
3888 #define rtw89_debug_priv_select_and_get(name) \
3889 { \
3890 .cb_write = rtw89_debug_priv_ ##name## _select, \
3891 .cb_read = rtw89_debug_priv_ ##name## _get, \
3892 }
3893
3894 #define rtw89_debug_priv_set_and_get(name) \
3895 { \
3896 .cb_write = rtw89_debug_priv_ ##name## _set, \
3897 .cb_read = rtw89_debug_priv_ ##name## _get, \
3898 }
3899
3900 static const struct rtw89_debugfs rtw89_debugfs_templ = {
3901 .read_reg = rtw89_debug_priv_select_and_get(read_reg),
3902 .write_reg = rtw89_debug_priv_set(write_reg),
3903 .read_rf = rtw89_debug_priv_select_and_get(read_rf),
3904 .write_rf = rtw89_debug_priv_set(write_rf),
3905 .rf_reg_dump = rtw89_debug_priv_get(rf_reg_dump),
3906 .txpwr_table = rtw89_debug_priv_get(txpwr_table),
3907 .mac_reg_dump = rtw89_debug_priv_select_and_get(mac_reg_dump),
3908 .mac_mem_dump = rtw89_debug_priv_select_and_get(mac_mem_dump),
3909 .mac_dbg_port_dump = rtw89_debug_priv_select_and_get(mac_dbg_port_dump),
3910 .send_h2c = rtw89_debug_priv_set(send_h2c),
3911 .early_h2c = rtw89_debug_priv_set_and_get(early_h2c),
3912 .fw_crash = rtw89_debug_priv_set_and_get(fw_crash),
3913 .btc_info = rtw89_debug_priv_get(btc_info),
3914 .btc_manual = rtw89_debug_priv_set(btc_manual),
3915 .fw_log_manual = rtw89_debug_priv_set(fw_log_manual),
3916 .phy_info = rtw89_debug_priv_get(phy_info),
3917 .stations = rtw89_debug_priv_get(stations),
3918 .disable_dm = rtw89_debug_priv_set_and_get(disable_dm),
3919 };
3920
3921 #define rtw89_debugfs_add(name, mode, fopname, parent) \
3922 do { \
3923 struct rtw89_debugfs_priv *priv = &rtwdev->debugfs->name; \
3924 priv->rtwdev = rtwdev; \
3925 if (IS_ERR(debugfs_create_file(#name, mode, parent, priv, \
3926 &file_ops_ ##fopname))) \
3927 pr_debug("Unable to initialize debugfs:%s\n", #name); \
3928 } while (0)
3929
3930 #define rtw89_debugfs_add_w(name) \
3931 rtw89_debugfs_add(name, S_IFREG | 0222, single_w, debugfs_topdir)
3932 #define rtw89_debugfs_add_rw(name) \
3933 rtw89_debugfs_add(name, S_IFREG | 0666, common_rw, debugfs_topdir)
3934 #define rtw89_debugfs_add_r(name) \
3935 rtw89_debugfs_add(name, S_IFREG | 0444, single_r, debugfs_topdir)
3936
3937 static
rtw89_debugfs_add_sec0(struct rtw89_dev * rtwdev,struct dentry * debugfs_topdir)3938 void rtw89_debugfs_add_sec0(struct rtw89_dev *rtwdev, struct dentry *debugfs_topdir)
3939 {
3940 rtw89_debugfs_add_rw(read_reg);
3941 rtw89_debugfs_add_w(write_reg);
3942 rtw89_debugfs_add_rw(read_rf);
3943 rtw89_debugfs_add_w(write_rf);
3944 rtw89_debugfs_add_r(rf_reg_dump);
3945 rtw89_debugfs_add_r(txpwr_table);
3946 rtw89_debugfs_add_rw(mac_reg_dump);
3947 rtw89_debugfs_add_rw(mac_mem_dump);
3948 rtw89_debugfs_add_rw(mac_dbg_port_dump);
3949 }
3950
3951 static
rtw89_debugfs_add_sec1(struct rtw89_dev * rtwdev,struct dentry * debugfs_topdir)3952 void rtw89_debugfs_add_sec1(struct rtw89_dev *rtwdev, struct dentry *debugfs_topdir)
3953 {
3954 rtw89_debugfs_add_w(send_h2c);
3955 rtw89_debugfs_add_rw(early_h2c);
3956 rtw89_debugfs_add_rw(fw_crash);
3957 rtw89_debugfs_add_r(btc_info);
3958 rtw89_debugfs_add_w(btc_manual);
3959 rtw89_debugfs_add_w(fw_log_manual);
3960 rtw89_debugfs_add_r(phy_info);
3961 rtw89_debugfs_add_r(stations);
3962 rtw89_debugfs_add_rw(disable_dm);
3963 }
3964
rtw89_debugfs_init(struct rtw89_dev * rtwdev)3965 void rtw89_debugfs_init(struct rtw89_dev *rtwdev)
3966 {
3967 struct dentry *debugfs_topdir;
3968
3969 rtwdev->debugfs = kmemdup(&rtw89_debugfs_templ,
3970 sizeof(rtw89_debugfs_templ), GFP_KERNEL);
3971 if (!rtwdev->debugfs)
3972 return;
3973
3974 debugfs_topdir = debugfs_create_dir("rtw89",
3975 rtwdev->hw->wiphy->debugfsdir);
3976
3977 rtw89_debugfs_add_sec0(rtwdev, debugfs_topdir);
3978 rtw89_debugfs_add_sec1(rtwdev, debugfs_topdir);
3979 }
3980
rtw89_debugfs_deinit(struct rtw89_dev * rtwdev)3981 void rtw89_debugfs_deinit(struct rtw89_dev *rtwdev)
3982 {
3983 kfree(rtwdev->debugfs);
3984 }
3985 #endif
3986
3987 #ifdef CONFIG_RTW89_DEBUGMSG
rtw89_debug(struct rtw89_dev * rtwdev,enum rtw89_debug_mask mask,const char * fmt,...)3988 void rtw89_debug(struct rtw89_dev *rtwdev, enum rtw89_debug_mask mask,
3989 const char *fmt, ...)
3990 {
3991 struct va_format vaf = {
3992 .fmt = fmt,
3993 };
3994
3995 va_list args;
3996
3997 va_start(args, fmt);
3998 vaf.va = &args;
3999
4000 if (rtw89_debug_mask & mask)
4001 dev_printk(KERN_DEBUG, rtwdev->dev, "%pV", &vaf);
4002
4003 va_end(args);
4004 }
4005 EXPORT_SYMBOL(rtw89_debug);
4006 #endif
4007