Home
last modified time | relevance | path

Searched refs:rq_regs (Results 1 – 25 of 25) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn201/
H A Ddcn201_hubp.c67 struct _vcs_dpi_display_rq_regs_st *rq_regs) in hubp201_program_requestor() argument
72 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); in hubp201_program_requestor()
75 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, in hubp201_program_requestor()
76 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, in hubp201_program_requestor()
77 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, in hubp201_program_requestor()
78 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); in hubp201_program_requestor()
82 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, in hubp201_program_requestor()
83 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, in hubp201_program_requestor()
84 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, in hubp201_program_requestor()
85 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, in hubp201_program_requestor()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn20/
H A Ddcn20_hubp.c198 struct _vcs_dpi_display_rq_regs_st *rq_regs) in hubp2_program_requestor() argument
203 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); in hubp2_program_requestor()
205 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, in hubp2_program_requestor()
206 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, in hubp2_program_requestor()
207 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, in hubp2_program_requestor()
208 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); in hubp2_program_requestor()
210 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, in hubp2_program_requestor()
211 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, in hubp2_program_requestor()
212 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, in hubp2_program_requestor()
213 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, in hubp2_program_requestor()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn10/
H A Ddcn10_hubp.c575 struct _vcs_dpi_display_rq_regs_st *rq_regs) in hubp1_program_requestor() argument
580 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); in hubp1_program_requestor()
582 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, in hubp1_program_requestor()
583 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, in hubp1_program_requestor()
584 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, in hubp1_program_requestor()
585 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); in hubp1_program_requestor()
587 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, in hubp1_program_requestor()
588 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, in hubp1_program_requestor()
589 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, in hubp1_program_requestor()
590 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, in hubp1_program_requestor()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn401/
H A Ddcn401_hubp.c222 struct dml2_display_rq_regs *rq_regs) in hubp401_program_requestor() argument
227 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); in hubp401_program_requestor()
229 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, in hubp401_program_requestor()
230 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, in hubp401_program_requestor()
231 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, in hubp401_program_requestor()
232 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); in hubp401_program_requestor()
234 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, in hubp401_program_requestor()
235 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, in hubp401_program_requestor()
236 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, in hubp401_program_requestor()
237 VM_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, in hubp401_program_requestor()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn30/
H A Ddcn30_hubp.c446 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; in hubp3_read_state() local
451 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, in hubp3_read_state()
452 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, in hubp3_read_state()
453 META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size, in hubp3_read_state()
454 MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size, in hubp3_read_state()
455 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, in hubp3_read_state()
456 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, in hubp3_read_state()
457 PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear); in hubp3_read_state()
460 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size, in hubp3_read_state()
461 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, in hubp3_read_state()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddisplay_mode_util.c218 void dml_print_data_rq_regs_st(const dml_display_plane_rq_regs_st *rq_regs) in dml_print_data_rq_regs_st() argument
222 dml_print("DML: chunk_size = 0x%x\n", rq_regs->chunk_size); in dml_print_data_rq_regs_st()
223 dml_print("DML: min_chunk_size = 0x%x\n", rq_regs->min_chunk_size); in dml_print_data_rq_regs_st()
224 dml_print("DML: meta_chunk_size = 0x%x\n", rq_regs->meta_chunk_size); in dml_print_data_rq_regs_st()
225 dml_print("DML: min_meta_chunk_size = 0x%x\n", rq_regs->min_meta_chunk_size); in dml_print_data_rq_regs_st()
226 dml_print("DML: dpte_group_size = 0x%x\n", rq_regs->dpte_group_size); in dml_print_data_rq_regs_st()
227 dml_print("DML: mpte_group_size = 0x%x\n", rq_regs->mpte_group_size); in dml_print_data_rq_regs_st()
228 dml_print("DML: swath_height = 0x%x\n", rq_regs->swath_height); in dml_print_data_rq_regs_st()
229 dml_print("DML: pte_row_height_linear = 0x%x\n", rq_regs->pte_row_height_linear); in dml_print_data_rq_regs_st()
233 void dml_print_rq_regs_st(const dml_display_rq_regs_st *rq_regs) in dml_print_rq_regs_st() argument
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddml1_display_rq_dlg_calc.c208 struct _vcs_dpi_display_data_rq_regs_st *rq_regs, in extract_rq_sizing_regs() argument
214 rq_regs->chunk_size = dml_log2(rq_sizing->chunk_bytes) - 10; in extract_rq_sizing_regs()
217 rq_regs->min_chunk_size = 0; in extract_rq_sizing_regs()
219 rq_regs->min_chunk_size = dml_log2(rq_sizing->min_chunk_bytes) - 8 + 1; in extract_rq_sizing_regs()
221 rq_regs->meta_chunk_size = dml_log2(rq_sizing->meta_chunk_bytes) - 10; in extract_rq_sizing_regs()
223 rq_regs->min_meta_chunk_size = 0; in extract_rq_sizing_regs()
225 rq_regs->min_meta_chunk_size = dml_log2(rq_sizing->min_meta_chunk_bytes) - 6 + 1; in extract_rq_sizing_regs()
227 rq_regs->dpte_group_size = dml_log2(rq_sizing->dpte_group_bytes) - 6; in extract_rq_sizing_regs()
228 rq_regs->mpte_group_size = dml_log2(rq_sizing->mpte_group_bytes) - 6; in extract_rq_sizing_regs()
233 struct _vcs_dpi_display_rq_regs_st *rq_regs, in dml1_extract_rq_regs() argument
[all …]
H A Ddisplay_mode_lib.h65 display_rq_regs_st *rq_regs,
76 void (*rq_dlg_get_rq_reg_v2)(display_rq_regs_st *rq_regs,
H A Ddml1_display_rq_dlg_calc.h35 struct _vcs_dpi_display_rq_regs_st *rq_regs,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_rq_dlg_calc_32.h44 void dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/
H A Ddisplay_rq_dlg_calc_21.h46 display_rq_regs_st *rq_regs,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddisplay_rq_dlg_calc_20.h45 display_rq_regs_st *rq_regs,
H A Ddisplay_rq_dlg_calc_20v2.h45 display_rq_regs_st *rq_regs,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddisplay_rq_dlg_calc_31.h43 display_rq_regs_st *rq_regs,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddisplay_rq_dlg_calc_314.h44 display_rq_regs_st *rq_regs,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddisplay_rq_dlg_calc_30.h43 display_rq_regs_st *rq_regs,
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c377 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; in dcn10_log_hubp_states() local
381 …pool->hubps[i]->inst, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expan… in dcn10_log_hubp_states()
382 rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size, in dcn10_log_hubp_states()
383 rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size, in dcn10_log_hubp_states()
384 rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs->rq_regs_l.dpte_group_size, in dcn10_log_hubp_states()
385 rq_regs->rq_regs_l.mpte_group_size, rq_regs->rq_regs_l.swath_height, in dcn10_log_hubp_states()
386 …rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_ch… in dcn10_log_hubp_states()
387 rq_regs->rq_regs_c.meta_chunk_size, rq_regs->rq_regs_c.min_meta_chunk_size, in dcn10_log_hubp_states()
388 rq_regs->rq_regs_c.dpte_group_size, rq_regs->rq_regs_c.mpte_group_size, in dcn10_log_hubp_states()
389 rq_regs->rq_regs_c.swath_height, rq_regs->rq_regs_c.pte_row_height_linear); in dcn10_log_hubp_states()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn21/
H A Ddcn21_hubp.h133 struct _vcs_dpi_display_rq_regs_st *rq_regs);
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc.c4453 &context->res_ctx.pipe_ctx[i].rq_regs, in commit_planes_for_stream()
6693 if (pipe_ctx->rq_regs.rq_regs_l.chunk_size > 0) { in dc_capture_register_software_state()
6694 state->hubp[i].rq_chunk_size = pipe_ctx->rq_regs.rq_regs_l.chunk_size; in dc_capture_register_software_state()
6695 state->hubp[i].rq_min_chunk_size = pipe_ctx->rq_regs.rq_regs_l.min_chunk_size; in dc_capture_register_software_state()
6696 state->hubp[i].rq_meta_chunk_size = pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size; in dc_capture_register_software_state()
6697 state->hubp[i].rq_min_meta_chunk_size = pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size; in dc_capture_register_software_state()
6698 state->hubp[i].rq_dpte_group_size = pipe_ctx->rq_regs.rq_regs_l.dpte_group_size; in dc_capture_register_software_state()
6699 state->hubp[i].rq_mpte_group_size = pipe_ctx->rq_regs.rq_regs_l.mpte_group_size; in dc_capture_register_software_state()
6700 state->hubp[i].rq_swath_height_l = pipe_ctx->rq_regs.rq_regs_l.swath_height; in dc_capture_register_software_state()
6701 state->hubp[i].rq_pte_row_height_l = pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear; in dc_capture_register_software_state()
[all …]
H A Ddc_hw_sequencer.c2976 struct _vcs_dpi_display_rq_regs_st *rq_regs = params->hubp_setup_params.rq_regs; in hwss_hubp_setup() local
2980 hubp->funcs->hubp_setup(hubp, dlg_regs, ttu_regs, rq_regs, pipe_dest); in hwss_hubp_setup()
3825 struct _vcs_dpi_display_rq_regs_st *rq_regs, in hwss_add_hubp_setup() argument
3833 seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.rq_regs = rq_regs; in hwss_add_hubp_setup()
/linux/drivers/gpu/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c461 struct _vcs_dpi_display_rq_regs_st *rq_regs = &pipe->rq_regs; in dcn_bw_calc_rq_dlg_ttu() local
472 memset(rq_regs, 0, sizeof(*rq_regs)); in dcn_bw_calc_rq_dlg_ttu()
508 dml1_extract_rq_regs(dml, rq_regs, rq_param); in dcn_bw_calc_rq_dlg_ttu()
/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Dcore_types.h484 struct _vcs_dpi_display_rq_regs_st rq_regs; member
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.c1651 memcmp(&old_pipe->rq_regs, &new_pipe->rq_regs, sizeof(old_pipe->rq_regs))) in dcn20_detect_pipe_changes()
1702 &pipe_ctx->rq_regs, in dcn20_update_dchubp_dpp()
2518 &pipe_ctx->rq_regs, in dcn20_update_bandwidth()
/linux/drivers/gpu/drm/amd/display/dc/hwss/
H A Dhw_sequencer.h652 struct _vcs_dpi_display_rq_regs_st *rq_regs; member
1926 struct _vcs_dpi_display_rq_regs_st *rq_regs,
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/
H A Ddml2_core_dcn4_calcs.c12253 static void rq_dlg_get_rq_reg(struct dml2_display_rq_regs *rq_regs, in rq_dlg_get_rq_reg() argument
12298 rq_regs->unbounded_request_enabled = dml_get_unbounded_request_enabled(mode_lib); in rq_dlg_get_rq_reg()
12299 rq_regs->rq_regs_l.chunk_size = log_and_substract_if_non_zero(pixel_chunk_bytes, 10); in rq_dlg_get_rq_reg()
12300 rq_regs->rq_regs_c.chunk_size = log_and_substract_if_non_zero(p1_pixel_chunk_bytes, 10); in rq_dlg_get_rq_reg()
12303 rq_regs->rq_regs_l.min_chunk_size = 0; in rq_dlg_get_rq_reg()
12305 rq_regs->rq_regs_l.min_chunk_size = log_and_substract_if_non_zero(min_pixel_chunk_bytes, 8 - 1); in rq_dlg_get_rq_reg()
12308 rq_regs->rq_regs_c.min_chunk_size = 0; in rq_dlg_get_rq_reg()
12310 …rq_regs->rq_regs_c.min_chunk_size = log_and_substract_if_non_zero(p1_min_pixel_chunk_bytes, 8 - 1); in rq_dlg_get_rq_reg()
12312 rq_regs->rq_regs_l.dpte_group_size = log_and_substract_if_non_zero(dpte_group_bytes, 6); in rq_dlg_get_rq_reg()
12313 rq_regs->rq_regs_l.mpte_group_size = log_and_substract_if_non_zero(mpte_group_bytes, 6); in rq_dlg_get_rq_reg()
[all …]