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Searched refs:rq_regs (Results 1 – 25 of 44) sorted by relevance

12

/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn21/
H A Ddcn21_hubp.c141 struct _vcs_dpi_display_rq_regs_st *rq_regs) in hubp21_program_requestor() argument
146 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); in hubp21_program_requestor()
148 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, in hubp21_program_requestor()
149 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, in hubp21_program_requestor()
150 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, in hubp21_program_requestor()
151 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); in hubp21_program_requestor()
153 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, in hubp21_program_requestor()
154 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, in hubp21_program_requestor()
155 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, in hubp21_program_requestor()
156 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, in hubp21_program_requestor()
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/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn201/
H A Ddcn201_hubp.c67 struct _vcs_dpi_display_rq_regs_st *rq_regs) in hubp201_program_requestor() argument
72 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); in hubp201_program_requestor()
75 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, in hubp201_program_requestor()
76 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, in hubp201_program_requestor()
77 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, in hubp201_program_requestor()
78 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); in hubp201_program_requestor()
82 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, in hubp201_program_requestor()
83 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, in hubp201_program_requestor()
84 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, in hubp201_program_requestor()
85 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, in hubp201_program_requestor()
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/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn20/
H A Ddcn20_hubp.c198 struct _vcs_dpi_display_rq_regs_st *rq_regs) in hubp2_program_requestor() argument
203 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); in hubp2_program_requestor()
205 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, in hubp2_program_requestor()
206 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, in hubp2_program_requestor()
207 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, in hubp2_program_requestor()
208 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); in hubp2_program_requestor()
210 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, in hubp2_program_requestor()
211 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, in hubp2_program_requestor()
212 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, in hubp2_program_requestor()
213 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, in hubp2_program_requestor()
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/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_rq_dlg_helpers.c156 …_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_data_rq_regs_st *rq_regs) in print__data_rq_regs_st() argument
160 dml_print("DML_RQ_DLG_CALC: chunk_size = 0x%0x\n", rq_regs->chunk_size); in print__data_rq_regs_st()
161 dml_print("DML_RQ_DLG_CALC: min_chunk_size = 0x%0x\n", rq_regs->min_chunk_size); in print__data_rq_regs_st()
162 dml_print("DML_RQ_DLG_CALC: meta_chunk_size = 0x%0x\n", rq_regs->meta_chunk_size); in print__data_rq_regs_st()
165 rq_regs->min_meta_chunk_size); in print__data_rq_regs_st()
166 dml_print("DML_RQ_DLG_CALC: dpte_group_size = 0x%0x\n", rq_regs->dpte_group_size); in print__data_rq_regs_st()
167 dml_print("DML_RQ_DLG_CALC: mpte_group_size = 0x%0x\n", rq_regs->mpte_group_size); in print__data_rq_regs_st()
168 dml_print("DML_RQ_DLG_CALC: swath_height = 0x%0x\n", rq_regs->swath_height); in print__data_rq_regs_st()
171 rq_regs->pte_row_height_linear); in print__data_rq_regs_st()
175 …t__rq_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_rq_regs_st *rq_regs) in print__rq_regs_st() argument
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H A Ddml1_display_rq_dlg_calc.c208 struct _vcs_dpi_display_data_rq_regs_st *rq_regs, in extract_rq_sizing_regs() argument
214 rq_regs->chunk_size = dml_log2(rq_sizing->chunk_bytes) - 10; in extract_rq_sizing_regs()
217 rq_regs->min_chunk_size = 0; in extract_rq_sizing_regs()
219 rq_regs->min_chunk_size = dml_log2(rq_sizing->min_chunk_bytes) - 8 + 1; in extract_rq_sizing_regs()
221 rq_regs->meta_chunk_size = dml_log2(rq_sizing->meta_chunk_bytes) - 10; in extract_rq_sizing_regs()
223 rq_regs->min_meta_chunk_size = 0; in extract_rq_sizing_regs()
225 rq_regs->min_meta_chunk_size = dml_log2(rq_sizing->min_meta_chunk_bytes) - 6 + 1; in extract_rq_sizing_regs()
227 rq_regs->dpte_group_size = dml_log2(rq_sizing->dpte_group_bytes) - 6; in extract_rq_sizing_regs()
228 rq_regs->mpte_group_size = dml_log2(rq_sizing->mpte_group_bytes) - 6; in extract_rq_sizing_regs()
233 struct _vcs_dpi_display_rq_regs_st *rq_regs, in dml1_extract_rq_regs() argument
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H A Ddisplay_rq_dlg_helpers.h41 …regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_data_rq_regs_st *rq_regs);
42 …__rq_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_rq_regs_st *rq_regs);
H A Ddisplay_mode_lib.h65 display_rq_regs_st *rq_regs,
76 void (*rq_dlg_get_rq_reg_v2)(display_rq_regs_st *rq_regs,
/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/
H A Ddml21_utils.c146 void dml21_update_pipe_ctx_dchub_regs(struct dml2_display_rq_regs *rq_regs, in dml21_update_pipe_ctx_dchub_regs() argument
151 memset(&out->rq_regs, 0, sizeof(out->rq_regs)); in dml21_update_pipe_ctx_dchub_regs()
152 out->rq_regs.rq_regs_l.chunk_size = rq_regs->rq_regs_l.chunk_size; in dml21_update_pipe_ctx_dchub_regs()
153 out->rq_regs.rq_regs_l.min_chunk_size = rq_regs->rq_regs_l.min_chunk_size; in dml21_update_pipe_ctx_dchub_regs()
156 out->rq_regs.rq_regs_l.dpte_group_size = rq_regs->rq_regs_l.dpte_group_size; in dml21_update_pipe_ctx_dchub_regs()
157 out->rq_regs.rq_regs_l.mpte_group_size = rq_regs->rq_regs_l.mpte_group_size; in dml21_update_pipe_ctx_dchub_regs()
158 out->rq_regs.rq_regs_l.swath_height = rq_regs->rq_regs_l.swath_height; in dml21_update_pipe_ctx_dchub_regs()
159 out->rq_regs.rq_regs_l.pte_row_height_linear = rq_regs->rq_regs_l.pte_row_height_linear; in dml21_update_pipe_ctx_dchub_regs()
161 out->rq_regs.rq_regs_c.chunk_size = rq_regs->rq_regs_c.chunk_size; in dml21_update_pipe_ctx_dchub_regs()
162 out->rq_regs.rq_regs_c.min_chunk_size = rq_regs->rq_regs_c.min_chunk_size; in dml21_update_pipe_ctx_dchub_regs()
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/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn10/
H A Ddcn10_hubp.c554 struct _vcs_dpi_display_rq_regs_st *rq_regs) in hubp1_program_requestor() argument
559 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); in hubp1_program_requestor()
561 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, in hubp1_program_requestor()
562 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, in hubp1_program_requestor()
563 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, in hubp1_program_requestor()
564 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); in hubp1_program_requestor()
566 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, in hubp1_program_requestor()
567 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, in hubp1_program_requestor()
568 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, in hubp1_program_requestor()
569 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, in hubp1_program_requestor()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_rq_dlg_calc_32.c43 void dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs, in dml32_rq_dlg_get_rq_reg() argument
72 memset(rq_regs, 0, sizeof(*rq_regs)); in dml32_rq_dlg_get_rq_reg()
98 rq_regs->rq_regs_l.chunk_size = dml_log2(pixel_chunk_bytes) - 10; in dml32_rq_dlg_get_rq_reg()
99 rq_regs->rq_regs_c.chunk_size = dml_log2(p1_pixel_chunk_bytes) - 10; in dml32_rq_dlg_get_rq_reg()
102 rq_regs->rq_regs_l.min_chunk_size = 0; in dml32_rq_dlg_get_rq_reg()
104 rq_regs->rq_regs_l.min_chunk_size = dml_log2(min_pixel_chunk_bytes) - 8 + 1; in dml32_rq_dlg_get_rq_reg()
107 rq_regs->rq_regs_c.min_chunk_size = 0; in dml32_rq_dlg_get_rq_reg()
109 rq_regs->rq_regs_c.min_chunk_size = dml_log2(p1_min_pixel_chunk_bytes) - 8 + 1; in dml32_rq_dlg_get_rq_reg()
111 rq_regs->rq_regs_l.meta_chunk_size = dml_log2(meta_chunk_bytes) - 10; in dml32_rq_dlg_get_rq_reg()
112 rq_regs->rq_regs_c.meta_chunk_size = dml_log2(p1_meta_chunk_bytes) - 10; in dml32_rq_dlg_get_rq_reg()
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H A Ddisplay_rq_dlg_calc_32.h44 void dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs,
/linux/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml_display_rq_dlg_calc.c39 void dml_rq_dlg_get_rq_reg(dml_display_rq_regs_st *rq_regs, in dml_rq_dlg_get_rq_reg() argument
73 memset(rq_regs, 0, sizeof(*rq_regs)); in dml_rq_dlg_get_rq_reg()
97 rq_regs->rq_regs_l.chunk_size = (dml_uint_t)(dml_log2((dml_float_t) pixel_chunk_bytes) - 10); in dml_rq_dlg_get_rq_reg()
98 rq_regs->rq_regs_c.chunk_size = (dml_uint_t)(dml_log2((dml_float_t) p1_pixel_chunk_bytes) - 10); in dml_rq_dlg_get_rq_reg()
101 rq_regs->rq_regs_l.min_chunk_size = 0; in dml_rq_dlg_get_rq_reg()
103 …rq_regs->rq_regs_l.min_chunk_size = (dml_uint_t)(dml_log2((dml_float_t) min_pixel_chunk_bytes) - 8… in dml_rq_dlg_get_rq_reg()
106 rq_regs->rq_regs_c.min_chunk_size = 0; in dml_rq_dlg_get_rq_reg()
108 …rq_regs->rq_regs_c.min_chunk_size = (dml_uint_t)(dml_log2((dml_float_t) p1_min_pixel_chunk_bytes) … in dml_rq_dlg_get_rq_reg()
110 rq_regs->rq_regs_l.meta_chunk_size = (dml_uint_t)(dml_log2((dml_float_t) meta_chunk_bytes) - 10); in dml_rq_dlg_get_rq_reg()
111 …rq_regs->rq_regs_c.meta_chunk_size = (dml_uint_t)(dml_log2((dml_float_t) p1_meta_chunk_bytes) - 10… in dml_rq_dlg_get_rq_reg()
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H A Ddml2_translation_helper.c1404 void dml2_update_pipe_ctx_dchub_regs(struct _vcs_dpi_dml_display_rq_regs_st *rq_regs, in dml2_update_pipe_ctx_dchub_regs() argument
1409 memset(&out->rq_regs, 0, sizeof(out->rq_regs)); in dml2_update_pipe_ctx_dchub_regs()
1410 out->rq_regs.rq_regs_l.chunk_size = rq_regs->rq_regs_l.chunk_size; in dml2_update_pipe_ctx_dchub_regs()
1411 out->rq_regs.rq_regs_l.min_chunk_size = rq_regs->rq_regs_l.min_chunk_size; in dml2_update_pipe_ctx_dchub_regs()
1412 out->rq_regs.rq_regs_l.meta_chunk_size = rq_regs->rq_regs_l.meta_chunk_size; in dml2_update_pipe_ctx_dchub_regs()
1413 out->rq_regs.rq_regs_l.min_meta_chunk_size = rq_regs->rq_regs_l.min_meta_chunk_size; in dml2_update_pipe_ctx_dchub_regs()
1414 out->rq_regs.rq_regs_l.dpte_group_size = rq_regs->rq_regs_l.dpte_group_size; in dml2_update_pipe_ctx_dchub_regs()
1415 out->rq_regs.rq_regs_l.mpte_group_size = rq_regs->rq_regs_l.mpte_group_size; in dml2_update_pipe_ctx_dchub_regs()
1416 out->rq_regs.rq_regs_l.swath_height = rq_regs->rq_regs_l.swath_height; in dml2_update_pipe_ctx_dchub_regs()
1417 out->rq_regs.rq_regs_l.pte_row_height_linear = rq_regs->rq_regs_l.pte_row_height_linear; in dml2_update_pipe_ctx_dchub_regs()
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H A Ddisplay_mode_util.c218 void dml_print_data_rq_regs_st(const dml_display_plane_rq_regs_st *rq_regs) in dml_print_data_rq_regs_st() argument
222 dml_print("DML: chunk_size = 0x%x\n", rq_regs->chunk_size); in dml_print_data_rq_regs_st()
223 dml_print("DML: min_chunk_size = 0x%x\n", rq_regs->min_chunk_size); in dml_print_data_rq_regs_st()
224 dml_print("DML: meta_chunk_size = 0x%x\n", rq_regs->meta_chunk_size); in dml_print_data_rq_regs_st()
225 dml_print("DML: min_meta_chunk_size = 0x%x\n", rq_regs->min_meta_chunk_size); in dml_print_data_rq_regs_st()
226 dml_print("DML: dpte_group_size = 0x%x\n", rq_regs->dpte_group_size); in dml_print_data_rq_regs_st()
227 dml_print("DML: mpte_group_size = 0x%x\n", rq_regs->mpte_group_size); in dml_print_data_rq_regs_st()
228 dml_print("DML: swath_height = 0x%x\n", rq_regs->swath_height); in dml_print_data_rq_regs_st()
229 dml_print("DML: pte_row_height_linear = 0x%x\n", rq_regs->pte_row_height_linear); in dml_print_data_rq_regs_st()
233 void dml_print_rq_regs_st(const dml_display_rq_regs_st *rq_regs) in dml_print_rq_regs_st() argument
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H A Ddml_display_rq_dlg_calc.h43 void dml_rq_dlg_get_rq_reg(dml_display_rq_regs_st *rq_regs,
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn401/
H A Ddcn401_hubp.c171 struct _vcs_dpi_display_rq_regs_st *rq_regs) in hubp401_program_requestor() argument
176 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); in hubp401_program_requestor()
178 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, in hubp401_program_requestor()
179 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, in hubp401_program_requestor()
180 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, in hubp401_program_requestor()
181 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); in hubp401_program_requestor()
183 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, in hubp401_program_requestor()
184 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, in hubp401_program_requestor()
185 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, in hubp401_program_requestor()
186 VM_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, in hubp401_program_requestor()
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/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn30/
H A Ddcn30_hubp.c430 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; in hubp3_read_state() local
435 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, in hubp3_read_state()
436 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, in hubp3_read_state()
437 META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size, in hubp3_read_state()
438 MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size, in hubp3_read_state()
439 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, in hubp3_read_state()
440 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, in hubp3_read_state()
441 PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear); in hubp3_read_state()
444 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size, in hubp3_read_state()
445 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, in hubp3_read_state()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/
H A Ddisplay_rq_dlg_calc_21.c143 display_data_rq_regs_st *rq_regs, in extract_rq_sizing_regs() argument
149 rq_regs->chunk_size = dml_log2(rq_sizing->chunk_bytes) - 10; in extract_rq_sizing_regs()
152 rq_regs->min_chunk_size = 0; in extract_rq_sizing_regs()
154 rq_regs->min_chunk_size = dml_log2(rq_sizing->min_chunk_bytes) - 8 + 1; in extract_rq_sizing_regs()
156 rq_regs->meta_chunk_size = dml_log2(rq_sizing->meta_chunk_bytes) - 10; in extract_rq_sizing_regs()
158 rq_regs->min_meta_chunk_size = 0; in extract_rq_sizing_regs()
160 rq_regs->min_meta_chunk_size = dml_log2(rq_sizing->min_meta_chunk_bytes) - 6 + 1; in extract_rq_sizing_regs()
162 rq_regs->dpte_group_size = dml_log2(rq_sizing->dpte_group_bytes) - 6; in extract_rq_sizing_regs()
163 rq_regs->mpte_group_size = dml_log2(rq_sizing->mpte_group_bytes) - 6; in extract_rq_sizing_regs()
168 display_rq_regs_st *rq_regs, in extract_rq_regs() argument
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H A Ddisplay_rq_dlg_calc_21.h46 display_rq_regs_st *rq_regs,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddisplay_rq_dlg_calc_20.c166 display_data_rq_regs_st *rq_regs, in extract_rq_sizing_regs() argument
172 rq_regs->chunk_size = dml_log2(rq_sizing->chunk_bytes) - 10; in extract_rq_sizing_regs()
175 rq_regs->min_chunk_size = 0; in extract_rq_sizing_regs()
177 rq_regs->min_chunk_size = dml_log2(rq_sizing->min_chunk_bytes) - 8 + 1; in extract_rq_sizing_regs()
179 rq_regs->meta_chunk_size = dml_log2(rq_sizing->meta_chunk_bytes) - 10; in extract_rq_sizing_regs()
181 rq_regs->min_meta_chunk_size = 0; in extract_rq_sizing_regs()
183 rq_regs->min_meta_chunk_size = dml_log2(rq_sizing->min_meta_chunk_bytes) - 6 + 1; in extract_rq_sizing_regs()
185 rq_regs->dpte_group_size = dml_log2(rq_sizing->dpte_group_bytes) - 6; in extract_rq_sizing_regs()
186 rq_regs->mpte_group_size = dml_log2(rq_sizing->mpte_group_bytes) - 6; in extract_rq_sizing_regs()
190 display_rq_regs_st *rq_regs, in extract_rq_regs() argument
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H A Ddisplay_rq_dlg_calc_20v2.c166 display_data_rq_regs_st *rq_regs, in extract_rq_sizing_regs() argument
172 rq_regs->chunk_size = dml_log2(rq_sizing->chunk_bytes) - 10; in extract_rq_sizing_regs()
175 rq_regs->min_chunk_size = 0; in extract_rq_sizing_regs()
177 rq_regs->min_chunk_size = dml_log2(rq_sizing->min_chunk_bytes) - 8 + 1; in extract_rq_sizing_regs()
179 rq_regs->meta_chunk_size = dml_log2(rq_sizing->meta_chunk_bytes) - 10; in extract_rq_sizing_regs()
181 rq_regs->min_meta_chunk_size = 0; in extract_rq_sizing_regs()
183 rq_regs->min_meta_chunk_size = dml_log2(rq_sizing->min_meta_chunk_bytes) - 6 + 1; in extract_rq_sizing_regs()
185 rq_regs->dpte_group_size = dml_log2(rq_sizing->dpte_group_bytes) - 6; in extract_rq_sizing_regs()
186 rq_regs->mpte_group_size = dml_log2(rq_sizing->mpte_group_bytes) - 6; in extract_rq_sizing_regs()
190 display_rq_regs_st *rq_regs, in extract_rq_regs() argument
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H A Ddisplay_rq_dlg_calc_20.h45 display_rq_regs_st *rq_regs,
H A Ddisplay_rq_dlg_calc_20v2.h45 display_rq_regs_st *rq_regs,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddisplay_rq_dlg_calc_31.h43 display_rq_regs_st *rq_regs,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddisplay_rq_dlg_calc_314.h44 display_rq_regs_st *rq_regs,

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