1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS = 0x1, 69 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 70 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 71 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 72 MLX5_SET_HCA_CAP_OP_MOD_IPSEC = 0x15, 73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 74 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25, 75 }; 76 77 enum { 78 MLX5_SHARED_RESOURCE_UID = 0xffff, 79 }; 80 81 enum { 82 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 83 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 84 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 85 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 86 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 87 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23, 88 MLX5_OBJ_TYPE_STC = 0x0040, 89 MLX5_OBJ_TYPE_RTC = 0x0041, 90 MLX5_OBJ_TYPE_STE = 0x0042, 91 MLX5_OBJ_TYPE_MODIFY_HDR_PATTERN = 0x0043, 92 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 93 MLX5_OBJ_TYPE_MKEY = 0xff01, 94 MLX5_OBJ_TYPE_QP = 0xff02, 95 MLX5_OBJ_TYPE_PSV = 0xff03, 96 MLX5_OBJ_TYPE_RMP = 0xff04, 97 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 98 MLX5_OBJ_TYPE_RQ = 0xff06, 99 MLX5_OBJ_TYPE_SQ = 0xff07, 100 MLX5_OBJ_TYPE_TIR = 0xff08, 101 MLX5_OBJ_TYPE_TIS = 0xff09, 102 MLX5_OBJ_TYPE_DCT = 0xff0a, 103 MLX5_OBJ_TYPE_XRQ = 0xff0b, 104 MLX5_OBJ_TYPE_RQT = 0xff0e, 105 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 106 MLX5_OBJ_TYPE_CQ = 0xff10, 107 MLX5_OBJ_TYPE_FT_ALIAS = 0xff15, 108 }; 109 110 enum { 111 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 112 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 113 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 114 MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT = 115 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT), 116 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 117 }; 118 119 enum { 120 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 121 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 122 MLX5_CMD_OP_INIT_HCA = 0x102, 123 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 124 MLX5_CMD_OP_ENABLE_HCA = 0x104, 125 MLX5_CMD_OP_DISABLE_HCA = 0x105, 126 MLX5_CMD_OP_QUERY_PAGES = 0x107, 127 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 128 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 129 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 130 MLX5_CMD_OP_SET_ISSI = 0x10b, 131 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 132 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 133 MLX5_CMD_OP_ALLOC_SF = 0x113, 134 MLX5_CMD_OP_DEALLOC_SF = 0x114, 135 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 136 MLX5_CMD_OP_RESUME_VHCA = 0x116, 137 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 138 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 139 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 140 MLX5_CMD_OP_CREATE_MKEY = 0x200, 141 MLX5_CMD_OP_QUERY_MKEY = 0x201, 142 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 143 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 144 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 145 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 146 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 147 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 148 MLX5_CMD_OP_CREATE_EQ = 0x301, 149 MLX5_CMD_OP_DESTROY_EQ = 0x302, 150 MLX5_CMD_OP_QUERY_EQ = 0x303, 151 MLX5_CMD_OP_GEN_EQE = 0x304, 152 MLX5_CMD_OP_CREATE_CQ = 0x400, 153 MLX5_CMD_OP_DESTROY_CQ = 0x401, 154 MLX5_CMD_OP_QUERY_CQ = 0x402, 155 MLX5_CMD_OP_MODIFY_CQ = 0x403, 156 MLX5_CMD_OP_CREATE_QP = 0x500, 157 MLX5_CMD_OP_DESTROY_QP = 0x501, 158 MLX5_CMD_OP_RST2INIT_QP = 0x502, 159 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 160 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 161 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 162 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 163 MLX5_CMD_OP_2ERR_QP = 0x507, 164 MLX5_CMD_OP_2RST_QP = 0x50a, 165 MLX5_CMD_OP_QUERY_QP = 0x50b, 166 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 167 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 168 MLX5_CMD_OP_CREATE_PSV = 0x600, 169 MLX5_CMD_OP_DESTROY_PSV = 0x601, 170 MLX5_CMD_OP_CREATE_SRQ = 0x700, 171 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 172 MLX5_CMD_OP_QUERY_SRQ = 0x702, 173 MLX5_CMD_OP_ARM_RQ = 0x703, 174 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 175 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 176 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 177 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 178 MLX5_CMD_OP_CREATE_DCT = 0x710, 179 MLX5_CMD_OP_DESTROY_DCT = 0x711, 180 MLX5_CMD_OP_DRAIN_DCT = 0x712, 181 MLX5_CMD_OP_QUERY_DCT = 0x713, 182 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 183 MLX5_CMD_OP_CREATE_XRQ = 0x717, 184 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 185 MLX5_CMD_OP_QUERY_XRQ = 0x719, 186 MLX5_CMD_OP_ARM_XRQ = 0x71a, 187 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 188 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 189 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 190 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 191 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 192 MLX5_CMD_OPCODE_QUERY_DELEGATED_VHCA = 0x732, 193 MLX5_CMD_OPCODE_CREATE_ESW_VPORT = 0x733, 194 MLX5_CMD_OPCODE_DESTROY_ESW_VPORT = 0x734, 195 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 196 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 197 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 198 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 199 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 200 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 201 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 202 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 203 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 204 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 205 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 206 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 207 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 208 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 209 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 210 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 211 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 212 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 213 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 214 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 215 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 216 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 217 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 218 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 219 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 220 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 221 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 222 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 223 MLX5_CMD_OP_ALLOC_PD = 0x800, 224 MLX5_CMD_OP_DEALLOC_PD = 0x801, 225 MLX5_CMD_OP_ALLOC_UAR = 0x802, 226 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 227 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 228 MLX5_CMD_OP_ACCESS_REG = 0x805, 229 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 230 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 231 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 232 MLX5_CMD_OP_MAD_IFC = 0x50d, 233 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 234 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 235 MLX5_CMD_OP_NOP = 0x80d, 236 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 237 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 238 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 239 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 240 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 241 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 242 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 243 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 244 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 245 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 246 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 247 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 248 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 249 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 250 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 251 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 252 MLX5_CMD_OP_CREATE_LAG = 0x840, 253 MLX5_CMD_OP_MODIFY_LAG = 0x841, 254 MLX5_CMD_OP_QUERY_LAG = 0x842, 255 MLX5_CMD_OP_DESTROY_LAG = 0x843, 256 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 257 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 258 MLX5_CMD_OP_CREATE_TIR = 0x900, 259 MLX5_CMD_OP_MODIFY_TIR = 0x901, 260 MLX5_CMD_OP_DESTROY_TIR = 0x902, 261 MLX5_CMD_OP_QUERY_TIR = 0x903, 262 MLX5_CMD_OP_CREATE_SQ = 0x904, 263 MLX5_CMD_OP_MODIFY_SQ = 0x905, 264 MLX5_CMD_OP_DESTROY_SQ = 0x906, 265 MLX5_CMD_OP_QUERY_SQ = 0x907, 266 MLX5_CMD_OP_CREATE_RQ = 0x908, 267 MLX5_CMD_OP_MODIFY_RQ = 0x909, 268 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 269 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 270 MLX5_CMD_OP_QUERY_RQ = 0x90b, 271 MLX5_CMD_OP_CREATE_RMP = 0x90c, 272 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 273 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 274 MLX5_CMD_OP_QUERY_RMP = 0x90f, 275 MLX5_CMD_OP_CREATE_TIS = 0x912, 276 MLX5_CMD_OP_MODIFY_TIS = 0x913, 277 MLX5_CMD_OP_DESTROY_TIS = 0x914, 278 MLX5_CMD_OP_QUERY_TIS = 0x915, 279 MLX5_CMD_OP_CREATE_RQT = 0x916, 280 MLX5_CMD_OP_MODIFY_RQT = 0x917, 281 MLX5_CMD_OP_DESTROY_RQT = 0x918, 282 MLX5_CMD_OP_QUERY_RQT = 0x919, 283 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 284 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 285 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 286 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 287 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 288 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 289 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 290 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 291 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 292 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 293 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 294 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 295 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 296 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 297 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 298 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 299 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 300 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 301 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 302 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 303 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 304 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 305 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 306 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 307 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 308 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 309 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 310 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 311 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 312 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 313 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 314 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 315 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 316 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 317 MLX5_CMD_OP_PSP_GEN_SPI = 0xb10, 318 MLX5_CMD_OP_PSP_ROTATE_KEY = 0xb11, 319 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 320 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 321 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 322 MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16, 323 MLX5_CMD_OP_GENERATE_WQE = 0xb17, 324 MLX5_CMD_OPCODE_QUERY_VUID = 0xb22, 325 MLX5_CMD_OP_MAX 326 }; 327 328 /* Valid range for general commands that don't work over an object */ 329 enum { 330 MLX5_CMD_OP_GENERAL_START = 0xb00, 331 MLX5_CMD_OP_GENERAL_END = 0xd00, 332 }; 333 334 enum { 335 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 336 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 337 }; 338 339 enum { 340 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1, 341 }; 342 343 struct mlx5_ifc_flow_table_fields_supported_bits { 344 u8 outer_dmac[0x1]; 345 u8 outer_smac[0x1]; 346 u8 outer_ether_type[0x1]; 347 u8 outer_ip_version[0x1]; 348 u8 outer_first_prio[0x1]; 349 u8 outer_first_cfi[0x1]; 350 u8 outer_first_vid[0x1]; 351 u8 outer_ipv4_ttl[0x1]; 352 u8 outer_second_prio[0x1]; 353 u8 outer_second_cfi[0x1]; 354 u8 outer_second_vid[0x1]; 355 u8 reserved_at_b[0x1]; 356 u8 outer_sip[0x1]; 357 u8 outer_dip[0x1]; 358 u8 outer_frag[0x1]; 359 u8 outer_ip_protocol[0x1]; 360 u8 outer_ip_ecn[0x1]; 361 u8 outer_ip_dscp[0x1]; 362 u8 outer_udp_sport[0x1]; 363 u8 outer_udp_dport[0x1]; 364 u8 outer_tcp_sport[0x1]; 365 u8 outer_tcp_dport[0x1]; 366 u8 outer_tcp_flags[0x1]; 367 u8 outer_gre_protocol[0x1]; 368 u8 outer_gre_key[0x1]; 369 u8 outer_vxlan_vni[0x1]; 370 u8 outer_geneve_vni[0x1]; 371 u8 outer_geneve_oam[0x1]; 372 u8 outer_geneve_protocol_type[0x1]; 373 u8 outer_geneve_opt_len[0x1]; 374 u8 source_vhca_port[0x1]; 375 u8 source_eswitch_port[0x1]; 376 377 u8 inner_dmac[0x1]; 378 u8 inner_smac[0x1]; 379 u8 inner_ether_type[0x1]; 380 u8 inner_ip_version[0x1]; 381 u8 inner_first_prio[0x1]; 382 u8 inner_first_cfi[0x1]; 383 u8 inner_first_vid[0x1]; 384 u8 reserved_at_27[0x1]; 385 u8 inner_second_prio[0x1]; 386 u8 inner_second_cfi[0x1]; 387 u8 inner_second_vid[0x1]; 388 u8 reserved_at_2b[0x1]; 389 u8 inner_sip[0x1]; 390 u8 inner_dip[0x1]; 391 u8 inner_frag[0x1]; 392 u8 inner_ip_protocol[0x1]; 393 u8 inner_ip_ecn[0x1]; 394 u8 inner_ip_dscp[0x1]; 395 u8 inner_udp_sport[0x1]; 396 u8 inner_udp_dport[0x1]; 397 u8 inner_tcp_sport[0x1]; 398 u8 inner_tcp_dport[0x1]; 399 u8 inner_tcp_flags[0x1]; 400 u8 reserved_at_37[0x9]; 401 402 u8 geneve_tlv_option_0_data[0x1]; 403 u8 geneve_tlv_option_0_exist[0x1]; 404 u8 reserved_at_42[0x3]; 405 u8 outer_first_mpls_over_udp[0x4]; 406 u8 outer_first_mpls_over_gre[0x4]; 407 u8 inner_first_mpls[0x4]; 408 u8 outer_first_mpls[0x4]; 409 u8 reserved_at_55[0x2]; 410 u8 outer_esp_spi[0x1]; 411 u8 reserved_at_58[0x2]; 412 u8 bth_dst_qp[0x1]; 413 u8 reserved_at_5b[0x5]; 414 415 u8 reserved_at_60[0x18]; 416 u8 metadata_reg_c_7[0x1]; 417 u8 metadata_reg_c_6[0x1]; 418 u8 metadata_reg_c_5[0x1]; 419 u8 metadata_reg_c_4[0x1]; 420 u8 metadata_reg_c_3[0x1]; 421 u8 metadata_reg_c_2[0x1]; 422 u8 metadata_reg_c_1[0x1]; 423 u8 metadata_reg_c_0[0x1]; 424 }; 425 426 /* Table 2170 - Flow Table Fields Supported 2 Format */ 427 struct mlx5_ifc_flow_table_fields_supported_2_bits { 428 u8 inner_l4_type_ext[0x1]; 429 u8 outer_l4_type_ext[0x1]; 430 u8 inner_l4_type[0x1]; 431 u8 outer_l4_type[0x1]; 432 u8 reserved_at_4[0xa]; 433 u8 bth_opcode[0x1]; 434 u8 reserved_at_f[0x1]; 435 u8 tunnel_header_0_1[0x1]; 436 u8 reserved_at_11[0xf]; 437 438 u8 reserved_at_20[0xf]; 439 u8 ipsec_next_header[0x1]; 440 u8 reserved_at_30[0x10]; 441 442 u8 reserved_at_40[0x40]; 443 }; 444 445 struct mlx5_ifc_flow_table_prop_layout_bits { 446 u8 ft_support[0x1]; 447 u8 reserved_at_1[0x1]; 448 u8 flow_counter[0x1]; 449 u8 flow_modify_en[0x1]; 450 u8 modify_root[0x1]; 451 u8 identified_miss_table_mode[0x1]; 452 u8 flow_table_modify[0x1]; 453 u8 reformat[0x1]; 454 u8 decap[0x1]; 455 u8 reset_root_to_default[0x1]; 456 u8 pop_vlan[0x1]; 457 u8 push_vlan[0x1]; 458 u8 reserved_at_c[0x1]; 459 u8 pop_vlan_2[0x1]; 460 u8 push_vlan_2[0x1]; 461 u8 reformat_and_vlan_action[0x1]; 462 u8 reserved_at_10[0x1]; 463 u8 sw_owner[0x1]; 464 u8 reformat_l3_tunnel_to_l2[0x1]; 465 u8 reformat_l2_to_l3_tunnel[0x1]; 466 u8 reformat_and_modify_action[0x1]; 467 u8 ignore_flow_level[0x1]; 468 u8 reserved_at_16[0x1]; 469 u8 table_miss_action_domain[0x1]; 470 u8 termination_table[0x1]; 471 u8 reformat_and_fwd_to_table[0x1]; 472 u8 reserved_at_1a[0x2]; 473 u8 ipsec_encrypt[0x1]; 474 u8 ipsec_decrypt[0x1]; 475 u8 sw_owner_v2[0x1]; 476 u8 reserved_at_1f[0x1]; 477 478 u8 termination_table_raw_traffic[0x1]; 479 u8 reserved_at_21[0x1]; 480 u8 log_max_ft_size[0x6]; 481 u8 log_max_modify_header_context[0x8]; 482 u8 max_modify_header_actions[0x8]; 483 u8 max_ft_level[0x8]; 484 485 u8 reformat_add_esp_trasport[0x1]; 486 u8 reformat_l2_to_l3_esp_tunnel[0x1]; 487 u8 reformat_add_esp_transport_over_udp[0x1]; 488 u8 reformat_del_esp_trasport[0x1]; 489 u8 reformat_l3_esp_tunnel_to_l2[0x1]; 490 u8 reformat_del_esp_transport_over_udp[0x1]; 491 u8 execute_aso[0x1]; 492 u8 reserved_at_47[0x19]; 493 494 u8 reformat_l2_to_l3_psp_tunnel[0x1]; 495 u8 reformat_l3_psp_tunnel_to_l2[0x1]; 496 u8 reformat_insert[0x1]; 497 u8 reformat_remove[0x1]; 498 u8 macsec_encrypt[0x1]; 499 u8 macsec_decrypt[0x1]; 500 u8 psp_encrypt[0x1]; 501 u8 psp_decrypt[0x1]; 502 u8 reformat_add_macsec[0x1]; 503 u8 reformat_remove_macsec[0x1]; 504 u8 reparse[0x1]; 505 u8 reserved_at_6b[0x1]; 506 u8 cross_vhca_object[0x1]; 507 u8 reformat_l2_to_l3_audp_tunnel[0x1]; 508 u8 reformat_l3_audp_tunnel_to_l2[0x1]; 509 u8 ignore_flow_level_rtc_valid[0x1]; 510 u8 reserved_at_70[0x8]; 511 u8 log_max_ft_num[0x8]; 512 513 u8 reserved_at_80[0x10]; 514 u8 log_max_flow_counter[0x8]; 515 u8 log_max_destination[0x8]; 516 517 u8 reserved_at_a0[0x18]; 518 u8 log_max_flow[0x8]; 519 520 u8 reserved_at_c0[0x40]; 521 522 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 523 524 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 525 }; 526 527 struct mlx5_ifc_odp_per_transport_service_cap_bits { 528 u8 send[0x1]; 529 u8 receive[0x1]; 530 u8 write[0x1]; 531 u8 read[0x1]; 532 u8 atomic[0x1]; 533 u8 srq_receive[0x1]; 534 u8 reserved_at_6[0x1a]; 535 }; 536 537 struct mlx5_ifc_ipv4_layout_bits { 538 u8 reserved_at_0[0x60]; 539 540 u8 ipv4[0x20]; 541 }; 542 543 struct mlx5_ifc_ipv6_layout_bits { 544 u8 ipv6[16][0x8]; 545 }; 546 547 struct mlx5_ifc_ipv6_simple_layout_bits { 548 u8 ipv6_127_96[0x20]; 549 u8 ipv6_95_64[0x20]; 550 u8 ipv6_63_32[0x20]; 551 u8 ipv6_31_0[0x20]; 552 }; 553 554 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 555 struct mlx5_ifc_ipv6_simple_layout_bits ipv6_simple_layout; 556 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 557 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 558 u8 reserved_at_0[0x80]; 559 }; 560 561 enum { 562 MLX5_PACKET_L4_TYPE_NONE, 563 MLX5_PACKET_L4_TYPE_TCP, 564 MLX5_PACKET_L4_TYPE_UDP, 565 }; 566 567 enum { 568 MLX5_PACKET_L4_TYPE_EXT_NONE, 569 MLX5_PACKET_L4_TYPE_EXT_TCP, 570 MLX5_PACKET_L4_TYPE_EXT_UDP, 571 MLX5_PACKET_L4_TYPE_EXT_ICMP, 572 }; 573 574 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 575 u8 smac_47_16[0x20]; 576 577 u8 smac_15_0[0x10]; 578 u8 ethertype[0x10]; 579 580 u8 dmac_47_16[0x20]; 581 582 u8 dmac_15_0[0x10]; 583 u8 first_prio[0x3]; 584 u8 first_cfi[0x1]; 585 u8 first_vid[0xc]; 586 587 u8 ip_protocol[0x8]; 588 u8 ip_dscp[0x6]; 589 u8 ip_ecn[0x2]; 590 u8 cvlan_tag[0x1]; 591 u8 svlan_tag[0x1]; 592 u8 frag[0x1]; 593 u8 ip_version[0x4]; 594 u8 tcp_flags[0x9]; 595 596 u8 tcp_sport[0x10]; 597 u8 tcp_dport[0x10]; 598 599 u8 l4_type[0x2]; 600 u8 l4_type_ext[0x4]; 601 u8 reserved_at_c6[0xa]; 602 u8 ipv4_ihl[0x4]; 603 u8 reserved_at_d4[0x4]; 604 u8 ttl_hoplimit[0x8]; 605 606 u8 udp_sport[0x10]; 607 u8 udp_dport[0x10]; 608 609 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 610 611 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 612 }; 613 614 struct mlx5_ifc_nvgre_key_bits { 615 u8 hi[0x18]; 616 u8 lo[0x8]; 617 }; 618 619 union mlx5_ifc_gre_key_bits { 620 struct mlx5_ifc_nvgre_key_bits nvgre; 621 u8 key[0x20]; 622 }; 623 624 struct mlx5_ifc_fte_match_set_misc_bits { 625 u8 gre_c_present[0x1]; 626 u8 reserved_at_1[0x1]; 627 u8 gre_k_present[0x1]; 628 u8 gre_s_present[0x1]; 629 u8 source_vhca_port[0x4]; 630 u8 source_sqn[0x18]; 631 632 u8 source_eswitch_owner_vhca_id[0x10]; 633 u8 source_port[0x10]; 634 635 u8 outer_second_prio[0x3]; 636 u8 outer_second_cfi[0x1]; 637 u8 outer_second_vid[0xc]; 638 u8 inner_second_prio[0x3]; 639 u8 inner_second_cfi[0x1]; 640 u8 inner_second_vid[0xc]; 641 642 u8 outer_second_cvlan_tag[0x1]; 643 u8 inner_second_cvlan_tag[0x1]; 644 u8 outer_second_svlan_tag[0x1]; 645 u8 inner_second_svlan_tag[0x1]; 646 u8 reserved_at_64[0xc]; 647 u8 gre_protocol[0x10]; 648 649 union mlx5_ifc_gre_key_bits gre_key; 650 651 u8 vxlan_vni[0x18]; 652 u8 bth_opcode[0x8]; 653 654 u8 geneve_vni[0x18]; 655 u8 reserved_at_d8[0x6]; 656 u8 geneve_tlv_option_0_exist[0x1]; 657 u8 geneve_oam[0x1]; 658 659 u8 reserved_at_e0[0xc]; 660 u8 outer_ipv6_flow_label[0x14]; 661 662 u8 reserved_at_100[0xc]; 663 u8 inner_ipv6_flow_label[0x14]; 664 665 u8 reserved_at_120[0xa]; 666 u8 geneve_opt_len[0x6]; 667 u8 geneve_protocol_type[0x10]; 668 669 u8 reserved_at_140[0x8]; 670 u8 bth_dst_qp[0x18]; 671 u8 inner_esp_spi[0x20]; 672 u8 outer_esp_spi[0x20]; 673 u8 reserved_at_1a0[0x60]; 674 }; 675 676 struct mlx5_ifc_fte_match_mpls_bits { 677 u8 mpls_label[0x14]; 678 u8 mpls_exp[0x3]; 679 u8 mpls_s_bos[0x1]; 680 u8 mpls_ttl[0x8]; 681 }; 682 683 struct mlx5_ifc_fte_match_set_misc2_bits { 684 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 685 686 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 687 688 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 689 690 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 691 692 u8 metadata_reg_c_7[0x20]; 693 694 u8 metadata_reg_c_6[0x20]; 695 696 u8 metadata_reg_c_5[0x20]; 697 698 u8 metadata_reg_c_4[0x20]; 699 700 u8 metadata_reg_c_3[0x20]; 701 702 u8 metadata_reg_c_2[0x20]; 703 704 u8 metadata_reg_c_1[0x20]; 705 706 u8 metadata_reg_c_0[0x20]; 707 708 u8 metadata_reg_a[0x20]; 709 710 u8 psp_syndrome[0x8]; 711 u8 macsec_syndrome[0x8]; 712 u8 ipsec_syndrome[0x8]; 713 u8 ipsec_next_header[0x8]; 714 715 u8 reserved_at_1c0[0x40]; 716 }; 717 718 struct mlx5_ifc_fte_match_set_misc3_bits { 719 u8 inner_tcp_seq_num[0x20]; 720 721 u8 outer_tcp_seq_num[0x20]; 722 723 u8 inner_tcp_ack_num[0x20]; 724 725 u8 outer_tcp_ack_num[0x20]; 726 727 u8 reserved_at_80[0x8]; 728 u8 outer_vxlan_gpe_vni[0x18]; 729 730 u8 outer_vxlan_gpe_next_protocol[0x8]; 731 u8 outer_vxlan_gpe_flags[0x8]; 732 u8 reserved_at_b0[0x10]; 733 734 u8 icmp_header_data[0x20]; 735 736 u8 icmpv6_header_data[0x20]; 737 738 u8 icmp_type[0x8]; 739 u8 icmp_code[0x8]; 740 u8 icmpv6_type[0x8]; 741 u8 icmpv6_code[0x8]; 742 743 u8 geneve_tlv_option_0_data[0x20]; 744 745 u8 gtpu_teid[0x20]; 746 747 u8 gtpu_msg_type[0x8]; 748 u8 gtpu_msg_flags[0x8]; 749 u8 reserved_at_170[0x10]; 750 751 u8 gtpu_dw_2[0x20]; 752 753 u8 gtpu_first_ext_dw_0[0x20]; 754 755 u8 gtpu_dw_0[0x20]; 756 757 u8 reserved_at_1e0[0x20]; 758 }; 759 760 struct mlx5_ifc_fte_match_set_misc4_bits { 761 u8 prog_sample_field_value_0[0x20]; 762 763 u8 prog_sample_field_id_0[0x20]; 764 765 u8 prog_sample_field_value_1[0x20]; 766 767 u8 prog_sample_field_id_1[0x20]; 768 769 u8 prog_sample_field_value_2[0x20]; 770 771 u8 prog_sample_field_id_2[0x20]; 772 773 u8 prog_sample_field_value_3[0x20]; 774 775 u8 prog_sample_field_id_3[0x20]; 776 777 u8 reserved_at_100[0x100]; 778 }; 779 780 struct mlx5_ifc_fte_match_set_misc5_bits { 781 u8 macsec_tag_0[0x20]; 782 783 u8 macsec_tag_1[0x20]; 784 785 u8 macsec_tag_2[0x20]; 786 787 u8 macsec_tag_3[0x20]; 788 789 u8 tunnel_header_0[0x20]; 790 791 u8 tunnel_header_1[0x20]; 792 793 u8 tunnel_header_2[0x20]; 794 795 u8 tunnel_header_3[0x20]; 796 797 u8 reserved_at_100[0x100]; 798 }; 799 800 struct mlx5_ifc_cmd_pas_bits { 801 u8 pa_h[0x20]; 802 803 u8 pa_l[0x14]; 804 u8 reserved_at_34[0xc]; 805 }; 806 807 struct mlx5_ifc_uint64_bits { 808 u8 hi[0x20]; 809 810 u8 lo[0x20]; 811 }; 812 813 enum { 814 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 815 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 816 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 817 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 818 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 819 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 820 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 821 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 822 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 823 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 824 }; 825 826 struct mlx5_ifc_ads_bits { 827 u8 fl[0x1]; 828 u8 free_ar[0x1]; 829 u8 reserved_at_2[0xe]; 830 u8 pkey_index[0x10]; 831 832 u8 plane_index[0x8]; 833 u8 grh[0x1]; 834 u8 mlid[0x7]; 835 u8 rlid[0x10]; 836 837 u8 ack_timeout[0x5]; 838 u8 reserved_at_45[0x3]; 839 u8 src_addr_index[0x8]; 840 u8 reserved_at_50[0x4]; 841 u8 stat_rate[0x4]; 842 u8 hop_limit[0x8]; 843 844 u8 reserved_at_60[0x4]; 845 u8 tclass[0x8]; 846 u8 flow_label[0x14]; 847 848 u8 rgid_rip[16][0x8]; 849 850 u8 reserved_at_100[0x4]; 851 u8 f_dscp[0x1]; 852 u8 f_ecn[0x1]; 853 u8 reserved_at_106[0x1]; 854 u8 f_eth_prio[0x1]; 855 u8 ecn[0x2]; 856 u8 dscp[0x6]; 857 u8 udp_sport[0x10]; 858 859 u8 dei_cfi[0x1]; 860 u8 eth_prio[0x3]; 861 u8 sl[0x4]; 862 u8 vhca_port_num[0x8]; 863 u8 rmac_47_32[0x10]; 864 865 u8 rmac_31_0[0x20]; 866 }; 867 868 struct mlx5_ifc_flow_table_nic_cap_bits { 869 u8 nic_rx_multi_path_tirs[0x1]; 870 u8 nic_rx_multi_path_tirs_fts[0x1]; 871 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 872 u8 reserved_at_3[0x4]; 873 u8 sw_owner_reformat_supported[0x1]; 874 u8 reserved_at_8[0x18]; 875 876 u8 encap_general_header[0x1]; 877 u8 reserved_at_21[0xa]; 878 u8 log_max_packet_reformat_context[0x5]; 879 u8 reserved_at_30[0x6]; 880 u8 max_encap_header_size[0xa]; 881 u8 reserved_at_40[0x1c0]; 882 883 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 884 885 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 886 887 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 888 889 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 890 891 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 892 893 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 894 895 u8 reserved_at_e00[0x600]; 896 897 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive; 898 899 u8 reserved_at_1480[0x80]; 900 901 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 902 903 u8 reserved_at_1580[0x280]; 904 905 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 906 907 u8 reserved_at_1880[0x780]; 908 909 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 910 911 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 912 913 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 914 915 u8 reserved_at_20c0[0x5f40]; 916 }; 917 918 struct mlx5_ifc_port_selection_cap_bits { 919 u8 reserved_at_0[0x10]; 920 u8 port_select_flow_table[0x1]; 921 u8 reserved_at_11[0x1]; 922 u8 port_select_flow_table_bypass[0x1]; 923 u8 reserved_at_13[0xd]; 924 925 u8 reserved_at_20[0x1e0]; 926 927 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 928 929 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_port_selection; 930 931 u8 reserved_at_480[0x7b80]; 932 }; 933 934 enum { 935 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 936 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 937 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 938 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 939 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 940 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 941 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 942 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 943 }; 944 945 struct mlx5_ifc_flow_table_eswitch_cap_bits { 946 u8 fdb_to_vport_reg_c_id[0x8]; 947 u8 reserved_at_8[0x5]; 948 u8 fdb_uplink_hairpin[0x1]; 949 u8 fdb_multi_path_any_table_limit_regc[0x1]; 950 u8 reserved_at_f[0x1]; 951 u8 fdb_dynamic_tunnel[0x1]; 952 u8 reserved_at_11[0x1]; 953 u8 fdb_multi_path_any_table[0x1]; 954 u8 reserved_at_13[0x2]; 955 u8 fdb_modify_header_fwd_to_table[0x1]; 956 u8 fdb_ipv4_ttl_modify[0x1]; 957 u8 flow_source[0x1]; 958 u8 reserved_at_18[0x2]; 959 u8 multi_fdb_encap[0x1]; 960 u8 egress_acl_forward_to_vport[0x1]; 961 u8 fdb_multi_path_to_table[0x1]; 962 u8 reserved_at_1d[0x3]; 963 964 u8 reserved_at_20[0x1e0]; 965 966 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 967 968 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 969 970 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 971 972 u8 reserved_at_800[0xC00]; 973 974 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb; 975 976 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb; 977 978 u8 reserved_at_1500[0x300]; 979 980 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 981 982 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 983 984 u8 sw_steering_uplink_icm_address_rx[0x40]; 985 986 u8 sw_steering_uplink_icm_address_tx[0x40]; 987 988 u8 reserved_at_1900[0x6700]; 989 }; 990 991 struct mlx5_ifc_wqe_based_flow_table_cap_bits { 992 u8 reserved_at_0[0x3]; 993 u8 log_max_num_ste[0x5]; 994 u8 reserved_at_8[0x3]; 995 u8 log_max_num_stc[0x5]; 996 u8 reserved_at_10[0x3]; 997 u8 log_max_num_rtc[0x5]; 998 u8 reserved_at_18[0x3]; 999 u8 log_max_num_header_modify_pattern[0x5]; 1000 1001 u8 rtc_hash_split_table[0x1]; 1002 u8 rtc_linear_lookup_table[0x1]; 1003 u8 reserved_at_22[0x1]; 1004 u8 stc_alloc_log_granularity[0x5]; 1005 u8 reserved_at_28[0x3]; 1006 u8 stc_alloc_log_max[0x5]; 1007 u8 reserved_at_30[0x3]; 1008 u8 ste_alloc_log_granularity[0x5]; 1009 u8 reserved_at_38[0x3]; 1010 u8 ste_alloc_log_max[0x5]; 1011 1012 u8 reserved_at_40[0xb]; 1013 u8 rtc_reparse_mode[0x5]; 1014 u8 reserved_at_50[0x3]; 1015 u8 rtc_index_mode[0x5]; 1016 u8 reserved_at_58[0x3]; 1017 u8 rtc_log_depth_max[0x5]; 1018 1019 u8 reserved_at_60[0x10]; 1020 u8 ste_format[0x10]; 1021 1022 u8 stc_action_type[0x80]; 1023 1024 u8 header_insert_type[0x10]; 1025 u8 header_remove_type[0x10]; 1026 1027 u8 trivial_match_definer[0x20]; 1028 1029 u8 reserved_at_140[0x1b]; 1030 u8 rtc_max_num_hash_definer_gen_wqe[0x5]; 1031 1032 u8 reserved_at_160[0x18]; 1033 u8 access_index_mode[0x8]; 1034 1035 u8 reserved_at_180[0x10]; 1036 u8 ste_format_gen_wqe[0x10]; 1037 1038 u8 linear_match_definer_reg_c3[0x20]; 1039 1040 u8 fdb_jump_to_tir_stc[0x1]; 1041 u8 reserved_at_1c1[0x1f]; 1042 }; 1043 1044 struct mlx5_ifc_esw_cap_bits { 1045 u8 reserved_at_0[0x1d]; 1046 u8 merged_eswitch[0x1]; 1047 u8 reserved_at_1e[0x2]; 1048 1049 u8 reserved_at_20[0x40]; 1050 1051 u8 esw_manager_vport_number_valid[0x1]; 1052 u8 reserved_at_61[0xf]; 1053 u8 esw_manager_vport_number[0x10]; 1054 1055 u8 reserved_at_80[0x780]; 1056 }; 1057 1058 enum { 1059 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 1060 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 1061 }; 1062 1063 struct mlx5_ifc_e_switch_cap_bits { 1064 u8 vport_svlan_strip[0x1]; 1065 u8 vport_cvlan_strip[0x1]; 1066 u8 vport_svlan_insert[0x1]; 1067 u8 vport_cvlan_insert_if_not_exist[0x1]; 1068 u8 vport_cvlan_insert_overwrite[0x1]; 1069 u8 reserved_at_5[0x1]; 1070 u8 vport_cvlan_insert_always[0x1]; 1071 u8 esw_shared_ingress_acl[0x1]; 1072 u8 esw_uplink_ingress_acl[0x1]; 1073 u8 root_ft_on_other_esw[0x1]; 1074 u8 reserved_at_a[0x1]; 1075 u8 esw_vport_state_max_tx_speed[0x1]; 1076 u8 reserved_at_c[0xd]; 1077 u8 esw_functions_changed[0x1]; 1078 u8 reserved_at_1a[0x1]; 1079 u8 ecpf_vport_exists[0x1]; 1080 u8 counter_eswitch_affinity[0x1]; 1081 u8 merged_eswitch[0x1]; 1082 u8 nic_vport_node_guid_modify[0x1]; 1083 u8 nic_vport_port_guid_modify[0x1]; 1084 1085 u8 vxlan_encap_decap[0x1]; 1086 u8 nvgre_encap_decap[0x1]; 1087 u8 reserved_at_22[0x1]; 1088 u8 log_max_fdb_encap_uplink[0x5]; 1089 u8 reserved_at_21[0x3]; 1090 u8 log_max_packet_reformat_context[0x5]; 1091 u8 reserved_2b[0x6]; 1092 u8 max_encap_header_size[0xa]; 1093 1094 u8 reserved_at_40[0xb]; 1095 u8 log_max_esw_sf[0x5]; 1096 u8 esw_sf_base_id[0x10]; 1097 1098 u8 reserved_at_60[0x7a0]; 1099 1100 }; 1101 1102 struct mlx5_ifc_qos_cap_bits { 1103 u8 packet_pacing[0x1]; 1104 u8 esw_scheduling[0x1]; 1105 u8 esw_bw_share[0x1]; 1106 u8 esw_rate_limit[0x1]; 1107 u8 reserved_at_4[0x1]; 1108 u8 packet_pacing_burst_bound[0x1]; 1109 u8 packet_pacing_typical_size[0x1]; 1110 u8 reserved_at_7[0x1]; 1111 u8 nic_sq_scheduling[0x1]; 1112 u8 nic_bw_share[0x1]; 1113 u8 nic_rate_limit[0x1]; 1114 u8 packet_pacing_uid[0x1]; 1115 u8 log_esw_max_sched_depth[0x4]; 1116 u8 reserved_at_10[0x10]; 1117 1118 u8 reserved_at_20[0x9]; 1119 u8 esw_cross_esw_sched[0x1]; 1120 u8 reserved_at_2a[0x1]; 1121 u8 log_max_qos_nic_queue_group[0x5]; 1122 u8 reserved_at_30[0x10]; 1123 1124 u8 packet_pacing_max_rate[0x20]; 1125 1126 u8 packet_pacing_min_rate[0x20]; 1127 1128 u8 reserved_at_80[0xb]; 1129 u8 log_esw_max_rate_limit[0x5]; 1130 u8 packet_pacing_rate_table_size[0x10]; 1131 1132 u8 esw_element_type[0x10]; 1133 u8 esw_tsar_type[0x10]; 1134 1135 u8 reserved_at_c0[0x10]; 1136 u8 max_qos_para_vport[0x10]; 1137 1138 u8 max_tsar_bw_share[0x20]; 1139 1140 u8 nic_element_type[0x10]; 1141 u8 nic_tsar_type[0x10]; 1142 1143 u8 reserved_at_120[0x3]; 1144 u8 log_meter_aso_granularity[0x5]; 1145 u8 reserved_at_128[0x3]; 1146 u8 log_meter_aso_max_alloc[0x5]; 1147 u8 reserved_at_130[0x3]; 1148 u8 log_max_num_meter_aso[0x5]; 1149 u8 reserved_at_138[0x8]; 1150 1151 u8 reserved_at_140[0x6c0]; 1152 }; 1153 1154 struct mlx5_ifc_debug_cap_bits { 1155 u8 core_dump_general[0x1]; 1156 u8 core_dump_qp[0x1]; 1157 u8 reserved_at_2[0x7]; 1158 u8 resource_dump[0x1]; 1159 u8 reserved_at_a[0x16]; 1160 1161 u8 reserved_at_20[0x2]; 1162 u8 stall_detect[0x1]; 1163 u8 reserved_at_23[0x1d]; 1164 1165 u8 reserved_at_40[0x7c0]; 1166 }; 1167 1168 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1169 u8 csum_cap[0x1]; 1170 u8 vlan_cap[0x1]; 1171 u8 lro_cap[0x1]; 1172 u8 lro_psh_flag[0x1]; 1173 u8 lro_time_stamp[0x1]; 1174 u8 reserved_at_5[0x2]; 1175 u8 wqe_vlan_insert[0x1]; 1176 u8 self_lb_en_modifiable[0x1]; 1177 u8 reserved_at_9[0x2]; 1178 u8 max_lso_cap[0x5]; 1179 u8 multi_pkt_send_wqe[0x2]; 1180 u8 wqe_inline_mode[0x2]; 1181 u8 rss_ind_tbl_cap[0x4]; 1182 u8 reg_umr_sq[0x1]; 1183 u8 scatter_fcs[0x1]; 1184 u8 enhanced_multi_pkt_send_wqe[0x1]; 1185 u8 tunnel_lso_const_out_ip_id[0x1]; 1186 u8 tunnel_lro_gre[0x1]; 1187 u8 tunnel_lro_vxlan[0x1]; 1188 u8 tunnel_stateless_gre[0x1]; 1189 u8 tunnel_stateless_vxlan[0x1]; 1190 1191 u8 swp[0x1]; 1192 u8 swp_csum[0x1]; 1193 u8 swp_lso[0x1]; 1194 u8 cqe_checksum_full[0x1]; 1195 u8 tunnel_stateless_geneve_tx[0x1]; 1196 u8 tunnel_stateless_mpls_over_udp[0x1]; 1197 u8 tunnel_stateless_mpls_over_gre[0x1]; 1198 u8 tunnel_stateless_vxlan_gpe[0x1]; 1199 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1200 u8 tunnel_stateless_ip_over_ip[0x1]; 1201 u8 insert_trailer[0x1]; 1202 u8 reserved_at_2b[0x1]; 1203 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1204 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1205 u8 reserved_at_2e[0x2]; 1206 u8 max_vxlan_udp_ports[0x8]; 1207 u8 swp_csum_l4_partial[0x1]; 1208 u8 reserved_at_39[0x5]; 1209 u8 max_geneve_opt_len[0x1]; 1210 u8 tunnel_stateless_geneve_rx[0x1]; 1211 1212 u8 reserved_at_40[0x10]; 1213 u8 lro_min_mss_size[0x10]; 1214 1215 u8 reserved_at_60[0x120]; 1216 1217 u8 lro_timer_supported_periods[4][0x20]; 1218 1219 u8 reserved_at_200[0x600]; 1220 }; 1221 1222 enum { 1223 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1224 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1225 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1226 }; 1227 1228 struct mlx5_ifc_roce_cap_bits { 1229 u8 roce_apm[0x1]; 1230 u8 reserved_at_1[0x3]; 1231 u8 sw_r_roce_src_udp_port[0x1]; 1232 u8 fl_rc_qp_when_roce_disabled[0x1]; 1233 u8 fl_rc_qp_when_roce_enabled[0x1]; 1234 u8 roce_cc_general[0x1]; 1235 u8 qp_ooo_transmit_default[0x1]; 1236 u8 reserved_at_9[0x15]; 1237 u8 qp_ts_format[0x2]; 1238 1239 u8 reserved_at_20[0x60]; 1240 1241 u8 reserved_at_80[0xc]; 1242 u8 l3_type[0x4]; 1243 u8 reserved_at_90[0x8]; 1244 u8 roce_version[0x8]; 1245 1246 u8 reserved_at_a0[0x10]; 1247 u8 r_roce_dest_udp_port[0x10]; 1248 1249 u8 r_roce_max_src_udp_port[0x10]; 1250 u8 r_roce_min_src_udp_port[0x10]; 1251 1252 u8 reserved_at_e0[0x10]; 1253 u8 roce_address_table_size[0x10]; 1254 1255 u8 reserved_at_100[0x700]; 1256 }; 1257 1258 struct mlx5_ifc_sync_steering_in_bits { 1259 u8 opcode[0x10]; 1260 u8 uid[0x10]; 1261 1262 u8 reserved_at_20[0x10]; 1263 u8 op_mod[0x10]; 1264 1265 u8 reserved_at_40[0xc0]; 1266 }; 1267 1268 struct mlx5_ifc_sync_steering_out_bits { 1269 u8 status[0x8]; 1270 u8 reserved_at_8[0x18]; 1271 1272 u8 syndrome[0x20]; 1273 1274 u8 reserved_at_40[0x40]; 1275 }; 1276 1277 struct mlx5_ifc_sync_crypto_in_bits { 1278 u8 opcode[0x10]; 1279 u8 uid[0x10]; 1280 1281 u8 reserved_at_20[0x10]; 1282 u8 op_mod[0x10]; 1283 1284 u8 reserved_at_40[0x20]; 1285 1286 u8 reserved_at_60[0x10]; 1287 u8 crypto_type[0x10]; 1288 1289 u8 reserved_at_80[0x80]; 1290 }; 1291 1292 struct mlx5_ifc_sync_crypto_out_bits { 1293 u8 status[0x8]; 1294 u8 reserved_at_8[0x18]; 1295 1296 u8 syndrome[0x20]; 1297 1298 u8 reserved_at_40[0x40]; 1299 }; 1300 1301 struct mlx5_ifc_device_mem_cap_bits { 1302 u8 memic[0x1]; 1303 u8 reserved_at_1[0x1f]; 1304 1305 u8 reserved_at_20[0xb]; 1306 u8 log_min_memic_alloc_size[0x5]; 1307 u8 reserved_at_30[0x8]; 1308 u8 log_max_memic_addr_alignment[0x8]; 1309 1310 u8 memic_bar_start_addr[0x40]; 1311 1312 u8 memic_bar_size[0x20]; 1313 1314 u8 max_memic_size[0x20]; 1315 1316 u8 steering_sw_icm_start_address[0x40]; 1317 1318 u8 reserved_at_100[0x8]; 1319 u8 log_header_modify_sw_icm_size[0x8]; 1320 u8 reserved_at_110[0x2]; 1321 u8 log_sw_icm_alloc_granularity[0x6]; 1322 u8 log_steering_sw_icm_size[0x8]; 1323 1324 u8 log_indirect_encap_sw_icm_size[0x8]; 1325 u8 reserved_at_128[0x10]; 1326 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1327 1328 u8 header_modify_sw_icm_start_address[0x40]; 1329 1330 u8 reserved_at_180[0x40]; 1331 1332 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1333 1334 u8 memic_operations[0x20]; 1335 1336 u8 reserved_at_220[0x20]; 1337 1338 u8 indirect_encap_sw_icm_start_address[0x40]; 1339 1340 u8 reserved_at_280[0x580]; 1341 }; 1342 1343 struct mlx5_ifc_device_event_cap_bits { 1344 u8 user_affiliated_events[4][0x40]; 1345 1346 u8 user_unaffiliated_events[4][0x40]; 1347 }; 1348 1349 struct mlx5_ifc_virtio_emulation_cap_bits { 1350 u8 desc_tunnel_offload_type[0x1]; 1351 u8 eth_frame_offload_type[0x1]; 1352 u8 virtio_version_1_0[0x1]; 1353 u8 device_features_bits_mask[0xd]; 1354 u8 event_mode[0x8]; 1355 u8 virtio_queue_type[0x8]; 1356 1357 u8 max_tunnel_desc[0x10]; 1358 u8 reserved_at_30[0x3]; 1359 u8 log_doorbell_stride[0x5]; 1360 u8 reserved_at_38[0x3]; 1361 u8 log_doorbell_bar_size[0x5]; 1362 1363 u8 doorbell_bar_offset[0x40]; 1364 1365 u8 max_emulated_devices[0x8]; 1366 u8 max_num_virtio_queues[0x18]; 1367 1368 u8 reserved_at_a0[0x20]; 1369 1370 u8 reserved_at_c0[0x13]; 1371 u8 desc_group_mkey_supported[0x1]; 1372 u8 freeze_to_rdy_supported[0x1]; 1373 u8 reserved_at_d5[0xb]; 1374 1375 u8 reserved_at_e0[0x20]; 1376 1377 u8 umem_1_buffer_param_a[0x20]; 1378 1379 u8 umem_1_buffer_param_b[0x20]; 1380 1381 u8 umem_2_buffer_param_a[0x20]; 1382 1383 u8 umem_2_buffer_param_b[0x20]; 1384 1385 u8 umem_3_buffer_param_a[0x20]; 1386 1387 u8 umem_3_buffer_param_b[0x20]; 1388 1389 u8 reserved_at_1c0[0x640]; 1390 }; 1391 1392 enum { 1393 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1394 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1395 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1396 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1397 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1398 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1399 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1400 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1401 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1402 }; 1403 1404 enum { 1405 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1406 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1407 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1408 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1409 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1410 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1411 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1412 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1413 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1414 }; 1415 1416 struct mlx5_ifc_atomic_caps_bits { 1417 u8 reserved_at_0[0x40]; 1418 1419 u8 atomic_req_8B_endianness_mode[0x2]; 1420 u8 reserved_at_42[0x4]; 1421 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1422 1423 u8 reserved_at_47[0x19]; 1424 1425 u8 reserved_at_60[0x20]; 1426 1427 u8 reserved_at_80[0x10]; 1428 u8 atomic_operations[0x10]; 1429 1430 u8 reserved_at_a0[0x10]; 1431 u8 atomic_size_qp[0x10]; 1432 1433 u8 reserved_at_c0[0x10]; 1434 u8 atomic_size_dc[0x10]; 1435 1436 u8 reserved_at_e0[0x720]; 1437 }; 1438 1439 struct mlx5_ifc_odp_scheme_cap_bits { 1440 u8 reserved_at_0[0x40]; 1441 1442 u8 sig[0x1]; 1443 u8 reserved_at_41[0x4]; 1444 u8 page_prefetch[0x1]; 1445 u8 reserved_at_46[0x1a]; 1446 1447 u8 reserved_at_60[0x20]; 1448 1449 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1450 1451 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1452 1453 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1454 1455 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1456 1457 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1458 1459 u8 reserved_at_120[0xe0]; 1460 }; 1461 1462 struct mlx5_ifc_odp_cap_bits { 1463 struct mlx5_ifc_odp_scheme_cap_bits transport_page_fault_scheme_cap; 1464 1465 struct mlx5_ifc_odp_scheme_cap_bits memory_page_fault_scheme_cap; 1466 1467 u8 reserved_at_400[0x200]; 1468 1469 u8 mem_page_fault[0x1]; 1470 u8 reserved_at_601[0x1f]; 1471 1472 u8 reserved_at_620[0x1e0]; 1473 }; 1474 1475 struct mlx5_ifc_tls_cap_bits { 1476 u8 tls_1_2_aes_gcm_128[0x1]; 1477 u8 tls_1_3_aes_gcm_128[0x1]; 1478 u8 tls_1_2_aes_gcm_256[0x1]; 1479 u8 tls_1_3_aes_gcm_256[0x1]; 1480 u8 reserved_at_4[0x1c]; 1481 1482 u8 reserved_at_20[0x7e0]; 1483 }; 1484 1485 struct mlx5_ifc_ipsec_cap_bits { 1486 u8 ipsec_full_offload[0x1]; 1487 u8 ipsec_crypto_offload[0x1]; 1488 u8 ipsec_esn[0x1]; 1489 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1490 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1491 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1492 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1493 u8 reserved_at_7[0x4]; 1494 u8 log_max_ipsec_offload[0x5]; 1495 u8 reserved_at_10[0x10]; 1496 1497 u8 min_log_ipsec_full_replay_window[0x8]; 1498 u8 max_log_ipsec_full_replay_window[0x8]; 1499 u8 reserved_at_30[0x7d0]; 1500 }; 1501 1502 struct mlx5_ifc_macsec_cap_bits { 1503 u8 macsec_epn[0x1]; 1504 u8 reserved_at_1[0x2]; 1505 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1506 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1507 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1508 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1509 u8 reserved_at_7[0x4]; 1510 u8 log_max_macsec_offload[0x5]; 1511 u8 reserved_at_10[0x10]; 1512 1513 u8 min_log_macsec_full_replay_window[0x8]; 1514 u8 max_log_macsec_full_replay_window[0x8]; 1515 u8 reserved_at_30[0x10]; 1516 1517 u8 reserved_at_40[0x7c0]; 1518 }; 1519 1520 struct mlx5_ifc_psp_cap_bits { 1521 u8 reserved_at_0[0x1]; 1522 u8 psp_crypto_offload[0x1]; 1523 u8 reserved_at_2[0x1]; 1524 u8 psp_crypto_esp_aes_gcm_256_encrypt[0x1]; 1525 u8 psp_crypto_esp_aes_gcm_128_encrypt[0x1]; 1526 u8 psp_crypto_esp_aes_gcm_256_decrypt[0x1]; 1527 u8 psp_crypto_esp_aes_gcm_128_decrypt[0x1]; 1528 u8 reserved_at_7[0x4]; 1529 u8 log_max_num_of_psp_spi[0x5]; 1530 u8 reserved_at_10[0x10]; 1531 1532 u8 reserved_at_20[0x7e0]; 1533 }; 1534 1535 enum { 1536 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1537 MLX5_WQ_TYPE_CYCLIC = 0x1, 1538 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1539 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1540 }; 1541 1542 enum { 1543 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1544 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1545 }; 1546 1547 enum { 1548 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1549 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1550 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1551 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1552 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1553 }; 1554 1555 enum { 1556 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1557 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1558 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1559 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1560 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1561 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1562 }; 1563 1564 enum { 1565 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1566 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1567 }; 1568 1569 enum { 1570 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1571 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1572 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1573 }; 1574 1575 enum { 1576 MLX5_CAP_PORT_TYPE_IB = 0x0, 1577 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1578 }; 1579 1580 enum { 1581 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1582 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1583 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1584 }; 1585 1586 enum { 1587 MLX5_FLEX_IPV4_OVER_VXLAN_ENABLED = 1 << 0, 1588 MLX5_FLEX_IPV6_OVER_VXLAN_ENABLED = 1 << 1, 1589 MLX5_FLEX_IPV6_OVER_IP_ENABLED = 1 << 2, 1590 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1591 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1592 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1593 MLX5_FLEX_P_BIT_VXLAN_GPE_ENABLED = 1 << 6, 1594 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1595 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1596 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1597 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1598 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1599 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1600 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1601 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1602 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1603 }; 1604 1605 enum { 1606 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1607 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1608 MLX5_UCTX_CAP_RDMA_CTRL = 1UL << 3, 1609 MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA = 1UL << 4, 1610 }; 1611 1612 #define MLX5_FC_BULK_SIZE_FACTOR 128 1613 1614 enum mlx5_fc_bulk_alloc_bitmask { 1615 MLX5_FC_BULK_128 = (1 << 0), 1616 MLX5_FC_BULK_256 = (1 << 1), 1617 MLX5_FC_BULK_512 = (1 << 2), 1618 MLX5_FC_BULK_1024 = (1 << 3), 1619 MLX5_FC_BULK_2048 = (1 << 4), 1620 MLX5_FC_BULK_4096 = (1 << 5), 1621 MLX5_FC_BULK_8192 = (1 << 6), 1622 MLX5_FC_BULK_16384 = (1 << 7), 1623 }; 1624 1625 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1626 1627 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1628 1629 enum { 1630 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1631 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1632 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1633 MLX5_STEERING_FORMAT_CONNECTX_8 = 3, 1634 }; 1635 1636 struct mlx5_ifc_cmd_hca_cap_bits { 1637 u8 reserved_at_0[0x6]; 1638 u8 page_request_disable[0x1]; 1639 u8 abs_native_port_num[0x1]; 1640 u8 reserved_at_8[0x8]; 1641 u8 shared_object_to_user_object_allowed[0x1]; 1642 u8 reserved_at_13[0xe]; 1643 u8 vhca_resource_manager[0x1]; 1644 1645 u8 hca_cap_2[0x1]; 1646 u8 create_lag_when_not_master_up[0x1]; 1647 u8 dtor[0x1]; 1648 u8 event_on_vhca_state_teardown_request[0x1]; 1649 u8 event_on_vhca_state_in_use[0x1]; 1650 u8 event_on_vhca_state_active[0x1]; 1651 u8 event_on_vhca_state_allocated[0x1]; 1652 u8 event_on_vhca_state_invalid[0x1]; 1653 u8 reserved_at_28[0x8]; 1654 u8 vhca_id[0x10]; 1655 1656 u8 reserved_at_40[0x40]; 1657 1658 u8 log_max_srq_sz[0x8]; 1659 u8 log_max_qp_sz[0x8]; 1660 u8 event_cap[0x1]; 1661 u8 reserved_at_91[0x2]; 1662 u8 isolate_vl_tc_new[0x1]; 1663 u8 reserved_at_94[0x4]; 1664 u8 prio_tag_required[0x1]; 1665 u8 reserved_at_99[0x2]; 1666 u8 log_max_qp[0x5]; 1667 1668 u8 reserved_at_a0[0x3]; 1669 u8 ece_support[0x1]; 1670 u8 reserved_at_a4[0x5]; 1671 u8 reg_c_preserve[0x1]; 1672 u8 reserved_at_aa[0x1]; 1673 u8 log_max_srq[0x5]; 1674 u8 reserved_at_b0[0x1]; 1675 u8 uplink_follow[0x1]; 1676 u8 ts_cqe_to_dest_cqn[0x1]; 1677 u8 reserved_at_b3[0x6]; 1678 u8 go_back_n[0x1]; 1679 u8 reserved_at_ba[0x6]; 1680 1681 u8 max_sgl_for_optimized_performance[0x8]; 1682 u8 log_max_cq_sz[0x8]; 1683 u8 relaxed_ordering_write_umr[0x1]; 1684 u8 relaxed_ordering_read_umr[0x1]; 1685 u8 reserved_at_d2[0x7]; 1686 u8 virtio_net_device_emualtion_manager[0x1]; 1687 u8 virtio_blk_device_emualtion_manager[0x1]; 1688 u8 log_max_cq[0x5]; 1689 1690 u8 log_max_eq_sz[0x8]; 1691 u8 relaxed_ordering_write[0x1]; 1692 u8 relaxed_ordering_read_pci_enabled[0x1]; 1693 u8 log_max_mkey[0x6]; 1694 u8 reserved_at_f0[0x6]; 1695 u8 terminate_scatter_list_mkey[0x1]; 1696 u8 repeated_mkey[0x1]; 1697 u8 dump_fill_mkey[0x1]; 1698 u8 reserved_at_f9[0x2]; 1699 u8 fast_teardown[0x1]; 1700 u8 log_max_eq[0x4]; 1701 1702 u8 max_indirection[0x8]; 1703 u8 fixed_buffer_size[0x1]; 1704 u8 log_max_mrw_sz[0x7]; 1705 u8 force_teardown[0x1]; 1706 u8 reserved_at_111[0x1]; 1707 u8 log_max_bsf_list_size[0x6]; 1708 u8 umr_extended_translation_offset[0x1]; 1709 u8 null_mkey[0x1]; 1710 u8 log_max_klm_list_size[0x6]; 1711 1712 u8 reserved_at_120[0x2]; 1713 u8 qpc_extension[0x1]; 1714 u8 reserved_at_123[0x7]; 1715 u8 log_max_ra_req_dc[0x6]; 1716 u8 reserved_at_130[0x2]; 1717 u8 eth_wqe_too_small[0x1]; 1718 u8 reserved_at_133[0x6]; 1719 u8 vnic_env_cq_overrun[0x1]; 1720 u8 log_max_ra_res_dc[0x6]; 1721 1722 u8 reserved_at_140[0x5]; 1723 u8 release_all_pages[0x1]; 1724 u8 must_not_use[0x1]; 1725 u8 reserved_at_147[0x2]; 1726 u8 roce_accl[0x1]; 1727 u8 log_max_ra_req_qp[0x6]; 1728 u8 reserved_at_150[0xa]; 1729 u8 log_max_ra_res_qp[0x6]; 1730 1731 u8 end_pad[0x1]; 1732 u8 cc_query_allowed[0x1]; 1733 u8 cc_modify_allowed[0x1]; 1734 u8 start_pad[0x1]; 1735 u8 cache_line_128byte[0x1]; 1736 u8 reserved_at_165[0x4]; 1737 u8 rts2rts_qp_counters_set_id[0x1]; 1738 u8 reserved_at_16a[0x2]; 1739 u8 vnic_env_int_rq_oob[0x1]; 1740 u8 sbcam_reg[0x1]; 1741 u8 reserved_at_16e[0x1]; 1742 u8 qcam_reg[0x1]; 1743 u8 gid_table_size[0x10]; 1744 1745 u8 out_of_seq_cnt[0x1]; 1746 u8 vport_counters[0x1]; 1747 u8 retransmission_q_counters[0x1]; 1748 u8 debug[0x1]; 1749 u8 modify_rq_counter_set_id[0x1]; 1750 u8 rq_delay_drop[0x1]; 1751 u8 max_qp_cnt[0xa]; 1752 u8 pkey_table_size[0x10]; 1753 1754 u8 vport_group_manager[0x1]; 1755 u8 vhca_group_manager[0x1]; 1756 u8 ib_virt[0x1]; 1757 u8 eth_virt[0x1]; 1758 u8 vnic_env_queue_counters[0x1]; 1759 u8 ets[0x1]; 1760 u8 nic_flow_table[0x1]; 1761 u8 eswitch_manager[0x1]; 1762 u8 device_memory[0x1]; 1763 u8 mcam_reg[0x1]; 1764 u8 pcam_reg[0x1]; 1765 u8 local_ca_ack_delay[0x5]; 1766 u8 port_module_event[0x1]; 1767 u8 enhanced_error_q_counters[0x1]; 1768 u8 ports_check[0x1]; 1769 u8 reserved_at_1b3[0x1]; 1770 u8 disable_link_up[0x1]; 1771 u8 beacon_led[0x1]; 1772 u8 port_type[0x2]; 1773 u8 num_ports[0x8]; 1774 1775 u8 reserved_at_1c0[0x1]; 1776 u8 pps[0x1]; 1777 u8 pps_modify[0x1]; 1778 u8 log_max_msg[0x5]; 1779 u8 reserved_at_1c8[0x4]; 1780 u8 max_tc[0x4]; 1781 u8 temp_warn_event[0x1]; 1782 u8 dcbx[0x1]; 1783 u8 general_notification_event[0x1]; 1784 u8 reserved_at_1d3[0x2]; 1785 u8 fpga[0x1]; 1786 u8 rol_s[0x1]; 1787 u8 rol_g[0x1]; 1788 u8 reserved_at_1d8[0x1]; 1789 u8 wol_s[0x1]; 1790 u8 wol_g[0x1]; 1791 u8 wol_a[0x1]; 1792 u8 wol_b[0x1]; 1793 u8 wol_m[0x1]; 1794 u8 wol_u[0x1]; 1795 u8 wol_p[0x1]; 1796 1797 u8 stat_rate_support[0x10]; 1798 u8 reserved_at_1f0[0x1]; 1799 u8 pci_sync_for_fw_update_event[0x1]; 1800 u8 reserved_at_1f2[0x6]; 1801 u8 init2_lag_tx_port_affinity[0x1]; 1802 u8 reserved_at_1fa[0x2]; 1803 u8 wqe_based_flow_table_update_cap[0x1]; 1804 u8 cqe_version[0x4]; 1805 1806 u8 compact_address_vector[0x1]; 1807 u8 striding_rq[0x1]; 1808 u8 reserved_at_202[0x1]; 1809 u8 ipoib_enhanced_offloads[0x1]; 1810 u8 ipoib_basic_offloads[0x1]; 1811 u8 reserved_at_205[0x1]; 1812 u8 repeated_block_disabled[0x1]; 1813 u8 umr_modify_entity_size_disabled[0x1]; 1814 u8 umr_modify_atomic_disabled[0x1]; 1815 u8 umr_indirect_mkey_disabled[0x1]; 1816 u8 umr_fence[0x2]; 1817 u8 dc_req_scat_data_cqe[0x1]; 1818 u8 reserved_at_20d[0x2]; 1819 u8 drain_sigerr[0x1]; 1820 u8 cmdif_checksum[0x2]; 1821 u8 sigerr_cqe[0x1]; 1822 u8 reserved_at_213[0x1]; 1823 u8 wq_signature[0x1]; 1824 u8 sctr_data_cqe[0x1]; 1825 u8 reserved_at_216[0x1]; 1826 u8 sho[0x1]; 1827 u8 tph[0x1]; 1828 u8 rf[0x1]; 1829 u8 dct[0x1]; 1830 u8 qos[0x1]; 1831 u8 eth_net_offloads[0x1]; 1832 u8 roce[0x1]; 1833 u8 atomic[0x1]; 1834 u8 reserved_at_21f[0x1]; 1835 1836 u8 cq_oi[0x1]; 1837 u8 cq_resize[0x1]; 1838 u8 cq_moderation[0x1]; 1839 u8 cq_period_mode_modify[0x1]; 1840 u8 reserved_at_224[0x2]; 1841 u8 cq_eq_remap[0x1]; 1842 u8 pg[0x1]; 1843 u8 block_lb_mc[0x1]; 1844 u8 reserved_at_229[0x1]; 1845 u8 scqe_break_moderation[0x1]; 1846 u8 cq_period_start_from_cqe[0x1]; 1847 u8 cd[0x1]; 1848 u8 reserved_at_22d[0x1]; 1849 u8 apm[0x1]; 1850 u8 vector_calc[0x1]; 1851 u8 umr_ptr_rlky[0x1]; 1852 u8 imaicl[0x1]; 1853 u8 qp_packet_based[0x1]; 1854 u8 reserved_at_233[0x3]; 1855 u8 qkv[0x1]; 1856 u8 pkv[0x1]; 1857 u8 set_deth_sqpn[0x1]; 1858 u8 reserved_at_239[0x3]; 1859 u8 xrc[0x1]; 1860 u8 ud[0x1]; 1861 u8 uc[0x1]; 1862 u8 rc[0x1]; 1863 1864 u8 uar_4k[0x1]; 1865 u8 reserved_at_241[0x7]; 1866 u8 fl_rc_qp_when_roce_disabled[0x1]; 1867 u8 regexp_params[0x1]; 1868 u8 uar_sz[0x6]; 1869 u8 port_selection_cap[0x1]; 1870 u8 nic_cap_reg[0x1]; 1871 u8 umem_uid_0[0x1]; 1872 u8 reserved_at_253[0x5]; 1873 u8 log_pg_sz[0x8]; 1874 1875 u8 bf[0x1]; 1876 u8 driver_version[0x1]; 1877 u8 pad_tx_eth_packet[0x1]; 1878 u8 reserved_at_263[0x3]; 1879 u8 mkey_by_name[0x1]; 1880 u8 reserved_at_267[0x4]; 1881 1882 u8 log_bf_reg_size[0x5]; 1883 1884 u8 disciplined_fr_counter[0x1]; 1885 u8 reserved_at_271[0x2]; 1886 u8 qp_error_syndrome[0x1]; 1887 u8 reserved_at_274[0x2]; 1888 u8 lag_dct[0x2]; 1889 u8 lag_tx_port_affinity[0x1]; 1890 u8 lag_native_fdb_selection[0x1]; 1891 u8 reserved_at_27a[0x1]; 1892 u8 lag_master[0x1]; 1893 u8 num_lag_ports[0x4]; 1894 1895 u8 reserved_at_280[0x10]; 1896 u8 max_wqe_sz_sq[0x10]; 1897 1898 u8 reserved_at_2a0[0x7]; 1899 u8 mkey_pcie_tph[0x1]; 1900 u8 reserved_at_2a8[0x1]; 1901 u8 tis_tir_td_order[0x1]; 1902 1903 u8 psp[0x1]; 1904 u8 shampo[0x1]; 1905 u8 reserved_at_2ac[0x4]; 1906 u8 max_wqe_sz_rq[0x10]; 1907 1908 u8 max_flow_counter_31_16[0x10]; 1909 u8 max_wqe_sz_sq_dc[0x10]; 1910 1911 u8 reserved_at_2e0[0x7]; 1912 u8 max_qp_mcg[0x19]; 1913 1914 u8 reserved_at_300[0x10]; 1915 u8 flow_counter_bulk_alloc[0x8]; 1916 u8 log_max_mcg[0x8]; 1917 1918 u8 reserved_at_320[0x3]; 1919 u8 log_max_transport_domain[0x5]; 1920 u8 reserved_at_328[0x2]; 1921 u8 relaxed_ordering_read[0x1]; 1922 u8 log_max_pd[0x5]; 1923 u8 dp_ordering_ooo_all_ud[0x1]; 1924 u8 dp_ordering_ooo_all_uc[0x1]; 1925 u8 dp_ordering_ooo_all_xrc[0x1]; 1926 u8 dp_ordering_ooo_all_dc[0x1]; 1927 u8 dp_ordering_ooo_all_rc[0x1]; 1928 u8 pcie_reset_using_hotreset_method[0x1]; 1929 u8 pci_sync_for_fw_update_with_driver_unload[0x1]; 1930 u8 vnic_env_cnt_steering_fail[0x1]; 1931 u8 vport_counter_local_loopback[0x1]; 1932 u8 q_counter_aggregation[0x1]; 1933 u8 q_counter_other_vport[0x1]; 1934 u8 log_max_xrcd[0x5]; 1935 1936 u8 nic_receive_steering_discard[0x1]; 1937 u8 receive_discard_vport_down[0x1]; 1938 u8 transmit_discard_vport_down[0x1]; 1939 u8 eq_overrun_count[0x1]; 1940 u8 reserved_at_344[0x1]; 1941 u8 invalid_command_count[0x1]; 1942 u8 quota_exceeded_count[0x1]; 1943 u8 reserved_at_347[0x1]; 1944 u8 log_max_flow_counter_bulk[0x8]; 1945 u8 max_flow_counter_15_0[0x10]; 1946 1947 1948 u8 reserved_at_360[0x3]; 1949 u8 log_max_rq[0x5]; 1950 u8 reserved_at_368[0x3]; 1951 u8 log_max_sq[0x5]; 1952 u8 reserved_at_370[0x3]; 1953 u8 log_max_tir[0x5]; 1954 u8 reserved_at_378[0x3]; 1955 u8 log_max_tis[0x5]; 1956 1957 u8 basic_cyclic_rcv_wqe[0x1]; 1958 u8 reserved_at_381[0x2]; 1959 u8 log_max_rmp[0x5]; 1960 u8 reserved_at_388[0x3]; 1961 u8 log_max_rqt[0x5]; 1962 u8 reserved_at_390[0x3]; 1963 u8 log_max_rqt_size[0x5]; 1964 u8 reserved_at_398[0x1]; 1965 u8 vnic_env_cnt_bar_uar_access[0x1]; 1966 u8 vnic_env_cnt_odp_page_fault[0x1]; 1967 u8 log_max_tis_per_sq[0x5]; 1968 1969 u8 ext_stride_num_range[0x1]; 1970 u8 roce_rw_supported[0x1]; 1971 u8 log_max_current_uc_list_wr_supported[0x1]; 1972 u8 log_max_stride_sz_rq[0x5]; 1973 u8 reserved_at_3a8[0x3]; 1974 u8 log_min_stride_sz_rq[0x5]; 1975 u8 reserved_at_3b0[0x3]; 1976 u8 log_max_stride_sz_sq[0x5]; 1977 u8 reserved_at_3b8[0x3]; 1978 u8 log_min_stride_sz_sq[0x5]; 1979 1980 u8 hairpin[0x1]; 1981 u8 reserved_at_3c1[0x2]; 1982 u8 log_max_hairpin_queues[0x5]; 1983 u8 reserved_at_3c8[0x3]; 1984 u8 log_max_hairpin_wq_data_sz[0x5]; 1985 u8 reserved_at_3d0[0x3]; 1986 u8 log_max_hairpin_num_packets[0x5]; 1987 u8 reserved_at_3d8[0x3]; 1988 u8 log_max_wq_sz[0x5]; 1989 1990 u8 nic_vport_change_event[0x1]; 1991 u8 disable_local_lb_uc[0x1]; 1992 u8 disable_local_lb_mc[0x1]; 1993 u8 log_min_hairpin_wq_data_sz[0x5]; 1994 u8 reserved_at_3e8[0x1]; 1995 u8 silent_mode[0x1]; 1996 u8 vhca_state[0x1]; 1997 u8 log_max_vlan_list[0x5]; 1998 u8 reserved_at_3f0[0x3]; 1999 u8 log_max_current_mc_list[0x5]; 2000 u8 reserved_at_3f8[0x3]; 2001 u8 log_max_current_uc_list[0x5]; 2002 2003 u8 general_obj_types[0x40]; 2004 2005 u8 sq_ts_format[0x2]; 2006 u8 rq_ts_format[0x2]; 2007 u8 steering_format_version[0x4]; 2008 u8 create_qp_start_hint[0x18]; 2009 2010 u8 reserved_at_460[0x1]; 2011 u8 ats[0x1]; 2012 u8 cross_vhca_rqt[0x1]; 2013 u8 log_max_uctx[0x5]; 2014 u8 reserved_at_468[0x1]; 2015 u8 crypto[0x1]; 2016 u8 ipsec_offload[0x1]; 2017 u8 log_max_umem[0x5]; 2018 u8 max_num_eqs[0x10]; 2019 2020 u8 reserved_at_480[0x1]; 2021 u8 tls_tx[0x1]; 2022 u8 tls_rx[0x1]; 2023 u8 log_max_l2_table[0x5]; 2024 u8 reserved_at_488[0x8]; 2025 u8 log_uar_page_sz[0x10]; 2026 2027 u8 reserved_at_4a0[0x20]; 2028 u8 device_frequency_mhz[0x20]; 2029 u8 device_frequency_khz[0x20]; 2030 2031 u8 reserved_at_500[0x20]; 2032 u8 num_of_uars_per_page[0x20]; 2033 2034 u8 flex_parser_protocols[0x20]; 2035 2036 u8 max_geneve_tlv_options[0x8]; 2037 u8 reserved_at_568[0x3]; 2038 u8 max_geneve_tlv_option_data_len[0x5]; 2039 u8 reserved_at_570[0x1]; 2040 u8 adv_rdma[0x1]; 2041 u8 reserved_at_572[0x7]; 2042 u8 adv_virtualization[0x1]; 2043 u8 reserved_at_57a[0x6]; 2044 2045 u8 reserved_at_580[0xb]; 2046 u8 log_max_dci_stream_channels[0x5]; 2047 u8 reserved_at_590[0x3]; 2048 u8 log_max_dci_errored_streams[0x5]; 2049 u8 reserved_at_598[0x8]; 2050 2051 u8 reserved_at_5a0[0x10]; 2052 u8 enhanced_cqe_compression[0x1]; 2053 u8 reserved_at_5b1[0x1]; 2054 u8 crossing_vhca_mkey[0x1]; 2055 u8 log_max_dek[0x5]; 2056 u8 reserved_at_5b8[0x4]; 2057 u8 mini_cqe_resp_stride_index[0x1]; 2058 u8 cqe_128_always[0x1]; 2059 u8 cqe_compression_128[0x1]; 2060 u8 cqe_compression[0x1]; 2061 2062 u8 cqe_compression_timeout[0x10]; 2063 u8 cqe_compression_max_num[0x10]; 2064 2065 u8 reserved_at_5e0[0x8]; 2066 u8 flex_parser_id_gtpu_dw_0[0x4]; 2067 u8 reserved_at_5ec[0x4]; 2068 u8 tag_matching[0x1]; 2069 u8 rndv_offload_rc[0x1]; 2070 u8 rndv_offload_dc[0x1]; 2071 u8 log_tag_matching_list_sz[0x5]; 2072 u8 reserved_at_5f8[0x3]; 2073 u8 log_max_xrq[0x5]; 2074 2075 u8 affiliate_nic_vport_criteria[0x8]; 2076 u8 native_port_num[0x8]; 2077 u8 num_vhca_ports[0x8]; 2078 u8 flex_parser_id_gtpu_teid[0x4]; 2079 u8 reserved_at_61c[0x2]; 2080 u8 sw_owner_id[0x1]; 2081 u8 reserved_at_61f[0x1]; 2082 2083 u8 max_num_of_monitor_counters[0x10]; 2084 u8 num_ppcnt_monitor_counters[0x10]; 2085 2086 u8 max_num_sf[0x10]; 2087 u8 num_q_monitor_counters[0x10]; 2088 2089 u8 reserved_at_660[0x20]; 2090 2091 u8 sf[0x1]; 2092 u8 sf_set_partition[0x1]; 2093 u8 reserved_at_682[0x1]; 2094 u8 log_max_sf[0x5]; 2095 u8 apu[0x1]; 2096 u8 reserved_at_689[0x4]; 2097 u8 migration[0x1]; 2098 u8 reserved_at_68e[0x2]; 2099 u8 log_min_sf_size[0x8]; 2100 u8 max_num_sf_partitions[0x8]; 2101 2102 u8 uctx_cap[0x20]; 2103 2104 u8 reserved_at_6c0[0x4]; 2105 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 2106 u8 flex_parser_id_icmp_dw1[0x4]; 2107 u8 flex_parser_id_icmp_dw0[0x4]; 2108 u8 flex_parser_id_icmpv6_dw1[0x4]; 2109 u8 flex_parser_id_icmpv6_dw0[0x4]; 2110 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 2111 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 2112 2113 u8 max_num_match_definer[0x10]; 2114 u8 sf_base_id[0x10]; 2115 2116 u8 flex_parser_id_gtpu_dw_2[0x4]; 2117 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 2118 u8 num_total_dynamic_vf_msix[0x18]; 2119 u8 reserved_at_720[0x14]; 2120 u8 dynamic_msix_table_size[0xc]; 2121 u8 reserved_at_740[0xc]; 2122 u8 min_dynamic_vf_msix_table_size[0x4]; 2123 u8 reserved_at_750[0x2]; 2124 u8 data_direct[0x1]; 2125 u8 reserved_at_753[0x1]; 2126 u8 max_dynamic_vf_msix_table_size[0xc]; 2127 2128 u8 reserved_at_760[0x3]; 2129 u8 log_max_num_header_modify_argument[0x5]; 2130 u8 log_header_modify_argument_granularity_offset[0x4]; 2131 u8 log_header_modify_argument_granularity[0x4]; 2132 u8 reserved_at_770[0x3]; 2133 u8 log_header_modify_argument_max_alloc[0x5]; 2134 u8 reserved_at_778[0x8]; 2135 2136 u8 vhca_tunnel_commands[0x40]; 2137 u8 match_definer_format_supported[0x40]; 2138 }; 2139 2140 enum { 2141 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS = 0x80000, 2142 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE = (1ULL << 20), 2143 }; 2144 2145 enum { 2146 MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE = 0x200, 2147 }; 2148 2149 struct mlx5_ifc_cmd_hca_cap_2_bits { 2150 u8 reserved_at_0[0x80]; 2151 2152 u8 migratable[0x1]; 2153 u8 reserved_at_81[0x7]; 2154 u8 dp_ordering_force[0x1]; 2155 u8 reserved_at_89[0x9]; 2156 u8 query_vuid[0x1]; 2157 u8 reserved_at_93[0x5]; 2158 u8 umr_log_entity_size_5[0x1]; 2159 u8 reserved_at_99[0x7]; 2160 2161 u8 max_reformat_insert_size[0x8]; 2162 u8 max_reformat_insert_offset[0x8]; 2163 u8 max_reformat_remove_size[0x8]; 2164 u8 max_reformat_remove_offset[0x8]; 2165 2166 u8 reserved_at_c0[0x8]; 2167 u8 migration_multi_load[0x1]; 2168 u8 migration_tracking_state[0x1]; 2169 u8 multiplane_qp_ud[0x1]; 2170 u8 reserved_at_cb[0x5]; 2171 u8 migration_in_chunks[0x1]; 2172 u8 reserved_at_d1[0x1]; 2173 u8 sf_eq_usage[0x1]; 2174 u8 reserved_at_d3[0x5]; 2175 u8 multiplane[0x1]; 2176 u8 reserved_at_d9[0x7]; 2177 2178 u8 cross_vhca_object_to_object_supported[0x20]; 2179 2180 u8 allowed_object_for_other_vhca_access[0x40]; 2181 2182 u8 reserved_at_140[0x60]; 2183 2184 u8 flow_table_type_2_type[0x8]; 2185 u8 reserved_at_1a8[0x2]; 2186 u8 format_select_dw_8_6_ext[0x1]; 2187 u8 log_min_mkey_entity_size[0x5]; 2188 u8 reserved_at_1b0[0x10]; 2189 2190 u8 general_obj_types_127_64[0x40]; 2191 u8 reserved_at_200[0x20]; 2192 2193 u8 reserved_at_220[0x1]; 2194 u8 sw_vhca_id_valid[0x1]; 2195 u8 sw_vhca_id[0xe]; 2196 u8 reserved_at_230[0x10]; 2197 2198 u8 reserved_at_240[0xb]; 2199 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 2200 u8 reserved_at_250[0x10]; 2201 2202 u8 reserved_at_260[0x20]; 2203 2204 u8 format_select_dw_gtpu_dw_0[0x8]; 2205 u8 format_select_dw_gtpu_dw_1[0x8]; 2206 u8 format_select_dw_gtpu_dw_2[0x8]; 2207 u8 format_select_dw_gtpu_first_ext_dw_0[0x8]; 2208 2209 u8 generate_wqe_type[0x20]; 2210 2211 u8 reserved_at_2c0[0xc0]; 2212 2213 u8 reserved_at_380[0xb]; 2214 u8 min_mkey_log_entity_size_fixed_buffer[0x5]; 2215 u8 ec_vf_vport_base[0x10]; 2216 2217 u8 reserved_at_3a0[0x2]; 2218 u8 max_mkey_log_entity_size_fixed_buffer[0x6]; 2219 u8 reserved_at_3a8[0x2]; 2220 u8 max_mkey_log_entity_size_mtt[0x6]; 2221 u8 max_rqt_vhca_id[0x10]; 2222 2223 u8 reserved_at_3c0[0x20]; 2224 2225 u8 reserved_at_3e0[0x10]; 2226 u8 pcc_ifa2[0x1]; 2227 u8 reserved_at_3f1[0xf]; 2228 2229 u8 reserved_at_400[0x1]; 2230 u8 min_mkey_log_entity_size_fixed_buffer_valid[0x1]; 2231 u8 reserved_at_402[0xe]; 2232 u8 return_reg_id[0x10]; 2233 2234 u8 reserved_at_420[0x1c]; 2235 u8 flow_table_hash_type[0x4]; 2236 2237 u8 reserved_at_440[0x8]; 2238 u8 max_num_eqs_24b[0x18]; 2239 2240 u8 reserved_at_460[0x144]; 2241 u8 load_balance_id[0x4]; 2242 u8 reserved_at_5a8[0x18]; 2243 2244 u8 query_adjacent_functions_id[0x1]; 2245 u8 ingress_egress_esw_vport_connect[0x1]; 2246 u8 function_id_type_vhca_id[0x1]; 2247 u8 reserved_at_5c3[0x1]; 2248 u8 lag_per_mp_group[0x1]; 2249 u8 reserved_at_5c5[0xb]; 2250 u8 delegate_vhca_management_profiles[0x10]; 2251 2252 u8 delegated_vhca_max[0x10]; 2253 u8 delegate_vhca_max[0x10]; 2254 2255 u8 reserved_at_600[0x200]; 2256 }; 2257 2258 enum mlx5_ifc_flow_destination_type { 2259 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 2260 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 2261 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 2262 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 2263 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 2264 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 2265 }; 2266 2267 enum mlx5_flow_table_miss_action { 2268 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 2269 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 2270 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 2271 }; 2272 2273 struct mlx5_ifc_dest_format_struct_bits { 2274 u8 destination_type[0x8]; 2275 u8 destination_id[0x18]; 2276 2277 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 2278 u8 packet_reformat[0x1]; 2279 u8 reserved_at_22[0x6]; 2280 u8 destination_table_type[0x8]; 2281 u8 destination_eswitch_owner_vhca_id[0x10]; 2282 }; 2283 2284 struct mlx5_ifc_flow_counter_list_bits { 2285 u8 flow_counter_id[0x20]; 2286 2287 u8 reserved_at_20[0x20]; 2288 }; 2289 2290 struct mlx5_ifc_extended_dest_format_bits { 2291 struct mlx5_ifc_dest_format_struct_bits destination_entry; 2292 2293 u8 packet_reformat_id[0x20]; 2294 2295 u8 reserved_at_60[0x20]; 2296 }; 2297 2298 union mlx5_ifc_dest_format_flow_counter_list_auto_bits { 2299 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 2300 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 2301 }; 2302 2303 struct mlx5_ifc_fte_match_param_bits { 2304 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2305 2306 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2307 2308 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2309 2310 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2311 2312 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2313 2314 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2315 2316 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2317 2318 u8 reserved_at_e00[0x200]; 2319 }; 2320 2321 enum { 2322 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2323 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2324 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2325 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2326 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2327 }; 2328 2329 struct mlx5_ifc_rx_hash_field_select_bits { 2330 u8 l3_prot_type[0x1]; 2331 u8 l4_prot_type[0x1]; 2332 u8 selected_fields[0x1e]; 2333 }; 2334 2335 enum { 2336 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2337 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2338 }; 2339 2340 enum { 2341 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2342 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2343 }; 2344 2345 struct mlx5_ifc_wq_bits { 2346 u8 wq_type[0x4]; 2347 u8 wq_signature[0x1]; 2348 u8 end_padding_mode[0x2]; 2349 u8 cd_slave[0x1]; 2350 u8 reserved_at_8[0x18]; 2351 2352 u8 hds_skip_first_sge[0x1]; 2353 u8 log2_hds_buf_size[0x3]; 2354 u8 reserved_at_24[0x7]; 2355 u8 page_offset[0x5]; 2356 u8 lwm[0x10]; 2357 2358 u8 reserved_at_40[0x8]; 2359 u8 pd[0x18]; 2360 2361 u8 reserved_at_60[0x8]; 2362 u8 uar_page[0x18]; 2363 2364 u8 dbr_addr[0x40]; 2365 2366 u8 hw_counter[0x20]; 2367 2368 u8 sw_counter[0x20]; 2369 2370 u8 reserved_at_100[0xc]; 2371 u8 log_wq_stride[0x4]; 2372 u8 reserved_at_110[0x3]; 2373 u8 log_wq_pg_sz[0x5]; 2374 u8 reserved_at_118[0x3]; 2375 u8 log_wq_sz[0x5]; 2376 2377 u8 dbr_umem_valid[0x1]; 2378 u8 wq_umem_valid[0x1]; 2379 u8 reserved_at_122[0x1]; 2380 u8 log_hairpin_num_packets[0x5]; 2381 u8 reserved_at_128[0x3]; 2382 u8 log_hairpin_data_sz[0x5]; 2383 2384 u8 reserved_at_130[0x4]; 2385 u8 log_wqe_num_of_strides[0x4]; 2386 u8 two_byte_shift_en[0x1]; 2387 u8 reserved_at_139[0x4]; 2388 u8 log_wqe_stride_size[0x3]; 2389 2390 u8 dbr_umem_id[0x20]; 2391 u8 wq_umem_id[0x20]; 2392 2393 u8 wq_umem_offset[0x40]; 2394 2395 u8 headers_mkey[0x20]; 2396 2397 u8 shampo_enable[0x1]; 2398 u8 reserved_at_1e1[0x1]; 2399 u8 shampo_mode[0x2]; 2400 u8 reserved_at_1e4[0x1]; 2401 u8 log_reservation_size[0x3]; 2402 u8 reserved_at_1e8[0x5]; 2403 u8 log_max_num_of_packets_per_reservation[0x3]; 2404 u8 reserved_at_1f0[0x6]; 2405 u8 log_headers_entry_size[0x2]; 2406 u8 reserved_at_1f8[0x4]; 2407 u8 log_headers_buffer_entry_num[0x4]; 2408 2409 u8 reserved_at_200[0x400]; 2410 2411 struct mlx5_ifc_cmd_pas_bits pas[]; 2412 }; 2413 2414 struct mlx5_ifc_rq_num_bits { 2415 u8 reserved_at_0[0x8]; 2416 u8 rq_num[0x18]; 2417 }; 2418 2419 struct mlx5_ifc_rq_vhca_bits { 2420 u8 reserved_at_0[0x8]; 2421 u8 rq_num[0x18]; 2422 u8 reserved_at_20[0x10]; 2423 u8 rq_vhca_id[0x10]; 2424 }; 2425 2426 struct mlx5_ifc_mac_address_layout_bits { 2427 u8 reserved_at_0[0x10]; 2428 u8 mac_addr_47_32[0x10]; 2429 2430 u8 mac_addr_31_0[0x20]; 2431 }; 2432 2433 struct mlx5_ifc_vlan_layout_bits { 2434 u8 reserved_at_0[0x14]; 2435 u8 vlan[0x0c]; 2436 2437 u8 reserved_at_20[0x20]; 2438 }; 2439 2440 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2441 u8 reserved_at_0[0xa0]; 2442 2443 u8 min_time_between_cnps[0x20]; 2444 2445 u8 reserved_at_c0[0x12]; 2446 u8 cnp_dscp[0x6]; 2447 u8 reserved_at_d8[0x4]; 2448 u8 cnp_prio_mode[0x1]; 2449 u8 cnp_802p_prio[0x3]; 2450 2451 u8 reserved_at_e0[0x720]; 2452 }; 2453 2454 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2455 u8 reserved_at_0[0x60]; 2456 2457 u8 reserved_at_60[0x4]; 2458 u8 clamp_tgt_rate[0x1]; 2459 u8 reserved_at_65[0x3]; 2460 u8 clamp_tgt_rate_after_time_inc[0x1]; 2461 u8 reserved_at_69[0x17]; 2462 2463 u8 reserved_at_80[0x20]; 2464 2465 u8 rpg_time_reset[0x20]; 2466 2467 u8 rpg_byte_reset[0x20]; 2468 2469 u8 rpg_threshold[0x20]; 2470 2471 u8 rpg_max_rate[0x20]; 2472 2473 u8 rpg_ai_rate[0x20]; 2474 2475 u8 rpg_hai_rate[0x20]; 2476 2477 u8 rpg_gd[0x20]; 2478 2479 u8 rpg_min_dec_fac[0x20]; 2480 2481 u8 rpg_min_rate[0x20]; 2482 2483 u8 reserved_at_1c0[0xe0]; 2484 2485 u8 rate_to_set_on_first_cnp[0x20]; 2486 2487 u8 dce_tcp_g[0x20]; 2488 2489 u8 dce_tcp_rtt[0x20]; 2490 2491 u8 rate_reduce_monitor_period[0x20]; 2492 2493 u8 reserved_at_320[0x20]; 2494 2495 u8 initial_alpha_value[0x20]; 2496 2497 u8 reserved_at_360[0x4a0]; 2498 }; 2499 2500 struct mlx5_ifc_cong_control_r_roce_general_bits { 2501 u8 reserved_at_0[0x80]; 2502 2503 u8 reserved_at_80[0x10]; 2504 u8 rtt_resp_dscp_valid[0x1]; 2505 u8 reserved_at_91[0x9]; 2506 u8 rtt_resp_dscp[0x6]; 2507 2508 u8 reserved_at_a0[0x760]; 2509 }; 2510 2511 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2512 u8 reserved_at_0[0x80]; 2513 2514 u8 rppp_max_rps[0x20]; 2515 2516 u8 rpg_time_reset[0x20]; 2517 2518 u8 rpg_byte_reset[0x20]; 2519 2520 u8 rpg_threshold[0x20]; 2521 2522 u8 rpg_max_rate[0x20]; 2523 2524 u8 rpg_ai_rate[0x20]; 2525 2526 u8 rpg_hai_rate[0x20]; 2527 2528 u8 rpg_gd[0x20]; 2529 2530 u8 rpg_min_dec_fac[0x20]; 2531 2532 u8 rpg_min_rate[0x20]; 2533 2534 u8 reserved_at_1c0[0x640]; 2535 }; 2536 2537 enum { 2538 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2539 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2540 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2541 }; 2542 2543 struct mlx5_ifc_resize_field_select_bits { 2544 u8 resize_field_select[0x20]; 2545 }; 2546 2547 struct mlx5_ifc_resource_dump_bits { 2548 u8 more_dump[0x1]; 2549 u8 inline_dump[0x1]; 2550 u8 reserved_at_2[0xa]; 2551 u8 seq_num[0x4]; 2552 u8 segment_type[0x10]; 2553 2554 u8 reserved_at_20[0x10]; 2555 u8 vhca_id[0x10]; 2556 2557 u8 index1[0x20]; 2558 2559 u8 index2[0x20]; 2560 2561 u8 num_of_obj1[0x10]; 2562 u8 num_of_obj2[0x10]; 2563 2564 u8 reserved_at_a0[0x20]; 2565 2566 u8 device_opaque[0x40]; 2567 2568 u8 mkey[0x20]; 2569 2570 u8 size[0x20]; 2571 2572 u8 address[0x40]; 2573 2574 u8 inline_data[52][0x20]; 2575 }; 2576 2577 struct mlx5_ifc_resource_dump_menu_record_bits { 2578 u8 reserved_at_0[0x4]; 2579 u8 num_of_obj2_supports_active[0x1]; 2580 u8 num_of_obj2_supports_all[0x1]; 2581 u8 must_have_num_of_obj2[0x1]; 2582 u8 support_num_of_obj2[0x1]; 2583 u8 num_of_obj1_supports_active[0x1]; 2584 u8 num_of_obj1_supports_all[0x1]; 2585 u8 must_have_num_of_obj1[0x1]; 2586 u8 support_num_of_obj1[0x1]; 2587 u8 must_have_index2[0x1]; 2588 u8 support_index2[0x1]; 2589 u8 must_have_index1[0x1]; 2590 u8 support_index1[0x1]; 2591 u8 segment_type[0x10]; 2592 2593 u8 segment_name[4][0x20]; 2594 2595 u8 index1_name[4][0x20]; 2596 2597 u8 index2_name[4][0x20]; 2598 }; 2599 2600 struct mlx5_ifc_resource_dump_segment_header_bits { 2601 u8 length_dw[0x10]; 2602 u8 segment_type[0x10]; 2603 }; 2604 2605 struct mlx5_ifc_resource_dump_command_segment_bits { 2606 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2607 2608 u8 segment_called[0x10]; 2609 u8 vhca_id[0x10]; 2610 2611 u8 index1[0x20]; 2612 2613 u8 index2[0x20]; 2614 2615 u8 num_of_obj1[0x10]; 2616 u8 num_of_obj2[0x10]; 2617 }; 2618 2619 struct mlx5_ifc_resource_dump_error_segment_bits { 2620 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2621 2622 u8 reserved_at_20[0x10]; 2623 u8 syndrome_id[0x10]; 2624 2625 u8 reserved_at_40[0x40]; 2626 2627 u8 error[8][0x20]; 2628 }; 2629 2630 struct mlx5_ifc_resource_dump_info_segment_bits { 2631 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2632 2633 u8 reserved_at_20[0x18]; 2634 u8 dump_version[0x8]; 2635 2636 u8 hw_version[0x20]; 2637 2638 u8 fw_version[0x20]; 2639 }; 2640 2641 struct mlx5_ifc_resource_dump_menu_segment_bits { 2642 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2643 2644 u8 reserved_at_20[0x10]; 2645 u8 num_of_records[0x10]; 2646 2647 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2648 }; 2649 2650 struct mlx5_ifc_resource_dump_resource_segment_bits { 2651 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2652 2653 u8 reserved_at_20[0x20]; 2654 2655 u8 index1[0x20]; 2656 2657 u8 index2[0x20]; 2658 2659 u8 payload[][0x20]; 2660 }; 2661 2662 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2663 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2664 }; 2665 2666 struct mlx5_ifc_menu_resource_dump_response_bits { 2667 struct mlx5_ifc_resource_dump_info_segment_bits info; 2668 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2669 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2670 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2671 }; 2672 2673 enum { 2674 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2675 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2676 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2677 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2678 }; 2679 2680 struct mlx5_ifc_modify_field_select_bits { 2681 u8 modify_field_select[0x20]; 2682 }; 2683 2684 struct mlx5_ifc_field_select_r_roce_np_bits { 2685 u8 field_select_r_roce_np[0x20]; 2686 }; 2687 2688 struct mlx5_ifc_field_select_r_roce_rp_bits { 2689 u8 field_select_r_roce_rp[0x20]; 2690 }; 2691 2692 enum { 2693 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2694 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2695 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2696 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2697 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2698 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2699 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2700 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2701 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2702 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2703 }; 2704 2705 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2706 u8 field_select_8021qaurp[0x20]; 2707 }; 2708 2709 struct mlx5_ifc_phys_layer_recovery_cntrs_bits { 2710 u8 total_successful_recovery_events[0x20]; 2711 2712 u8 reserved_at_20[0x7a0]; 2713 }; 2714 2715 struct mlx5_ifc_phys_layer_cntrs_bits { 2716 u8 time_since_last_clear_high[0x20]; 2717 2718 u8 time_since_last_clear_low[0x20]; 2719 2720 u8 symbol_errors_high[0x20]; 2721 2722 u8 symbol_errors_low[0x20]; 2723 2724 u8 sync_headers_errors_high[0x20]; 2725 2726 u8 sync_headers_errors_low[0x20]; 2727 2728 u8 edpl_bip_errors_lane0_high[0x20]; 2729 2730 u8 edpl_bip_errors_lane0_low[0x20]; 2731 2732 u8 edpl_bip_errors_lane1_high[0x20]; 2733 2734 u8 edpl_bip_errors_lane1_low[0x20]; 2735 2736 u8 edpl_bip_errors_lane2_high[0x20]; 2737 2738 u8 edpl_bip_errors_lane2_low[0x20]; 2739 2740 u8 edpl_bip_errors_lane3_high[0x20]; 2741 2742 u8 edpl_bip_errors_lane3_low[0x20]; 2743 2744 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2745 2746 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2747 2748 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2749 2750 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2751 2752 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2753 2754 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2755 2756 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2757 2758 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2759 2760 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2761 2762 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2763 2764 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2765 2766 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2767 2768 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2769 2770 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2771 2772 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2773 2774 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2775 2776 u8 rs_fec_corrected_blocks_high[0x20]; 2777 2778 u8 rs_fec_corrected_blocks_low[0x20]; 2779 2780 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2781 2782 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2783 2784 u8 rs_fec_no_errors_blocks_high[0x20]; 2785 2786 u8 rs_fec_no_errors_blocks_low[0x20]; 2787 2788 u8 rs_fec_single_error_blocks_high[0x20]; 2789 2790 u8 rs_fec_single_error_blocks_low[0x20]; 2791 2792 u8 rs_fec_corrected_symbols_total_high[0x20]; 2793 2794 u8 rs_fec_corrected_symbols_total_low[0x20]; 2795 2796 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2797 2798 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2799 2800 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2801 2802 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2803 2804 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2805 2806 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2807 2808 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2809 2810 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2811 2812 u8 link_down_events[0x20]; 2813 2814 u8 successful_recovery_events[0x20]; 2815 2816 u8 reserved_at_640[0x180]; 2817 }; 2818 2819 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2820 u8 time_since_last_clear_high[0x20]; 2821 2822 u8 time_since_last_clear_low[0x20]; 2823 2824 u8 phy_received_bits_high[0x20]; 2825 2826 u8 phy_received_bits_low[0x20]; 2827 2828 u8 phy_symbol_errors_high[0x20]; 2829 2830 u8 phy_symbol_errors_low[0x20]; 2831 2832 u8 phy_corrected_bits_high[0x20]; 2833 2834 u8 phy_corrected_bits_low[0x20]; 2835 2836 u8 phy_corrected_bits_lane0_high[0x20]; 2837 2838 u8 phy_corrected_bits_lane0_low[0x20]; 2839 2840 u8 phy_corrected_bits_lane1_high[0x20]; 2841 2842 u8 phy_corrected_bits_lane1_low[0x20]; 2843 2844 u8 phy_corrected_bits_lane2_high[0x20]; 2845 2846 u8 phy_corrected_bits_lane2_low[0x20]; 2847 2848 u8 phy_corrected_bits_lane3_high[0x20]; 2849 2850 u8 phy_corrected_bits_lane3_low[0x20]; 2851 2852 u8 reserved_at_200[0x5c0]; 2853 }; 2854 2855 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2856 u8 symbol_error_counter[0x10]; 2857 2858 u8 link_error_recovery_counter[0x8]; 2859 2860 u8 link_downed_counter[0x8]; 2861 2862 u8 port_rcv_errors[0x10]; 2863 2864 u8 port_rcv_remote_physical_errors[0x10]; 2865 2866 u8 port_rcv_switch_relay_errors[0x10]; 2867 2868 u8 port_xmit_discards[0x10]; 2869 2870 u8 port_xmit_constraint_errors[0x8]; 2871 2872 u8 port_rcv_constraint_errors[0x8]; 2873 2874 u8 reserved_at_70[0x8]; 2875 2876 u8 link_overrun_errors[0x8]; 2877 2878 u8 reserved_at_80[0x10]; 2879 2880 u8 vl_15_dropped[0x10]; 2881 2882 u8 reserved_at_a0[0x80]; 2883 2884 u8 port_xmit_wait[0x20]; 2885 }; 2886 2887 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits { 2888 u8 reserved_at_0[0x300]; 2889 2890 u8 port_xmit_data_high[0x20]; 2891 2892 u8 port_xmit_data_low[0x20]; 2893 2894 u8 port_rcv_data_high[0x20]; 2895 2896 u8 port_rcv_data_low[0x20]; 2897 2898 u8 port_xmit_pkts_high[0x20]; 2899 2900 u8 port_xmit_pkts_low[0x20]; 2901 2902 u8 port_rcv_pkts_high[0x20]; 2903 2904 u8 port_rcv_pkts_low[0x20]; 2905 2906 u8 reserved_at_400[0x80]; 2907 2908 u8 port_unicast_xmit_pkts_high[0x20]; 2909 2910 u8 port_unicast_xmit_pkts_low[0x20]; 2911 2912 u8 port_multicast_xmit_pkts_high[0x20]; 2913 2914 u8 port_multicast_xmit_pkts_low[0x20]; 2915 2916 u8 port_unicast_rcv_pkts_high[0x20]; 2917 2918 u8 port_unicast_rcv_pkts_low[0x20]; 2919 2920 u8 port_multicast_rcv_pkts_high[0x20]; 2921 2922 u8 port_multicast_rcv_pkts_low[0x20]; 2923 2924 u8 reserved_at_580[0x240]; 2925 }; 2926 2927 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2928 u8 transmit_queue_high[0x20]; 2929 2930 u8 transmit_queue_low[0x20]; 2931 2932 u8 no_buffer_discard_uc_high[0x20]; 2933 2934 u8 no_buffer_discard_uc_low[0x20]; 2935 2936 u8 reserved_at_80[0x740]; 2937 }; 2938 2939 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2940 u8 wred_discard_high[0x20]; 2941 2942 u8 wred_discard_low[0x20]; 2943 2944 u8 ecn_marked_tc_high[0x20]; 2945 2946 u8 ecn_marked_tc_low[0x20]; 2947 2948 u8 reserved_at_80[0x740]; 2949 }; 2950 2951 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2952 u8 rx_octets_high[0x20]; 2953 2954 u8 rx_octets_low[0x20]; 2955 2956 u8 reserved_at_40[0xc0]; 2957 2958 u8 rx_frames_high[0x20]; 2959 2960 u8 rx_frames_low[0x20]; 2961 2962 u8 tx_octets_high[0x20]; 2963 2964 u8 tx_octets_low[0x20]; 2965 2966 u8 reserved_at_180[0xc0]; 2967 2968 u8 tx_frames_high[0x20]; 2969 2970 u8 tx_frames_low[0x20]; 2971 2972 u8 rx_pause_high[0x20]; 2973 2974 u8 rx_pause_low[0x20]; 2975 2976 u8 rx_pause_duration_high[0x20]; 2977 2978 u8 rx_pause_duration_low[0x20]; 2979 2980 u8 tx_pause_high[0x20]; 2981 2982 u8 tx_pause_low[0x20]; 2983 2984 u8 tx_pause_duration_high[0x20]; 2985 2986 u8 tx_pause_duration_low[0x20]; 2987 2988 u8 rx_pause_transition_high[0x20]; 2989 2990 u8 rx_pause_transition_low[0x20]; 2991 2992 u8 rx_discards_high[0x20]; 2993 2994 u8 rx_discards_low[0x20]; 2995 2996 u8 device_stall_minor_watermark_cnt_high[0x20]; 2997 2998 u8 device_stall_minor_watermark_cnt_low[0x20]; 2999 3000 u8 device_stall_critical_watermark_cnt_high[0x20]; 3001 3002 u8 device_stall_critical_watermark_cnt_low[0x20]; 3003 3004 u8 reserved_at_480[0x340]; 3005 }; 3006 3007 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 3008 u8 port_transmit_wait_high[0x20]; 3009 3010 u8 port_transmit_wait_low[0x20]; 3011 3012 u8 reserved_at_40[0x100]; 3013 3014 u8 rx_buffer_almost_full_high[0x20]; 3015 3016 u8 rx_buffer_almost_full_low[0x20]; 3017 3018 u8 rx_buffer_full_high[0x20]; 3019 3020 u8 rx_buffer_full_low[0x20]; 3021 3022 u8 rx_icrc_encapsulated_high[0x20]; 3023 3024 u8 rx_icrc_encapsulated_low[0x20]; 3025 3026 u8 reserved_at_200[0x5c0]; 3027 }; 3028 3029 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 3030 u8 dot3stats_alignment_errors_high[0x20]; 3031 3032 u8 dot3stats_alignment_errors_low[0x20]; 3033 3034 u8 dot3stats_fcs_errors_high[0x20]; 3035 3036 u8 dot3stats_fcs_errors_low[0x20]; 3037 3038 u8 dot3stats_single_collision_frames_high[0x20]; 3039 3040 u8 dot3stats_single_collision_frames_low[0x20]; 3041 3042 u8 dot3stats_multiple_collision_frames_high[0x20]; 3043 3044 u8 dot3stats_multiple_collision_frames_low[0x20]; 3045 3046 u8 dot3stats_sqe_test_errors_high[0x20]; 3047 3048 u8 dot3stats_sqe_test_errors_low[0x20]; 3049 3050 u8 dot3stats_deferred_transmissions_high[0x20]; 3051 3052 u8 dot3stats_deferred_transmissions_low[0x20]; 3053 3054 u8 dot3stats_late_collisions_high[0x20]; 3055 3056 u8 dot3stats_late_collisions_low[0x20]; 3057 3058 u8 dot3stats_excessive_collisions_high[0x20]; 3059 3060 u8 dot3stats_excessive_collisions_low[0x20]; 3061 3062 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 3063 3064 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 3065 3066 u8 dot3stats_carrier_sense_errors_high[0x20]; 3067 3068 u8 dot3stats_carrier_sense_errors_low[0x20]; 3069 3070 u8 dot3stats_frame_too_longs_high[0x20]; 3071 3072 u8 dot3stats_frame_too_longs_low[0x20]; 3073 3074 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 3075 3076 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 3077 3078 u8 dot3stats_symbol_errors_high[0x20]; 3079 3080 u8 dot3stats_symbol_errors_low[0x20]; 3081 3082 u8 dot3control_in_unknown_opcodes_high[0x20]; 3083 3084 u8 dot3control_in_unknown_opcodes_low[0x20]; 3085 3086 u8 dot3in_pause_frames_high[0x20]; 3087 3088 u8 dot3in_pause_frames_low[0x20]; 3089 3090 u8 dot3out_pause_frames_high[0x20]; 3091 3092 u8 dot3out_pause_frames_low[0x20]; 3093 3094 u8 reserved_at_400[0x3c0]; 3095 }; 3096 3097 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 3098 u8 ether_stats_drop_events_high[0x20]; 3099 3100 u8 ether_stats_drop_events_low[0x20]; 3101 3102 u8 ether_stats_octets_high[0x20]; 3103 3104 u8 ether_stats_octets_low[0x20]; 3105 3106 u8 ether_stats_pkts_high[0x20]; 3107 3108 u8 ether_stats_pkts_low[0x20]; 3109 3110 u8 ether_stats_broadcast_pkts_high[0x20]; 3111 3112 u8 ether_stats_broadcast_pkts_low[0x20]; 3113 3114 u8 ether_stats_multicast_pkts_high[0x20]; 3115 3116 u8 ether_stats_multicast_pkts_low[0x20]; 3117 3118 u8 ether_stats_crc_align_errors_high[0x20]; 3119 3120 u8 ether_stats_crc_align_errors_low[0x20]; 3121 3122 u8 ether_stats_undersize_pkts_high[0x20]; 3123 3124 u8 ether_stats_undersize_pkts_low[0x20]; 3125 3126 u8 ether_stats_oversize_pkts_high[0x20]; 3127 3128 u8 ether_stats_oversize_pkts_low[0x20]; 3129 3130 u8 ether_stats_fragments_high[0x20]; 3131 3132 u8 ether_stats_fragments_low[0x20]; 3133 3134 u8 ether_stats_jabbers_high[0x20]; 3135 3136 u8 ether_stats_jabbers_low[0x20]; 3137 3138 u8 ether_stats_collisions_high[0x20]; 3139 3140 u8 ether_stats_collisions_low[0x20]; 3141 3142 u8 ether_stats_pkts64octets_high[0x20]; 3143 3144 u8 ether_stats_pkts64octets_low[0x20]; 3145 3146 u8 ether_stats_pkts65to127octets_high[0x20]; 3147 3148 u8 ether_stats_pkts65to127octets_low[0x20]; 3149 3150 u8 ether_stats_pkts128to255octets_high[0x20]; 3151 3152 u8 ether_stats_pkts128to255octets_low[0x20]; 3153 3154 u8 ether_stats_pkts256to511octets_high[0x20]; 3155 3156 u8 ether_stats_pkts256to511octets_low[0x20]; 3157 3158 u8 ether_stats_pkts512to1023octets_high[0x20]; 3159 3160 u8 ether_stats_pkts512to1023octets_low[0x20]; 3161 3162 u8 ether_stats_pkts1024to1518octets_high[0x20]; 3163 3164 u8 ether_stats_pkts1024to1518octets_low[0x20]; 3165 3166 u8 ether_stats_pkts1519to2047octets_high[0x20]; 3167 3168 u8 ether_stats_pkts1519to2047octets_low[0x20]; 3169 3170 u8 ether_stats_pkts2048to4095octets_high[0x20]; 3171 3172 u8 ether_stats_pkts2048to4095octets_low[0x20]; 3173 3174 u8 ether_stats_pkts4096to8191octets_high[0x20]; 3175 3176 u8 ether_stats_pkts4096to8191octets_low[0x20]; 3177 3178 u8 ether_stats_pkts8192to10239octets_high[0x20]; 3179 3180 u8 ether_stats_pkts8192to10239octets_low[0x20]; 3181 3182 u8 reserved_at_540[0x280]; 3183 }; 3184 3185 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 3186 u8 if_in_octets_high[0x20]; 3187 3188 u8 if_in_octets_low[0x20]; 3189 3190 u8 if_in_ucast_pkts_high[0x20]; 3191 3192 u8 if_in_ucast_pkts_low[0x20]; 3193 3194 u8 if_in_discards_high[0x20]; 3195 3196 u8 if_in_discards_low[0x20]; 3197 3198 u8 if_in_errors_high[0x20]; 3199 3200 u8 if_in_errors_low[0x20]; 3201 3202 u8 if_in_unknown_protos_high[0x20]; 3203 3204 u8 if_in_unknown_protos_low[0x20]; 3205 3206 u8 if_out_octets_high[0x20]; 3207 3208 u8 if_out_octets_low[0x20]; 3209 3210 u8 if_out_ucast_pkts_high[0x20]; 3211 3212 u8 if_out_ucast_pkts_low[0x20]; 3213 3214 u8 if_out_discards_high[0x20]; 3215 3216 u8 if_out_discards_low[0x20]; 3217 3218 u8 if_out_errors_high[0x20]; 3219 3220 u8 if_out_errors_low[0x20]; 3221 3222 u8 if_in_multicast_pkts_high[0x20]; 3223 3224 u8 if_in_multicast_pkts_low[0x20]; 3225 3226 u8 if_in_broadcast_pkts_high[0x20]; 3227 3228 u8 if_in_broadcast_pkts_low[0x20]; 3229 3230 u8 if_out_multicast_pkts_high[0x20]; 3231 3232 u8 if_out_multicast_pkts_low[0x20]; 3233 3234 u8 if_out_broadcast_pkts_high[0x20]; 3235 3236 u8 if_out_broadcast_pkts_low[0x20]; 3237 3238 u8 reserved_at_340[0x480]; 3239 }; 3240 3241 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 3242 u8 a_frames_transmitted_ok_high[0x20]; 3243 3244 u8 a_frames_transmitted_ok_low[0x20]; 3245 3246 u8 a_frames_received_ok_high[0x20]; 3247 3248 u8 a_frames_received_ok_low[0x20]; 3249 3250 u8 a_frame_check_sequence_errors_high[0x20]; 3251 3252 u8 a_frame_check_sequence_errors_low[0x20]; 3253 3254 u8 a_alignment_errors_high[0x20]; 3255 3256 u8 a_alignment_errors_low[0x20]; 3257 3258 u8 a_octets_transmitted_ok_high[0x20]; 3259 3260 u8 a_octets_transmitted_ok_low[0x20]; 3261 3262 u8 a_octets_received_ok_high[0x20]; 3263 3264 u8 a_octets_received_ok_low[0x20]; 3265 3266 u8 a_multicast_frames_xmitted_ok_high[0x20]; 3267 3268 u8 a_multicast_frames_xmitted_ok_low[0x20]; 3269 3270 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 3271 3272 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 3273 3274 u8 a_multicast_frames_received_ok_high[0x20]; 3275 3276 u8 a_multicast_frames_received_ok_low[0x20]; 3277 3278 u8 a_broadcast_frames_received_ok_high[0x20]; 3279 3280 u8 a_broadcast_frames_received_ok_low[0x20]; 3281 3282 u8 a_in_range_length_errors_high[0x20]; 3283 3284 u8 a_in_range_length_errors_low[0x20]; 3285 3286 u8 a_out_of_range_length_field_high[0x20]; 3287 3288 u8 a_out_of_range_length_field_low[0x20]; 3289 3290 u8 a_frame_too_long_errors_high[0x20]; 3291 3292 u8 a_frame_too_long_errors_low[0x20]; 3293 3294 u8 a_symbol_error_during_carrier_high[0x20]; 3295 3296 u8 a_symbol_error_during_carrier_low[0x20]; 3297 3298 u8 a_mac_control_frames_transmitted_high[0x20]; 3299 3300 u8 a_mac_control_frames_transmitted_low[0x20]; 3301 3302 u8 a_mac_control_frames_received_high[0x20]; 3303 3304 u8 a_mac_control_frames_received_low[0x20]; 3305 3306 u8 a_unsupported_opcodes_received_high[0x20]; 3307 3308 u8 a_unsupported_opcodes_received_low[0x20]; 3309 3310 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 3311 3312 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 3313 3314 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 3315 3316 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 3317 3318 u8 reserved_at_4c0[0x300]; 3319 }; 3320 3321 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 3322 u8 life_time_counter_high[0x20]; 3323 3324 u8 life_time_counter_low[0x20]; 3325 3326 u8 rx_errors[0x20]; 3327 3328 u8 tx_errors[0x20]; 3329 3330 u8 l0_to_recovery_eieos[0x20]; 3331 3332 u8 l0_to_recovery_ts[0x20]; 3333 3334 u8 l0_to_recovery_framing[0x20]; 3335 3336 u8 l0_to_recovery_retrain[0x20]; 3337 3338 u8 crc_error_dllp[0x20]; 3339 3340 u8 crc_error_tlp[0x20]; 3341 3342 u8 tx_overflow_buffer_pkt_high[0x20]; 3343 3344 u8 tx_overflow_buffer_pkt_low[0x20]; 3345 3346 u8 outbound_stalled_reads[0x20]; 3347 3348 u8 outbound_stalled_writes[0x20]; 3349 3350 u8 outbound_stalled_reads_events[0x20]; 3351 3352 u8 outbound_stalled_writes_events[0x20]; 3353 3354 u8 reserved_at_200[0x5c0]; 3355 }; 3356 3357 struct mlx5_ifc_cmd_inter_comp_event_bits { 3358 u8 command_completion_vector[0x20]; 3359 3360 u8 reserved_at_20[0xc0]; 3361 }; 3362 3363 struct mlx5_ifc_stall_vl_event_bits { 3364 u8 reserved_at_0[0x18]; 3365 u8 port_num[0x1]; 3366 u8 reserved_at_19[0x3]; 3367 u8 vl[0x4]; 3368 3369 u8 reserved_at_20[0xa0]; 3370 }; 3371 3372 struct mlx5_ifc_db_bf_congestion_event_bits { 3373 u8 event_subtype[0x8]; 3374 u8 reserved_at_8[0x8]; 3375 u8 congestion_level[0x8]; 3376 u8 reserved_at_18[0x8]; 3377 3378 u8 reserved_at_20[0xa0]; 3379 }; 3380 3381 struct mlx5_ifc_gpio_event_bits { 3382 u8 reserved_at_0[0x60]; 3383 3384 u8 gpio_event_hi[0x20]; 3385 3386 u8 gpio_event_lo[0x20]; 3387 3388 u8 reserved_at_a0[0x40]; 3389 }; 3390 3391 struct mlx5_ifc_port_state_change_event_bits { 3392 u8 reserved_at_0[0x40]; 3393 3394 u8 port_num[0x4]; 3395 u8 reserved_at_44[0x1c]; 3396 3397 u8 reserved_at_60[0x80]; 3398 }; 3399 3400 struct mlx5_ifc_dropped_packet_logged_bits { 3401 u8 reserved_at_0[0xe0]; 3402 }; 3403 3404 struct mlx5_ifc_nic_cap_reg_bits { 3405 u8 reserved_at_0[0x1a]; 3406 u8 vhca_icm_ctrl[0x1]; 3407 u8 reserved_at_1b[0x5]; 3408 3409 u8 reserved_at_20[0x60]; 3410 }; 3411 3412 struct mlx5_ifc_default_timeout_bits { 3413 u8 to_multiplier[0x3]; 3414 u8 reserved_at_3[0x9]; 3415 u8 to_value[0x14]; 3416 }; 3417 3418 struct mlx5_ifc_dtor_reg_bits { 3419 u8 reserved_at_0[0x20]; 3420 3421 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3422 3423 u8 reserved_at_40[0x60]; 3424 3425 struct mlx5_ifc_default_timeout_bits health_poll_to; 3426 3427 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3428 3429 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3430 3431 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3432 3433 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3434 3435 struct mlx5_ifc_default_timeout_bits tear_down_to; 3436 3437 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3438 3439 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3440 3441 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3442 3443 struct mlx5_ifc_default_timeout_bits reset_unload_to; 3444 3445 u8 reserved_at_1c0[0x20]; 3446 }; 3447 3448 struct mlx5_ifc_vhca_icm_ctrl_reg_bits { 3449 u8 vhca_id_valid[0x1]; 3450 u8 reserved_at_1[0xf]; 3451 u8 vhca_id[0x10]; 3452 3453 u8 reserved_at_20[0xa0]; 3454 3455 u8 cur_alloc_icm[0x20]; 3456 3457 u8 reserved_at_e0[0x120]; 3458 }; 3459 3460 enum { 3461 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3462 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3463 }; 3464 3465 struct mlx5_ifc_cq_error_bits { 3466 u8 reserved_at_0[0x8]; 3467 u8 cqn[0x18]; 3468 3469 u8 reserved_at_20[0x20]; 3470 3471 u8 reserved_at_40[0x18]; 3472 u8 syndrome[0x8]; 3473 3474 u8 reserved_at_60[0x80]; 3475 }; 3476 3477 struct mlx5_ifc_rdma_page_fault_event_bits { 3478 u8 bytes_committed[0x20]; 3479 3480 u8 r_key[0x20]; 3481 3482 u8 reserved_at_40[0x10]; 3483 u8 packet_len[0x10]; 3484 3485 u8 rdma_op_len[0x20]; 3486 3487 u8 rdma_va[0x40]; 3488 3489 u8 reserved_at_c0[0x5]; 3490 u8 rdma[0x1]; 3491 u8 write[0x1]; 3492 u8 requestor[0x1]; 3493 u8 qp_number[0x18]; 3494 }; 3495 3496 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3497 u8 bytes_committed[0x20]; 3498 3499 u8 reserved_at_20[0x10]; 3500 u8 wqe_index[0x10]; 3501 3502 u8 reserved_at_40[0x10]; 3503 u8 len[0x10]; 3504 3505 u8 reserved_at_60[0x60]; 3506 3507 u8 reserved_at_c0[0x5]; 3508 u8 rdma[0x1]; 3509 u8 write_read[0x1]; 3510 u8 requestor[0x1]; 3511 u8 qpn[0x18]; 3512 }; 3513 3514 struct mlx5_ifc_qp_events_bits { 3515 u8 reserved_at_0[0xa0]; 3516 3517 u8 type[0x8]; 3518 u8 reserved_at_a8[0x18]; 3519 3520 u8 reserved_at_c0[0x8]; 3521 u8 qpn_rqn_sqn[0x18]; 3522 }; 3523 3524 struct mlx5_ifc_dct_events_bits { 3525 u8 reserved_at_0[0xc0]; 3526 3527 u8 reserved_at_c0[0x8]; 3528 u8 dct_number[0x18]; 3529 }; 3530 3531 struct mlx5_ifc_comp_event_bits { 3532 u8 reserved_at_0[0xc0]; 3533 3534 u8 reserved_at_c0[0x8]; 3535 u8 cq_number[0x18]; 3536 }; 3537 3538 enum { 3539 MLX5_QPC_STATE_RST = 0x0, 3540 MLX5_QPC_STATE_INIT = 0x1, 3541 MLX5_QPC_STATE_RTR = 0x2, 3542 MLX5_QPC_STATE_RTS = 0x3, 3543 MLX5_QPC_STATE_SQER = 0x4, 3544 MLX5_QPC_STATE_ERR = 0x6, 3545 MLX5_QPC_STATE_SQD = 0x7, 3546 MLX5_QPC_STATE_SUSPENDED = 0x9, 3547 }; 3548 3549 enum { 3550 MLX5_QPC_ST_RC = 0x0, 3551 MLX5_QPC_ST_UC = 0x1, 3552 MLX5_QPC_ST_UD = 0x2, 3553 MLX5_QPC_ST_XRC = 0x3, 3554 MLX5_QPC_ST_DCI = 0x5, 3555 MLX5_QPC_ST_QP0 = 0x7, 3556 MLX5_QPC_ST_QP1 = 0x8, 3557 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3558 MLX5_QPC_ST_REG_UMR = 0xc, 3559 }; 3560 3561 enum { 3562 MLX5_QPC_PM_STATE_ARMED = 0x0, 3563 MLX5_QPC_PM_STATE_REARM = 0x1, 3564 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3565 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3566 }; 3567 3568 enum { 3569 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3570 }; 3571 3572 enum { 3573 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3574 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3575 }; 3576 3577 enum { 3578 MLX5_QPC_MTU_256_BYTES = 0x1, 3579 MLX5_QPC_MTU_512_BYTES = 0x2, 3580 MLX5_QPC_MTU_1K_BYTES = 0x3, 3581 MLX5_QPC_MTU_2K_BYTES = 0x4, 3582 MLX5_QPC_MTU_4K_BYTES = 0x5, 3583 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3584 }; 3585 3586 enum { 3587 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3588 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3589 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3590 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3591 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3592 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3593 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3594 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3595 }; 3596 3597 enum { 3598 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3599 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3600 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3601 }; 3602 3603 enum { 3604 MLX5_QPC_CS_RES_DISABLE = 0x0, 3605 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3606 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3607 }; 3608 3609 enum { 3610 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3611 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3612 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3613 }; 3614 3615 struct mlx5_ifc_qpc_bits { 3616 u8 state[0x4]; 3617 u8 lag_tx_port_affinity[0x4]; 3618 u8 st[0x8]; 3619 u8 reserved_at_10[0x2]; 3620 u8 isolate_vl_tc[0x1]; 3621 u8 pm_state[0x2]; 3622 u8 reserved_at_15[0x1]; 3623 u8 req_e2e_credit_mode[0x2]; 3624 u8 offload_type[0x4]; 3625 u8 end_padding_mode[0x2]; 3626 u8 reserved_at_1e[0x2]; 3627 3628 u8 wq_signature[0x1]; 3629 u8 block_lb_mc[0x1]; 3630 u8 atomic_like_write_en[0x1]; 3631 u8 latency_sensitive[0x1]; 3632 u8 reserved_at_24[0x1]; 3633 u8 drain_sigerr[0x1]; 3634 u8 reserved_at_26[0x1]; 3635 u8 dp_ordering_force[0x1]; 3636 u8 pd[0x18]; 3637 3638 u8 mtu[0x3]; 3639 u8 log_msg_max[0x5]; 3640 u8 reserved_at_48[0x1]; 3641 u8 log_rq_size[0x4]; 3642 u8 log_rq_stride[0x3]; 3643 u8 no_sq[0x1]; 3644 u8 log_sq_size[0x4]; 3645 u8 reserved_at_55[0x1]; 3646 u8 retry_mode[0x2]; 3647 u8 ts_format[0x2]; 3648 u8 reserved_at_5a[0x1]; 3649 u8 rlky[0x1]; 3650 u8 ulp_stateless_offload_mode[0x4]; 3651 3652 u8 counter_set_id[0x8]; 3653 u8 uar_page[0x18]; 3654 3655 u8 reserved_at_80[0x8]; 3656 u8 user_index[0x18]; 3657 3658 u8 reserved_at_a0[0x3]; 3659 u8 log_page_size[0x5]; 3660 u8 remote_qpn[0x18]; 3661 3662 struct mlx5_ifc_ads_bits primary_address_path; 3663 3664 struct mlx5_ifc_ads_bits secondary_address_path; 3665 3666 u8 log_ack_req_freq[0x4]; 3667 u8 reserved_at_384[0x4]; 3668 u8 log_sra_max[0x3]; 3669 u8 reserved_at_38b[0x2]; 3670 u8 retry_count[0x3]; 3671 u8 rnr_retry[0x3]; 3672 u8 reserved_at_393[0x1]; 3673 u8 fre[0x1]; 3674 u8 cur_rnr_retry[0x3]; 3675 u8 cur_retry_count[0x3]; 3676 u8 reserved_at_39b[0x5]; 3677 3678 u8 reserved_at_3a0[0x20]; 3679 3680 u8 reserved_at_3c0[0x8]; 3681 u8 next_send_psn[0x18]; 3682 3683 u8 reserved_at_3e0[0x3]; 3684 u8 log_num_dci_stream_channels[0x5]; 3685 u8 cqn_snd[0x18]; 3686 3687 u8 reserved_at_400[0x3]; 3688 u8 log_num_dci_errored_streams[0x5]; 3689 u8 deth_sqpn[0x18]; 3690 3691 u8 reserved_at_420[0x20]; 3692 3693 u8 reserved_at_440[0x8]; 3694 u8 last_acked_psn[0x18]; 3695 3696 u8 reserved_at_460[0x8]; 3697 u8 ssn[0x18]; 3698 3699 u8 reserved_at_480[0x8]; 3700 u8 log_rra_max[0x3]; 3701 u8 reserved_at_48b[0x1]; 3702 u8 atomic_mode[0x4]; 3703 u8 rre[0x1]; 3704 u8 rwe[0x1]; 3705 u8 rae[0x1]; 3706 u8 reserved_at_493[0x1]; 3707 u8 page_offset[0x6]; 3708 u8 reserved_at_49a[0x2]; 3709 u8 dp_ordering_1[0x1]; 3710 u8 cd_slave_receive[0x1]; 3711 u8 cd_slave_send[0x1]; 3712 u8 cd_master[0x1]; 3713 3714 u8 reserved_at_4a0[0x3]; 3715 u8 min_rnr_nak[0x5]; 3716 u8 next_rcv_psn[0x18]; 3717 3718 u8 reserved_at_4c0[0x8]; 3719 u8 xrcd[0x18]; 3720 3721 u8 reserved_at_4e0[0x8]; 3722 u8 cqn_rcv[0x18]; 3723 3724 u8 dbr_addr[0x40]; 3725 3726 u8 q_key[0x20]; 3727 3728 u8 reserved_at_560[0x5]; 3729 u8 rq_type[0x3]; 3730 u8 srqn_rmpn_xrqn[0x18]; 3731 3732 u8 reserved_at_580[0x8]; 3733 u8 rmsn[0x18]; 3734 3735 u8 hw_sq_wqebb_counter[0x10]; 3736 u8 sw_sq_wqebb_counter[0x10]; 3737 3738 u8 hw_rq_counter[0x20]; 3739 3740 u8 sw_rq_counter[0x20]; 3741 3742 u8 reserved_at_600[0x20]; 3743 3744 u8 reserved_at_620[0xf]; 3745 u8 cgs[0x1]; 3746 u8 cs_req[0x8]; 3747 u8 cs_res[0x8]; 3748 3749 u8 dc_access_key[0x40]; 3750 3751 u8 reserved_at_680[0x3]; 3752 u8 dbr_umem_valid[0x1]; 3753 3754 u8 reserved_at_684[0xbc]; 3755 }; 3756 3757 struct mlx5_ifc_roce_addr_layout_bits { 3758 u8 source_l3_address[16][0x8]; 3759 3760 u8 reserved_at_80[0x3]; 3761 u8 vlan_valid[0x1]; 3762 u8 vlan_id[0xc]; 3763 u8 source_mac_47_32[0x10]; 3764 3765 u8 source_mac_31_0[0x20]; 3766 3767 u8 reserved_at_c0[0x14]; 3768 u8 roce_l3_type[0x4]; 3769 u8 roce_version[0x8]; 3770 3771 u8 reserved_at_e0[0x20]; 3772 }; 3773 3774 struct mlx5_ifc_crypto_cap_bits { 3775 u8 reserved_at_0[0x3]; 3776 u8 synchronize_dek[0x1]; 3777 u8 int_kek_manual[0x1]; 3778 u8 int_kek_auto[0x1]; 3779 u8 reserved_at_6[0x1a]; 3780 3781 u8 reserved_at_20[0x3]; 3782 u8 log_dek_max_alloc[0x5]; 3783 u8 reserved_at_28[0x3]; 3784 u8 log_max_num_deks[0x5]; 3785 u8 reserved_at_30[0x10]; 3786 3787 u8 reserved_at_40[0x20]; 3788 3789 u8 reserved_at_60[0x3]; 3790 u8 log_dek_granularity[0x5]; 3791 u8 reserved_at_68[0x3]; 3792 u8 log_max_num_int_kek[0x5]; 3793 u8 sw_wrapped_dek[0x10]; 3794 3795 u8 reserved_at_80[0x780]; 3796 }; 3797 3798 struct mlx5_ifc_shampo_cap_bits { 3799 u8 reserved_at_0[0x3]; 3800 u8 shampo_log_max_reservation_size[0x5]; 3801 u8 reserved_at_8[0x3]; 3802 u8 shampo_log_min_reservation_size[0x5]; 3803 u8 shampo_min_mss_size[0x10]; 3804 3805 u8 shampo_header_split[0x1]; 3806 u8 shampo_header_split_data_merge[0x1]; 3807 u8 reserved_at_22[0x1]; 3808 u8 shampo_log_max_headers_entry_size[0x5]; 3809 u8 reserved_at_28[0x18]; 3810 3811 u8 reserved_at_40[0x7c0]; 3812 }; 3813 3814 union mlx5_ifc_hca_cap_union_bits { 3815 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3816 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3817 struct mlx5_ifc_odp_cap_bits odp_cap; 3818 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3819 struct mlx5_ifc_roce_cap_bits roce_cap; 3820 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3821 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3822 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3823 struct mlx5_ifc_wqe_based_flow_table_cap_bits wqe_based_flow_table_cap; 3824 struct mlx5_ifc_esw_cap_bits esw_cap; 3825 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3826 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3827 struct mlx5_ifc_qos_cap_bits qos_cap; 3828 struct mlx5_ifc_debug_cap_bits debug_cap; 3829 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3830 struct mlx5_ifc_tls_cap_bits tls_cap; 3831 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3832 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3833 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3834 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3835 struct mlx5_ifc_ipsec_cap_bits ipsec_cap; 3836 struct mlx5_ifc_psp_cap_bits psp_cap; 3837 u8 reserved_at_0[0x8000]; 3838 }; 3839 3840 enum { 3841 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3842 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3843 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3844 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3845 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3846 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3847 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3848 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3849 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3850 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3851 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3852 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3853 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3854 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3855 }; 3856 3857 enum { 3858 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3859 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3860 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3861 }; 3862 3863 enum { 3864 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3865 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3866 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_PSP = 0x2, 3867 }; 3868 3869 struct mlx5_ifc_vlan_bits { 3870 u8 ethtype[0x10]; 3871 u8 prio[0x3]; 3872 u8 cfi[0x1]; 3873 u8 vid[0xc]; 3874 }; 3875 3876 enum { 3877 MLX5_FLOW_METER_COLOR_RED = 0x0, 3878 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3879 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3880 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3881 }; 3882 3883 enum { 3884 MLX5_EXE_ASO_FLOW_METER = 0x2, 3885 }; 3886 3887 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3888 u8 return_reg_id[0x4]; 3889 u8 aso_type[0x4]; 3890 u8 reserved_at_8[0x14]; 3891 u8 action[0x1]; 3892 u8 init_color[0x2]; 3893 u8 meter_id[0x1]; 3894 }; 3895 3896 union mlx5_ifc_exe_aso_ctrl { 3897 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3898 }; 3899 3900 struct mlx5_ifc_execute_aso_bits { 3901 u8 valid[0x1]; 3902 u8 reserved_at_1[0x7]; 3903 u8 aso_object_id[0x18]; 3904 3905 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3906 }; 3907 3908 struct mlx5_ifc_flow_context_bits { 3909 struct mlx5_ifc_vlan_bits push_vlan; 3910 3911 u8 group_id[0x20]; 3912 3913 u8 reserved_at_40[0x8]; 3914 u8 flow_tag[0x18]; 3915 3916 u8 reserved_at_60[0x10]; 3917 u8 action[0x10]; 3918 3919 u8 extended_destination[0x1]; 3920 u8 uplink_hairpin_en[0x1]; 3921 u8 flow_source[0x2]; 3922 u8 encrypt_decrypt_type[0x4]; 3923 u8 destination_list_size[0x18]; 3924 3925 u8 reserved_at_a0[0x8]; 3926 u8 flow_counter_list_size[0x18]; 3927 3928 u8 packet_reformat_id[0x20]; 3929 3930 u8 modify_header_id[0x20]; 3931 3932 struct mlx5_ifc_vlan_bits push_vlan_2; 3933 3934 u8 encrypt_decrypt_obj_id[0x20]; 3935 u8 reserved_at_140[0xc0]; 3936 3937 struct mlx5_ifc_fte_match_param_bits match_value; 3938 3939 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3940 3941 u8 reserved_at_1300[0x500]; 3942 3943 union mlx5_ifc_dest_format_flow_counter_list_auto_bits destination[]; 3944 }; 3945 3946 enum { 3947 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3948 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3949 }; 3950 3951 struct mlx5_ifc_xrc_srqc_bits { 3952 u8 state[0x4]; 3953 u8 log_xrc_srq_size[0x4]; 3954 u8 reserved_at_8[0x18]; 3955 3956 u8 wq_signature[0x1]; 3957 u8 cont_srq[0x1]; 3958 u8 reserved_at_22[0x1]; 3959 u8 rlky[0x1]; 3960 u8 basic_cyclic_rcv_wqe[0x1]; 3961 u8 log_rq_stride[0x3]; 3962 u8 xrcd[0x18]; 3963 3964 u8 page_offset[0x6]; 3965 u8 reserved_at_46[0x1]; 3966 u8 dbr_umem_valid[0x1]; 3967 u8 cqn[0x18]; 3968 3969 u8 reserved_at_60[0x20]; 3970 3971 u8 user_index_equal_xrc_srqn[0x1]; 3972 u8 reserved_at_81[0x1]; 3973 u8 log_page_size[0x6]; 3974 u8 user_index[0x18]; 3975 3976 u8 reserved_at_a0[0x20]; 3977 3978 u8 reserved_at_c0[0x8]; 3979 u8 pd[0x18]; 3980 3981 u8 lwm[0x10]; 3982 u8 wqe_cnt[0x10]; 3983 3984 u8 reserved_at_100[0x40]; 3985 3986 u8 db_record_addr_h[0x20]; 3987 3988 u8 db_record_addr_l[0x1e]; 3989 u8 reserved_at_17e[0x2]; 3990 3991 u8 reserved_at_180[0x80]; 3992 }; 3993 3994 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3995 u8 counter_error_queues[0x20]; 3996 3997 u8 total_error_queues[0x20]; 3998 3999 u8 send_queue_priority_update_flow[0x20]; 4000 4001 u8 reserved_at_60[0x20]; 4002 4003 u8 nic_receive_steering_discard[0x40]; 4004 4005 u8 receive_discard_vport_down[0x40]; 4006 4007 u8 transmit_discard_vport_down[0x40]; 4008 4009 u8 async_eq_overrun[0x20]; 4010 4011 u8 comp_eq_overrun[0x20]; 4012 4013 u8 reserved_at_180[0x20]; 4014 4015 u8 invalid_command[0x20]; 4016 4017 u8 quota_exceeded_command[0x20]; 4018 4019 u8 internal_rq_out_of_buffer[0x20]; 4020 4021 u8 cq_overrun[0x20]; 4022 4023 u8 eth_wqe_too_small[0x20]; 4024 4025 u8 reserved_at_220[0xc0]; 4026 4027 u8 generated_pkt_steering_fail[0x40]; 4028 4029 u8 handled_pkt_steering_fail[0x40]; 4030 4031 u8 bar_uar_access[0x20]; 4032 4033 u8 odp_local_triggered_page_fault[0x20]; 4034 4035 u8 odp_remote_triggered_page_fault[0x20]; 4036 4037 u8 reserved_at_3c0[0xc20]; 4038 }; 4039 4040 struct mlx5_ifc_traffic_counter_bits { 4041 u8 packets[0x40]; 4042 4043 u8 octets[0x40]; 4044 }; 4045 4046 struct mlx5_ifc_tisc_bits { 4047 u8 strict_lag_tx_port_affinity[0x1]; 4048 u8 tls_en[0x1]; 4049 u8 reserved_at_2[0x2]; 4050 u8 lag_tx_port_affinity[0x04]; 4051 4052 u8 reserved_at_8[0x4]; 4053 u8 prio[0x4]; 4054 u8 reserved_at_10[0x10]; 4055 4056 u8 reserved_at_20[0x100]; 4057 4058 u8 reserved_at_120[0x8]; 4059 u8 transport_domain[0x18]; 4060 4061 u8 reserved_at_140[0x8]; 4062 u8 underlay_qpn[0x18]; 4063 4064 u8 reserved_at_160[0x8]; 4065 u8 pd[0x18]; 4066 4067 u8 reserved_at_180[0x380]; 4068 }; 4069 4070 enum { 4071 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 4072 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 4073 }; 4074 4075 enum { 4076 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 4077 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 4078 }; 4079 4080 enum { 4081 MLX5_RX_HASH_FN_NONE = 0x0, 4082 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 4083 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 4084 }; 4085 4086 enum { 4087 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 4088 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 4089 }; 4090 4091 struct mlx5_ifc_tirc_bits { 4092 u8 reserved_at_0[0x20]; 4093 4094 u8 disp_type[0x4]; 4095 u8 tls_en[0x1]; 4096 u8 reserved_at_25[0x1b]; 4097 4098 u8 reserved_at_40[0x40]; 4099 4100 u8 reserved_at_80[0x4]; 4101 u8 lro_timeout_period_usecs[0x10]; 4102 u8 packet_merge_mask[0x4]; 4103 u8 lro_max_ip_payload_size[0x8]; 4104 4105 u8 reserved_at_a0[0x40]; 4106 4107 u8 reserved_at_e0[0x8]; 4108 u8 inline_rqn[0x18]; 4109 4110 u8 rx_hash_symmetric[0x1]; 4111 u8 reserved_at_101[0x1]; 4112 u8 tunneled_offload_en[0x1]; 4113 u8 reserved_at_103[0x5]; 4114 u8 indirect_table[0x18]; 4115 4116 u8 rx_hash_fn[0x4]; 4117 u8 reserved_at_124[0x2]; 4118 u8 self_lb_block[0x2]; 4119 u8 transport_domain[0x18]; 4120 4121 u8 rx_hash_toeplitz_key[10][0x20]; 4122 4123 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 4124 4125 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 4126 4127 u8 reserved_at_2c0[0x4c0]; 4128 }; 4129 4130 enum { 4131 MLX5_SRQC_STATE_GOOD = 0x0, 4132 MLX5_SRQC_STATE_ERROR = 0x1, 4133 }; 4134 4135 struct mlx5_ifc_srqc_bits { 4136 u8 state[0x4]; 4137 u8 log_srq_size[0x4]; 4138 u8 reserved_at_8[0x18]; 4139 4140 u8 wq_signature[0x1]; 4141 u8 cont_srq[0x1]; 4142 u8 reserved_at_22[0x1]; 4143 u8 rlky[0x1]; 4144 u8 reserved_at_24[0x1]; 4145 u8 log_rq_stride[0x3]; 4146 u8 xrcd[0x18]; 4147 4148 u8 page_offset[0x6]; 4149 u8 reserved_at_46[0x2]; 4150 u8 cqn[0x18]; 4151 4152 u8 reserved_at_60[0x20]; 4153 4154 u8 reserved_at_80[0x2]; 4155 u8 log_page_size[0x6]; 4156 u8 reserved_at_88[0x18]; 4157 4158 u8 reserved_at_a0[0x20]; 4159 4160 u8 reserved_at_c0[0x8]; 4161 u8 pd[0x18]; 4162 4163 u8 lwm[0x10]; 4164 u8 wqe_cnt[0x10]; 4165 4166 u8 reserved_at_100[0x40]; 4167 4168 u8 dbr_addr[0x40]; 4169 4170 u8 reserved_at_180[0x80]; 4171 }; 4172 4173 enum { 4174 MLX5_SQC_STATE_RST = 0x0, 4175 MLX5_SQC_STATE_RDY = 0x1, 4176 MLX5_SQC_STATE_ERR = 0x3, 4177 }; 4178 4179 struct mlx5_ifc_sqc_bits { 4180 u8 rlky[0x1]; 4181 u8 cd_master[0x1]; 4182 u8 fre[0x1]; 4183 u8 flush_in_error_en[0x1]; 4184 u8 allow_multi_pkt_send_wqe[0x1]; 4185 u8 min_wqe_inline_mode[0x3]; 4186 u8 state[0x4]; 4187 u8 reg_umr[0x1]; 4188 u8 allow_swp[0x1]; 4189 u8 hairpin[0x1]; 4190 u8 non_wire[0x1]; 4191 u8 reserved_at_10[0xa]; 4192 u8 ts_format[0x2]; 4193 u8 reserved_at_1c[0x4]; 4194 4195 u8 reserved_at_20[0x8]; 4196 u8 user_index[0x18]; 4197 4198 u8 reserved_at_40[0x8]; 4199 u8 cqn[0x18]; 4200 4201 u8 reserved_at_60[0x8]; 4202 u8 hairpin_peer_rq[0x18]; 4203 4204 u8 reserved_at_80[0x10]; 4205 u8 hairpin_peer_vhca[0x10]; 4206 4207 u8 reserved_at_a0[0x20]; 4208 4209 u8 reserved_at_c0[0x8]; 4210 u8 ts_cqe_to_dest_cqn[0x18]; 4211 4212 u8 reserved_at_e0[0x10]; 4213 u8 packet_pacing_rate_limit_index[0x10]; 4214 u8 tis_lst_sz[0x10]; 4215 u8 qos_queue_group_id[0x10]; 4216 4217 u8 reserved_at_120[0x40]; 4218 4219 u8 reserved_at_160[0x8]; 4220 u8 tis_num_0[0x18]; 4221 4222 struct mlx5_ifc_wq_bits wq; 4223 }; 4224 4225 enum { 4226 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 4227 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 4228 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 4229 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 4230 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 4231 SCHEDULING_CONTEXT_ELEMENT_TYPE_RATE_LIMIT = 0x5, 4232 }; 4233 4234 enum { 4235 ELEMENT_TYPE_CAP_MASK_TSAR = 1 << 0, 4236 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 4237 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 4238 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 4239 ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP = 1 << 4, 4240 ELEMENT_TYPE_CAP_MASK_RATE_LIMIT = 1 << 5, 4241 }; 4242 4243 enum { 4244 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4245 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4246 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4247 TSAR_ELEMENT_TSAR_TYPE_TC_ARB = 0x3, 4248 }; 4249 4250 enum { 4251 TSAR_TYPE_CAP_MASK_DWRR = 1 << 0, 4252 TSAR_TYPE_CAP_MASK_ROUND_ROBIN = 1 << 1, 4253 TSAR_TYPE_CAP_MASK_ETS = 1 << 2, 4254 TSAR_TYPE_CAP_MASK_TC_ARB = 1 << 3, 4255 }; 4256 4257 struct mlx5_ifc_tsar_element_bits { 4258 u8 traffic_class[0x4]; 4259 u8 reserved_at_4[0x4]; 4260 u8 tsar_type[0x8]; 4261 u8 reserved_at_10[0x10]; 4262 }; 4263 4264 struct mlx5_ifc_vport_element_bits { 4265 u8 reserved_at_0[0x4]; 4266 u8 eswitch_owner_vhca_id_valid[0x1]; 4267 u8 eswitch_owner_vhca_id[0xb]; 4268 u8 vport_number[0x10]; 4269 }; 4270 4271 struct mlx5_ifc_vport_tc_element_bits { 4272 u8 traffic_class[0x4]; 4273 u8 eswitch_owner_vhca_id_valid[0x1]; 4274 u8 eswitch_owner_vhca_id[0xb]; 4275 u8 vport_number[0x10]; 4276 }; 4277 4278 union mlx5_ifc_element_attributes_bits { 4279 struct mlx5_ifc_tsar_element_bits tsar; 4280 struct mlx5_ifc_vport_element_bits vport; 4281 struct mlx5_ifc_vport_tc_element_bits vport_tc; 4282 u8 reserved_at_0[0x20]; 4283 }; 4284 4285 struct mlx5_ifc_scheduling_context_bits { 4286 u8 element_type[0x8]; 4287 u8 reserved_at_8[0x18]; 4288 4289 union mlx5_ifc_element_attributes_bits element_attributes; 4290 4291 u8 parent_element_id[0x20]; 4292 4293 u8 reserved_at_60[0x40]; 4294 4295 u8 bw_share[0x20]; 4296 4297 u8 max_average_bw[0x20]; 4298 4299 u8 max_bw_obj_id[0x20]; 4300 4301 u8 reserved_at_100[0x100]; 4302 }; 4303 4304 struct mlx5_ifc_rqtc_bits { 4305 u8 reserved_at_0[0xa0]; 4306 4307 u8 reserved_at_a0[0x5]; 4308 u8 list_q_type[0x3]; 4309 u8 reserved_at_a8[0x8]; 4310 u8 rqt_max_size[0x10]; 4311 4312 u8 rq_vhca_id_format[0x1]; 4313 u8 reserved_at_c1[0xf]; 4314 u8 rqt_actual_size[0x10]; 4315 4316 u8 reserved_at_e0[0x6a0]; 4317 4318 union { 4319 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num); 4320 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca); 4321 }; 4322 }; 4323 4324 enum { 4325 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 4326 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 4327 }; 4328 4329 enum { 4330 MLX5_RQC_STATE_RST = 0x0, 4331 MLX5_RQC_STATE_RDY = 0x1, 4332 MLX5_RQC_STATE_ERR = 0x3, 4333 }; 4334 4335 enum { 4336 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 4337 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 4338 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 4339 }; 4340 4341 enum { 4342 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 4343 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 4344 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 4345 }; 4346 4347 struct mlx5_ifc_rqc_bits { 4348 u8 rlky[0x1]; 4349 u8 delay_drop_en[0x1]; 4350 u8 scatter_fcs[0x1]; 4351 u8 vsd[0x1]; 4352 u8 mem_rq_type[0x4]; 4353 u8 state[0x4]; 4354 u8 reserved_at_c[0x1]; 4355 u8 flush_in_error_en[0x1]; 4356 u8 hairpin[0x1]; 4357 u8 reserved_at_f[0xb]; 4358 u8 ts_format[0x2]; 4359 u8 reserved_at_1c[0x4]; 4360 4361 u8 reserved_at_20[0x8]; 4362 u8 user_index[0x18]; 4363 4364 u8 reserved_at_40[0x8]; 4365 u8 cqn[0x18]; 4366 4367 u8 counter_set_id[0x8]; 4368 u8 reserved_at_68[0x18]; 4369 4370 u8 reserved_at_80[0x8]; 4371 u8 rmpn[0x18]; 4372 4373 u8 reserved_at_a0[0x8]; 4374 u8 hairpin_peer_sq[0x18]; 4375 4376 u8 reserved_at_c0[0x10]; 4377 u8 hairpin_peer_vhca[0x10]; 4378 4379 u8 reserved_at_e0[0x46]; 4380 u8 shampo_no_match_alignment_granularity[0x2]; 4381 u8 reserved_at_128[0x6]; 4382 u8 shampo_match_criteria_type[0x2]; 4383 u8 reservation_timeout[0x10]; 4384 4385 u8 reserved_at_140[0x40]; 4386 4387 struct mlx5_ifc_wq_bits wq; 4388 }; 4389 4390 enum { 4391 MLX5_RMPC_STATE_RDY = 0x1, 4392 MLX5_RMPC_STATE_ERR = 0x3, 4393 }; 4394 4395 struct mlx5_ifc_rmpc_bits { 4396 u8 reserved_at_0[0x8]; 4397 u8 state[0x4]; 4398 u8 reserved_at_c[0x14]; 4399 4400 u8 basic_cyclic_rcv_wqe[0x1]; 4401 u8 reserved_at_21[0x1f]; 4402 4403 u8 reserved_at_40[0x140]; 4404 4405 struct mlx5_ifc_wq_bits wq; 4406 }; 4407 4408 enum { 4409 VHCA_ID_TYPE_HW = 0, 4410 VHCA_ID_TYPE_SW = 1, 4411 }; 4412 4413 struct mlx5_ifc_nic_vport_context_bits { 4414 u8 reserved_at_0[0x5]; 4415 u8 min_wqe_inline_mode[0x3]; 4416 u8 reserved_at_8[0x15]; 4417 u8 disable_mc_local_lb[0x1]; 4418 u8 disable_uc_local_lb[0x1]; 4419 u8 roce_en[0x1]; 4420 4421 u8 arm_change_event[0x1]; 4422 u8 reserved_at_21[0x1a]; 4423 u8 event_on_mtu[0x1]; 4424 u8 event_on_promisc_change[0x1]; 4425 u8 event_on_vlan_change[0x1]; 4426 u8 event_on_mc_address_change[0x1]; 4427 u8 event_on_uc_address_change[0x1]; 4428 4429 u8 vhca_id_type[0x1]; 4430 u8 reserved_at_41[0xb]; 4431 u8 affiliation_criteria[0x4]; 4432 u8 affiliated_vhca_id[0x10]; 4433 4434 u8 reserved_at_60[0xa0]; 4435 4436 u8 reserved_at_100[0x1]; 4437 u8 sd_group[0x3]; 4438 u8 reserved_at_104[0x1c]; 4439 4440 u8 reserved_at_120[0x10]; 4441 u8 mtu[0x10]; 4442 4443 u8 system_image_guid[0x40]; 4444 u8 port_guid[0x40]; 4445 u8 node_guid[0x40]; 4446 4447 u8 reserved_at_200[0x140]; 4448 u8 qkey_violation_counter[0x10]; 4449 u8 reserved_at_350[0x430]; 4450 4451 u8 promisc_uc[0x1]; 4452 u8 promisc_mc[0x1]; 4453 u8 promisc_all[0x1]; 4454 u8 reserved_at_783[0x2]; 4455 u8 allowed_list_type[0x3]; 4456 u8 reserved_at_788[0xc]; 4457 u8 allowed_list_size[0xc]; 4458 4459 struct mlx5_ifc_mac_address_layout_bits permanent_address; 4460 4461 u8 reserved_at_7e0[0x20]; 4462 4463 u8 current_uc_mac_address[][0x40]; 4464 }; 4465 4466 enum { 4467 MLX5_MKC_ACCESS_MODE_PA = 0x0, 4468 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4469 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4470 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4471 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4472 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4473 MLX5_MKC_ACCESS_MODE_CROSSING = 0x6, 4474 }; 4475 4476 enum { 4477 MLX5_MKC_PCIE_TPH_NO_STEERING_TAG_INDEX = 0, 4478 }; 4479 4480 struct mlx5_ifc_mkc_bits { 4481 u8 reserved_at_0[0x1]; 4482 u8 free[0x1]; 4483 u8 reserved_at_2[0x1]; 4484 u8 access_mode_4_2[0x3]; 4485 u8 reserved_at_6[0x7]; 4486 u8 relaxed_ordering_write[0x1]; 4487 u8 reserved_at_e[0x1]; 4488 u8 small_fence_on_rdma_read_response[0x1]; 4489 u8 umr_en[0x1]; 4490 u8 a[0x1]; 4491 u8 rw[0x1]; 4492 u8 rr[0x1]; 4493 u8 lw[0x1]; 4494 u8 lr[0x1]; 4495 u8 access_mode_1_0[0x2]; 4496 u8 reserved_at_18[0x2]; 4497 u8 ma_translation_mode[0x2]; 4498 u8 reserved_at_1c[0x4]; 4499 4500 u8 qpn[0x18]; 4501 u8 mkey_7_0[0x8]; 4502 4503 u8 reserved_at_40[0x20]; 4504 4505 u8 length64[0x1]; 4506 u8 bsf_en[0x1]; 4507 u8 sync_umr[0x1]; 4508 u8 reserved_at_63[0x2]; 4509 u8 expected_sigerr_count[0x1]; 4510 u8 reserved_at_66[0x1]; 4511 u8 en_rinval[0x1]; 4512 u8 pd[0x18]; 4513 4514 u8 start_addr[0x40]; 4515 4516 u8 len[0x40]; 4517 4518 u8 bsf_octword_size[0x20]; 4519 4520 u8 reserved_at_120[0x60]; 4521 4522 u8 crossing_target_vhca_id[0x10]; 4523 u8 reserved_at_190[0x10]; 4524 4525 u8 translations_octword_size[0x20]; 4526 4527 u8 reserved_at_1c0[0x19]; 4528 u8 relaxed_ordering_read[0x1]; 4529 u8 log_page_size[0x6]; 4530 4531 u8 reserved_at_1e0[0x5]; 4532 u8 pcie_tph_en[0x1]; 4533 u8 pcie_tph_ph[0x2]; 4534 u8 pcie_tph_steering_tag_index[0x8]; 4535 u8 reserved_at_1f0[0x10]; 4536 }; 4537 4538 struct mlx5_ifc_pkey_bits { 4539 u8 reserved_at_0[0x10]; 4540 u8 pkey[0x10]; 4541 }; 4542 4543 struct mlx5_ifc_array128_auto_bits { 4544 u8 array128_auto[16][0x8]; 4545 }; 4546 4547 struct mlx5_ifc_hca_vport_context_bits { 4548 u8 field_select[0x20]; 4549 4550 u8 reserved_at_20[0xe0]; 4551 4552 u8 sm_virt_aware[0x1]; 4553 u8 has_smi[0x1]; 4554 u8 has_raw[0x1]; 4555 u8 grh_required[0x1]; 4556 u8 reserved_at_104[0x4]; 4557 u8 num_port_plane[0x8]; 4558 u8 port_physical_state[0x4]; 4559 u8 vport_state_policy[0x4]; 4560 u8 port_state[0x4]; 4561 u8 vport_state[0x4]; 4562 4563 u8 reserved_at_120[0x20]; 4564 4565 u8 system_image_guid[0x40]; 4566 4567 u8 port_guid[0x40]; 4568 4569 u8 node_guid[0x40]; 4570 4571 u8 cap_mask1[0x20]; 4572 4573 u8 cap_mask1_field_select[0x20]; 4574 4575 u8 cap_mask2[0x20]; 4576 4577 u8 cap_mask2_field_select[0x20]; 4578 4579 u8 reserved_at_280[0x80]; 4580 4581 u8 lid[0x10]; 4582 u8 reserved_at_310[0x4]; 4583 u8 init_type_reply[0x4]; 4584 u8 lmc[0x3]; 4585 u8 subnet_timeout[0x5]; 4586 4587 u8 sm_lid[0x10]; 4588 u8 sm_sl[0x4]; 4589 u8 reserved_at_334[0xc]; 4590 4591 u8 qkey_violation_counter[0x10]; 4592 u8 pkey_violation_counter[0x10]; 4593 4594 u8 reserved_at_360[0xca0]; 4595 }; 4596 4597 struct mlx5_ifc_esw_vport_context_bits { 4598 u8 fdb_to_vport_reg_c[0x1]; 4599 u8 reserved_at_1[0x2]; 4600 u8 vport_svlan_strip[0x1]; 4601 u8 vport_cvlan_strip[0x1]; 4602 u8 vport_svlan_insert[0x1]; 4603 u8 vport_cvlan_insert[0x2]; 4604 u8 fdb_to_vport_reg_c_id[0x8]; 4605 u8 reserved_at_10[0x10]; 4606 4607 u8 reserved_at_20[0x20]; 4608 4609 u8 svlan_cfi[0x1]; 4610 u8 svlan_pcp[0x3]; 4611 u8 svlan_id[0xc]; 4612 u8 cvlan_cfi[0x1]; 4613 u8 cvlan_pcp[0x3]; 4614 u8 cvlan_id[0xc]; 4615 4616 u8 reserved_at_60[0x720]; 4617 4618 u8 sw_steering_vport_icm_address_rx[0x40]; 4619 4620 u8 sw_steering_vport_icm_address_tx[0x40]; 4621 }; 4622 4623 enum { 4624 MLX5_EQC_STATUS_OK = 0x0, 4625 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4626 }; 4627 4628 enum { 4629 MLX5_EQC_ST_ARMED = 0x9, 4630 MLX5_EQC_ST_FIRED = 0xa, 4631 }; 4632 4633 struct mlx5_ifc_eqc_bits { 4634 u8 status[0x4]; 4635 u8 reserved_at_4[0x9]; 4636 u8 ec[0x1]; 4637 u8 oi[0x1]; 4638 u8 reserved_at_f[0x5]; 4639 u8 st[0x4]; 4640 u8 reserved_at_18[0x8]; 4641 4642 u8 reserved_at_20[0x20]; 4643 4644 u8 reserved_at_40[0x14]; 4645 u8 page_offset[0x6]; 4646 u8 reserved_at_5a[0x6]; 4647 4648 u8 reserved_at_60[0x3]; 4649 u8 log_eq_size[0x5]; 4650 u8 uar_page[0x18]; 4651 4652 u8 reserved_at_80[0x20]; 4653 4654 u8 reserved_at_a0[0x14]; 4655 u8 intr[0xc]; 4656 4657 u8 reserved_at_c0[0x3]; 4658 u8 log_page_size[0x5]; 4659 u8 reserved_at_c8[0x18]; 4660 4661 u8 reserved_at_e0[0x60]; 4662 4663 u8 reserved_at_140[0x8]; 4664 u8 consumer_counter[0x18]; 4665 4666 u8 reserved_at_160[0x8]; 4667 u8 producer_counter[0x18]; 4668 4669 u8 reserved_at_180[0x80]; 4670 }; 4671 4672 enum { 4673 MLX5_DCTC_STATE_ACTIVE = 0x0, 4674 MLX5_DCTC_STATE_DRAINING = 0x1, 4675 MLX5_DCTC_STATE_DRAINED = 0x2, 4676 }; 4677 4678 enum { 4679 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4680 MLX5_DCTC_CS_RES_NA = 0x1, 4681 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4682 }; 4683 4684 enum { 4685 MLX5_DCTC_MTU_256_BYTES = 0x1, 4686 MLX5_DCTC_MTU_512_BYTES = 0x2, 4687 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4688 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4689 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4690 }; 4691 4692 struct mlx5_ifc_dctc_bits { 4693 u8 reserved_at_0[0x4]; 4694 u8 state[0x4]; 4695 u8 reserved_at_8[0x18]; 4696 4697 u8 reserved_at_20[0x7]; 4698 u8 dp_ordering_force[0x1]; 4699 u8 user_index[0x18]; 4700 4701 u8 reserved_at_40[0x8]; 4702 u8 cqn[0x18]; 4703 4704 u8 counter_set_id[0x8]; 4705 u8 atomic_mode[0x4]; 4706 u8 rre[0x1]; 4707 u8 rwe[0x1]; 4708 u8 rae[0x1]; 4709 u8 atomic_like_write_en[0x1]; 4710 u8 latency_sensitive[0x1]; 4711 u8 rlky[0x1]; 4712 u8 free_ar[0x1]; 4713 u8 reserved_at_73[0x1]; 4714 u8 dp_ordering_1[0x1]; 4715 u8 reserved_at_75[0xb]; 4716 4717 u8 reserved_at_80[0x8]; 4718 u8 cs_res[0x8]; 4719 u8 reserved_at_90[0x3]; 4720 u8 min_rnr_nak[0x5]; 4721 u8 reserved_at_98[0x8]; 4722 4723 u8 reserved_at_a0[0x8]; 4724 u8 srqn_xrqn[0x18]; 4725 4726 u8 reserved_at_c0[0x8]; 4727 u8 pd[0x18]; 4728 4729 u8 tclass[0x8]; 4730 u8 reserved_at_e8[0x4]; 4731 u8 flow_label[0x14]; 4732 4733 u8 dc_access_key[0x40]; 4734 4735 u8 reserved_at_140[0x5]; 4736 u8 mtu[0x3]; 4737 u8 port[0x8]; 4738 u8 pkey_index[0x10]; 4739 4740 u8 reserved_at_160[0x8]; 4741 u8 my_addr_index[0x8]; 4742 u8 reserved_at_170[0x8]; 4743 u8 hop_limit[0x8]; 4744 4745 u8 dc_access_key_violation_count[0x20]; 4746 4747 u8 reserved_at_1a0[0x14]; 4748 u8 dei_cfi[0x1]; 4749 u8 eth_prio[0x3]; 4750 u8 ecn[0x2]; 4751 u8 dscp[0x6]; 4752 4753 u8 reserved_at_1c0[0x20]; 4754 u8 ece[0x20]; 4755 }; 4756 4757 enum { 4758 MLX5_CQC_STATUS_OK = 0x0, 4759 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4760 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4761 }; 4762 4763 enum { 4764 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4765 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4766 }; 4767 4768 enum { 4769 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4770 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4771 MLX5_CQC_ST_FIRED = 0xa, 4772 }; 4773 4774 enum mlx5_cq_period_mode { 4775 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4776 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4777 MLX5_CQ_PERIOD_NUM_MODES, 4778 }; 4779 4780 struct mlx5_ifc_cqc_bits { 4781 u8 status[0x4]; 4782 u8 reserved_at_4[0x2]; 4783 u8 dbr_umem_valid[0x1]; 4784 u8 apu_cq[0x1]; 4785 u8 cqe_sz[0x3]; 4786 u8 cc[0x1]; 4787 u8 reserved_at_c[0x1]; 4788 u8 scqe_break_moderation_en[0x1]; 4789 u8 oi[0x1]; 4790 u8 cq_period_mode[0x2]; 4791 u8 cqe_comp_en[0x1]; 4792 u8 mini_cqe_res_format[0x2]; 4793 u8 st[0x4]; 4794 u8 reserved_at_18[0x6]; 4795 u8 cqe_compression_layout[0x2]; 4796 4797 u8 reserved_at_20[0x20]; 4798 4799 u8 reserved_at_40[0x14]; 4800 u8 page_offset[0x6]; 4801 u8 reserved_at_5a[0x6]; 4802 4803 u8 reserved_at_60[0x3]; 4804 u8 log_cq_size[0x5]; 4805 u8 uar_page[0x18]; 4806 4807 u8 reserved_at_80[0x4]; 4808 u8 cq_period[0xc]; 4809 u8 cq_max_count[0x10]; 4810 4811 u8 c_eqn_or_apu_element[0x20]; 4812 4813 u8 reserved_at_c0[0x3]; 4814 u8 log_page_size[0x5]; 4815 u8 reserved_at_c8[0x18]; 4816 4817 u8 reserved_at_e0[0x20]; 4818 4819 u8 reserved_at_100[0x8]; 4820 u8 last_notified_index[0x18]; 4821 4822 u8 reserved_at_120[0x8]; 4823 u8 last_solicit_index[0x18]; 4824 4825 u8 reserved_at_140[0x8]; 4826 u8 consumer_counter[0x18]; 4827 4828 u8 reserved_at_160[0x8]; 4829 u8 producer_counter[0x18]; 4830 4831 u8 reserved_at_180[0x40]; 4832 4833 u8 dbr_addr[0x40]; 4834 }; 4835 4836 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4837 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4838 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4839 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4840 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; 4841 u8 reserved_at_0[0x800]; 4842 }; 4843 4844 struct mlx5_ifc_query_adapter_param_block_bits { 4845 u8 reserved_at_0[0xc0]; 4846 4847 u8 reserved_at_c0[0x8]; 4848 u8 ieee_vendor_id[0x18]; 4849 4850 u8 reserved_at_e0[0x10]; 4851 u8 vsd_vendor_id[0x10]; 4852 4853 u8 vsd[208][0x8]; 4854 4855 u8 vsd_contd_psid[16][0x8]; 4856 }; 4857 4858 enum { 4859 MLX5_XRQC_STATE_GOOD = 0x0, 4860 MLX5_XRQC_STATE_ERROR = 0x1, 4861 }; 4862 4863 enum { 4864 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4865 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4866 }; 4867 4868 enum { 4869 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4870 }; 4871 4872 struct mlx5_ifc_tag_matching_topology_context_bits { 4873 u8 log_matching_list_sz[0x4]; 4874 u8 reserved_at_4[0xc]; 4875 u8 append_next_index[0x10]; 4876 4877 u8 sw_phase_cnt[0x10]; 4878 u8 hw_phase_cnt[0x10]; 4879 4880 u8 reserved_at_40[0x40]; 4881 }; 4882 4883 struct mlx5_ifc_xrqc_bits { 4884 u8 state[0x4]; 4885 u8 rlkey[0x1]; 4886 u8 reserved_at_5[0xf]; 4887 u8 topology[0x4]; 4888 u8 reserved_at_18[0x4]; 4889 u8 offload[0x4]; 4890 4891 u8 reserved_at_20[0x8]; 4892 u8 user_index[0x18]; 4893 4894 u8 reserved_at_40[0x8]; 4895 u8 cqn[0x18]; 4896 4897 u8 reserved_at_60[0xa0]; 4898 4899 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4900 4901 u8 reserved_at_180[0x280]; 4902 4903 struct mlx5_ifc_wq_bits wq; 4904 }; 4905 4906 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4907 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4908 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4909 u8 reserved_at_0[0x20]; 4910 }; 4911 4912 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4913 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4914 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4915 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4916 u8 reserved_at_0[0x20]; 4917 }; 4918 4919 struct mlx5_ifc_rs_histogram_cntrs_bits { 4920 u8 hist[16][0x40]; 4921 u8 reserved_at_400[0x2c0]; 4922 }; 4923 4924 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4925 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4926 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4927 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4928 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4929 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4930 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4931 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4932 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4933 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4934 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits ib_ext_port_cntrs_grp_data_layout; 4935 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4936 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4937 struct mlx5_ifc_phys_layer_recovery_cntrs_bits phys_layer_recovery_cntrs; 4938 struct mlx5_ifc_rs_histogram_cntrs_bits rs_histogram_cntrs; 4939 u8 reserved_at_0[0x7c0]; 4940 }; 4941 4942 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4943 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4944 u8 reserved_at_0[0x7c0]; 4945 }; 4946 4947 union mlx5_ifc_event_auto_bits { 4948 struct mlx5_ifc_comp_event_bits comp_event; 4949 struct mlx5_ifc_dct_events_bits dct_events; 4950 struct mlx5_ifc_qp_events_bits qp_events; 4951 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4952 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4953 struct mlx5_ifc_cq_error_bits cq_error; 4954 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4955 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4956 struct mlx5_ifc_gpio_event_bits gpio_event; 4957 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4958 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4959 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4960 u8 reserved_at_0[0xe0]; 4961 }; 4962 4963 struct mlx5_ifc_health_buffer_bits { 4964 u8 reserved_at_0[0x100]; 4965 4966 u8 assert_existptr[0x20]; 4967 4968 u8 assert_callra[0x20]; 4969 4970 u8 reserved_at_140[0x20]; 4971 4972 u8 time[0x20]; 4973 4974 u8 fw_version[0x20]; 4975 4976 u8 hw_id[0x20]; 4977 4978 u8 rfr[0x1]; 4979 u8 reserved_at_1c1[0x3]; 4980 u8 valid[0x1]; 4981 u8 severity[0x3]; 4982 u8 reserved_at_1c8[0x18]; 4983 4984 u8 irisc_index[0x8]; 4985 u8 synd[0x8]; 4986 u8 ext_synd[0x10]; 4987 }; 4988 4989 struct mlx5_ifc_register_loopback_control_bits { 4990 u8 no_lb[0x1]; 4991 u8 reserved_at_1[0x7]; 4992 u8 port[0x8]; 4993 u8 reserved_at_10[0x10]; 4994 4995 u8 reserved_at_20[0x60]; 4996 }; 4997 4998 enum { 4999 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 5000 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 5001 }; 5002 5003 struct mlx5_ifc_teardown_hca_out_bits { 5004 u8 status[0x8]; 5005 u8 reserved_at_8[0x18]; 5006 5007 u8 syndrome[0x20]; 5008 5009 u8 reserved_at_40[0x3f]; 5010 5011 u8 state[0x1]; 5012 }; 5013 5014 enum { 5015 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 5016 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 5017 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 5018 }; 5019 5020 struct mlx5_ifc_teardown_hca_in_bits { 5021 u8 opcode[0x10]; 5022 u8 reserved_at_10[0x10]; 5023 5024 u8 reserved_at_20[0x10]; 5025 u8 op_mod[0x10]; 5026 5027 u8 reserved_at_40[0x10]; 5028 u8 profile[0x10]; 5029 5030 u8 reserved_at_60[0x20]; 5031 }; 5032 5033 struct mlx5_ifc_sqerr2rts_qp_out_bits { 5034 u8 status[0x8]; 5035 u8 reserved_at_8[0x18]; 5036 5037 u8 syndrome[0x20]; 5038 5039 u8 reserved_at_40[0x40]; 5040 }; 5041 5042 struct mlx5_ifc_sqerr2rts_qp_in_bits { 5043 u8 opcode[0x10]; 5044 u8 uid[0x10]; 5045 5046 u8 reserved_at_20[0x10]; 5047 u8 op_mod[0x10]; 5048 5049 u8 reserved_at_40[0x8]; 5050 u8 qpn[0x18]; 5051 5052 u8 reserved_at_60[0x20]; 5053 5054 u8 opt_param_mask[0x20]; 5055 5056 u8 reserved_at_a0[0x20]; 5057 5058 struct mlx5_ifc_qpc_bits qpc; 5059 5060 u8 reserved_at_800[0x80]; 5061 }; 5062 5063 struct mlx5_ifc_sqd2rts_qp_out_bits { 5064 u8 status[0x8]; 5065 u8 reserved_at_8[0x18]; 5066 5067 u8 syndrome[0x20]; 5068 5069 u8 reserved_at_40[0x40]; 5070 }; 5071 5072 struct mlx5_ifc_sqd2rts_qp_in_bits { 5073 u8 opcode[0x10]; 5074 u8 uid[0x10]; 5075 5076 u8 reserved_at_20[0x10]; 5077 u8 op_mod[0x10]; 5078 5079 u8 reserved_at_40[0x8]; 5080 u8 qpn[0x18]; 5081 5082 u8 reserved_at_60[0x20]; 5083 5084 u8 opt_param_mask[0x20]; 5085 5086 u8 reserved_at_a0[0x20]; 5087 5088 struct mlx5_ifc_qpc_bits qpc; 5089 5090 u8 reserved_at_800[0x80]; 5091 }; 5092 5093 struct mlx5_ifc_set_roce_address_out_bits { 5094 u8 status[0x8]; 5095 u8 reserved_at_8[0x18]; 5096 5097 u8 syndrome[0x20]; 5098 5099 u8 reserved_at_40[0x40]; 5100 }; 5101 5102 struct mlx5_ifc_set_roce_address_in_bits { 5103 u8 opcode[0x10]; 5104 u8 reserved_at_10[0x10]; 5105 5106 u8 reserved_at_20[0x10]; 5107 u8 op_mod[0x10]; 5108 5109 u8 roce_address_index[0x10]; 5110 u8 reserved_at_50[0xc]; 5111 u8 vhca_port_num[0x4]; 5112 5113 u8 reserved_at_60[0x20]; 5114 5115 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5116 }; 5117 5118 struct mlx5_ifc_set_mad_demux_out_bits { 5119 u8 status[0x8]; 5120 u8 reserved_at_8[0x18]; 5121 5122 u8 syndrome[0x20]; 5123 5124 u8 reserved_at_40[0x40]; 5125 }; 5126 5127 enum { 5128 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 5129 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 5130 }; 5131 5132 struct mlx5_ifc_set_mad_demux_in_bits { 5133 u8 opcode[0x10]; 5134 u8 reserved_at_10[0x10]; 5135 5136 u8 reserved_at_20[0x10]; 5137 u8 op_mod[0x10]; 5138 5139 u8 reserved_at_40[0x20]; 5140 5141 u8 reserved_at_60[0x6]; 5142 u8 demux_mode[0x2]; 5143 u8 reserved_at_68[0x18]; 5144 }; 5145 5146 struct mlx5_ifc_set_l2_table_entry_out_bits { 5147 u8 status[0x8]; 5148 u8 reserved_at_8[0x18]; 5149 5150 u8 syndrome[0x20]; 5151 5152 u8 reserved_at_40[0x40]; 5153 }; 5154 5155 struct mlx5_ifc_set_l2_table_entry_in_bits { 5156 u8 opcode[0x10]; 5157 u8 reserved_at_10[0x10]; 5158 5159 u8 reserved_at_20[0x10]; 5160 u8 op_mod[0x10]; 5161 5162 u8 reserved_at_40[0x60]; 5163 5164 u8 reserved_at_a0[0x8]; 5165 u8 table_index[0x18]; 5166 5167 u8 reserved_at_c0[0x20]; 5168 5169 u8 reserved_at_e0[0x10]; 5170 u8 silent_mode_valid[0x1]; 5171 u8 silent_mode[0x1]; 5172 u8 reserved_at_f2[0x1]; 5173 u8 vlan_valid[0x1]; 5174 u8 vlan[0xc]; 5175 5176 struct mlx5_ifc_mac_address_layout_bits mac_address; 5177 5178 u8 reserved_at_140[0xc0]; 5179 }; 5180 5181 struct mlx5_ifc_set_issi_out_bits { 5182 u8 status[0x8]; 5183 u8 reserved_at_8[0x18]; 5184 5185 u8 syndrome[0x20]; 5186 5187 u8 reserved_at_40[0x40]; 5188 }; 5189 5190 struct mlx5_ifc_set_issi_in_bits { 5191 u8 opcode[0x10]; 5192 u8 reserved_at_10[0x10]; 5193 5194 u8 reserved_at_20[0x10]; 5195 u8 op_mod[0x10]; 5196 5197 u8 reserved_at_40[0x10]; 5198 u8 current_issi[0x10]; 5199 5200 u8 reserved_at_60[0x20]; 5201 }; 5202 5203 struct mlx5_ifc_set_hca_cap_out_bits { 5204 u8 status[0x8]; 5205 u8 reserved_at_8[0x18]; 5206 5207 u8 syndrome[0x20]; 5208 5209 u8 reserved_at_40[0x40]; 5210 }; 5211 5212 struct mlx5_ifc_set_hca_cap_in_bits { 5213 u8 opcode[0x10]; 5214 u8 reserved_at_10[0x10]; 5215 5216 u8 reserved_at_20[0x10]; 5217 u8 op_mod[0x10]; 5218 5219 u8 other_function[0x1]; 5220 u8 ec_vf_function[0x1]; 5221 u8 reserved_at_42[0x1]; 5222 u8 function_id_type[0x1]; 5223 u8 reserved_at_44[0xc]; 5224 u8 function_id[0x10]; 5225 5226 u8 reserved_at_60[0x20]; 5227 5228 union mlx5_ifc_hca_cap_union_bits capability; 5229 }; 5230 5231 enum { 5232 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 5233 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 5234 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 5235 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 5236 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 5237 }; 5238 5239 struct mlx5_ifc_set_fte_out_bits { 5240 u8 status[0x8]; 5241 u8 reserved_at_8[0x18]; 5242 5243 u8 syndrome[0x20]; 5244 5245 u8 reserved_at_40[0x40]; 5246 }; 5247 5248 struct mlx5_ifc_set_fte_in_bits { 5249 u8 opcode[0x10]; 5250 u8 reserved_at_10[0x10]; 5251 5252 u8 reserved_at_20[0x10]; 5253 u8 op_mod[0x10]; 5254 5255 u8 other_vport[0x1]; 5256 u8 other_eswitch[0x1]; 5257 u8 reserved_at_42[0xe]; 5258 u8 vport_number[0x10]; 5259 5260 u8 reserved_at_60[0x20]; 5261 5262 u8 table_type[0x8]; 5263 u8 reserved_at_88[0x8]; 5264 u8 eswitch_owner_vhca_id[0x10]; 5265 5266 u8 reserved_at_a0[0x8]; 5267 u8 table_id[0x18]; 5268 5269 u8 ignore_flow_level[0x1]; 5270 u8 reserved_at_c1[0x17]; 5271 u8 modify_enable_mask[0x8]; 5272 5273 u8 reserved_at_e0[0x20]; 5274 5275 u8 flow_index[0x20]; 5276 5277 u8 reserved_at_120[0xe0]; 5278 5279 struct mlx5_ifc_flow_context_bits flow_context; 5280 }; 5281 5282 struct mlx5_ifc_dest_format_bits { 5283 u8 destination_type[0x8]; 5284 u8 destination_id[0x18]; 5285 5286 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 5287 u8 packet_reformat[0x1]; 5288 u8 reserved_at_22[0xe]; 5289 u8 destination_eswitch_owner_vhca_id[0x10]; 5290 }; 5291 5292 struct mlx5_ifc_rts2rts_qp_out_bits { 5293 u8 status[0x8]; 5294 u8 reserved_at_8[0x18]; 5295 5296 u8 syndrome[0x20]; 5297 5298 u8 reserved_at_40[0x20]; 5299 u8 ece[0x20]; 5300 }; 5301 5302 struct mlx5_ifc_rts2rts_qp_in_bits { 5303 u8 opcode[0x10]; 5304 u8 uid[0x10]; 5305 5306 u8 reserved_at_20[0x10]; 5307 u8 op_mod[0x10]; 5308 5309 u8 reserved_at_40[0x8]; 5310 u8 qpn[0x18]; 5311 5312 u8 reserved_at_60[0x20]; 5313 5314 u8 opt_param_mask[0x20]; 5315 5316 u8 ece[0x20]; 5317 5318 struct mlx5_ifc_qpc_bits qpc; 5319 5320 u8 reserved_at_800[0x80]; 5321 }; 5322 5323 struct mlx5_ifc_rtr2rts_qp_out_bits { 5324 u8 status[0x8]; 5325 u8 reserved_at_8[0x18]; 5326 5327 u8 syndrome[0x20]; 5328 5329 u8 reserved_at_40[0x20]; 5330 u8 ece[0x20]; 5331 }; 5332 5333 struct mlx5_ifc_rtr2rts_qp_in_bits { 5334 u8 opcode[0x10]; 5335 u8 uid[0x10]; 5336 5337 u8 reserved_at_20[0x10]; 5338 u8 op_mod[0x10]; 5339 5340 u8 reserved_at_40[0x8]; 5341 u8 qpn[0x18]; 5342 5343 u8 reserved_at_60[0x20]; 5344 5345 u8 opt_param_mask[0x20]; 5346 5347 u8 ece[0x20]; 5348 5349 struct mlx5_ifc_qpc_bits qpc; 5350 5351 u8 reserved_at_800[0x80]; 5352 }; 5353 5354 struct mlx5_ifc_rst2init_qp_out_bits { 5355 u8 status[0x8]; 5356 u8 reserved_at_8[0x18]; 5357 5358 u8 syndrome[0x20]; 5359 5360 u8 reserved_at_40[0x20]; 5361 u8 ece[0x20]; 5362 }; 5363 5364 struct mlx5_ifc_rst2init_qp_in_bits { 5365 u8 opcode[0x10]; 5366 u8 uid[0x10]; 5367 5368 u8 reserved_at_20[0x10]; 5369 u8 op_mod[0x10]; 5370 5371 u8 reserved_at_40[0x8]; 5372 u8 qpn[0x18]; 5373 5374 u8 reserved_at_60[0x20]; 5375 5376 u8 opt_param_mask[0x20]; 5377 5378 u8 ece[0x20]; 5379 5380 struct mlx5_ifc_qpc_bits qpc; 5381 5382 u8 reserved_at_800[0x80]; 5383 }; 5384 5385 struct mlx5_ifc_query_xrq_out_bits { 5386 u8 status[0x8]; 5387 u8 reserved_at_8[0x18]; 5388 5389 u8 syndrome[0x20]; 5390 5391 u8 reserved_at_40[0x40]; 5392 5393 struct mlx5_ifc_xrqc_bits xrq_context; 5394 }; 5395 5396 struct mlx5_ifc_query_xrq_in_bits { 5397 u8 opcode[0x10]; 5398 u8 reserved_at_10[0x10]; 5399 5400 u8 reserved_at_20[0x10]; 5401 u8 op_mod[0x10]; 5402 5403 u8 reserved_at_40[0x8]; 5404 u8 xrqn[0x18]; 5405 5406 u8 reserved_at_60[0x20]; 5407 }; 5408 5409 struct mlx5_ifc_query_xrc_srq_out_bits { 5410 u8 status[0x8]; 5411 u8 reserved_at_8[0x18]; 5412 5413 u8 syndrome[0x20]; 5414 5415 u8 reserved_at_40[0x40]; 5416 5417 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 5418 5419 u8 reserved_at_280[0x600]; 5420 5421 u8 pas[][0x40]; 5422 }; 5423 5424 struct mlx5_ifc_query_xrc_srq_in_bits { 5425 u8 opcode[0x10]; 5426 u8 reserved_at_10[0x10]; 5427 5428 u8 reserved_at_20[0x10]; 5429 u8 op_mod[0x10]; 5430 5431 u8 reserved_at_40[0x8]; 5432 u8 xrc_srqn[0x18]; 5433 5434 u8 reserved_at_60[0x20]; 5435 }; 5436 5437 enum { 5438 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 5439 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 5440 }; 5441 5442 struct mlx5_ifc_query_vport_state_out_bits { 5443 u8 status[0x8]; 5444 u8 reserved_at_8[0x18]; 5445 5446 u8 syndrome[0x20]; 5447 5448 u8 reserved_at_40[0x20]; 5449 5450 u8 max_tx_speed[0x10]; 5451 u8 reserved_at_70[0x8]; 5452 u8 admin_state[0x4]; 5453 u8 state[0x4]; 5454 }; 5455 5456 struct mlx5_ifc_array1024_auto_bits { 5457 u8 array1024_auto[32][0x20]; 5458 }; 5459 5460 struct mlx5_ifc_query_vuid_in_bits { 5461 u8 opcode[0x10]; 5462 u8 uid[0x10]; 5463 5464 u8 reserved_at_20[0x40]; 5465 5466 u8 query_vfs_vuid[0x1]; 5467 u8 data_direct[0x1]; 5468 u8 reserved_at_62[0xe]; 5469 u8 vhca_id[0x10]; 5470 }; 5471 5472 struct mlx5_ifc_query_vuid_out_bits { 5473 u8 status[0x8]; 5474 u8 reserved_at_8[0x18]; 5475 5476 u8 syndrome[0x20]; 5477 5478 u8 reserved_at_40[0x1a0]; 5479 5480 u8 reserved_at_1e0[0x10]; 5481 u8 num_of_entries[0x10]; 5482 5483 struct mlx5_ifc_array1024_auto_bits vuid[]; 5484 }; 5485 5486 enum { 5487 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 5488 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 5489 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 5490 }; 5491 5492 struct mlx5_ifc_arm_monitor_counter_in_bits { 5493 u8 opcode[0x10]; 5494 u8 uid[0x10]; 5495 5496 u8 reserved_at_20[0x10]; 5497 u8 op_mod[0x10]; 5498 5499 u8 reserved_at_40[0x20]; 5500 5501 u8 reserved_at_60[0x20]; 5502 }; 5503 5504 struct mlx5_ifc_arm_monitor_counter_out_bits { 5505 u8 status[0x8]; 5506 u8 reserved_at_8[0x18]; 5507 5508 u8 syndrome[0x20]; 5509 5510 u8 reserved_at_40[0x40]; 5511 }; 5512 5513 enum { 5514 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 5515 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 5516 }; 5517 5518 enum mlx5_monitor_counter_ppcnt { 5519 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5520 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5521 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5522 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5523 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5524 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5525 }; 5526 5527 enum { 5528 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5529 }; 5530 5531 struct mlx5_ifc_monitor_counter_output_bits { 5532 u8 reserved_at_0[0x4]; 5533 u8 type[0x4]; 5534 u8 reserved_at_8[0x8]; 5535 u8 counter[0x10]; 5536 5537 u8 counter_group_id[0x20]; 5538 }; 5539 5540 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5541 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5542 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5543 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5544 5545 struct mlx5_ifc_set_monitor_counter_in_bits { 5546 u8 opcode[0x10]; 5547 u8 uid[0x10]; 5548 5549 u8 reserved_at_20[0x10]; 5550 u8 op_mod[0x10]; 5551 5552 u8 reserved_at_40[0x10]; 5553 u8 num_of_counters[0x10]; 5554 5555 u8 reserved_at_60[0x20]; 5556 5557 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5558 }; 5559 5560 struct mlx5_ifc_set_monitor_counter_out_bits { 5561 u8 status[0x8]; 5562 u8 reserved_at_8[0x18]; 5563 5564 u8 syndrome[0x20]; 5565 5566 u8 reserved_at_40[0x40]; 5567 }; 5568 5569 struct mlx5_ifc_query_vport_state_in_bits { 5570 u8 opcode[0x10]; 5571 u8 reserved_at_10[0x10]; 5572 5573 u8 reserved_at_20[0x10]; 5574 u8 op_mod[0x10]; 5575 5576 u8 other_vport[0x1]; 5577 u8 reserved_at_41[0xf]; 5578 u8 vport_number[0x10]; 5579 5580 u8 reserved_at_60[0x20]; 5581 }; 5582 5583 struct mlx5_ifc_query_vnic_env_out_bits { 5584 u8 status[0x8]; 5585 u8 reserved_at_8[0x18]; 5586 5587 u8 syndrome[0x20]; 5588 5589 u8 reserved_at_40[0x40]; 5590 5591 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5592 }; 5593 5594 enum { 5595 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5596 }; 5597 5598 struct mlx5_ifc_query_vnic_env_in_bits { 5599 u8 opcode[0x10]; 5600 u8 reserved_at_10[0x10]; 5601 5602 u8 reserved_at_20[0x10]; 5603 u8 op_mod[0x10]; 5604 5605 u8 other_vport[0x1]; 5606 u8 reserved_at_41[0xf]; 5607 u8 vport_number[0x10]; 5608 5609 u8 reserved_at_60[0x20]; 5610 }; 5611 5612 struct mlx5_ifc_query_vport_counter_out_bits { 5613 u8 status[0x8]; 5614 u8 reserved_at_8[0x18]; 5615 5616 u8 syndrome[0x20]; 5617 5618 u8 reserved_at_40[0x40]; 5619 5620 struct mlx5_ifc_traffic_counter_bits received_errors; 5621 5622 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5623 5624 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5625 5626 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5627 5628 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5629 5630 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5631 5632 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5633 5634 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5635 5636 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5637 5638 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5639 5640 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5641 5642 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5643 5644 struct mlx5_ifc_traffic_counter_bits local_loopback; 5645 5646 u8 reserved_at_700[0x980]; 5647 }; 5648 5649 enum { 5650 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5651 }; 5652 5653 struct mlx5_ifc_query_vport_counter_in_bits { 5654 u8 opcode[0x10]; 5655 u8 reserved_at_10[0x10]; 5656 5657 u8 reserved_at_20[0x10]; 5658 u8 op_mod[0x10]; 5659 5660 u8 other_vport[0x1]; 5661 u8 reserved_at_41[0xb]; 5662 u8 port_num[0x4]; 5663 u8 vport_number[0x10]; 5664 5665 u8 reserved_at_60[0x60]; 5666 5667 u8 clear[0x1]; 5668 u8 reserved_at_c1[0x1f]; 5669 5670 u8 reserved_at_e0[0x20]; 5671 }; 5672 5673 struct mlx5_ifc_query_tis_out_bits { 5674 u8 status[0x8]; 5675 u8 reserved_at_8[0x18]; 5676 5677 u8 syndrome[0x20]; 5678 5679 u8 reserved_at_40[0x40]; 5680 5681 struct mlx5_ifc_tisc_bits tis_context; 5682 }; 5683 5684 struct mlx5_ifc_query_tis_in_bits { 5685 u8 opcode[0x10]; 5686 u8 reserved_at_10[0x10]; 5687 5688 u8 reserved_at_20[0x10]; 5689 u8 op_mod[0x10]; 5690 5691 u8 reserved_at_40[0x8]; 5692 u8 tisn[0x18]; 5693 5694 u8 reserved_at_60[0x20]; 5695 }; 5696 5697 struct mlx5_ifc_query_tir_out_bits { 5698 u8 status[0x8]; 5699 u8 reserved_at_8[0x18]; 5700 5701 u8 syndrome[0x20]; 5702 5703 u8 reserved_at_40[0xc0]; 5704 5705 struct mlx5_ifc_tirc_bits tir_context; 5706 }; 5707 5708 struct mlx5_ifc_query_tir_in_bits { 5709 u8 opcode[0x10]; 5710 u8 reserved_at_10[0x10]; 5711 5712 u8 reserved_at_20[0x10]; 5713 u8 op_mod[0x10]; 5714 5715 u8 reserved_at_40[0x8]; 5716 u8 tirn[0x18]; 5717 5718 u8 reserved_at_60[0x20]; 5719 }; 5720 5721 struct mlx5_ifc_query_srq_out_bits { 5722 u8 status[0x8]; 5723 u8 reserved_at_8[0x18]; 5724 5725 u8 syndrome[0x20]; 5726 5727 u8 reserved_at_40[0x40]; 5728 5729 struct mlx5_ifc_srqc_bits srq_context_entry; 5730 5731 u8 reserved_at_280[0x600]; 5732 5733 u8 pas[][0x40]; 5734 }; 5735 5736 struct mlx5_ifc_query_srq_in_bits { 5737 u8 opcode[0x10]; 5738 u8 reserved_at_10[0x10]; 5739 5740 u8 reserved_at_20[0x10]; 5741 u8 op_mod[0x10]; 5742 5743 u8 reserved_at_40[0x8]; 5744 u8 srqn[0x18]; 5745 5746 u8 reserved_at_60[0x20]; 5747 }; 5748 5749 struct mlx5_ifc_query_sq_out_bits { 5750 u8 status[0x8]; 5751 u8 reserved_at_8[0x18]; 5752 5753 u8 syndrome[0x20]; 5754 5755 u8 reserved_at_40[0xc0]; 5756 5757 struct mlx5_ifc_sqc_bits sq_context; 5758 }; 5759 5760 struct mlx5_ifc_query_sq_in_bits { 5761 u8 opcode[0x10]; 5762 u8 reserved_at_10[0x10]; 5763 5764 u8 reserved_at_20[0x10]; 5765 u8 op_mod[0x10]; 5766 5767 u8 reserved_at_40[0x8]; 5768 u8 sqn[0x18]; 5769 5770 u8 reserved_at_60[0x20]; 5771 }; 5772 5773 struct mlx5_ifc_query_special_contexts_out_bits { 5774 u8 status[0x8]; 5775 u8 reserved_at_8[0x18]; 5776 5777 u8 syndrome[0x20]; 5778 5779 u8 dump_fill_mkey[0x20]; 5780 5781 u8 resd_lkey[0x20]; 5782 5783 u8 null_mkey[0x20]; 5784 5785 u8 terminate_scatter_list_mkey[0x20]; 5786 5787 u8 repeated_mkey[0x20]; 5788 5789 u8 reserved_at_a0[0x20]; 5790 }; 5791 5792 struct mlx5_ifc_query_special_contexts_in_bits { 5793 u8 opcode[0x10]; 5794 u8 reserved_at_10[0x10]; 5795 5796 u8 reserved_at_20[0x10]; 5797 u8 op_mod[0x10]; 5798 5799 u8 reserved_at_40[0x40]; 5800 }; 5801 5802 struct mlx5_ifc_query_scheduling_element_out_bits { 5803 u8 opcode[0x10]; 5804 u8 reserved_at_10[0x10]; 5805 5806 u8 reserved_at_20[0x10]; 5807 u8 op_mod[0x10]; 5808 5809 u8 reserved_at_40[0xc0]; 5810 5811 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5812 5813 u8 reserved_at_300[0x100]; 5814 }; 5815 5816 enum { 5817 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5818 SCHEDULING_HIERARCHY_NIC = 0x3, 5819 }; 5820 5821 struct mlx5_ifc_query_scheduling_element_in_bits { 5822 u8 opcode[0x10]; 5823 u8 reserved_at_10[0x10]; 5824 5825 u8 reserved_at_20[0x10]; 5826 u8 op_mod[0x10]; 5827 5828 u8 scheduling_hierarchy[0x8]; 5829 u8 reserved_at_48[0x18]; 5830 5831 u8 scheduling_element_id[0x20]; 5832 5833 u8 reserved_at_80[0x180]; 5834 }; 5835 5836 struct mlx5_ifc_query_rqt_out_bits { 5837 u8 status[0x8]; 5838 u8 reserved_at_8[0x18]; 5839 5840 u8 syndrome[0x20]; 5841 5842 u8 reserved_at_40[0xc0]; 5843 5844 struct mlx5_ifc_rqtc_bits rqt_context; 5845 }; 5846 5847 struct mlx5_ifc_query_rqt_in_bits { 5848 u8 opcode[0x10]; 5849 u8 reserved_at_10[0x10]; 5850 5851 u8 reserved_at_20[0x10]; 5852 u8 op_mod[0x10]; 5853 5854 u8 reserved_at_40[0x8]; 5855 u8 rqtn[0x18]; 5856 5857 u8 reserved_at_60[0x20]; 5858 }; 5859 5860 struct mlx5_ifc_query_rq_out_bits { 5861 u8 status[0x8]; 5862 u8 reserved_at_8[0x18]; 5863 5864 u8 syndrome[0x20]; 5865 5866 u8 reserved_at_40[0xc0]; 5867 5868 struct mlx5_ifc_rqc_bits rq_context; 5869 }; 5870 5871 struct mlx5_ifc_query_rq_in_bits { 5872 u8 opcode[0x10]; 5873 u8 reserved_at_10[0x10]; 5874 5875 u8 reserved_at_20[0x10]; 5876 u8 op_mod[0x10]; 5877 5878 u8 reserved_at_40[0x8]; 5879 u8 rqn[0x18]; 5880 5881 u8 reserved_at_60[0x20]; 5882 }; 5883 5884 struct mlx5_ifc_query_roce_address_out_bits { 5885 u8 status[0x8]; 5886 u8 reserved_at_8[0x18]; 5887 5888 u8 syndrome[0x20]; 5889 5890 u8 reserved_at_40[0x40]; 5891 5892 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5893 }; 5894 5895 struct mlx5_ifc_query_roce_address_in_bits { 5896 u8 opcode[0x10]; 5897 u8 reserved_at_10[0x10]; 5898 5899 u8 reserved_at_20[0x10]; 5900 u8 op_mod[0x10]; 5901 5902 u8 roce_address_index[0x10]; 5903 u8 reserved_at_50[0xc]; 5904 u8 vhca_port_num[0x4]; 5905 5906 u8 reserved_at_60[0x20]; 5907 }; 5908 5909 struct mlx5_ifc_query_rmp_out_bits { 5910 u8 status[0x8]; 5911 u8 reserved_at_8[0x18]; 5912 5913 u8 syndrome[0x20]; 5914 5915 u8 reserved_at_40[0xc0]; 5916 5917 struct mlx5_ifc_rmpc_bits rmp_context; 5918 }; 5919 5920 struct mlx5_ifc_query_rmp_in_bits { 5921 u8 opcode[0x10]; 5922 u8 reserved_at_10[0x10]; 5923 5924 u8 reserved_at_20[0x10]; 5925 u8 op_mod[0x10]; 5926 5927 u8 reserved_at_40[0x8]; 5928 u8 rmpn[0x18]; 5929 5930 u8 reserved_at_60[0x20]; 5931 }; 5932 5933 struct mlx5_ifc_cqe_error_syndrome_bits { 5934 u8 hw_error_syndrome[0x8]; 5935 u8 hw_syndrome_type[0x4]; 5936 u8 reserved_at_c[0x4]; 5937 u8 vendor_error_syndrome[0x8]; 5938 u8 syndrome[0x8]; 5939 }; 5940 5941 struct mlx5_ifc_qp_context_extension_bits { 5942 u8 reserved_at_0[0x60]; 5943 5944 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5945 5946 u8 reserved_at_80[0x580]; 5947 }; 5948 5949 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5950 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5951 5952 u8 pas[0][0x40]; 5953 }; 5954 5955 struct mlx5_ifc_qp_pas_list_in_bits { 5956 struct mlx5_ifc_cmd_pas_bits pas[0]; 5957 }; 5958 5959 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5960 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5961 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5962 }; 5963 5964 struct mlx5_ifc_query_qp_out_bits { 5965 u8 status[0x8]; 5966 u8 reserved_at_8[0x18]; 5967 5968 u8 syndrome[0x20]; 5969 5970 u8 reserved_at_40[0x40]; 5971 5972 u8 opt_param_mask[0x20]; 5973 5974 u8 ece[0x20]; 5975 5976 struct mlx5_ifc_qpc_bits qpc; 5977 5978 u8 reserved_at_800[0x80]; 5979 5980 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 5981 }; 5982 5983 struct mlx5_ifc_query_qp_in_bits { 5984 u8 opcode[0x10]; 5985 u8 reserved_at_10[0x10]; 5986 5987 u8 reserved_at_20[0x10]; 5988 u8 op_mod[0x10]; 5989 5990 u8 qpc_ext[0x1]; 5991 u8 reserved_at_41[0x7]; 5992 u8 qpn[0x18]; 5993 5994 u8 reserved_at_60[0x20]; 5995 }; 5996 5997 struct mlx5_ifc_query_q_counter_out_bits { 5998 u8 status[0x8]; 5999 u8 reserved_at_8[0x18]; 6000 6001 u8 syndrome[0x20]; 6002 6003 u8 reserved_at_40[0x40]; 6004 6005 u8 rx_write_requests[0x20]; 6006 6007 u8 reserved_at_a0[0x20]; 6008 6009 u8 rx_read_requests[0x20]; 6010 6011 u8 reserved_at_e0[0x20]; 6012 6013 u8 rx_atomic_requests[0x20]; 6014 6015 u8 reserved_at_120[0x20]; 6016 6017 u8 rx_dct_connect[0x20]; 6018 6019 u8 reserved_at_160[0x20]; 6020 6021 u8 out_of_buffer[0x20]; 6022 6023 u8 reserved_at_1a0[0x20]; 6024 6025 u8 out_of_sequence[0x20]; 6026 6027 u8 reserved_at_1e0[0x20]; 6028 6029 u8 duplicate_request[0x20]; 6030 6031 u8 reserved_at_220[0x20]; 6032 6033 u8 rnr_nak_retry_err[0x20]; 6034 6035 u8 reserved_at_260[0x20]; 6036 6037 u8 packet_seq_err[0x20]; 6038 6039 u8 reserved_at_2a0[0x20]; 6040 6041 u8 implied_nak_seq_err[0x20]; 6042 6043 u8 reserved_at_2e0[0x20]; 6044 6045 u8 local_ack_timeout_err[0x20]; 6046 6047 u8 reserved_at_320[0x60]; 6048 6049 u8 req_rnr_retries_exceeded[0x20]; 6050 6051 u8 reserved_at_3a0[0x20]; 6052 6053 u8 resp_local_length_error[0x20]; 6054 6055 u8 req_local_length_error[0x20]; 6056 6057 u8 resp_local_qp_error[0x20]; 6058 6059 u8 local_operation_error[0x20]; 6060 6061 u8 resp_local_protection[0x20]; 6062 6063 u8 req_local_protection[0x20]; 6064 6065 u8 resp_cqe_error[0x20]; 6066 6067 u8 req_cqe_error[0x20]; 6068 6069 u8 req_mw_binding[0x20]; 6070 6071 u8 req_bad_response[0x20]; 6072 6073 u8 req_remote_invalid_request[0x20]; 6074 6075 u8 resp_remote_invalid_request[0x20]; 6076 6077 u8 req_remote_access_errors[0x20]; 6078 6079 u8 resp_remote_access_errors[0x20]; 6080 6081 u8 req_remote_operation_errors[0x20]; 6082 6083 u8 req_transport_retries_exceeded[0x20]; 6084 6085 u8 cq_overflow[0x20]; 6086 6087 u8 resp_cqe_flush_error[0x20]; 6088 6089 u8 req_cqe_flush_error[0x20]; 6090 6091 u8 reserved_at_620[0x20]; 6092 6093 u8 roce_adp_retrans[0x20]; 6094 6095 u8 roce_adp_retrans_to[0x20]; 6096 6097 u8 roce_slow_restart[0x20]; 6098 6099 u8 roce_slow_restart_cnps[0x20]; 6100 6101 u8 roce_slow_restart_trans[0x20]; 6102 6103 u8 reserved_at_6e0[0x120]; 6104 }; 6105 6106 struct mlx5_ifc_query_q_counter_in_bits { 6107 u8 opcode[0x10]; 6108 u8 reserved_at_10[0x10]; 6109 6110 u8 reserved_at_20[0x10]; 6111 u8 op_mod[0x10]; 6112 6113 u8 other_vport[0x1]; 6114 u8 reserved_at_41[0xf]; 6115 u8 vport_number[0x10]; 6116 6117 u8 reserved_at_60[0x60]; 6118 6119 u8 clear[0x1]; 6120 u8 aggregate[0x1]; 6121 u8 reserved_at_c2[0x1e]; 6122 6123 u8 reserved_at_e0[0x18]; 6124 u8 counter_set_id[0x8]; 6125 }; 6126 6127 struct mlx5_ifc_query_pages_out_bits { 6128 u8 status[0x8]; 6129 u8 reserved_at_8[0x18]; 6130 6131 u8 syndrome[0x20]; 6132 6133 u8 embedded_cpu_function[0x1]; 6134 u8 reserved_at_41[0xf]; 6135 u8 function_id[0x10]; 6136 6137 u8 num_pages[0x20]; 6138 }; 6139 6140 enum { 6141 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 6142 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 6143 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 6144 }; 6145 6146 struct mlx5_ifc_query_pages_in_bits { 6147 u8 opcode[0x10]; 6148 u8 reserved_at_10[0x10]; 6149 6150 u8 reserved_at_20[0x10]; 6151 u8 op_mod[0x10]; 6152 6153 u8 embedded_cpu_function[0x1]; 6154 u8 reserved_at_41[0xf]; 6155 u8 function_id[0x10]; 6156 6157 u8 reserved_at_60[0x20]; 6158 }; 6159 6160 struct mlx5_ifc_query_nic_vport_context_out_bits { 6161 u8 status[0x8]; 6162 u8 reserved_at_8[0x18]; 6163 6164 u8 syndrome[0x20]; 6165 6166 u8 reserved_at_40[0x40]; 6167 6168 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6169 }; 6170 6171 struct mlx5_ifc_query_nic_vport_context_in_bits { 6172 u8 opcode[0x10]; 6173 u8 reserved_at_10[0x10]; 6174 6175 u8 reserved_at_20[0x10]; 6176 u8 op_mod[0x10]; 6177 6178 u8 other_vport[0x1]; 6179 u8 reserved_at_41[0xf]; 6180 u8 vport_number[0x10]; 6181 6182 u8 reserved_at_60[0x5]; 6183 u8 allowed_list_type[0x3]; 6184 u8 reserved_at_68[0x18]; 6185 }; 6186 6187 struct mlx5_ifc_query_mkey_out_bits { 6188 u8 status[0x8]; 6189 u8 reserved_at_8[0x18]; 6190 6191 u8 syndrome[0x20]; 6192 6193 u8 reserved_at_40[0x40]; 6194 6195 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 6196 6197 u8 reserved_at_280[0x600]; 6198 6199 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 6200 6201 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 6202 }; 6203 6204 struct mlx5_ifc_query_mkey_in_bits { 6205 u8 opcode[0x10]; 6206 u8 reserved_at_10[0x10]; 6207 6208 u8 reserved_at_20[0x10]; 6209 u8 op_mod[0x10]; 6210 6211 u8 reserved_at_40[0x8]; 6212 u8 mkey_index[0x18]; 6213 6214 u8 pg_access[0x1]; 6215 u8 reserved_at_61[0x1f]; 6216 }; 6217 6218 struct mlx5_ifc_query_mad_demux_out_bits { 6219 u8 status[0x8]; 6220 u8 reserved_at_8[0x18]; 6221 6222 u8 syndrome[0x20]; 6223 6224 u8 reserved_at_40[0x40]; 6225 6226 u8 mad_dumux_parameters_block[0x20]; 6227 }; 6228 6229 struct mlx5_ifc_query_mad_demux_in_bits { 6230 u8 opcode[0x10]; 6231 u8 reserved_at_10[0x10]; 6232 6233 u8 reserved_at_20[0x10]; 6234 u8 op_mod[0x10]; 6235 6236 u8 reserved_at_40[0x40]; 6237 }; 6238 6239 struct mlx5_ifc_query_l2_table_entry_out_bits { 6240 u8 status[0x8]; 6241 u8 reserved_at_8[0x18]; 6242 6243 u8 syndrome[0x20]; 6244 6245 u8 reserved_at_40[0xa0]; 6246 6247 u8 reserved_at_e0[0x13]; 6248 u8 vlan_valid[0x1]; 6249 u8 vlan[0xc]; 6250 6251 struct mlx5_ifc_mac_address_layout_bits mac_address; 6252 6253 u8 reserved_at_140[0xc0]; 6254 }; 6255 6256 struct mlx5_ifc_query_l2_table_entry_in_bits { 6257 u8 opcode[0x10]; 6258 u8 reserved_at_10[0x10]; 6259 6260 u8 reserved_at_20[0x10]; 6261 u8 op_mod[0x10]; 6262 6263 u8 reserved_at_40[0x60]; 6264 6265 u8 reserved_at_a0[0x8]; 6266 u8 table_index[0x18]; 6267 6268 u8 reserved_at_c0[0x140]; 6269 }; 6270 6271 struct mlx5_ifc_query_issi_out_bits { 6272 u8 status[0x8]; 6273 u8 reserved_at_8[0x18]; 6274 6275 u8 syndrome[0x20]; 6276 6277 u8 reserved_at_40[0x10]; 6278 u8 current_issi[0x10]; 6279 6280 u8 reserved_at_60[0xa0]; 6281 6282 u8 reserved_at_100[76][0x8]; 6283 u8 supported_issi_dw0[0x20]; 6284 }; 6285 6286 struct mlx5_ifc_query_issi_in_bits { 6287 u8 opcode[0x10]; 6288 u8 reserved_at_10[0x10]; 6289 6290 u8 reserved_at_20[0x10]; 6291 u8 op_mod[0x10]; 6292 6293 u8 reserved_at_40[0x40]; 6294 }; 6295 6296 struct mlx5_ifc_set_driver_version_out_bits { 6297 u8 status[0x8]; 6298 u8 reserved_0[0x18]; 6299 6300 u8 syndrome[0x20]; 6301 u8 reserved_1[0x40]; 6302 }; 6303 6304 struct mlx5_ifc_set_driver_version_in_bits { 6305 u8 opcode[0x10]; 6306 u8 reserved_0[0x10]; 6307 6308 u8 reserved_1[0x10]; 6309 u8 op_mod[0x10]; 6310 6311 u8 reserved_2[0x40]; 6312 u8 driver_version[64][0x8]; 6313 }; 6314 6315 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 6316 u8 status[0x8]; 6317 u8 reserved_at_8[0x18]; 6318 6319 u8 syndrome[0x20]; 6320 6321 u8 reserved_at_40[0x40]; 6322 6323 struct mlx5_ifc_pkey_bits pkey[]; 6324 }; 6325 6326 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 6327 u8 opcode[0x10]; 6328 u8 reserved_at_10[0x10]; 6329 6330 u8 reserved_at_20[0x10]; 6331 u8 op_mod[0x10]; 6332 6333 u8 other_vport[0x1]; 6334 u8 reserved_at_41[0xb]; 6335 u8 port_num[0x4]; 6336 u8 vport_number[0x10]; 6337 6338 u8 reserved_at_60[0x10]; 6339 u8 pkey_index[0x10]; 6340 }; 6341 6342 enum { 6343 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 6344 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 6345 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 6346 }; 6347 6348 struct mlx5_ifc_query_hca_vport_gid_out_bits { 6349 u8 status[0x8]; 6350 u8 reserved_at_8[0x18]; 6351 6352 u8 syndrome[0x20]; 6353 6354 u8 reserved_at_40[0x20]; 6355 6356 u8 gids_num[0x10]; 6357 u8 reserved_at_70[0x10]; 6358 6359 struct mlx5_ifc_array128_auto_bits gid[]; 6360 }; 6361 6362 struct mlx5_ifc_query_hca_vport_gid_in_bits { 6363 u8 opcode[0x10]; 6364 u8 reserved_at_10[0x10]; 6365 6366 u8 reserved_at_20[0x10]; 6367 u8 op_mod[0x10]; 6368 6369 u8 other_vport[0x1]; 6370 u8 reserved_at_41[0xb]; 6371 u8 port_num[0x4]; 6372 u8 vport_number[0x10]; 6373 6374 u8 reserved_at_60[0x10]; 6375 u8 gid_index[0x10]; 6376 }; 6377 6378 struct mlx5_ifc_query_hca_vport_context_out_bits { 6379 u8 status[0x8]; 6380 u8 reserved_at_8[0x18]; 6381 6382 u8 syndrome[0x20]; 6383 6384 u8 reserved_at_40[0x40]; 6385 6386 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6387 }; 6388 6389 struct mlx5_ifc_query_hca_vport_context_in_bits { 6390 u8 opcode[0x10]; 6391 u8 reserved_at_10[0x10]; 6392 6393 u8 reserved_at_20[0x10]; 6394 u8 op_mod[0x10]; 6395 6396 u8 other_vport[0x1]; 6397 u8 reserved_at_41[0xb]; 6398 u8 port_num[0x4]; 6399 u8 vport_number[0x10]; 6400 6401 u8 reserved_at_60[0x20]; 6402 }; 6403 6404 struct mlx5_ifc_query_hca_cap_out_bits { 6405 u8 status[0x8]; 6406 u8 reserved_at_8[0x18]; 6407 6408 u8 syndrome[0x20]; 6409 6410 u8 reserved_at_40[0x40]; 6411 6412 union mlx5_ifc_hca_cap_union_bits capability; 6413 }; 6414 6415 struct mlx5_ifc_query_hca_cap_in_bits { 6416 u8 opcode[0x10]; 6417 u8 reserved_at_10[0x10]; 6418 6419 u8 reserved_at_20[0x10]; 6420 u8 op_mod[0x10]; 6421 6422 u8 other_function[0x1]; 6423 u8 ec_vf_function[0x1]; 6424 u8 reserved_at_42[0x1]; 6425 u8 function_id_type[0x1]; 6426 u8 reserved_at_44[0xc]; 6427 u8 function_id[0x10]; 6428 6429 u8 reserved_at_60[0x20]; 6430 }; 6431 6432 struct mlx5_ifc_other_hca_cap_bits { 6433 u8 roce[0x1]; 6434 u8 reserved_at_1[0x27f]; 6435 }; 6436 6437 struct mlx5_ifc_query_other_hca_cap_out_bits { 6438 u8 status[0x8]; 6439 u8 reserved_at_8[0x18]; 6440 6441 u8 syndrome[0x20]; 6442 6443 u8 reserved_at_40[0x40]; 6444 6445 struct mlx5_ifc_other_hca_cap_bits other_capability; 6446 }; 6447 6448 struct mlx5_ifc_query_other_hca_cap_in_bits { 6449 u8 opcode[0x10]; 6450 u8 reserved_at_10[0x10]; 6451 6452 u8 reserved_at_20[0x10]; 6453 u8 op_mod[0x10]; 6454 6455 u8 reserved_at_40[0x10]; 6456 u8 function_id[0x10]; 6457 6458 u8 reserved_at_60[0x20]; 6459 }; 6460 6461 struct mlx5_ifc_modify_other_hca_cap_out_bits { 6462 u8 status[0x8]; 6463 u8 reserved_at_8[0x18]; 6464 6465 u8 syndrome[0x20]; 6466 6467 u8 reserved_at_40[0x40]; 6468 }; 6469 6470 struct mlx5_ifc_modify_other_hca_cap_in_bits { 6471 u8 opcode[0x10]; 6472 u8 reserved_at_10[0x10]; 6473 6474 u8 reserved_at_20[0x10]; 6475 u8 op_mod[0x10]; 6476 6477 u8 reserved_at_40[0x10]; 6478 u8 function_id[0x10]; 6479 u8 field_select[0x20]; 6480 6481 struct mlx5_ifc_other_hca_cap_bits other_capability; 6482 }; 6483 6484 struct mlx5_ifc_sw_owner_icm_root_params_bits { 6485 u8 sw_owner_icm_root_1[0x40]; 6486 6487 u8 sw_owner_icm_root_0[0x40]; 6488 }; 6489 6490 struct mlx5_ifc_rtc_params_bits { 6491 u8 rtc_id_0[0x20]; 6492 6493 u8 rtc_id_1[0x20]; 6494 6495 u8 reserved_at_40[0x40]; 6496 }; 6497 6498 struct mlx5_ifc_flow_table_context_bits { 6499 u8 reformat_en[0x1]; 6500 u8 decap_en[0x1]; 6501 u8 sw_owner[0x1]; 6502 u8 termination_table[0x1]; 6503 u8 table_miss_action[0x4]; 6504 u8 level[0x8]; 6505 u8 rtc_valid[0x1]; 6506 u8 reserved_at_11[0x7]; 6507 u8 log_size[0x8]; 6508 6509 u8 reserved_at_20[0x8]; 6510 u8 table_miss_id[0x18]; 6511 6512 u8 reserved_at_40[0x8]; 6513 u8 lag_master_next_table_id[0x18]; 6514 6515 u8 reserved_at_60[0x60]; 6516 6517 union { 6518 struct mlx5_ifc_sw_owner_icm_root_params_bits sws; 6519 struct mlx5_ifc_rtc_params_bits hws; 6520 }; 6521 }; 6522 6523 struct mlx5_ifc_query_flow_table_out_bits { 6524 u8 status[0x8]; 6525 u8 reserved_at_8[0x18]; 6526 6527 u8 syndrome[0x20]; 6528 6529 u8 reserved_at_40[0x80]; 6530 6531 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6532 }; 6533 6534 struct mlx5_ifc_query_flow_table_in_bits { 6535 u8 opcode[0x10]; 6536 u8 reserved_at_10[0x10]; 6537 6538 u8 reserved_at_20[0x10]; 6539 u8 op_mod[0x10]; 6540 6541 u8 reserved_at_40[0x40]; 6542 6543 u8 table_type[0x8]; 6544 u8 reserved_at_88[0x18]; 6545 6546 u8 reserved_at_a0[0x8]; 6547 u8 table_id[0x18]; 6548 6549 u8 reserved_at_c0[0x140]; 6550 }; 6551 6552 struct mlx5_ifc_query_fte_out_bits { 6553 u8 status[0x8]; 6554 u8 reserved_at_8[0x18]; 6555 6556 u8 syndrome[0x20]; 6557 6558 u8 reserved_at_40[0x1c0]; 6559 6560 struct mlx5_ifc_flow_context_bits flow_context; 6561 }; 6562 6563 struct mlx5_ifc_query_fte_in_bits { 6564 u8 opcode[0x10]; 6565 u8 reserved_at_10[0x10]; 6566 6567 u8 reserved_at_20[0x10]; 6568 u8 op_mod[0x10]; 6569 6570 u8 reserved_at_40[0x40]; 6571 6572 u8 table_type[0x8]; 6573 u8 reserved_at_88[0x18]; 6574 6575 u8 reserved_at_a0[0x8]; 6576 u8 table_id[0x18]; 6577 6578 u8 reserved_at_c0[0x40]; 6579 6580 u8 flow_index[0x20]; 6581 6582 u8 reserved_at_120[0xe0]; 6583 }; 6584 6585 struct mlx5_ifc_match_definer_format_0_bits { 6586 u8 reserved_at_0[0x100]; 6587 6588 u8 metadata_reg_c_0[0x20]; 6589 6590 u8 metadata_reg_c_1[0x20]; 6591 6592 u8 outer_dmac_47_16[0x20]; 6593 6594 u8 outer_dmac_15_0[0x10]; 6595 u8 outer_ethertype[0x10]; 6596 6597 u8 reserved_at_180[0x1]; 6598 u8 sx_sniffer[0x1]; 6599 u8 functional_lb[0x1]; 6600 u8 outer_ip_frag[0x1]; 6601 u8 outer_qp_type[0x2]; 6602 u8 outer_encap_type[0x2]; 6603 u8 port_number[0x2]; 6604 u8 outer_l3_type[0x2]; 6605 u8 outer_l4_type[0x2]; 6606 u8 outer_first_vlan_type[0x2]; 6607 u8 outer_first_vlan_prio[0x3]; 6608 u8 outer_first_vlan_cfi[0x1]; 6609 u8 outer_first_vlan_vid[0xc]; 6610 6611 u8 outer_l4_type_ext[0x4]; 6612 u8 reserved_at_1a4[0x2]; 6613 u8 outer_ipsec_layer[0x2]; 6614 u8 outer_l2_type[0x2]; 6615 u8 force_lb[0x1]; 6616 u8 outer_l2_ok[0x1]; 6617 u8 outer_l3_ok[0x1]; 6618 u8 outer_l4_ok[0x1]; 6619 u8 outer_second_vlan_type[0x2]; 6620 u8 outer_second_vlan_prio[0x3]; 6621 u8 outer_second_vlan_cfi[0x1]; 6622 u8 outer_second_vlan_vid[0xc]; 6623 6624 u8 outer_smac_47_16[0x20]; 6625 6626 u8 outer_smac_15_0[0x10]; 6627 u8 inner_ipv4_checksum_ok[0x1]; 6628 u8 inner_l4_checksum_ok[0x1]; 6629 u8 outer_ipv4_checksum_ok[0x1]; 6630 u8 outer_l4_checksum_ok[0x1]; 6631 u8 inner_l3_ok[0x1]; 6632 u8 inner_l4_ok[0x1]; 6633 u8 outer_l3_ok_duplicate[0x1]; 6634 u8 outer_l4_ok_duplicate[0x1]; 6635 u8 outer_tcp_cwr[0x1]; 6636 u8 outer_tcp_ece[0x1]; 6637 u8 outer_tcp_urg[0x1]; 6638 u8 outer_tcp_ack[0x1]; 6639 u8 outer_tcp_psh[0x1]; 6640 u8 outer_tcp_rst[0x1]; 6641 u8 outer_tcp_syn[0x1]; 6642 u8 outer_tcp_fin[0x1]; 6643 }; 6644 6645 struct mlx5_ifc_match_definer_format_22_bits { 6646 u8 reserved_at_0[0x100]; 6647 6648 u8 outer_ip_src_addr[0x20]; 6649 6650 u8 outer_ip_dest_addr[0x20]; 6651 6652 u8 outer_l4_sport[0x10]; 6653 u8 outer_l4_dport[0x10]; 6654 6655 u8 reserved_at_160[0x1]; 6656 u8 sx_sniffer[0x1]; 6657 u8 functional_lb[0x1]; 6658 u8 outer_ip_frag[0x1]; 6659 u8 outer_qp_type[0x2]; 6660 u8 outer_encap_type[0x2]; 6661 u8 port_number[0x2]; 6662 u8 outer_l3_type[0x2]; 6663 u8 outer_l4_type[0x2]; 6664 u8 outer_first_vlan_type[0x2]; 6665 u8 outer_first_vlan_prio[0x3]; 6666 u8 outer_first_vlan_cfi[0x1]; 6667 u8 outer_first_vlan_vid[0xc]; 6668 6669 u8 metadata_reg_c_0[0x20]; 6670 6671 u8 outer_dmac_47_16[0x20]; 6672 6673 u8 outer_smac_47_16[0x20]; 6674 6675 u8 outer_smac_15_0[0x10]; 6676 u8 outer_dmac_15_0[0x10]; 6677 }; 6678 6679 struct mlx5_ifc_match_definer_format_23_bits { 6680 u8 reserved_at_0[0x100]; 6681 6682 u8 inner_ip_src_addr[0x20]; 6683 6684 u8 inner_ip_dest_addr[0x20]; 6685 6686 u8 inner_l4_sport[0x10]; 6687 u8 inner_l4_dport[0x10]; 6688 6689 u8 reserved_at_160[0x1]; 6690 u8 sx_sniffer[0x1]; 6691 u8 functional_lb[0x1]; 6692 u8 inner_ip_frag[0x1]; 6693 u8 inner_qp_type[0x2]; 6694 u8 inner_encap_type[0x2]; 6695 u8 port_number[0x2]; 6696 u8 inner_l3_type[0x2]; 6697 u8 inner_l4_type[0x2]; 6698 u8 inner_first_vlan_type[0x2]; 6699 u8 inner_first_vlan_prio[0x3]; 6700 u8 inner_first_vlan_cfi[0x1]; 6701 u8 inner_first_vlan_vid[0xc]; 6702 6703 u8 tunnel_header_0[0x20]; 6704 6705 u8 inner_dmac_47_16[0x20]; 6706 6707 u8 inner_smac_47_16[0x20]; 6708 6709 u8 inner_smac_15_0[0x10]; 6710 u8 inner_dmac_15_0[0x10]; 6711 }; 6712 6713 struct mlx5_ifc_match_definer_format_29_bits { 6714 u8 reserved_at_0[0xc0]; 6715 6716 u8 outer_ip_dest_addr[0x80]; 6717 6718 u8 outer_ip_src_addr[0x80]; 6719 6720 u8 outer_l4_sport[0x10]; 6721 u8 outer_l4_dport[0x10]; 6722 6723 u8 reserved_at_1e0[0x20]; 6724 }; 6725 6726 struct mlx5_ifc_match_definer_format_30_bits { 6727 u8 reserved_at_0[0xa0]; 6728 6729 u8 outer_ip_dest_addr[0x80]; 6730 6731 u8 outer_ip_src_addr[0x80]; 6732 6733 u8 outer_dmac_47_16[0x20]; 6734 6735 u8 outer_smac_47_16[0x20]; 6736 6737 u8 outer_smac_15_0[0x10]; 6738 u8 outer_dmac_15_0[0x10]; 6739 }; 6740 6741 struct mlx5_ifc_match_definer_format_31_bits { 6742 u8 reserved_at_0[0xc0]; 6743 6744 u8 inner_ip_dest_addr[0x80]; 6745 6746 u8 inner_ip_src_addr[0x80]; 6747 6748 u8 inner_l4_sport[0x10]; 6749 u8 inner_l4_dport[0x10]; 6750 6751 u8 reserved_at_1e0[0x20]; 6752 }; 6753 6754 struct mlx5_ifc_match_definer_format_32_bits { 6755 u8 reserved_at_0[0xa0]; 6756 6757 u8 inner_ip_dest_addr[0x80]; 6758 6759 u8 inner_ip_src_addr[0x80]; 6760 6761 u8 inner_dmac_47_16[0x20]; 6762 6763 u8 inner_smac_47_16[0x20]; 6764 6765 u8 inner_smac_15_0[0x10]; 6766 u8 inner_dmac_15_0[0x10]; 6767 }; 6768 6769 enum { 6770 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6771 }; 6772 6773 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6774 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6775 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6776 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6777 6778 struct mlx5_ifc_match_definer_match_mask_bits { 6779 u8 reserved_at_1c0[5][0x20]; 6780 u8 match_dw_8[0x20]; 6781 u8 match_dw_7[0x20]; 6782 u8 match_dw_6[0x20]; 6783 u8 match_dw_5[0x20]; 6784 u8 match_dw_4[0x20]; 6785 u8 match_dw_3[0x20]; 6786 u8 match_dw_2[0x20]; 6787 u8 match_dw_1[0x20]; 6788 u8 match_dw_0[0x20]; 6789 6790 u8 match_byte_7[0x8]; 6791 u8 match_byte_6[0x8]; 6792 u8 match_byte_5[0x8]; 6793 u8 match_byte_4[0x8]; 6794 6795 u8 match_byte_3[0x8]; 6796 u8 match_byte_2[0x8]; 6797 u8 match_byte_1[0x8]; 6798 u8 match_byte_0[0x8]; 6799 }; 6800 6801 struct mlx5_ifc_match_definer_bits { 6802 u8 modify_field_select[0x40]; 6803 6804 u8 reserved_at_40[0x40]; 6805 6806 u8 reserved_at_80[0x10]; 6807 u8 format_id[0x10]; 6808 6809 u8 reserved_at_a0[0x60]; 6810 6811 u8 format_select_dw3[0x8]; 6812 u8 format_select_dw2[0x8]; 6813 u8 format_select_dw1[0x8]; 6814 u8 format_select_dw0[0x8]; 6815 6816 u8 format_select_dw7[0x8]; 6817 u8 format_select_dw6[0x8]; 6818 u8 format_select_dw5[0x8]; 6819 u8 format_select_dw4[0x8]; 6820 6821 u8 reserved_at_100[0x18]; 6822 u8 format_select_dw8[0x8]; 6823 6824 u8 reserved_at_120[0x20]; 6825 6826 u8 format_select_byte3[0x8]; 6827 u8 format_select_byte2[0x8]; 6828 u8 format_select_byte1[0x8]; 6829 u8 format_select_byte0[0x8]; 6830 6831 u8 format_select_byte7[0x8]; 6832 u8 format_select_byte6[0x8]; 6833 u8 format_select_byte5[0x8]; 6834 u8 format_select_byte4[0x8]; 6835 6836 u8 reserved_at_180[0x40]; 6837 6838 union { 6839 struct { 6840 u8 match_mask[16][0x20]; 6841 }; 6842 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6843 }; 6844 }; 6845 6846 struct mlx5_ifc_general_obj_create_param_bits { 6847 u8 alias_object[0x1]; 6848 u8 reserved_at_1[0x2]; 6849 u8 log_obj_range[0x5]; 6850 u8 reserved_at_8[0x18]; 6851 }; 6852 6853 struct mlx5_ifc_general_obj_query_param_bits { 6854 u8 alias_object[0x1]; 6855 u8 obj_offset[0x1f]; 6856 }; 6857 6858 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6859 u8 opcode[0x10]; 6860 u8 uid[0x10]; 6861 6862 u8 vhca_tunnel_id[0x10]; 6863 u8 obj_type[0x10]; 6864 6865 u8 obj_id[0x20]; 6866 6867 union { 6868 struct mlx5_ifc_general_obj_create_param_bits create; 6869 struct mlx5_ifc_general_obj_query_param_bits query; 6870 } op_param; 6871 }; 6872 6873 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6874 u8 status[0x8]; 6875 u8 reserved_at_8[0x18]; 6876 6877 u8 syndrome[0x20]; 6878 6879 u8 obj_id[0x20]; 6880 6881 u8 reserved_at_60[0x20]; 6882 }; 6883 6884 struct mlx5_ifc_allow_other_vhca_access_in_bits { 6885 u8 opcode[0x10]; 6886 u8 uid[0x10]; 6887 u8 reserved_at_20[0x10]; 6888 u8 op_mod[0x10]; 6889 u8 reserved_at_40[0x50]; 6890 u8 object_type_to_be_accessed[0x10]; 6891 u8 object_id_to_be_accessed[0x20]; 6892 u8 reserved_at_c0[0x40]; 6893 union { 6894 u8 access_key_raw[0x100]; 6895 u8 access_key[8][0x20]; 6896 }; 6897 }; 6898 6899 struct mlx5_ifc_allow_other_vhca_access_out_bits { 6900 u8 status[0x8]; 6901 u8 reserved_at_8[0x18]; 6902 u8 syndrome[0x20]; 6903 u8 reserved_at_40[0x40]; 6904 }; 6905 6906 struct mlx5_ifc_modify_header_arg_bits { 6907 u8 reserved_at_0[0x80]; 6908 6909 u8 reserved_at_80[0x8]; 6910 u8 access_pd[0x18]; 6911 }; 6912 6913 struct mlx5_ifc_create_modify_header_arg_in_bits { 6914 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6915 struct mlx5_ifc_modify_header_arg_bits arg; 6916 }; 6917 6918 struct mlx5_ifc_create_match_definer_in_bits { 6919 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6920 6921 struct mlx5_ifc_match_definer_bits obj_context; 6922 }; 6923 6924 struct mlx5_ifc_create_match_definer_out_bits { 6925 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6926 }; 6927 6928 struct mlx5_ifc_alias_context_bits { 6929 u8 vhca_id_to_be_accessed[0x10]; 6930 u8 reserved_at_10[0xd]; 6931 u8 status[0x3]; 6932 u8 object_id_to_be_accessed[0x20]; 6933 u8 reserved_at_40[0x40]; 6934 union { 6935 u8 access_key_raw[0x100]; 6936 u8 access_key[8][0x20]; 6937 }; 6938 u8 metadata[0x80]; 6939 }; 6940 6941 struct mlx5_ifc_create_alias_obj_in_bits { 6942 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6943 struct mlx5_ifc_alias_context_bits alias_ctx; 6944 }; 6945 6946 enum { 6947 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6948 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6949 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6950 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6951 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6952 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6953 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6954 }; 6955 6956 struct mlx5_ifc_query_flow_group_out_bits { 6957 u8 status[0x8]; 6958 u8 reserved_at_8[0x18]; 6959 6960 u8 syndrome[0x20]; 6961 6962 u8 reserved_at_40[0xa0]; 6963 6964 u8 start_flow_index[0x20]; 6965 6966 u8 reserved_at_100[0x20]; 6967 6968 u8 end_flow_index[0x20]; 6969 6970 u8 reserved_at_140[0xa0]; 6971 6972 u8 reserved_at_1e0[0x18]; 6973 u8 match_criteria_enable[0x8]; 6974 6975 struct mlx5_ifc_fte_match_param_bits match_criteria; 6976 6977 u8 reserved_at_1200[0xe00]; 6978 }; 6979 6980 struct mlx5_ifc_query_flow_group_in_bits { 6981 u8 opcode[0x10]; 6982 u8 reserved_at_10[0x10]; 6983 6984 u8 reserved_at_20[0x10]; 6985 u8 op_mod[0x10]; 6986 6987 u8 reserved_at_40[0x40]; 6988 6989 u8 table_type[0x8]; 6990 u8 reserved_at_88[0x18]; 6991 6992 u8 reserved_at_a0[0x8]; 6993 u8 table_id[0x18]; 6994 6995 u8 group_id[0x20]; 6996 6997 u8 reserved_at_e0[0x120]; 6998 }; 6999 7000 struct mlx5_ifc_query_flow_counter_out_bits { 7001 u8 status[0x8]; 7002 u8 reserved_at_8[0x18]; 7003 7004 u8 syndrome[0x20]; 7005 7006 u8 reserved_at_40[0x40]; 7007 7008 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 7009 }; 7010 7011 struct mlx5_ifc_query_flow_counter_in_bits { 7012 u8 opcode[0x10]; 7013 u8 reserved_at_10[0x10]; 7014 7015 u8 reserved_at_20[0x10]; 7016 u8 op_mod[0x10]; 7017 7018 u8 reserved_at_40[0x80]; 7019 7020 u8 clear[0x1]; 7021 u8 reserved_at_c1[0xf]; 7022 u8 num_of_counters[0x10]; 7023 7024 u8 flow_counter_id[0x20]; 7025 }; 7026 7027 struct mlx5_ifc_query_esw_vport_context_out_bits { 7028 u8 status[0x8]; 7029 u8 reserved_at_8[0x18]; 7030 7031 u8 syndrome[0x20]; 7032 7033 u8 reserved_at_40[0x40]; 7034 7035 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 7036 }; 7037 7038 struct mlx5_ifc_query_esw_vport_context_in_bits { 7039 u8 opcode[0x10]; 7040 u8 reserved_at_10[0x10]; 7041 7042 u8 reserved_at_20[0x10]; 7043 u8 op_mod[0x10]; 7044 7045 u8 other_vport[0x1]; 7046 u8 reserved_at_41[0xf]; 7047 u8 vport_number[0x10]; 7048 7049 u8 reserved_at_60[0x20]; 7050 }; 7051 7052 struct mlx5_ifc_destroy_esw_vport_out_bits { 7053 u8 status[0x8]; 7054 u8 reserved_at_8[0x18]; 7055 7056 u8 syndrome[0x20]; 7057 7058 u8 reserved_at_40[0x20]; 7059 }; 7060 7061 struct mlx5_ifc_destroy_esw_vport_in_bits { 7062 u8 opcode[0x10]; 7063 u8 uid[0x10]; 7064 7065 u8 reserved_at_20[0x10]; 7066 u8 op_mod[0x10]; 7067 7068 u8 reserved_at_40[0x10]; 7069 u8 vport_num[0x10]; 7070 7071 u8 reserved_at_60[0x20]; 7072 }; 7073 7074 struct mlx5_ifc_modify_esw_vport_context_out_bits { 7075 u8 status[0x8]; 7076 u8 reserved_at_8[0x18]; 7077 7078 u8 syndrome[0x20]; 7079 7080 u8 reserved_at_40[0x40]; 7081 }; 7082 7083 struct mlx5_ifc_esw_vport_context_fields_select_bits { 7084 u8 reserved_at_0[0x1b]; 7085 u8 fdb_to_vport_reg_c_id[0x1]; 7086 u8 vport_cvlan_insert[0x1]; 7087 u8 vport_svlan_insert[0x1]; 7088 u8 vport_cvlan_strip[0x1]; 7089 u8 vport_svlan_strip[0x1]; 7090 }; 7091 7092 struct mlx5_ifc_modify_esw_vport_context_in_bits { 7093 u8 opcode[0x10]; 7094 u8 reserved_at_10[0x10]; 7095 7096 u8 reserved_at_20[0x10]; 7097 u8 op_mod[0x10]; 7098 7099 u8 other_vport[0x1]; 7100 u8 reserved_at_41[0xf]; 7101 u8 vport_number[0x10]; 7102 7103 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 7104 7105 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 7106 }; 7107 7108 struct mlx5_ifc_query_eq_out_bits { 7109 u8 status[0x8]; 7110 u8 reserved_at_8[0x18]; 7111 7112 u8 syndrome[0x20]; 7113 7114 u8 reserved_at_40[0x40]; 7115 7116 struct mlx5_ifc_eqc_bits eq_context_entry; 7117 7118 u8 reserved_at_280[0x40]; 7119 7120 u8 event_bitmask[0x40]; 7121 7122 u8 reserved_at_300[0x580]; 7123 7124 u8 pas[][0x40]; 7125 }; 7126 7127 struct mlx5_ifc_query_eq_in_bits { 7128 u8 opcode[0x10]; 7129 u8 reserved_at_10[0x10]; 7130 7131 u8 reserved_at_20[0x10]; 7132 u8 op_mod[0x10]; 7133 7134 u8 reserved_at_40[0x18]; 7135 u8 eq_number[0x8]; 7136 7137 u8 reserved_at_60[0x20]; 7138 }; 7139 7140 struct mlx5_ifc_packet_reformat_context_in_bits { 7141 u8 reformat_type[0x8]; 7142 u8 reserved_at_8[0x4]; 7143 u8 reformat_param_0[0x4]; 7144 u8 reserved_at_10[0x6]; 7145 u8 reformat_data_size[0xa]; 7146 7147 u8 reformat_param_1[0x8]; 7148 u8 reserved_at_28[0x8]; 7149 u8 reformat_data[2][0x8]; 7150 7151 u8 more_reformat_data[][0x8]; 7152 }; 7153 7154 struct mlx5_ifc_query_packet_reformat_context_out_bits { 7155 u8 status[0x8]; 7156 u8 reserved_at_8[0x18]; 7157 7158 u8 syndrome[0x20]; 7159 7160 u8 reserved_at_40[0xa0]; 7161 7162 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 7163 }; 7164 7165 struct mlx5_ifc_query_packet_reformat_context_in_bits { 7166 u8 opcode[0x10]; 7167 u8 reserved_at_10[0x10]; 7168 7169 u8 reserved_at_20[0x10]; 7170 u8 op_mod[0x10]; 7171 7172 u8 packet_reformat_id[0x20]; 7173 7174 u8 reserved_at_60[0xa0]; 7175 }; 7176 7177 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 7178 u8 status[0x8]; 7179 u8 reserved_at_8[0x18]; 7180 7181 u8 syndrome[0x20]; 7182 7183 u8 packet_reformat_id[0x20]; 7184 7185 u8 reserved_at_60[0x20]; 7186 }; 7187 7188 enum { 7189 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 7190 MLX5_REFORMAT_CONTEXT_ANCHOR_VLAN_START = 0x2, 7191 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 7192 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 7193 }; 7194 7195 enum mlx5_reformat_ctx_type { 7196 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 7197 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 7198 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 7199 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 7200 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 7201 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 7202 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6, 7203 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7, 7204 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 7205 MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9, 7206 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa, 7207 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 7208 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc, 7209 MLX5_REFORMAT_TYPE_ADD_PSP_TUNNEL = 0xd, 7210 MLX5_REFORMAT_TYPE_DEL_PSP_TUNNEL = 0xe, 7211 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 7212 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 7213 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 7214 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 7215 }; 7216 7217 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 7218 u8 opcode[0x10]; 7219 u8 reserved_at_10[0x10]; 7220 7221 u8 reserved_at_20[0x10]; 7222 u8 op_mod[0x10]; 7223 7224 u8 reserved_at_40[0xa0]; 7225 7226 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 7227 }; 7228 7229 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 7230 u8 status[0x8]; 7231 u8 reserved_at_8[0x18]; 7232 7233 u8 syndrome[0x20]; 7234 7235 u8 reserved_at_40[0x40]; 7236 }; 7237 7238 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 7239 u8 opcode[0x10]; 7240 u8 reserved_at_10[0x10]; 7241 7242 u8 reserved_20[0x10]; 7243 u8 op_mod[0x10]; 7244 7245 u8 packet_reformat_id[0x20]; 7246 7247 u8 reserved_60[0x20]; 7248 }; 7249 7250 struct mlx5_ifc_set_action_in_bits { 7251 u8 action_type[0x4]; 7252 u8 field[0xc]; 7253 u8 reserved_at_10[0x3]; 7254 u8 offset[0x5]; 7255 u8 reserved_at_18[0x3]; 7256 u8 length[0x5]; 7257 7258 u8 data[0x20]; 7259 }; 7260 7261 struct mlx5_ifc_add_action_in_bits { 7262 u8 action_type[0x4]; 7263 u8 field[0xc]; 7264 u8 reserved_at_10[0x10]; 7265 7266 u8 data[0x20]; 7267 }; 7268 7269 struct mlx5_ifc_copy_action_in_bits { 7270 u8 action_type[0x4]; 7271 u8 src_field[0xc]; 7272 u8 reserved_at_10[0x3]; 7273 u8 src_offset[0x5]; 7274 u8 reserved_at_18[0x3]; 7275 u8 length[0x5]; 7276 7277 u8 reserved_at_20[0x4]; 7278 u8 dst_field[0xc]; 7279 u8 reserved_at_30[0x3]; 7280 u8 dst_offset[0x5]; 7281 u8 reserved_at_38[0x8]; 7282 }; 7283 7284 union mlx5_ifc_set_add_copy_action_in_auto_bits { 7285 struct mlx5_ifc_set_action_in_bits set_action_in; 7286 struct mlx5_ifc_add_action_in_bits add_action_in; 7287 struct mlx5_ifc_copy_action_in_bits copy_action_in; 7288 u8 reserved_at_0[0x40]; 7289 }; 7290 7291 enum { 7292 MLX5_ACTION_TYPE_SET = 0x1, 7293 MLX5_ACTION_TYPE_ADD = 0x2, 7294 MLX5_ACTION_TYPE_COPY = 0x3, 7295 }; 7296 7297 enum { 7298 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 7299 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 7300 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 7301 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 7302 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 7303 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 7304 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 7305 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 7306 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 7307 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 7308 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 7309 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 7310 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 7311 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 7312 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 7313 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 7314 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 7315 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 7316 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 7317 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 7318 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 7319 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 7320 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 7321 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 7322 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 7323 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 7324 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 7325 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 7326 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 7327 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 7328 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 7329 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 7330 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 7331 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 7332 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 7333 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 7334 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 7335 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 7336 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 7337 MLX5_ACTION_IN_FIELD_PSP_SYNDROME = 0x71, 7338 }; 7339 7340 struct mlx5_ifc_alloc_modify_header_context_out_bits { 7341 u8 status[0x8]; 7342 u8 reserved_at_8[0x18]; 7343 7344 u8 syndrome[0x20]; 7345 7346 u8 modify_header_id[0x20]; 7347 7348 u8 reserved_at_60[0x20]; 7349 }; 7350 7351 struct mlx5_ifc_alloc_modify_header_context_in_bits { 7352 u8 opcode[0x10]; 7353 u8 reserved_at_10[0x10]; 7354 7355 u8 reserved_at_20[0x10]; 7356 u8 op_mod[0x10]; 7357 7358 u8 reserved_at_40[0x20]; 7359 7360 u8 table_type[0x8]; 7361 u8 reserved_at_68[0x10]; 7362 u8 num_of_actions[0x8]; 7363 7364 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 7365 }; 7366 7367 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 7368 u8 status[0x8]; 7369 u8 reserved_at_8[0x18]; 7370 7371 u8 syndrome[0x20]; 7372 7373 u8 reserved_at_40[0x40]; 7374 }; 7375 7376 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 7377 u8 opcode[0x10]; 7378 u8 reserved_at_10[0x10]; 7379 7380 u8 reserved_at_20[0x10]; 7381 u8 op_mod[0x10]; 7382 7383 u8 modify_header_id[0x20]; 7384 7385 u8 reserved_at_60[0x20]; 7386 }; 7387 7388 struct mlx5_ifc_query_modify_header_context_in_bits { 7389 u8 opcode[0x10]; 7390 u8 uid[0x10]; 7391 7392 u8 reserved_at_20[0x10]; 7393 u8 op_mod[0x10]; 7394 7395 u8 modify_header_id[0x20]; 7396 7397 u8 reserved_at_60[0xa0]; 7398 }; 7399 7400 struct mlx5_ifc_query_dct_out_bits { 7401 u8 status[0x8]; 7402 u8 reserved_at_8[0x18]; 7403 7404 u8 syndrome[0x20]; 7405 7406 u8 reserved_at_40[0x40]; 7407 7408 struct mlx5_ifc_dctc_bits dct_context_entry; 7409 7410 u8 reserved_at_280[0x180]; 7411 }; 7412 7413 struct mlx5_ifc_query_dct_in_bits { 7414 u8 opcode[0x10]; 7415 u8 reserved_at_10[0x10]; 7416 7417 u8 reserved_at_20[0x10]; 7418 u8 op_mod[0x10]; 7419 7420 u8 reserved_at_40[0x8]; 7421 u8 dctn[0x18]; 7422 7423 u8 reserved_at_60[0x20]; 7424 }; 7425 7426 struct mlx5_ifc_query_cq_out_bits { 7427 u8 status[0x8]; 7428 u8 reserved_at_8[0x18]; 7429 7430 u8 syndrome[0x20]; 7431 7432 u8 reserved_at_40[0x40]; 7433 7434 struct mlx5_ifc_cqc_bits cq_context; 7435 7436 u8 reserved_at_280[0x600]; 7437 7438 u8 pas[][0x40]; 7439 }; 7440 7441 struct mlx5_ifc_query_cq_in_bits { 7442 u8 opcode[0x10]; 7443 u8 reserved_at_10[0x10]; 7444 7445 u8 reserved_at_20[0x10]; 7446 u8 op_mod[0x10]; 7447 7448 u8 reserved_at_40[0x8]; 7449 u8 cqn[0x18]; 7450 7451 u8 reserved_at_60[0x20]; 7452 }; 7453 7454 struct mlx5_ifc_query_cong_status_out_bits { 7455 u8 status[0x8]; 7456 u8 reserved_at_8[0x18]; 7457 7458 u8 syndrome[0x20]; 7459 7460 u8 reserved_at_40[0x20]; 7461 7462 u8 enable[0x1]; 7463 u8 tag_enable[0x1]; 7464 u8 reserved_at_62[0x1e]; 7465 }; 7466 7467 struct mlx5_ifc_query_cong_status_in_bits { 7468 u8 opcode[0x10]; 7469 u8 reserved_at_10[0x10]; 7470 7471 u8 reserved_at_20[0x10]; 7472 u8 op_mod[0x10]; 7473 7474 u8 reserved_at_40[0x18]; 7475 u8 priority[0x4]; 7476 u8 cong_protocol[0x4]; 7477 7478 u8 reserved_at_60[0x20]; 7479 }; 7480 7481 struct mlx5_ifc_query_cong_statistics_out_bits { 7482 u8 status[0x8]; 7483 u8 reserved_at_8[0x18]; 7484 7485 u8 syndrome[0x20]; 7486 7487 u8 reserved_at_40[0x40]; 7488 7489 u8 rp_cur_flows[0x20]; 7490 7491 u8 sum_flows[0x20]; 7492 7493 u8 rp_cnp_ignored_high[0x20]; 7494 7495 u8 rp_cnp_ignored_low[0x20]; 7496 7497 u8 rp_cnp_handled_high[0x20]; 7498 7499 u8 rp_cnp_handled_low[0x20]; 7500 7501 u8 reserved_at_140[0x100]; 7502 7503 u8 time_stamp_high[0x20]; 7504 7505 u8 time_stamp_low[0x20]; 7506 7507 u8 accumulators_period[0x20]; 7508 7509 u8 np_ecn_marked_roce_packets_high[0x20]; 7510 7511 u8 np_ecn_marked_roce_packets_low[0x20]; 7512 7513 u8 np_cnp_sent_high[0x20]; 7514 7515 u8 np_cnp_sent_low[0x20]; 7516 7517 u8 reserved_at_320[0x560]; 7518 }; 7519 7520 struct mlx5_ifc_query_cong_statistics_in_bits { 7521 u8 opcode[0x10]; 7522 u8 reserved_at_10[0x10]; 7523 7524 u8 reserved_at_20[0x10]; 7525 u8 op_mod[0x10]; 7526 7527 u8 clear[0x1]; 7528 u8 reserved_at_41[0x1f]; 7529 7530 u8 reserved_at_60[0x20]; 7531 }; 7532 7533 struct mlx5_ifc_query_cong_params_out_bits { 7534 u8 status[0x8]; 7535 u8 reserved_at_8[0x18]; 7536 7537 u8 syndrome[0x20]; 7538 7539 u8 reserved_at_40[0x40]; 7540 7541 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7542 }; 7543 7544 struct mlx5_ifc_query_cong_params_in_bits { 7545 u8 opcode[0x10]; 7546 u8 reserved_at_10[0x10]; 7547 7548 u8 reserved_at_20[0x10]; 7549 u8 op_mod[0x10]; 7550 7551 u8 reserved_at_40[0x1c]; 7552 u8 cong_protocol[0x4]; 7553 7554 u8 reserved_at_60[0x20]; 7555 }; 7556 7557 struct mlx5_ifc_query_adapter_out_bits { 7558 u8 status[0x8]; 7559 u8 reserved_at_8[0x18]; 7560 7561 u8 syndrome[0x20]; 7562 7563 u8 reserved_at_40[0x40]; 7564 7565 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 7566 }; 7567 7568 struct mlx5_ifc_query_adapter_in_bits { 7569 u8 opcode[0x10]; 7570 u8 reserved_at_10[0x10]; 7571 7572 u8 reserved_at_20[0x10]; 7573 u8 op_mod[0x10]; 7574 7575 u8 reserved_at_40[0x40]; 7576 }; 7577 7578 struct mlx5_ifc_function_vhca_rid_info_reg_bits { 7579 u8 host_number[0x8]; 7580 u8 host_pci_device_function[0x8]; 7581 u8 host_pci_bus[0x8]; 7582 u8 reserved_at_18[0x3]; 7583 u8 pci_bus_assigned[0x1]; 7584 u8 function_type[0x4]; 7585 7586 u8 parent_pci_device_function[0x8]; 7587 u8 parent_pci_bus[0x8]; 7588 u8 vhca_id[0x10]; 7589 7590 u8 reserved_at_40[0x10]; 7591 u8 function_id[0x10]; 7592 7593 u8 reserved_at_60[0x20]; 7594 }; 7595 7596 struct mlx5_ifc_delegated_function_vhca_rid_info_bits { 7597 struct mlx5_ifc_function_vhca_rid_info_reg_bits function_vhca_rid_info; 7598 7599 u8 reserved_at_80[0x18]; 7600 u8 manage_profile[0x8]; 7601 7602 u8 reserved_at_a0[0x60]; 7603 }; 7604 7605 struct mlx5_ifc_query_delegated_vhca_out_bits { 7606 u8 status[0x8]; 7607 u8 reserved_at_8[0x18]; 7608 7609 u8 syndrome[0x20]; 7610 7611 u8 reserved_at_40[0x20]; 7612 7613 u8 reserved_at_60[0x10]; 7614 u8 functions_count[0x10]; 7615 7616 u8 reserved_at_80[0x80]; 7617 7618 struct mlx5_ifc_delegated_function_vhca_rid_info_bits 7619 delegated_function_vhca_rid_info[]; 7620 }; 7621 7622 struct mlx5_ifc_query_delegated_vhca_in_bits { 7623 u8 opcode[0x10]; 7624 u8 uid[0x10]; 7625 7626 u8 reserved_at_20[0x10]; 7627 u8 op_mod[0x10]; 7628 7629 u8 reserved_at_40[0x40]; 7630 }; 7631 7632 struct mlx5_ifc_create_esw_vport_out_bits { 7633 u8 status[0x8]; 7634 u8 reserved_at_8[0x18]; 7635 7636 u8 syndrome[0x20]; 7637 7638 u8 reserved_at_40[0x20]; 7639 7640 u8 reserved_at_60[0x10]; 7641 u8 vport_num[0x10]; 7642 }; 7643 7644 struct mlx5_ifc_create_esw_vport_in_bits { 7645 u8 opcode[0x10]; 7646 u8 reserved_at_10[0x10]; 7647 7648 u8 reserved_at_20[0x10]; 7649 u8 op_mod[0x10]; 7650 7651 u8 reserved_at_40[0x10]; 7652 u8 managed_vhca_id[0x10]; 7653 7654 u8 reserved_at_60[0x20]; 7655 }; 7656 7657 struct mlx5_ifc_qp_2rst_out_bits { 7658 u8 status[0x8]; 7659 u8 reserved_at_8[0x18]; 7660 7661 u8 syndrome[0x20]; 7662 7663 u8 reserved_at_40[0x40]; 7664 }; 7665 7666 struct mlx5_ifc_qp_2rst_in_bits { 7667 u8 opcode[0x10]; 7668 u8 uid[0x10]; 7669 7670 u8 reserved_at_20[0x10]; 7671 u8 op_mod[0x10]; 7672 7673 u8 reserved_at_40[0x8]; 7674 u8 qpn[0x18]; 7675 7676 u8 reserved_at_60[0x20]; 7677 }; 7678 7679 struct mlx5_ifc_qp_2err_out_bits { 7680 u8 status[0x8]; 7681 u8 reserved_at_8[0x18]; 7682 7683 u8 syndrome[0x20]; 7684 7685 u8 reserved_at_40[0x40]; 7686 }; 7687 7688 struct mlx5_ifc_qp_2err_in_bits { 7689 u8 opcode[0x10]; 7690 u8 uid[0x10]; 7691 7692 u8 reserved_at_20[0x10]; 7693 u8 op_mod[0x10]; 7694 7695 u8 reserved_at_40[0x8]; 7696 u8 qpn[0x18]; 7697 7698 u8 reserved_at_60[0x20]; 7699 }; 7700 7701 struct mlx5_ifc_trans_page_fault_info_bits { 7702 u8 error[0x1]; 7703 u8 reserved_at_1[0x4]; 7704 u8 page_fault_type[0x3]; 7705 u8 wq_number[0x18]; 7706 7707 u8 reserved_at_20[0x8]; 7708 u8 fault_token[0x18]; 7709 }; 7710 7711 struct mlx5_ifc_mem_page_fault_info_bits { 7712 u8 error[0x1]; 7713 u8 reserved_at_1[0xf]; 7714 u8 fault_token_47_32[0x10]; 7715 7716 u8 fault_token_31_0[0x20]; 7717 }; 7718 7719 union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits { 7720 struct mlx5_ifc_trans_page_fault_info_bits trans_page_fault_info; 7721 struct mlx5_ifc_mem_page_fault_info_bits mem_page_fault_info; 7722 u8 reserved_at_0[0x40]; 7723 }; 7724 7725 struct mlx5_ifc_page_fault_resume_out_bits { 7726 u8 status[0x8]; 7727 u8 reserved_at_8[0x18]; 7728 7729 u8 syndrome[0x20]; 7730 7731 u8 reserved_at_40[0x40]; 7732 }; 7733 7734 struct mlx5_ifc_page_fault_resume_in_bits { 7735 u8 opcode[0x10]; 7736 u8 reserved_at_10[0x10]; 7737 7738 u8 reserved_at_20[0x10]; 7739 u8 op_mod[0x10]; 7740 7741 union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits 7742 page_fault_info; 7743 }; 7744 7745 struct mlx5_ifc_nop_out_bits { 7746 u8 status[0x8]; 7747 u8 reserved_at_8[0x18]; 7748 7749 u8 syndrome[0x20]; 7750 7751 u8 reserved_at_40[0x40]; 7752 }; 7753 7754 struct mlx5_ifc_nop_in_bits { 7755 u8 opcode[0x10]; 7756 u8 reserved_at_10[0x10]; 7757 7758 u8 reserved_at_20[0x10]; 7759 u8 op_mod[0x10]; 7760 7761 u8 reserved_at_40[0x40]; 7762 }; 7763 7764 struct mlx5_ifc_modify_vport_state_out_bits { 7765 u8 status[0x8]; 7766 u8 reserved_at_8[0x18]; 7767 7768 u8 syndrome[0x20]; 7769 7770 u8 reserved_at_40[0x40]; 7771 }; 7772 7773 struct mlx5_ifc_modify_vport_state_in_bits { 7774 u8 opcode[0x10]; 7775 u8 reserved_at_10[0x10]; 7776 7777 u8 reserved_at_20[0x10]; 7778 u8 op_mod[0x10]; 7779 7780 u8 other_vport[0x1]; 7781 u8 reserved_at_41[0xf]; 7782 u8 vport_number[0x10]; 7783 7784 u8 max_tx_speed[0x10]; 7785 u8 ingress_connect[0x1]; 7786 u8 egress_connect[0x1]; 7787 u8 ingress_connect_valid[0x1]; 7788 u8 egress_connect_valid[0x1]; 7789 u8 reserved_at_74[0x4]; 7790 u8 admin_state[0x4]; 7791 u8 reserved_at_7c[0x4]; 7792 }; 7793 7794 struct mlx5_ifc_modify_tis_out_bits { 7795 u8 status[0x8]; 7796 u8 reserved_at_8[0x18]; 7797 7798 u8 syndrome[0x20]; 7799 7800 u8 reserved_at_40[0x40]; 7801 }; 7802 7803 struct mlx5_ifc_modify_tis_bitmask_bits { 7804 u8 reserved_at_0[0x20]; 7805 7806 u8 reserved_at_20[0x1d]; 7807 u8 lag_tx_port_affinity[0x1]; 7808 u8 strict_lag_tx_port_affinity[0x1]; 7809 u8 prio[0x1]; 7810 }; 7811 7812 struct mlx5_ifc_modify_tis_in_bits { 7813 u8 opcode[0x10]; 7814 u8 uid[0x10]; 7815 7816 u8 reserved_at_20[0x10]; 7817 u8 op_mod[0x10]; 7818 7819 u8 reserved_at_40[0x8]; 7820 u8 tisn[0x18]; 7821 7822 u8 reserved_at_60[0x20]; 7823 7824 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7825 7826 u8 reserved_at_c0[0x40]; 7827 7828 struct mlx5_ifc_tisc_bits ctx; 7829 }; 7830 7831 struct mlx5_ifc_modify_tir_bitmask_bits { 7832 u8 reserved_at_0[0x20]; 7833 7834 u8 reserved_at_20[0x1b]; 7835 u8 self_lb_en[0x1]; 7836 u8 reserved_at_3c[0x1]; 7837 u8 hash[0x1]; 7838 u8 reserved_at_3e[0x1]; 7839 u8 packet_merge[0x1]; 7840 }; 7841 7842 struct mlx5_ifc_modify_tir_out_bits { 7843 u8 status[0x8]; 7844 u8 reserved_at_8[0x18]; 7845 7846 u8 syndrome[0x20]; 7847 7848 u8 reserved_at_40[0x40]; 7849 }; 7850 7851 struct mlx5_ifc_modify_tir_in_bits { 7852 u8 opcode[0x10]; 7853 u8 uid[0x10]; 7854 7855 u8 reserved_at_20[0x10]; 7856 u8 op_mod[0x10]; 7857 7858 u8 reserved_at_40[0x8]; 7859 u8 tirn[0x18]; 7860 7861 u8 reserved_at_60[0x20]; 7862 7863 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7864 7865 u8 reserved_at_c0[0x40]; 7866 7867 struct mlx5_ifc_tirc_bits ctx; 7868 }; 7869 7870 struct mlx5_ifc_modify_sq_out_bits { 7871 u8 status[0x8]; 7872 u8 reserved_at_8[0x18]; 7873 7874 u8 syndrome[0x20]; 7875 7876 u8 reserved_at_40[0x40]; 7877 }; 7878 7879 struct mlx5_ifc_modify_sq_in_bits { 7880 u8 opcode[0x10]; 7881 u8 uid[0x10]; 7882 7883 u8 reserved_at_20[0x10]; 7884 u8 op_mod[0x10]; 7885 7886 u8 sq_state[0x4]; 7887 u8 reserved_at_44[0x4]; 7888 u8 sqn[0x18]; 7889 7890 u8 reserved_at_60[0x20]; 7891 7892 u8 modify_bitmask[0x40]; 7893 7894 u8 reserved_at_c0[0x40]; 7895 7896 struct mlx5_ifc_sqc_bits ctx; 7897 }; 7898 7899 struct mlx5_ifc_modify_scheduling_element_out_bits { 7900 u8 status[0x8]; 7901 u8 reserved_at_8[0x18]; 7902 7903 u8 syndrome[0x20]; 7904 7905 u8 reserved_at_40[0x1c0]; 7906 }; 7907 7908 enum { 7909 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7910 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7911 }; 7912 7913 struct mlx5_ifc_modify_scheduling_element_in_bits { 7914 u8 opcode[0x10]; 7915 u8 reserved_at_10[0x10]; 7916 7917 u8 reserved_at_20[0x10]; 7918 u8 op_mod[0x10]; 7919 7920 u8 scheduling_hierarchy[0x8]; 7921 u8 reserved_at_48[0x18]; 7922 7923 u8 scheduling_element_id[0x20]; 7924 7925 u8 reserved_at_80[0x20]; 7926 7927 u8 modify_bitmask[0x20]; 7928 7929 u8 reserved_at_c0[0x40]; 7930 7931 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7932 7933 u8 reserved_at_300[0x100]; 7934 }; 7935 7936 struct mlx5_ifc_modify_rqt_out_bits { 7937 u8 status[0x8]; 7938 u8 reserved_at_8[0x18]; 7939 7940 u8 syndrome[0x20]; 7941 7942 u8 reserved_at_40[0x40]; 7943 }; 7944 7945 struct mlx5_ifc_rqt_bitmask_bits { 7946 u8 reserved_at_0[0x20]; 7947 7948 u8 reserved_at_20[0x1f]; 7949 u8 rqn_list[0x1]; 7950 }; 7951 7952 struct mlx5_ifc_modify_rqt_in_bits { 7953 u8 opcode[0x10]; 7954 u8 uid[0x10]; 7955 7956 u8 reserved_at_20[0x10]; 7957 u8 op_mod[0x10]; 7958 7959 u8 reserved_at_40[0x8]; 7960 u8 rqtn[0x18]; 7961 7962 u8 reserved_at_60[0x20]; 7963 7964 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7965 7966 u8 reserved_at_c0[0x40]; 7967 7968 struct mlx5_ifc_rqtc_bits ctx; 7969 }; 7970 7971 struct mlx5_ifc_modify_rq_out_bits { 7972 u8 status[0x8]; 7973 u8 reserved_at_8[0x18]; 7974 7975 u8 syndrome[0x20]; 7976 7977 u8 reserved_at_40[0x40]; 7978 }; 7979 7980 enum { 7981 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7982 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7983 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7984 }; 7985 7986 struct mlx5_ifc_modify_rq_in_bits { 7987 u8 opcode[0x10]; 7988 u8 uid[0x10]; 7989 7990 u8 reserved_at_20[0x10]; 7991 u8 op_mod[0x10]; 7992 7993 u8 rq_state[0x4]; 7994 u8 reserved_at_44[0x4]; 7995 u8 rqn[0x18]; 7996 7997 u8 reserved_at_60[0x20]; 7998 7999 u8 modify_bitmask[0x40]; 8000 8001 u8 reserved_at_c0[0x40]; 8002 8003 struct mlx5_ifc_rqc_bits ctx; 8004 }; 8005 8006 struct mlx5_ifc_modify_rmp_out_bits { 8007 u8 status[0x8]; 8008 u8 reserved_at_8[0x18]; 8009 8010 u8 syndrome[0x20]; 8011 8012 u8 reserved_at_40[0x40]; 8013 }; 8014 8015 struct mlx5_ifc_rmp_bitmask_bits { 8016 u8 reserved_at_0[0x20]; 8017 8018 u8 reserved_at_20[0x1f]; 8019 u8 lwm[0x1]; 8020 }; 8021 8022 struct mlx5_ifc_modify_rmp_in_bits { 8023 u8 opcode[0x10]; 8024 u8 uid[0x10]; 8025 8026 u8 reserved_at_20[0x10]; 8027 u8 op_mod[0x10]; 8028 8029 u8 rmp_state[0x4]; 8030 u8 reserved_at_44[0x4]; 8031 u8 rmpn[0x18]; 8032 8033 u8 reserved_at_60[0x20]; 8034 8035 struct mlx5_ifc_rmp_bitmask_bits bitmask; 8036 8037 u8 reserved_at_c0[0x40]; 8038 8039 struct mlx5_ifc_rmpc_bits ctx; 8040 }; 8041 8042 struct mlx5_ifc_modify_nic_vport_context_out_bits { 8043 u8 status[0x8]; 8044 u8 reserved_at_8[0x18]; 8045 8046 u8 syndrome[0x20]; 8047 8048 u8 reserved_at_40[0x40]; 8049 }; 8050 8051 struct mlx5_ifc_modify_nic_vport_field_select_bits { 8052 u8 reserved_at_0[0x12]; 8053 u8 affiliation[0x1]; 8054 u8 reserved_at_13[0x1]; 8055 u8 disable_uc_local_lb[0x1]; 8056 u8 disable_mc_local_lb[0x1]; 8057 u8 node_guid[0x1]; 8058 u8 port_guid[0x1]; 8059 u8 min_inline[0x1]; 8060 u8 mtu[0x1]; 8061 u8 change_event[0x1]; 8062 u8 promisc[0x1]; 8063 u8 permanent_address[0x1]; 8064 u8 addresses_list[0x1]; 8065 u8 roce_en[0x1]; 8066 u8 reserved_at_1f[0x1]; 8067 }; 8068 8069 struct mlx5_ifc_modify_nic_vport_context_in_bits { 8070 u8 opcode[0x10]; 8071 u8 reserved_at_10[0x10]; 8072 8073 u8 reserved_at_20[0x10]; 8074 u8 op_mod[0x10]; 8075 8076 u8 other_vport[0x1]; 8077 u8 reserved_at_41[0xf]; 8078 u8 vport_number[0x10]; 8079 8080 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 8081 8082 u8 reserved_at_80[0x780]; 8083 8084 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 8085 }; 8086 8087 struct mlx5_ifc_modify_hca_vport_context_out_bits { 8088 u8 status[0x8]; 8089 u8 reserved_at_8[0x18]; 8090 8091 u8 syndrome[0x20]; 8092 8093 u8 reserved_at_40[0x40]; 8094 }; 8095 8096 struct mlx5_ifc_modify_hca_vport_context_in_bits { 8097 u8 opcode[0x10]; 8098 u8 reserved_at_10[0x10]; 8099 8100 u8 reserved_at_20[0x10]; 8101 u8 op_mod[0x10]; 8102 8103 u8 other_vport[0x1]; 8104 u8 reserved_at_41[0xb]; 8105 u8 port_num[0x4]; 8106 u8 vport_number[0x10]; 8107 8108 u8 reserved_at_60[0x20]; 8109 8110 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 8111 }; 8112 8113 struct mlx5_ifc_modify_cq_out_bits { 8114 u8 status[0x8]; 8115 u8 reserved_at_8[0x18]; 8116 8117 u8 syndrome[0x20]; 8118 8119 u8 reserved_at_40[0x40]; 8120 }; 8121 8122 enum { 8123 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 8124 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 8125 }; 8126 8127 struct mlx5_ifc_modify_cq_in_bits { 8128 u8 opcode[0x10]; 8129 u8 uid[0x10]; 8130 8131 u8 reserved_at_20[0x10]; 8132 u8 op_mod[0x10]; 8133 8134 u8 reserved_at_40[0x8]; 8135 u8 cqn[0x18]; 8136 8137 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 8138 8139 struct mlx5_ifc_cqc_bits cq_context; 8140 8141 u8 reserved_at_280[0x60]; 8142 8143 u8 cq_umem_valid[0x1]; 8144 u8 reserved_at_2e1[0x1f]; 8145 8146 u8 reserved_at_300[0x580]; 8147 8148 u8 pas[][0x40]; 8149 }; 8150 8151 struct mlx5_ifc_modify_cong_status_out_bits { 8152 u8 status[0x8]; 8153 u8 reserved_at_8[0x18]; 8154 8155 u8 syndrome[0x20]; 8156 8157 u8 reserved_at_40[0x40]; 8158 }; 8159 8160 struct mlx5_ifc_modify_cong_status_in_bits { 8161 u8 opcode[0x10]; 8162 u8 reserved_at_10[0x10]; 8163 8164 u8 reserved_at_20[0x10]; 8165 u8 op_mod[0x10]; 8166 8167 u8 reserved_at_40[0x18]; 8168 u8 priority[0x4]; 8169 u8 cong_protocol[0x4]; 8170 8171 u8 enable[0x1]; 8172 u8 tag_enable[0x1]; 8173 u8 reserved_at_62[0x1e]; 8174 }; 8175 8176 struct mlx5_ifc_modify_cong_params_out_bits { 8177 u8 status[0x8]; 8178 u8 reserved_at_8[0x18]; 8179 8180 u8 syndrome[0x20]; 8181 8182 u8 reserved_at_40[0x40]; 8183 }; 8184 8185 struct mlx5_ifc_modify_cong_params_in_bits { 8186 u8 opcode[0x10]; 8187 u8 reserved_at_10[0x10]; 8188 8189 u8 reserved_at_20[0x10]; 8190 u8 op_mod[0x10]; 8191 8192 u8 reserved_at_40[0x1c]; 8193 u8 cong_protocol[0x4]; 8194 8195 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 8196 8197 u8 reserved_at_80[0x80]; 8198 8199 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 8200 }; 8201 8202 struct mlx5_ifc_manage_pages_out_bits { 8203 u8 status[0x8]; 8204 u8 reserved_at_8[0x18]; 8205 8206 u8 syndrome[0x20]; 8207 8208 u8 output_num_entries[0x20]; 8209 8210 u8 reserved_at_60[0x20]; 8211 8212 u8 pas[][0x40]; 8213 }; 8214 8215 enum { 8216 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 8217 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 8218 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 8219 }; 8220 8221 struct mlx5_ifc_manage_pages_in_bits { 8222 u8 opcode[0x10]; 8223 u8 reserved_at_10[0x10]; 8224 8225 u8 reserved_at_20[0x10]; 8226 u8 op_mod[0x10]; 8227 8228 u8 embedded_cpu_function[0x1]; 8229 u8 reserved_at_41[0xf]; 8230 u8 function_id[0x10]; 8231 8232 u8 input_num_entries[0x20]; 8233 8234 u8 pas[][0x40]; 8235 }; 8236 8237 struct mlx5_ifc_mad_ifc_out_bits { 8238 u8 status[0x8]; 8239 u8 reserved_at_8[0x18]; 8240 8241 u8 syndrome[0x20]; 8242 8243 u8 reserved_at_40[0x40]; 8244 8245 u8 response_mad_packet[256][0x8]; 8246 }; 8247 8248 struct mlx5_ifc_mad_ifc_in_bits { 8249 u8 opcode[0x10]; 8250 u8 reserved_at_10[0x10]; 8251 8252 u8 reserved_at_20[0x10]; 8253 u8 op_mod[0x10]; 8254 8255 u8 remote_lid[0x10]; 8256 u8 plane_index[0x8]; 8257 u8 port[0x8]; 8258 8259 u8 reserved_at_60[0x20]; 8260 8261 u8 mad[256][0x8]; 8262 }; 8263 8264 struct mlx5_ifc_init_hca_out_bits { 8265 u8 status[0x8]; 8266 u8 reserved_at_8[0x18]; 8267 8268 u8 syndrome[0x20]; 8269 8270 u8 reserved_at_40[0x40]; 8271 }; 8272 8273 struct mlx5_ifc_init_hca_in_bits { 8274 u8 opcode[0x10]; 8275 u8 reserved_at_10[0x10]; 8276 8277 u8 reserved_at_20[0x10]; 8278 u8 op_mod[0x10]; 8279 8280 u8 reserved_at_40[0x20]; 8281 8282 u8 reserved_at_60[0x2]; 8283 u8 sw_vhca_id[0xe]; 8284 u8 reserved_at_70[0x10]; 8285 8286 u8 sw_owner_id[4][0x20]; 8287 }; 8288 8289 struct mlx5_ifc_init2rtr_qp_out_bits { 8290 u8 status[0x8]; 8291 u8 reserved_at_8[0x18]; 8292 8293 u8 syndrome[0x20]; 8294 8295 u8 reserved_at_40[0x20]; 8296 u8 ece[0x20]; 8297 }; 8298 8299 struct mlx5_ifc_init2rtr_qp_in_bits { 8300 u8 opcode[0x10]; 8301 u8 uid[0x10]; 8302 8303 u8 reserved_at_20[0x10]; 8304 u8 op_mod[0x10]; 8305 8306 u8 reserved_at_40[0x8]; 8307 u8 qpn[0x18]; 8308 8309 u8 reserved_at_60[0x20]; 8310 8311 u8 opt_param_mask[0x20]; 8312 8313 u8 ece[0x20]; 8314 8315 struct mlx5_ifc_qpc_bits qpc; 8316 8317 u8 reserved_at_800[0x80]; 8318 }; 8319 8320 struct mlx5_ifc_init2init_qp_out_bits { 8321 u8 status[0x8]; 8322 u8 reserved_at_8[0x18]; 8323 8324 u8 syndrome[0x20]; 8325 8326 u8 reserved_at_40[0x20]; 8327 u8 ece[0x20]; 8328 }; 8329 8330 struct mlx5_ifc_init2init_qp_in_bits { 8331 u8 opcode[0x10]; 8332 u8 uid[0x10]; 8333 8334 u8 reserved_at_20[0x10]; 8335 u8 op_mod[0x10]; 8336 8337 u8 reserved_at_40[0x8]; 8338 u8 qpn[0x18]; 8339 8340 u8 reserved_at_60[0x20]; 8341 8342 u8 opt_param_mask[0x20]; 8343 8344 u8 ece[0x20]; 8345 8346 struct mlx5_ifc_qpc_bits qpc; 8347 8348 u8 reserved_at_800[0x80]; 8349 }; 8350 8351 struct mlx5_ifc_get_dropped_packet_log_out_bits { 8352 u8 status[0x8]; 8353 u8 reserved_at_8[0x18]; 8354 8355 u8 syndrome[0x20]; 8356 8357 u8 reserved_at_40[0x40]; 8358 8359 u8 packet_headers_log[128][0x8]; 8360 8361 u8 packet_syndrome[64][0x8]; 8362 }; 8363 8364 struct mlx5_ifc_get_dropped_packet_log_in_bits { 8365 u8 opcode[0x10]; 8366 u8 reserved_at_10[0x10]; 8367 8368 u8 reserved_at_20[0x10]; 8369 u8 op_mod[0x10]; 8370 8371 u8 reserved_at_40[0x40]; 8372 }; 8373 8374 struct mlx5_ifc_gen_eqe_in_bits { 8375 u8 opcode[0x10]; 8376 u8 reserved_at_10[0x10]; 8377 8378 u8 reserved_at_20[0x10]; 8379 u8 op_mod[0x10]; 8380 8381 u8 reserved_at_40[0x18]; 8382 u8 eq_number[0x8]; 8383 8384 u8 reserved_at_60[0x20]; 8385 8386 u8 eqe[64][0x8]; 8387 }; 8388 8389 struct mlx5_ifc_gen_eq_out_bits { 8390 u8 status[0x8]; 8391 u8 reserved_at_8[0x18]; 8392 8393 u8 syndrome[0x20]; 8394 8395 u8 reserved_at_40[0x40]; 8396 }; 8397 8398 struct mlx5_ifc_enable_hca_out_bits { 8399 u8 status[0x8]; 8400 u8 reserved_at_8[0x18]; 8401 8402 u8 syndrome[0x20]; 8403 8404 u8 reserved_at_40[0x20]; 8405 }; 8406 8407 struct mlx5_ifc_enable_hca_in_bits { 8408 u8 opcode[0x10]; 8409 u8 reserved_at_10[0x10]; 8410 8411 u8 reserved_at_20[0x10]; 8412 u8 op_mod[0x10]; 8413 8414 u8 embedded_cpu_function[0x1]; 8415 u8 reserved_at_41[0xf]; 8416 u8 function_id[0x10]; 8417 8418 u8 reserved_at_60[0x20]; 8419 }; 8420 8421 struct mlx5_ifc_drain_dct_out_bits { 8422 u8 status[0x8]; 8423 u8 reserved_at_8[0x18]; 8424 8425 u8 syndrome[0x20]; 8426 8427 u8 reserved_at_40[0x40]; 8428 }; 8429 8430 struct mlx5_ifc_drain_dct_in_bits { 8431 u8 opcode[0x10]; 8432 u8 uid[0x10]; 8433 8434 u8 reserved_at_20[0x10]; 8435 u8 op_mod[0x10]; 8436 8437 u8 reserved_at_40[0x8]; 8438 u8 dctn[0x18]; 8439 8440 u8 reserved_at_60[0x20]; 8441 }; 8442 8443 struct mlx5_ifc_disable_hca_out_bits { 8444 u8 status[0x8]; 8445 u8 reserved_at_8[0x18]; 8446 8447 u8 syndrome[0x20]; 8448 8449 u8 reserved_at_40[0x20]; 8450 }; 8451 8452 struct mlx5_ifc_disable_hca_in_bits { 8453 u8 opcode[0x10]; 8454 u8 reserved_at_10[0x10]; 8455 8456 u8 reserved_at_20[0x10]; 8457 u8 op_mod[0x10]; 8458 8459 u8 embedded_cpu_function[0x1]; 8460 u8 reserved_at_41[0xf]; 8461 u8 function_id[0x10]; 8462 8463 u8 reserved_at_60[0x20]; 8464 }; 8465 8466 struct mlx5_ifc_detach_from_mcg_out_bits { 8467 u8 status[0x8]; 8468 u8 reserved_at_8[0x18]; 8469 8470 u8 syndrome[0x20]; 8471 8472 u8 reserved_at_40[0x40]; 8473 }; 8474 8475 struct mlx5_ifc_detach_from_mcg_in_bits { 8476 u8 opcode[0x10]; 8477 u8 uid[0x10]; 8478 8479 u8 reserved_at_20[0x10]; 8480 u8 op_mod[0x10]; 8481 8482 u8 reserved_at_40[0x8]; 8483 u8 qpn[0x18]; 8484 8485 u8 reserved_at_60[0x20]; 8486 8487 u8 multicast_gid[16][0x8]; 8488 }; 8489 8490 struct mlx5_ifc_destroy_xrq_out_bits { 8491 u8 status[0x8]; 8492 u8 reserved_at_8[0x18]; 8493 8494 u8 syndrome[0x20]; 8495 8496 u8 reserved_at_40[0x40]; 8497 }; 8498 8499 struct mlx5_ifc_destroy_xrq_in_bits { 8500 u8 opcode[0x10]; 8501 u8 uid[0x10]; 8502 8503 u8 reserved_at_20[0x10]; 8504 u8 op_mod[0x10]; 8505 8506 u8 reserved_at_40[0x8]; 8507 u8 xrqn[0x18]; 8508 8509 u8 reserved_at_60[0x20]; 8510 }; 8511 8512 struct mlx5_ifc_destroy_xrc_srq_out_bits { 8513 u8 status[0x8]; 8514 u8 reserved_at_8[0x18]; 8515 8516 u8 syndrome[0x20]; 8517 8518 u8 reserved_at_40[0x40]; 8519 }; 8520 8521 struct mlx5_ifc_destroy_xrc_srq_in_bits { 8522 u8 opcode[0x10]; 8523 u8 uid[0x10]; 8524 8525 u8 reserved_at_20[0x10]; 8526 u8 op_mod[0x10]; 8527 8528 u8 reserved_at_40[0x8]; 8529 u8 xrc_srqn[0x18]; 8530 8531 u8 reserved_at_60[0x20]; 8532 }; 8533 8534 struct mlx5_ifc_destroy_tis_out_bits { 8535 u8 status[0x8]; 8536 u8 reserved_at_8[0x18]; 8537 8538 u8 syndrome[0x20]; 8539 8540 u8 reserved_at_40[0x40]; 8541 }; 8542 8543 struct mlx5_ifc_destroy_tis_in_bits { 8544 u8 opcode[0x10]; 8545 u8 uid[0x10]; 8546 8547 u8 reserved_at_20[0x10]; 8548 u8 op_mod[0x10]; 8549 8550 u8 reserved_at_40[0x8]; 8551 u8 tisn[0x18]; 8552 8553 u8 reserved_at_60[0x20]; 8554 }; 8555 8556 struct mlx5_ifc_destroy_tir_out_bits { 8557 u8 status[0x8]; 8558 u8 reserved_at_8[0x18]; 8559 8560 u8 syndrome[0x20]; 8561 8562 u8 reserved_at_40[0x40]; 8563 }; 8564 8565 struct mlx5_ifc_destroy_tir_in_bits { 8566 u8 opcode[0x10]; 8567 u8 uid[0x10]; 8568 8569 u8 reserved_at_20[0x10]; 8570 u8 op_mod[0x10]; 8571 8572 u8 reserved_at_40[0x8]; 8573 u8 tirn[0x18]; 8574 8575 u8 reserved_at_60[0x20]; 8576 }; 8577 8578 struct mlx5_ifc_destroy_srq_out_bits { 8579 u8 status[0x8]; 8580 u8 reserved_at_8[0x18]; 8581 8582 u8 syndrome[0x20]; 8583 8584 u8 reserved_at_40[0x40]; 8585 }; 8586 8587 struct mlx5_ifc_destroy_srq_in_bits { 8588 u8 opcode[0x10]; 8589 u8 uid[0x10]; 8590 8591 u8 reserved_at_20[0x10]; 8592 u8 op_mod[0x10]; 8593 8594 u8 reserved_at_40[0x8]; 8595 u8 srqn[0x18]; 8596 8597 u8 reserved_at_60[0x20]; 8598 }; 8599 8600 struct mlx5_ifc_destroy_sq_out_bits { 8601 u8 status[0x8]; 8602 u8 reserved_at_8[0x18]; 8603 8604 u8 syndrome[0x20]; 8605 8606 u8 reserved_at_40[0x40]; 8607 }; 8608 8609 struct mlx5_ifc_destroy_sq_in_bits { 8610 u8 opcode[0x10]; 8611 u8 uid[0x10]; 8612 8613 u8 reserved_at_20[0x10]; 8614 u8 op_mod[0x10]; 8615 8616 u8 reserved_at_40[0x8]; 8617 u8 sqn[0x18]; 8618 8619 u8 reserved_at_60[0x20]; 8620 }; 8621 8622 struct mlx5_ifc_destroy_scheduling_element_out_bits { 8623 u8 status[0x8]; 8624 u8 reserved_at_8[0x18]; 8625 8626 u8 syndrome[0x20]; 8627 8628 u8 reserved_at_40[0x1c0]; 8629 }; 8630 8631 struct mlx5_ifc_destroy_scheduling_element_in_bits { 8632 u8 opcode[0x10]; 8633 u8 reserved_at_10[0x10]; 8634 8635 u8 reserved_at_20[0x10]; 8636 u8 op_mod[0x10]; 8637 8638 u8 scheduling_hierarchy[0x8]; 8639 u8 reserved_at_48[0x18]; 8640 8641 u8 scheduling_element_id[0x20]; 8642 8643 u8 reserved_at_80[0x180]; 8644 }; 8645 8646 struct mlx5_ifc_destroy_rqt_out_bits { 8647 u8 status[0x8]; 8648 u8 reserved_at_8[0x18]; 8649 8650 u8 syndrome[0x20]; 8651 8652 u8 reserved_at_40[0x40]; 8653 }; 8654 8655 struct mlx5_ifc_destroy_rqt_in_bits { 8656 u8 opcode[0x10]; 8657 u8 uid[0x10]; 8658 8659 u8 reserved_at_20[0x10]; 8660 u8 op_mod[0x10]; 8661 8662 u8 reserved_at_40[0x8]; 8663 u8 rqtn[0x18]; 8664 8665 u8 reserved_at_60[0x20]; 8666 }; 8667 8668 struct mlx5_ifc_destroy_rq_out_bits { 8669 u8 status[0x8]; 8670 u8 reserved_at_8[0x18]; 8671 8672 u8 syndrome[0x20]; 8673 8674 u8 reserved_at_40[0x40]; 8675 }; 8676 8677 struct mlx5_ifc_destroy_rq_in_bits { 8678 u8 opcode[0x10]; 8679 u8 uid[0x10]; 8680 8681 u8 reserved_at_20[0x10]; 8682 u8 op_mod[0x10]; 8683 8684 u8 reserved_at_40[0x8]; 8685 u8 rqn[0x18]; 8686 8687 u8 reserved_at_60[0x20]; 8688 }; 8689 8690 struct mlx5_ifc_set_delay_drop_params_in_bits { 8691 u8 opcode[0x10]; 8692 u8 reserved_at_10[0x10]; 8693 8694 u8 reserved_at_20[0x10]; 8695 u8 op_mod[0x10]; 8696 8697 u8 reserved_at_40[0x20]; 8698 8699 u8 reserved_at_60[0x10]; 8700 u8 delay_drop_timeout[0x10]; 8701 }; 8702 8703 struct mlx5_ifc_set_delay_drop_params_out_bits { 8704 u8 status[0x8]; 8705 u8 reserved_at_8[0x18]; 8706 8707 u8 syndrome[0x20]; 8708 8709 u8 reserved_at_40[0x40]; 8710 }; 8711 8712 struct mlx5_ifc_destroy_rmp_out_bits { 8713 u8 status[0x8]; 8714 u8 reserved_at_8[0x18]; 8715 8716 u8 syndrome[0x20]; 8717 8718 u8 reserved_at_40[0x40]; 8719 }; 8720 8721 struct mlx5_ifc_destroy_rmp_in_bits { 8722 u8 opcode[0x10]; 8723 u8 uid[0x10]; 8724 8725 u8 reserved_at_20[0x10]; 8726 u8 op_mod[0x10]; 8727 8728 u8 reserved_at_40[0x8]; 8729 u8 rmpn[0x18]; 8730 8731 u8 reserved_at_60[0x20]; 8732 }; 8733 8734 struct mlx5_ifc_destroy_qp_out_bits { 8735 u8 status[0x8]; 8736 u8 reserved_at_8[0x18]; 8737 8738 u8 syndrome[0x20]; 8739 8740 u8 reserved_at_40[0x40]; 8741 }; 8742 8743 struct mlx5_ifc_destroy_qp_in_bits { 8744 u8 opcode[0x10]; 8745 u8 uid[0x10]; 8746 8747 u8 reserved_at_20[0x10]; 8748 u8 op_mod[0x10]; 8749 8750 u8 reserved_at_40[0x8]; 8751 u8 qpn[0x18]; 8752 8753 u8 reserved_at_60[0x20]; 8754 }; 8755 8756 struct mlx5_ifc_destroy_psv_out_bits { 8757 u8 status[0x8]; 8758 u8 reserved_at_8[0x18]; 8759 8760 u8 syndrome[0x20]; 8761 8762 u8 reserved_at_40[0x40]; 8763 }; 8764 8765 struct mlx5_ifc_destroy_psv_in_bits { 8766 u8 opcode[0x10]; 8767 u8 reserved_at_10[0x10]; 8768 8769 u8 reserved_at_20[0x10]; 8770 u8 op_mod[0x10]; 8771 8772 u8 reserved_at_40[0x8]; 8773 u8 psvn[0x18]; 8774 8775 u8 reserved_at_60[0x20]; 8776 }; 8777 8778 struct mlx5_ifc_destroy_mkey_out_bits { 8779 u8 status[0x8]; 8780 u8 reserved_at_8[0x18]; 8781 8782 u8 syndrome[0x20]; 8783 8784 u8 reserved_at_40[0x40]; 8785 }; 8786 8787 struct mlx5_ifc_destroy_mkey_in_bits { 8788 u8 opcode[0x10]; 8789 u8 uid[0x10]; 8790 8791 u8 reserved_at_20[0x10]; 8792 u8 op_mod[0x10]; 8793 8794 u8 reserved_at_40[0x8]; 8795 u8 mkey_index[0x18]; 8796 8797 u8 reserved_at_60[0x20]; 8798 }; 8799 8800 struct mlx5_ifc_destroy_flow_table_out_bits { 8801 u8 status[0x8]; 8802 u8 reserved_at_8[0x18]; 8803 8804 u8 syndrome[0x20]; 8805 8806 u8 reserved_at_40[0x40]; 8807 }; 8808 8809 struct mlx5_ifc_destroy_flow_table_in_bits { 8810 u8 opcode[0x10]; 8811 u8 reserved_at_10[0x10]; 8812 8813 u8 reserved_at_20[0x10]; 8814 u8 op_mod[0x10]; 8815 8816 u8 other_vport[0x1]; 8817 u8 other_eswitch[0x1]; 8818 u8 reserved_at_42[0xe]; 8819 u8 vport_number[0x10]; 8820 8821 u8 reserved_at_60[0x20]; 8822 8823 u8 table_type[0x8]; 8824 u8 reserved_at_88[0x8]; 8825 u8 eswitch_owner_vhca_id[0x10]; 8826 8827 u8 reserved_at_a0[0x8]; 8828 u8 table_id[0x18]; 8829 8830 u8 reserved_at_c0[0x140]; 8831 }; 8832 8833 struct mlx5_ifc_destroy_flow_group_out_bits { 8834 u8 status[0x8]; 8835 u8 reserved_at_8[0x18]; 8836 8837 u8 syndrome[0x20]; 8838 8839 u8 reserved_at_40[0x40]; 8840 }; 8841 8842 struct mlx5_ifc_destroy_flow_group_in_bits { 8843 u8 opcode[0x10]; 8844 u8 reserved_at_10[0x10]; 8845 8846 u8 reserved_at_20[0x10]; 8847 u8 op_mod[0x10]; 8848 8849 u8 other_vport[0x1]; 8850 u8 other_eswitch[0x1]; 8851 u8 reserved_at_42[0xe]; 8852 u8 vport_number[0x10]; 8853 8854 u8 reserved_at_60[0x20]; 8855 8856 u8 table_type[0x8]; 8857 u8 reserved_at_88[0x8]; 8858 u8 eswitch_owner_vhca_id[0x10]; 8859 8860 u8 reserved_at_a0[0x8]; 8861 u8 table_id[0x18]; 8862 8863 u8 group_id[0x20]; 8864 8865 u8 reserved_at_e0[0x120]; 8866 }; 8867 8868 struct mlx5_ifc_destroy_eq_out_bits { 8869 u8 status[0x8]; 8870 u8 reserved_at_8[0x18]; 8871 8872 u8 syndrome[0x20]; 8873 8874 u8 reserved_at_40[0x40]; 8875 }; 8876 8877 struct mlx5_ifc_destroy_eq_in_bits { 8878 u8 opcode[0x10]; 8879 u8 reserved_at_10[0x10]; 8880 8881 u8 reserved_at_20[0x10]; 8882 u8 op_mod[0x10]; 8883 8884 u8 reserved_at_40[0x18]; 8885 u8 eq_number[0x8]; 8886 8887 u8 reserved_at_60[0x20]; 8888 }; 8889 8890 struct mlx5_ifc_destroy_dct_out_bits { 8891 u8 status[0x8]; 8892 u8 reserved_at_8[0x18]; 8893 8894 u8 syndrome[0x20]; 8895 8896 u8 reserved_at_40[0x40]; 8897 }; 8898 8899 struct mlx5_ifc_destroy_dct_in_bits { 8900 u8 opcode[0x10]; 8901 u8 uid[0x10]; 8902 8903 u8 reserved_at_20[0x10]; 8904 u8 op_mod[0x10]; 8905 8906 u8 reserved_at_40[0x8]; 8907 u8 dctn[0x18]; 8908 8909 u8 reserved_at_60[0x20]; 8910 }; 8911 8912 struct mlx5_ifc_destroy_cq_out_bits { 8913 u8 status[0x8]; 8914 u8 reserved_at_8[0x18]; 8915 8916 u8 syndrome[0x20]; 8917 8918 u8 reserved_at_40[0x40]; 8919 }; 8920 8921 struct mlx5_ifc_destroy_cq_in_bits { 8922 u8 opcode[0x10]; 8923 u8 uid[0x10]; 8924 8925 u8 reserved_at_20[0x10]; 8926 u8 op_mod[0x10]; 8927 8928 u8 reserved_at_40[0x8]; 8929 u8 cqn[0x18]; 8930 8931 u8 reserved_at_60[0x20]; 8932 }; 8933 8934 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8935 u8 status[0x8]; 8936 u8 reserved_at_8[0x18]; 8937 8938 u8 syndrome[0x20]; 8939 8940 u8 reserved_at_40[0x40]; 8941 }; 8942 8943 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8944 u8 opcode[0x10]; 8945 u8 reserved_at_10[0x10]; 8946 8947 u8 reserved_at_20[0x10]; 8948 u8 op_mod[0x10]; 8949 8950 u8 reserved_at_40[0x20]; 8951 8952 u8 reserved_at_60[0x10]; 8953 u8 vxlan_udp_port[0x10]; 8954 }; 8955 8956 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8957 u8 status[0x8]; 8958 u8 reserved_at_8[0x18]; 8959 8960 u8 syndrome[0x20]; 8961 8962 u8 reserved_at_40[0x40]; 8963 }; 8964 8965 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8966 u8 opcode[0x10]; 8967 u8 reserved_at_10[0x10]; 8968 8969 u8 reserved_at_20[0x10]; 8970 u8 op_mod[0x10]; 8971 8972 u8 reserved_at_40[0x60]; 8973 8974 u8 reserved_at_a0[0x8]; 8975 u8 table_index[0x18]; 8976 8977 u8 reserved_at_c0[0x140]; 8978 }; 8979 8980 struct mlx5_ifc_delete_fte_out_bits { 8981 u8 status[0x8]; 8982 u8 reserved_at_8[0x18]; 8983 8984 u8 syndrome[0x20]; 8985 8986 u8 reserved_at_40[0x40]; 8987 }; 8988 8989 struct mlx5_ifc_delete_fte_in_bits { 8990 u8 opcode[0x10]; 8991 u8 reserved_at_10[0x10]; 8992 8993 u8 reserved_at_20[0x10]; 8994 u8 op_mod[0x10]; 8995 8996 u8 other_vport[0x1]; 8997 u8 other_eswitch[0x1]; 8998 u8 reserved_at_42[0xe]; 8999 u8 vport_number[0x10]; 9000 9001 u8 reserved_at_60[0x20]; 9002 9003 u8 table_type[0x8]; 9004 u8 reserved_at_88[0x8]; 9005 u8 eswitch_owner_vhca_id[0x10]; 9006 9007 u8 reserved_at_a0[0x8]; 9008 u8 table_id[0x18]; 9009 9010 u8 reserved_at_c0[0x40]; 9011 9012 u8 flow_index[0x20]; 9013 9014 u8 reserved_at_120[0xe0]; 9015 }; 9016 9017 struct mlx5_ifc_dealloc_xrcd_out_bits { 9018 u8 status[0x8]; 9019 u8 reserved_at_8[0x18]; 9020 9021 u8 syndrome[0x20]; 9022 9023 u8 reserved_at_40[0x40]; 9024 }; 9025 9026 struct mlx5_ifc_dealloc_xrcd_in_bits { 9027 u8 opcode[0x10]; 9028 u8 uid[0x10]; 9029 9030 u8 reserved_at_20[0x10]; 9031 u8 op_mod[0x10]; 9032 9033 u8 reserved_at_40[0x8]; 9034 u8 xrcd[0x18]; 9035 9036 u8 reserved_at_60[0x20]; 9037 }; 9038 9039 struct mlx5_ifc_dealloc_uar_out_bits { 9040 u8 status[0x8]; 9041 u8 reserved_at_8[0x18]; 9042 9043 u8 syndrome[0x20]; 9044 9045 u8 reserved_at_40[0x40]; 9046 }; 9047 9048 struct mlx5_ifc_dealloc_uar_in_bits { 9049 u8 opcode[0x10]; 9050 u8 uid[0x10]; 9051 9052 u8 reserved_at_20[0x10]; 9053 u8 op_mod[0x10]; 9054 9055 u8 reserved_at_40[0x8]; 9056 u8 uar[0x18]; 9057 9058 u8 reserved_at_60[0x20]; 9059 }; 9060 9061 struct mlx5_ifc_dealloc_transport_domain_out_bits { 9062 u8 status[0x8]; 9063 u8 reserved_at_8[0x18]; 9064 9065 u8 syndrome[0x20]; 9066 9067 u8 reserved_at_40[0x40]; 9068 }; 9069 9070 struct mlx5_ifc_dealloc_transport_domain_in_bits { 9071 u8 opcode[0x10]; 9072 u8 uid[0x10]; 9073 9074 u8 reserved_at_20[0x10]; 9075 u8 op_mod[0x10]; 9076 9077 u8 reserved_at_40[0x8]; 9078 u8 transport_domain[0x18]; 9079 9080 u8 reserved_at_60[0x20]; 9081 }; 9082 9083 struct mlx5_ifc_dealloc_q_counter_out_bits { 9084 u8 status[0x8]; 9085 u8 reserved_at_8[0x18]; 9086 9087 u8 syndrome[0x20]; 9088 9089 u8 reserved_at_40[0x40]; 9090 }; 9091 9092 struct mlx5_ifc_dealloc_q_counter_in_bits { 9093 u8 opcode[0x10]; 9094 u8 reserved_at_10[0x10]; 9095 9096 u8 reserved_at_20[0x10]; 9097 u8 op_mod[0x10]; 9098 9099 u8 reserved_at_40[0x18]; 9100 u8 counter_set_id[0x8]; 9101 9102 u8 reserved_at_60[0x20]; 9103 }; 9104 9105 struct mlx5_ifc_dealloc_pd_out_bits { 9106 u8 status[0x8]; 9107 u8 reserved_at_8[0x18]; 9108 9109 u8 syndrome[0x20]; 9110 9111 u8 reserved_at_40[0x40]; 9112 }; 9113 9114 struct mlx5_ifc_dealloc_pd_in_bits { 9115 u8 opcode[0x10]; 9116 u8 uid[0x10]; 9117 9118 u8 reserved_at_20[0x10]; 9119 u8 op_mod[0x10]; 9120 9121 u8 reserved_at_40[0x8]; 9122 u8 pd[0x18]; 9123 9124 u8 reserved_at_60[0x20]; 9125 }; 9126 9127 struct mlx5_ifc_dealloc_flow_counter_out_bits { 9128 u8 status[0x8]; 9129 u8 reserved_at_8[0x18]; 9130 9131 u8 syndrome[0x20]; 9132 9133 u8 reserved_at_40[0x40]; 9134 }; 9135 9136 struct mlx5_ifc_dealloc_flow_counter_in_bits { 9137 u8 opcode[0x10]; 9138 u8 reserved_at_10[0x10]; 9139 9140 u8 reserved_at_20[0x10]; 9141 u8 op_mod[0x10]; 9142 9143 u8 flow_counter_id[0x20]; 9144 9145 u8 reserved_at_60[0x20]; 9146 }; 9147 9148 struct mlx5_ifc_create_xrq_out_bits { 9149 u8 status[0x8]; 9150 u8 reserved_at_8[0x18]; 9151 9152 u8 syndrome[0x20]; 9153 9154 u8 reserved_at_40[0x8]; 9155 u8 xrqn[0x18]; 9156 9157 u8 reserved_at_60[0x20]; 9158 }; 9159 9160 struct mlx5_ifc_create_xrq_in_bits { 9161 u8 opcode[0x10]; 9162 u8 uid[0x10]; 9163 9164 u8 reserved_at_20[0x10]; 9165 u8 op_mod[0x10]; 9166 9167 u8 reserved_at_40[0x40]; 9168 9169 struct mlx5_ifc_xrqc_bits xrq_context; 9170 }; 9171 9172 struct mlx5_ifc_create_xrc_srq_out_bits { 9173 u8 status[0x8]; 9174 u8 reserved_at_8[0x18]; 9175 9176 u8 syndrome[0x20]; 9177 9178 u8 reserved_at_40[0x8]; 9179 u8 xrc_srqn[0x18]; 9180 9181 u8 reserved_at_60[0x20]; 9182 }; 9183 9184 struct mlx5_ifc_create_xrc_srq_in_bits { 9185 u8 opcode[0x10]; 9186 u8 uid[0x10]; 9187 9188 u8 reserved_at_20[0x10]; 9189 u8 op_mod[0x10]; 9190 9191 u8 reserved_at_40[0x40]; 9192 9193 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 9194 9195 u8 reserved_at_280[0x60]; 9196 9197 u8 xrc_srq_umem_valid[0x1]; 9198 u8 reserved_at_2e1[0x1f]; 9199 9200 u8 reserved_at_300[0x580]; 9201 9202 u8 pas[][0x40]; 9203 }; 9204 9205 struct mlx5_ifc_create_tis_out_bits { 9206 u8 status[0x8]; 9207 u8 reserved_at_8[0x18]; 9208 9209 u8 syndrome[0x20]; 9210 9211 u8 reserved_at_40[0x8]; 9212 u8 tisn[0x18]; 9213 9214 u8 reserved_at_60[0x20]; 9215 }; 9216 9217 struct mlx5_ifc_create_tis_in_bits { 9218 u8 opcode[0x10]; 9219 u8 uid[0x10]; 9220 9221 u8 reserved_at_20[0x10]; 9222 u8 op_mod[0x10]; 9223 9224 u8 reserved_at_40[0xc0]; 9225 9226 struct mlx5_ifc_tisc_bits ctx; 9227 }; 9228 9229 struct mlx5_ifc_create_tir_out_bits { 9230 u8 status[0x8]; 9231 u8 icm_address_63_40[0x18]; 9232 9233 u8 syndrome[0x20]; 9234 9235 u8 icm_address_39_32[0x8]; 9236 u8 tirn[0x18]; 9237 9238 u8 icm_address_31_0[0x20]; 9239 }; 9240 9241 struct mlx5_ifc_create_tir_in_bits { 9242 u8 opcode[0x10]; 9243 u8 uid[0x10]; 9244 9245 u8 reserved_at_20[0x10]; 9246 u8 op_mod[0x10]; 9247 9248 u8 reserved_at_40[0xc0]; 9249 9250 struct mlx5_ifc_tirc_bits ctx; 9251 }; 9252 9253 struct mlx5_ifc_create_srq_out_bits { 9254 u8 status[0x8]; 9255 u8 reserved_at_8[0x18]; 9256 9257 u8 syndrome[0x20]; 9258 9259 u8 reserved_at_40[0x8]; 9260 u8 srqn[0x18]; 9261 9262 u8 reserved_at_60[0x20]; 9263 }; 9264 9265 struct mlx5_ifc_create_srq_in_bits { 9266 u8 opcode[0x10]; 9267 u8 uid[0x10]; 9268 9269 u8 reserved_at_20[0x10]; 9270 u8 op_mod[0x10]; 9271 9272 u8 reserved_at_40[0x40]; 9273 9274 struct mlx5_ifc_srqc_bits srq_context_entry; 9275 9276 u8 reserved_at_280[0x600]; 9277 9278 u8 pas[][0x40]; 9279 }; 9280 9281 struct mlx5_ifc_create_sq_out_bits { 9282 u8 status[0x8]; 9283 u8 reserved_at_8[0x18]; 9284 9285 u8 syndrome[0x20]; 9286 9287 u8 reserved_at_40[0x8]; 9288 u8 sqn[0x18]; 9289 9290 u8 reserved_at_60[0x20]; 9291 }; 9292 9293 struct mlx5_ifc_create_sq_in_bits { 9294 u8 opcode[0x10]; 9295 u8 uid[0x10]; 9296 9297 u8 reserved_at_20[0x10]; 9298 u8 op_mod[0x10]; 9299 9300 u8 reserved_at_40[0xc0]; 9301 9302 struct mlx5_ifc_sqc_bits ctx; 9303 }; 9304 9305 struct mlx5_ifc_create_scheduling_element_out_bits { 9306 u8 status[0x8]; 9307 u8 reserved_at_8[0x18]; 9308 9309 u8 syndrome[0x20]; 9310 9311 u8 reserved_at_40[0x40]; 9312 9313 u8 scheduling_element_id[0x20]; 9314 9315 u8 reserved_at_a0[0x160]; 9316 }; 9317 9318 struct mlx5_ifc_create_scheduling_element_in_bits { 9319 u8 opcode[0x10]; 9320 u8 reserved_at_10[0x10]; 9321 9322 u8 reserved_at_20[0x10]; 9323 u8 op_mod[0x10]; 9324 9325 u8 scheduling_hierarchy[0x8]; 9326 u8 reserved_at_48[0x18]; 9327 9328 u8 reserved_at_60[0xa0]; 9329 9330 struct mlx5_ifc_scheduling_context_bits scheduling_context; 9331 9332 u8 reserved_at_300[0x100]; 9333 }; 9334 9335 struct mlx5_ifc_create_rqt_out_bits { 9336 u8 status[0x8]; 9337 u8 reserved_at_8[0x18]; 9338 9339 u8 syndrome[0x20]; 9340 9341 u8 reserved_at_40[0x8]; 9342 u8 rqtn[0x18]; 9343 9344 u8 reserved_at_60[0x20]; 9345 }; 9346 9347 struct mlx5_ifc_create_rqt_in_bits { 9348 u8 opcode[0x10]; 9349 u8 uid[0x10]; 9350 9351 u8 reserved_at_20[0x10]; 9352 u8 op_mod[0x10]; 9353 9354 u8 reserved_at_40[0xc0]; 9355 9356 struct mlx5_ifc_rqtc_bits rqt_context; 9357 }; 9358 9359 struct mlx5_ifc_create_rq_out_bits { 9360 u8 status[0x8]; 9361 u8 reserved_at_8[0x18]; 9362 9363 u8 syndrome[0x20]; 9364 9365 u8 reserved_at_40[0x8]; 9366 u8 rqn[0x18]; 9367 9368 u8 reserved_at_60[0x20]; 9369 }; 9370 9371 struct mlx5_ifc_create_rq_in_bits { 9372 u8 opcode[0x10]; 9373 u8 uid[0x10]; 9374 9375 u8 reserved_at_20[0x10]; 9376 u8 op_mod[0x10]; 9377 9378 u8 reserved_at_40[0xc0]; 9379 9380 struct mlx5_ifc_rqc_bits ctx; 9381 }; 9382 9383 struct mlx5_ifc_create_rmp_out_bits { 9384 u8 status[0x8]; 9385 u8 reserved_at_8[0x18]; 9386 9387 u8 syndrome[0x20]; 9388 9389 u8 reserved_at_40[0x8]; 9390 u8 rmpn[0x18]; 9391 9392 u8 reserved_at_60[0x20]; 9393 }; 9394 9395 struct mlx5_ifc_create_rmp_in_bits { 9396 u8 opcode[0x10]; 9397 u8 uid[0x10]; 9398 9399 u8 reserved_at_20[0x10]; 9400 u8 op_mod[0x10]; 9401 9402 u8 reserved_at_40[0xc0]; 9403 9404 struct mlx5_ifc_rmpc_bits ctx; 9405 }; 9406 9407 struct mlx5_ifc_create_qp_out_bits { 9408 u8 status[0x8]; 9409 u8 reserved_at_8[0x18]; 9410 9411 u8 syndrome[0x20]; 9412 9413 u8 reserved_at_40[0x8]; 9414 u8 qpn[0x18]; 9415 9416 u8 ece[0x20]; 9417 }; 9418 9419 struct mlx5_ifc_create_qp_in_bits { 9420 u8 opcode[0x10]; 9421 u8 uid[0x10]; 9422 9423 u8 reserved_at_20[0x10]; 9424 u8 op_mod[0x10]; 9425 9426 u8 qpc_ext[0x1]; 9427 u8 reserved_at_41[0x7]; 9428 u8 input_qpn[0x18]; 9429 9430 u8 reserved_at_60[0x20]; 9431 u8 opt_param_mask[0x20]; 9432 9433 u8 ece[0x20]; 9434 9435 struct mlx5_ifc_qpc_bits qpc; 9436 9437 u8 wq_umem_offset[0x40]; 9438 9439 u8 wq_umem_id[0x20]; 9440 9441 u8 wq_umem_valid[0x1]; 9442 u8 reserved_at_861[0x1f]; 9443 9444 u8 pas[][0x40]; 9445 }; 9446 9447 struct mlx5_ifc_create_psv_out_bits { 9448 u8 status[0x8]; 9449 u8 reserved_at_8[0x18]; 9450 9451 u8 syndrome[0x20]; 9452 9453 u8 reserved_at_40[0x40]; 9454 9455 u8 reserved_at_80[0x8]; 9456 u8 psv0_index[0x18]; 9457 9458 u8 reserved_at_a0[0x8]; 9459 u8 psv1_index[0x18]; 9460 9461 u8 reserved_at_c0[0x8]; 9462 u8 psv2_index[0x18]; 9463 9464 u8 reserved_at_e0[0x8]; 9465 u8 psv3_index[0x18]; 9466 }; 9467 9468 struct mlx5_ifc_create_psv_in_bits { 9469 u8 opcode[0x10]; 9470 u8 reserved_at_10[0x10]; 9471 9472 u8 reserved_at_20[0x10]; 9473 u8 op_mod[0x10]; 9474 9475 u8 num_psv[0x4]; 9476 u8 reserved_at_44[0x4]; 9477 u8 pd[0x18]; 9478 9479 u8 reserved_at_60[0x20]; 9480 }; 9481 9482 struct mlx5_ifc_create_mkey_out_bits { 9483 u8 status[0x8]; 9484 u8 reserved_at_8[0x18]; 9485 9486 u8 syndrome[0x20]; 9487 9488 u8 reserved_at_40[0x8]; 9489 u8 mkey_index[0x18]; 9490 9491 u8 reserved_at_60[0x20]; 9492 }; 9493 9494 struct mlx5_ifc_create_mkey_in_bits { 9495 u8 opcode[0x10]; 9496 u8 uid[0x10]; 9497 9498 u8 reserved_at_20[0x10]; 9499 u8 op_mod[0x10]; 9500 9501 u8 reserved_at_40[0x20]; 9502 9503 u8 pg_access[0x1]; 9504 u8 mkey_umem_valid[0x1]; 9505 u8 data_direct[0x1]; 9506 u8 reserved_at_63[0x1d]; 9507 9508 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 9509 9510 u8 reserved_at_280[0x80]; 9511 9512 u8 translations_octword_actual_size[0x20]; 9513 9514 u8 reserved_at_320[0x560]; 9515 9516 u8 klm_pas_mtt[][0x20]; 9517 }; 9518 9519 enum { 9520 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 9521 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 9522 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 9523 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 9524 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 9525 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 9526 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 9527 }; 9528 9529 struct mlx5_ifc_create_flow_table_out_bits { 9530 u8 status[0x8]; 9531 u8 icm_address_63_40[0x18]; 9532 9533 u8 syndrome[0x20]; 9534 9535 u8 icm_address_39_32[0x8]; 9536 u8 table_id[0x18]; 9537 9538 u8 icm_address_31_0[0x20]; 9539 }; 9540 9541 struct mlx5_ifc_create_flow_table_in_bits { 9542 u8 opcode[0x10]; 9543 u8 uid[0x10]; 9544 9545 u8 reserved_at_20[0x10]; 9546 u8 op_mod[0x10]; 9547 9548 u8 other_vport[0x1]; 9549 u8 other_eswitch[0x1]; 9550 u8 reserved_at_42[0xe]; 9551 u8 vport_number[0x10]; 9552 9553 u8 reserved_at_60[0x20]; 9554 9555 u8 table_type[0x8]; 9556 u8 reserved_at_88[0x8]; 9557 u8 eswitch_owner_vhca_id[0x10]; 9558 9559 u8 reserved_at_a0[0x20]; 9560 9561 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9562 }; 9563 9564 struct mlx5_ifc_create_flow_group_out_bits { 9565 u8 status[0x8]; 9566 u8 reserved_at_8[0x18]; 9567 9568 u8 syndrome[0x20]; 9569 9570 u8 reserved_at_40[0x8]; 9571 u8 group_id[0x18]; 9572 9573 u8 reserved_at_60[0x20]; 9574 }; 9575 9576 enum { 9577 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 9578 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 9579 }; 9580 9581 enum { 9582 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 9583 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 9584 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 9585 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 9586 }; 9587 9588 struct mlx5_ifc_create_flow_group_in_bits { 9589 u8 opcode[0x10]; 9590 u8 reserved_at_10[0x10]; 9591 9592 u8 reserved_at_20[0x10]; 9593 u8 op_mod[0x10]; 9594 9595 u8 other_vport[0x1]; 9596 u8 other_eswitch[0x1]; 9597 u8 reserved_at_42[0xe]; 9598 u8 vport_number[0x10]; 9599 9600 u8 reserved_at_60[0x20]; 9601 9602 u8 table_type[0x8]; 9603 u8 reserved_at_88[0x4]; 9604 u8 group_type[0x4]; 9605 u8 eswitch_owner_vhca_id[0x10]; 9606 9607 u8 reserved_at_a0[0x8]; 9608 u8 table_id[0x18]; 9609 9610 u8 source_eswitch_owner_vhca_id_valid[0x1]; 9611 9612 u8 reserved_at_c1[0x1f]; 9613 9614 u8 start_flow_index[0x20]; 9615 9616 u8 reserved_at_100[0x20]; 9617 9618 u8 end_flow_index[0x20]; 9619 9620 u8 reserved_at_140[0x10]; 9621 u8 match_definer_id[0x10]; 9622 9623 u8 reserved_at_160[0x80]; 9624 9625 u8 reserved_at_1e0[0x18]; 9626 u8 match_criteria_enable[0x8]; 9627 9628 struct mlx5_ifc_fte_match_param_bits match_criteria; 9629 9630 u8 reserved_at_1200[0xe00]; 9631 }; 9632 9633 struct mlx5_ifc_create_eq_out_bits { 9634 u8 status[0x8]; 9635 u8 reserved_at_8[0x18]; 9636 9637 u8 syndrome[0x20]; 9638 9639 u8 reserved_at_40[0x18]; 9640 u8 eq_number[0x8]; 9641 9642 u8 reserved_at_60[0x20]; 9643 }; 9644 9645 struct mlx5_ifc_create_eq_in_bits { 9646 u8 opcode[0x10]; 9647 u8 uid[0x10]; 9648 9649 u8 reserved_at_20[0x10]; 9650 u8 op_mod[0x10]; 9651 9652 u8 reserved_at_40[0x40]; 9653 9654 struct mlx5_ifc_eqc_bits eq_context_entry; 9655 9656 u8 reserved_at_280[0x40]; 9657 9658 u8 event_bitmask[4][0x40]; 9659 9660 u8 reserved_at_3c0[0x4c0]; 9661 9662 u8 pas[][0x40]; 9663 }; 9664 9665 struct mlx5_ifc_create_dct_out_bits { 9666 u8 status[0x8]; 9667 u8 reserved_at_8[0x18]; 9668 9669 u8 syndrome[0x20]; 9670 9671 u8 reserved_at_40[0x8]; 9672 u8 dctn[0x18]; 9673 9674 u8 ece[0x20]; 9675 }; 9676 9677 struct mlx5_ifc_create_dct_in_bits { 9678 u8 opcode[0x10]; 9679 u8 uid[0x10]; 9680 9681 u8 reserved_at_20[0x10]; 9682 u8 op_mod[0x10]; 9683 9684 u8 reserved_at_40[0x40]; 9685 9686 struct mlx5_ifc_dctc_bits dct_context_entry; 9687 9688 u8 reserved_at_280[0x180]; 9689 }; 9690 9691 struct mlx5_ifc_create_cq_out_bits { 9692 u8 status[0x8]; 9693 u8 reserved_at_8[0x18]; 9694 9695 u8 syndrome[0x20]; 9696 9697 u8 reserved_at_40[0x8]; 9698 u8 cqn[0x18]; 9699 9700 u8 reserved_at_60[0x20]; 9701 }; 9702 9703 struct mlx5_ifc_create_cq_in_bits { 9704 u8 opcode[0x10]; 9705 u8 uid[0x10]; 9706 9707 u8 reserved_at_20[0x10]; 9708 u8 op_mod[0x10]; 9709 9710 u8 reserved_at_40[0x40]; 9711 9712 struct mlx5_ifc_cqc_bits cq_context; 9713 9714 u8 reserved_at_280[0x60]; 9715 9716 u8 cq_umem_valid[0x1]; 9717 u8 reserved_at_2e1[0x59f]; 9718 9719 u8 pas[][0x40]; 9720 }; 9721 9722 struct mlx5_ifc_config_int_moderation_out_bits { 9723 u8 status[0x8]; 9724 u8 reserved_at_8[0x18]; 9725 9726 u8 syndrome[0x20]; 9727 9728 u8 reserved_at_40[0x4]; 9729 u8 min_delay[0xc]; 9730 u8 int_vector[0x10]; 9731 9732 u8 reserved_at_60[0x20]; 9733 }; 9734 9735 enum { 9736 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 9737 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 9738 }; 9739 9740 struct mlx5_ifc_config_int_moderation_in_bits { 9741 u8 opcode[0x10]; 9742 u8 reserved_at_10[0x10]; 9743 9744 u8 reserved_at_20[0x10]; 9745 u8 op_mod[0x10]; 9746 9747 u8 reserved_at_40[0x4]; 9748 u8 min_delay[0xc]; 9749 u8 int_vector[0x10]; 9750 9751 u8 reserved_at_60[0x20]; 9752 }; 9753 9754 struct mlx5_ifc_attach_to_mcg_out_bits { 9755 u8 status[0x8]; 9756 u8 reserved_at_8[0x18]; 9757 9758 u8 syndrome[0x20]; 9759 9760 u8 reserved_at_40[0x40]; 9761 }; 9762 9763 struct mlx5_ifc_attach_to_mcg_in_bits { 9764 u8 opcode[0x10]; 9765 u8 uid[0x10]; 9766 9767 u8 reserved_at_20[0x10]; 9768 u8 op_mod[0x10]; 9769 9770 u8 reserved_at_40[0x8]; 9771 u8 qpn[0x18]; 9772 9773 u8 reserved_at_60[0x20]; 9774 9775 u8 multicast_gid[16][0x8]; 9776 }; 9777 9778 struct mlx5_ifc_arm_xrq_out_bits { 9779 u8 status[0x8]; 9780 u8 reserved_at_8[0x18]; 9781 9782 u8 syndrome[0x20]; 9783 9784 u8 reserved_at_40[0x40]; 9785 }; 9786 9787 struct mlx5_ifc_arm_xrq_in_bits { 9788 u8 opcode[0x10]; 9789 u8 reserved_at_10[0x10]; 9790 9791 u8 reserved_at_20[0x10]; 9792 u8 op_mod[0x10]; 9793 9794 u8 reserved_at_40[0x8]; 9795 u8 xrqn[0x18]; 9796 9797 u8 reserved_at_60[0x10]; 9798 u8 lwm[0x10]; 9799 }; 9800 9801 struct mlx5_ifc_arm_xrc_srq_out_bits { 9802 u8 status[0x8]; 9803 u8 reserved_at_8[0x18]; 9804 9805 u8 syndrome[0x20]; 9806 9807 u8 reserved_at_40[0x40]; 9808 }; 9809 9810 enum { 9811 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9812 }; 9813 9814 struct mlx5_ifc_arm_xrc_srq_in_bits { 9815 u8 opcode[0x10]; 9816 u8 uid[0x10]; 9817 9818 u8 reserved_at_20[0x10]; 9819 u8 op_mod[0x10]; 9820 9821 u8 reserved_at_40[0x8]; 9822 u8 xrc_srqn[0x18]; 9823 9824 u8 reserved_at_60[0x10]; 9825 u8 lwm[0x10]; 9826 }; 9827 9828 struct mlx5_ifc_arm_rq_out_bits { 9829 u8 status[0x8]; 9830 u8 reserved_at_8[0x18]; 9831 9832 u8 syndrome[0x20]; 9833 9834 u8 reserved_at_40[0x40]; 9835 }; 9836 9837 enum { 9838 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9839 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9840 }; 9841 9842 struct mlx5_ifc_arm_rq_in_bits { 9843 u8 opcode[0x10]; 9844 u8 uid[0x10]; 9845 9846 u8 reserved_at_20[0x10]; 9847 u8 op_mod[0x10]; 9848 9849 u8 reserved_at_40[0x8]; 9850 u8 srq_number[0x18]; 9851 9852 u8 reserved_at_60[0x10]; 9853 u8 lwm[0x10]; 9854 }; 9855 9856 struct mlx5_ifc_arm_dct_out_bits { 9857 u8 status[0x8]; 9858 u8 reserved_at_8[0x18]; 9859 9860 u8 syndrome[0x20]; 9861 9862 u8 reserved_at_40[0x40]; 9863 }; 9864 9865 struct mlx5_ifc_arm_dct_in_bits { 9866 u8 opcode[0x10]; 9867 u8 reserved_at_10[0x10]; 9868 9869 u8 reserved_at_20[0x10]; 9870 u8 op_mod[0x10]; 9871 9872 u8 reserved_at_40[0x8]; 9873 u8 dct_number[0x18]; 9874 9875 u8 reserved_at_60[0x20]; 9876 }; 9877 9878 struct mlx5_ifc_alloc_xrcd_out_bits { 9879 u8 status[0x8]; 9880 u8 reserved_at_8[0x18]; 9881 9882 u8 syndrome[0x20]; 9883 9884 u8 reserved_at_40[0x8]; 9885 u8 xrcd[0x18]; 9886 9887 u8 reserved_at_60[0x20]; 9888 }; 9889 9890 struct mlx5_ifc_alloc_xrcd_in_bits { 9891 u8 opcode[0x10]; 9892 u8 uid[0x10]; 9893 9894 u8 reserved_at_20[0x10]; 9895 u8 op_mod[0x10]; 9896 9897 u8 reserved_at_40[0x40]; 9898 }; 9899 9900 struct mlx5_ifc_alloc_uar_out_bits { 9901 u8 status[0x8]; 9902 u8 reserved_at_8[0x18]; 9903 9904 u8 syndrome[0x20]; 9905 9906 u8 reserved_at_40[0x8]; 9907 u8 uar[0x18]; 9908 9909 u8 reserved_at_60[0x20]; 9910 }; 9911 9912 struct mlx5_ifc_alloc_uar_in_bits { 9913 u8 opcode[0x10]; 9914 u8 uid[0x10]; 9915 9916 u8 reserved_at_20[0x10]; 9917 u8 op_mod[0x10]; 9918 9919 u8 reserved_at_40[0x40]; 9920 }; 9921 9922 struct mlx5_ifc_alloc_transport_domain_out_bits { 9923 u8 status[0x8]; 9924 u8 reserved_at_8[0x18]; 9925 9926 u8 syndrome[0x20]; 9927 9928 u8 reserved_at_40[0x8]; 9929 u8 transport_domain[0x18]; 9930 9931 u8 reserved_at_60[0x20]; 9932 }; 9933 9934 struct mlx5_ifc_alloc_transport_domain_in_bits { 9935 u8 opcode[0x10]; 9936 u8 uid[0x10]; 9937 9938 u8 reserved_at_20[0x10]; 9939 u8 op_mod[0x10]; 9940 9941 u8 reserved_at_40[0x40]; 9942 }; 9943 9944 struct mlx5_ifc_alloc_q_counter_out_bits { 9945 u8 status[0x8]; 9946 u8 reserved_at_8[0x18]; 9947 9948 u8 syndrome[0x20]; 9949 9950 u8 reserved_at_40[0x18]; 9951 u8 counter_set_id[0x8]; 9952 9953 u8 reserved_at_60[0x20]; 9954 }; 9955 9956 struct mlx5_ifc_alloc_q_counter_in_bits { 9957 u8 opcode[0x10]; 9958 u8 uid[0x10]; 9959 9960 u8 reserved_at_20[0x10]; 9961 u8 op_mod[0x10]; 9962 9963 u8 reserved_at_40[0x40]; 9964 }; 9965 9966 struct mlx5_ifc_alloc_pd_out_bits { 9967 u8 status[0x8]; 9968 u8 reserved_at_8[0x18]; 9969 9970 u8 syndrome[0x20]; 9971 9972 u8 reserved_at_40[0x8]; 9973 u8 pd[0x18]; 9974 9975 u8 reserved_at_60[0x20]; 9976 }; 9977 9978 struct mlx5_ifc_alloc_pd_in_bits { 9979 u8 opcode[0x10]; 9980 u8 uid[0x10]; 9981 9982 u8 reserved_at_20[0x10]; 9983 u8 op_mod[0x10]; 9984 9985 u8 reserved_at_40[0x40]; 9986 }; 9987 9988 struct mlx5_ifc_alloc_flow_counter_out_bits { 9989 u8 status[0x8]; 9990 u8 reserved_at_8[0x18]; 9991 9992 u8 syndrome[0x20]; 9993 9994 u8 flow_counter_id[0x20]; 9995 9996 u8 reserved_at_60[0x20]; 9997 }; 9998 9999 struct mlx5_ifc_alloc_flow_counter_in_bits { 10000 u8 opcode[0x10]; 10001 u8 reserved_at_10[0x10]; 10002 10003 u8 reserved_at_20[0x10]; 10004 u8 op_mod[0x10]; 10005 10006 u8 reserved_at_40[0x33]; 10007 u8 flow_counter_bulk_log_size[0x5]; 10008 u8 flow_counter_bulk[0x8]; 10009 }; 10010 10011 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 10012 u8 status[0x8]; 10013 u8 reserved_at_8[0x18]; 10014 10015 u8 syndrome[0x20]; 10016 10017 u8 reserved_at_40[0x40]; 10018 }; 10019 10020 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 10021 u8 opcode[0x10]; 10022 u8 reserved_at_10[0x10]; 10023 10024 u8 reserved_at_20[0x10]; 10025 u8 op_mod[0x10]; 10026 10027 u8 reserved_at_40[0x20]; 10028 10029 u8 reserved_at_60[0x10]; 10030 u8 vxlan_udp_port[0x10]; 10031 }; 10032 10033 struct mlx5_ifc_set_pp_rate_limit_out_bits { 10034 u8 status[0x8]; 10035 u8 reserved_at_8[0x18]; 10036 10037 u8 syndrome[0x20]; 10038 10039 u8 reserved_at_40[0x40]; 10040 }; 10041 10042 struct mlx5_ifc_set_pp_rate_limit_context_bits { 10043 u8 rate_limit[0x20]; 10044 10045 u8 burst_upper_bound[0x20]; 10046 10047 u8 reserved_at_40[0x10]; 10048 u8 typical_packet_size[0x10]; 10049 10050 u8 reserved_at_60[0x120]; 10051 }; 10052 10053 struct mlx5_ifc_set_pp_rate_limit_in_bits { 10054 u8 opcode[0x10]; 10055 u8 uid[0x10]; 10056 10057 u8 reserved_at_20[0x10]; 10058 u8 op_mod[0x10]; 10059 10060 u8 reserved_at_40[0x10]; 10061 u8 rate_limit_index[0x10]; 10062 10063 u8 reserved_at_60[0x20]; 10064 10065 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 10066 }; 10067 10068 struct mlx5_ifc_access_register_out_bits { 10069 u8 status[0x8]; 10070 u8 reserved_at_8[0x18]; 10071 10072 u8 syndrome[0x20]; 10073 10074 u8 reserved_at_40[0x40]; 10075 10076 u8 register_data[][0x20]; 10077 }; 10078 10079 enum { 10080 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 10081 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 10082 }; 10083 10084 struct mlx5_ifc_access_register_in_bits { 10085 u8 opcode[0x10]; 10086 u8 reserved_at_10[0x10]; 10087 10088 u8 reserved_at_20[0x10]; 10089 u8 op_mod[0x10]; 10090 10091 u8 reserved_at_40[0x10]; 10092 u8 register_id[0x10]; 10093 10094 u8 argument[0x20]; 10095 10096 u8 register_data[][0x20]; 10097 }; 10098 10099 struct mlx5_ifc_sltp_reg_bits { 10100 u8 status[0x4]; 10101 u8 version[0x4]; 10102 u8 local_port[0x8]; 10103 u8 pnat[0x2]; 10104 u8 reserved_at_12[0x2]; 10105 u8 lane[0x4]; 10106 u8 reserved_at_18[0x8]; 10107 10108 u8 reserved_at_20[0x20]; 10109 10110 u8 reserved_at_40[0x7]; 10111 u8 polarity[0x1]; 10112 u8 ob_tap0[0x8]; 10113 u8 ob_tap1[0x8]; 10114 u8 ob_tap2[0x8]; 10115 10116 u8 reserved_at_60[0xc]; 10117 u8 ob_preemp_mode[0x4]; 10118 u8 ob_reg[0x8]; 10119 u8 ob_bias[0x8]; 10120 10121 u8 reserved_at_80[0x20]; 10122 }; 10123 10124 struct mlx5_ifc_slrg_reg_bits { 10125 u8 status[0x4]; 10126 u8 version[0x4]; 10127 u8 local_port[0x8]; 10128 u8 pnat[0x2]; 10129 u8 reserved_at_12[0x2]; 10130 u8 lane[0x4]; 10131 u8 reserved_at_18[0x8]; 10132 10133 u8 time_to_link_up[0x10]; 10134 u8 reserved_at_30[0xc]; 10135 u8 grade_lane_speed[0x4]; 10136 10137 u8 grade_version[0x8]; 10138 u8 grade[0x18]; 10139 10140 u8 reserved_at_60[0x4]; 10141 u8 height_grade_type[0x4]; 10142 u8 height_grade[0x18]; 10143 10144 u8 height_dz[0x10]; 10145 u8 height_dv[0x10]; 10146 10147 u8 reserved_at_a0[0x10]; 10148 u8 height_sigma[0x10]; 10149 10150 u8 reserved_at_c0[0x20]; 10151 10152 u8 reserved_at_e0[0x4]; 10153 u8 phase_grade_type[0x4]; 10154 u8 phase_grade[0x18]; 10155 10156 u8 reserved_at_100[0x8]; 10157 u8 phase_eo_pos[0x8]; 10158 u8 reserved_at_110[0x8]; 10159 u8 phase_eo_neg[0x8]; 10160 10161 u8 ffe_set_tested[0x10]; 10162 u8 test_errors_per_lane[0x10]; 10163 }; 10164 10165 struct mlx5_ifc_pvlc_reg_bits { 10166 u8 reserved_at_0[0x8]; 10167 u8 local_port[0x8]; 10168 u8 reserved_at_10[0x10]; 10169 10170 u8 reserved_at_20[0x1c]; 10171 u8 vl_hw_cap[0x4]; 10172 10173 u8 reserved_at_40[0x1c]; 10174 u8 vl_admin[0x4]; 10175 10176 u8 reserved_at_60[0x1c]; 10177 u8 vl_operational[0x4]; 10178 }; 10179 10180 struct mlx5_ifc_pude_reg_bits { 10181 u8 swid[0x8]; 10182 u8 local_port[0x8]; 10183 u8 reserved_at_10[0x4]; 10184 u8 admin_status[0x4]; 10185 u8 reserved_at_18[0x4]; 10186 u8 oper_status[0x4]; 10187 10188 u8 reserved_at_20[0x60]; 10189 }; 10190 10191 enum { 10192 MLX5_PTYS_CONNECTOR_TYPE_PORT_DA = 0x7, 10193 }; 10194 10195 struct mlx5_ifc_ptys_reg_bits { 10196 u8 reserved_at_0[0x1]; 10197 u8 an_disable_admin[0x1]; 10198 u8 an_disable_cap[0x1]; 10199 u8 reserved_at_3[0x5]; 10200 u8 local_port[0x8]; 10201 u8 reserved_at_10[0x8]; 10202 u8 plane_ind[0x4]; 10203 u8 reserved_at_1c[0x1]; 10204 u8 proto_mask[0x3]; 10205 10206 u8 an_status[0x4]; 10207 u8 reserved_at_24[0xc]; 10208 u8 data_rate_oper[0x10]; 10209 10210 u8 ext_eth_proto_capability[0x20]; 10211 10212 u8 eth_proto_capability[0x20]; 10213 10214 u8 ib_link_width_capability[0x10]; 10215 u8 ib_proto_capability[0x10]; 10216 10217 u8 ext_eth_proto_admin[0x20]; 10218 10219 u8 eth_proto_admin[0x20]; 10220 10221 u8 ib_link_width_admin[0x10]; 10222 u8 ib_proto_admin[0x10]; 10223 10224 u8 ext_eth_proto_oper[0x20]; 10225 10226 u8 eth_proto_oper[0x20]; 10227 10228 u8 ib_link_width_oper[0x10]; 10229 u8 ib_proto_oper[0x10]; 10230 10231 u8 reserved_at_160[0x8]; 10232 u8 lane_rate_oper[0x14]; 10233 u8 connector_type[0x4]; 10234 10235 u8 eth_proto_lp_advertise[0x20]; 10236 10237 u8 reserved_at_1a0[0x60]; 10238 }; 10239 10240 struct mlx5_ifc_mlcr_reg_bits { 10241 u8 reserved_at_0[0x8]; 10242 u8 local_port[0x8]; 10243 u8 reserved_at_10[0x20]; 10244 10245 u8 beacon_duration[0x10]; 10246 u8 reserved_at_40[0x10]; 10247 10248 u8 beacon_remain[0x10]; 10249 }; 10250 10251 struct mlx5_ifc_ptas_reg_bits { 10252 u8 reserved_at_0[0x20]; 10253 10254 u8 algorithm_options[0x10]; 10255 u8 reserved_at_30[0x4]; 10256 u8 repetitions_mode[0x4]; 10257 u8 num_of_repetitions[0x8]; 10258 10259 u8 grade_version[0x8]; 10260 u8 height_grade_type[0x4]; 10261 u8 phase_grade_type[0x4]; 10262 u8 height_grade_weight[0x8]; 10263 u8 phase_grade_weight[0x8]; 10264 10265 u8 gisim_measure_bits[0x10]; 10266 u8 adaptive_tap_measure_bits[0x10]; 10267 10268 u8 ber_bath_high_error_threshold[0x10]; 10269 u8 ber_bath_mid_error_threshold[0x10]; 10270 10271 u8 ber_bath_low_error_threshold[0x10]; 10272 u8 one_ratio_high_threshold[0x10]; 10273 10274 u8 one_ratio_high_mid_threshold[0x10]; 10275 u8 one_ratio_low_mid_threshold[0x10]; 10276 10277 u8 one_ratio_low_threshold[0x10]; 10278 u8 ndeo_error_threshold[0x10]; 10279 10280 u8 mixer_offset_step_size[0x10]; 10281 u8 reserved_at_110[0x8]; 10282 u8 mix90_phase_for_voltage_bath[0x8]; 10283 10284 u8 mixer_offset_start[0x10]; 10285 u8 mixer_offset_end[0x10]; 10286 10287 u8 reserved_at_140[0x15]; 10288 u8 ber_test_time[0xb]; 10289 }; 10290 10291 struct mlx5_ifc_pspa_reg_bits { 10292 u8 swid[0x8]; 10293 u8 local_port[0x8]; 10294 u8 sub_port[0x8]; 10295 u8 reserved_at_18[0x8]; 10296 10297 u8 reserved_at_20[0x20]; 10298 }; 10299 10300 struct mlx5_ifc_pqdr_reg_bits { 10301 u8 reserved_at_0[0x8]; 10302 u8 local_port[0x8]; 10303 u8 reserved_at_10[0x5]; 10304 u8 prio[0x3]; 10305 u8 reserved_at_18[0x6]; 10306 u8 mode[0x2]; 10307 10308 u8 reserved_at_20[0x20]; 10309 10310 u8 reserved_at_40[0x10]; 10311 u8 min_threshold[0x10]; 10312 10313 u8 reserved_at_60[0x10]; 10314 u8 max_threshold[0x10]; 10315 10316 u8 reserved_at_80[0x10]; 10317 u8 mark_probability_denominator[0x10]; 10318 10319 u8 reserved_at_a0[0x60]; 10320 }; 10321 10322 struct mlx5_ifc_ppsc_reg_bits { 10323 u8 reserved_at_0[0x8]; 10324 u8 local_port[0x8]; 10325 u8 reserved_at_10[0x10]; 10326 10327 u8 reserved_at_20[0x60]; 10328 10329 u8 reserved_at_80[0x1c]; 10330 u8 wrps_admin[0x4]; 10331 10332 u8 reserved_at_a0[0x1c]; 10333 u8 wrps_status[0x4]; 10334 10335 u8 reserved_at_c0[0x8]; 10336 u8 up_threshold[0x8]; 10337 u8 reserved_at_d0[0x8]; 10338 u8 down_threshold[0x8]; 10339 10340 u8 reserved_at_e0[0x20]; 10341 10342 u8 reserved_at_100[0x1c]; 10343 u8 srps_admin[0x4]; 10344 10345 u8 reserved_at_120[0x1c]; 10346 u8 srps_status[0x4]; 10347 10348 u8 reserved_at_140[0x40]; 10349 }; 10350 10351 struct mlx5_ifc_pplr_reg_bits { 10352 u8 reserved_at_0[0x8]; 10353 u8 local_port[0x8]; 10354 u8 reserved_at_10[0x10]; 10355 10356 u8 reserved_at_20[0x8]; 10357 u8 lb_cap[0x8]; 10358 u8 reserved_at_30[0x8]; 10359 u8 lb_en[0x8]; 10360 }; 10361 10362 struct mlx5_ifc_pplm_reg_bits { 10363 u8 reserved_at_0[0x8]; 10364 u8 local_port[0x8]; 10365 u8 reserved_at_10[0x10]; 10366 10367 u8 reserved_at_20[0x20]; 10368 10369 u8 port_profile_mode[0x8]; 10370 u8 static_port_profile[0x8]; 10371 u8 active_port_profile[0x8]; 10372 u8 reserved_at_58[0x8]; 10373 10374 u8 retransmission_active[0x8]; 10375 u8 fec_mode_active[0x18]; 10376 10377 u8 rs_fec_correction_bypass_cap[0x4]; 10378 u8 reserved_at_84[0x8]; 10379 u8 fec_override_cap_56g[0x4]; 10380 u8 fec_override_cap_100g[0x4]; 10381 u8 fec_override_cap_50g[0x4]; 10382 u8 fec_override_cap_25g[0x4]; 10383 u8 fec_override_cap_10g_40g[0x4]; 10384 10385 u8 rs_fec_correction_bypass_admin[0x4]; 10386 u8 reserved_at_a4[0x8]; 10387 u8 fec_override_admin_56g[0x4]; 10388 u8 fec_override_admin_100g[0x4]; 10389 u8 fec_override_admin_50g[0x4]; 10390 u8 fec_override_admin_25g[0x4]; 10391 u8 fec_override_admin_10g_40g[0x4]; 10392 10393 u8 fec_override_cap_400g_8x[0x10]; 10394 u8 fec_override_cap_200g_4x[0x10]; 10395 10396 u8 fec_override_cap_100g_2x[0x10]; 10397 u8 fec_override_cap_50g_1x[0x10]; 10398 10399 u8 fec_override_admin_400g_8x[0x10]; 10400 u8 fec_override_admin_200g_4x[0x10]; 10401 10402 u8 fec_override_admin_100g_2x[0x10]; 10403 u8 fec_override_admin_50g_1x[0x10]; 10404 10405 u8 fec_override_cap_800g_8x[0x10]; 10406 u8 fec_override_cap_400g_4x[0x10]; 10407 10408 u8 fec_override_cap_200g_2x[0x10]; 10409 u8 fec_override_cap_100g_1x[0x10]; 10410 10411 u8 reserved_at_180[0xa0]; 10412 10413 u8 fec_override_admin_800g_8x[0x10]; 10414 u8 fec_override_admin_400g_4x[0x10]; 10415 10416 u8 fec_override_admin_200g_2x[0x10]; 10417 u8 fec_override_admin_100g_1x[0x10]; 10418 10419 u8 reserved_at_260[0x60]; 10420 10421 u8 fec_override_cap_1600g_8x[0x10]; 10422 u8 fec_override_cap_800g_4x[0x10]; 10423 10424 u8 fec_override_cap_400g_2x[0x10]; 10425 u8 fec_override_cap_200g_1x[0x10]; 10426 10427 u8 fec_override_admin_1600g_8x[0x10]; 10428 u8 fec_override_admin_800g_4x[0x10]; 10429 10430 u8 fec_override_admin_400g_2x[0x10]; 10431 u8 fec_override_admin_200g_1x[0x10]; 10432 10433 u8 reserved_at_340[0x80]; 10434 }; 10435 10436 struct mlx5_ifc_ppcnt_reg_bits { 10437 u8 swid[0x8]; 10438 u8 local_port[0x8]; 10439 u8 pnat[0x2]; 10440 u8 reserved_at_12[0x8]; 10441 u8 grp[0x6]; 10442 10443 u8 clr[0x1]; 10444 u8 reserved_at_21[0x13]; 10445 u8 plane_ind[0x4]; 10446 u8 reserved_at_38[0x3]; 10447 u8 prio_tc[0x5]; 10448 10449 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 10450 }; 10451 10452 struct mlx5_ifc_mpein_reg_bits { 10453 u8 reserved_at_0[0x2]; 10454 u8 depth[0x6]; 10455 u8 pcie_index[0x8]; 10456 u8 node[0x8]; 10457 u8 reserved_at_18[0x8]; 10458 10459 u8 capability_mask[0x20]; 10460 10461 u8 reserved_at_40[0x8]; 10462 u8 link_width_enabled[0x8]; 10463 u8 link_speed_enabled[0x10]; 10464 10465 u8 lane0_physical_position[0x8]; 10466 u8 link_width_active[0x8]; 10467 u8 link_speed_active[0x10]; 10468 10469 u8 num_of_pfs[0x10]; 10470 u8 num_of_vfs[0x10]; 10471 10472 u8 bdf0[0x10]; 10473 u8 reserved_at_b0[0x10]; 10474 10475 u8 max_read_request_size[0x4]; 10476 u8 max_payload_size[0x4]; 10477 u8 reserved_at_c8[0x5]; 10478 u8 pwr_status[0x3]; 10479 u8 port_type[0x4]; 10480 u8 reserved_at_d4[0xb]; 10481 u8 lane_reversal[0x1]; 10482 10483 u8 reserved_at_e0[0x14]; 10484 u8 pci_power[0xc]; 10485 10486 u8 reserved_at_100[0x20]; 10487 10488 u8 device_status[0x10]; 10489 u8 port_state[0x8]; 10490 u8 reserved_at_138[0x8]; 10491 10492 u8 reserved_at_140[0x10]; 10493 u8 receiver_detect_result[0x10]; 10494 10495 u8 reserved_at_160[0x20]; 10496 }; 10497 10498 struct mlx5_ifc_mpcnt_reg_bits { 10499 u8 reserved_at_0[0x8]; 10500 u8 pcie_index[0x8]; 10501 u8 reserved_at_10[0xa]; 10502 u8 grp[0x6]; 10503 10504 u8 clr[0x1]; 10505 u8 reserved_at_21[0x1f]; 10506 10507 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 10508 }; 10509 10510 struct mlx5_ifc_ppad_reg_bits { 10511 u8 reserved_at_0[0x3]; 10512 u8 single_mac[0x1]; 10513 u8 reserved_at_4[0x4]; 10514 u8 local_port[0x8]; 10515 u8 mac_47_32[0x10]; 10516 10517 u8 mac_31_0[0x20]; 10518 10519 u8 reserved_at_40[0x40]; 10520 }; 10521 10522 struct mlx5_ifc_pmtu_reg_bits { 10523 u8 reserved_at_0[0x8]; 10524 u8 local_port[0x8]; 10525 u8 reserved_at_10[0x10]; 10526 10527 u8 max_mtu[0x10]; 10528 u8 reserved_at_30[0x10]; 10529 10530 u8 admin_mtu[0x10]; 10531 u8 reserved_at_50[0x10]; 10532 10533 u8 oper_mtu[0x10]; 10534 u8 reserved_at_70[0x10]; 10535 }; 10536 10537 struct mlx5_ifc_pmpr_reg_bits { 10538 u8 reserved_at_0[0x8]; 10539 u8 module[0x8]; 10540 u8 reserved_at_10[0x10]; 10541 10542 u8 reserved_at_20[0x18]; 10543 u8 attenuation_5g[0x8]; 10544 10545 u8 reserved_at_40[0x18]; 10546 u8 attenuation_7g[0x8]; 10547 10548 u8 reserved_at_60[0x18]; 10549 u8 attenuation_12g[0x8]; 10550 }; 10551 10552 struct mlx5_ifc_pmpe_reg_bits { 10553 u8 reserved_at_0[0x8]; 10554 u8 module[0x8]; 10555 u8 reserved_at_10[0xc]; 10556 u8 module_status[0x4]; 10557 10558 u8 reserved_at_20[0x60]; 10559 }; 10560 10561 struct mlx5_ifc_pmpc_reg_bits { 10562 u8 module_state_updated[32][0x8]; 10563 }; 10564 10565 struct mlx5_ifc_pmlpn_reg_bits { 10566 u8 reserved_at_0[0x4]; 10567 u8 mlpn_status[0x4]; 10568 u8 local_port[0x8]; 10569 u8 reserved_at_10[0x10]; 10570 10571 u8 e[0x1]; 10572 u8 reserved_at_21[0x1f]; 10573 }; 10574 10575 struct mlx5_ifc_pmlp_reg_bits { 10576 u8 rxtx[0x1]; 10577 u8 reserved_at_1[0x7]; 10578 u8 local_port[0x8]; 10579 u8 reserved_at_10[0x8]; 10580 u8 width[0x8]; 10581 10582 u8 lane0_module_mapping[0x20]; 10583 10584 u8 lane1_module_mapping[0x20]; 10585 10586 u8 lane2_module_mapping[0x20]; 10587 10588 u8 lane3_module_mapping[0x20]; 10589 10590 u8 reserved_at_a0[0x160]; 10591 }; 10592 10593 struct mlx5_ifc_pmaos_reg_bits { 10594 u8 reserved_at_0[0x8]; 10595 u8 module[0x8]; 10596 u8 reserved_at_10[0x4]; 10597 u8 admin_status[0x4]; 10598 u8 reserved_at_18[0x4]; 10599 u8 oper_status[0x4]; 10600 10601 u8 ase[0x1]; 10602 u8 ee[0x1]; 10603 u8 reserved_at_22[0x1c]; 10604 u8 e[0x2]; 10605 10606 u8 reserved_at_40[0x40]; 10607 }; 10608 10609 struct mlx5_ifc_plpc_reg_bits { 10610 u8 reserved_at_0[0x4]; 10611 u8 profile_id[0xc]; 10612 u8 reserved_at_10[0x4]; 10613 u8 proto_mask[0x4]; 10614 u8 reserved_at_18[0x8]; 10615 10616 u8 reserved_at_20[0x10]; 10617 u8 lane_speed[0x10]; 10618 10619 u8 reserved_at_40[0x17]; 10620 u8 lpbf[0x1]; 10621 u8 fec_mode_policy[0x8]; 10622 10623 u8 retransmission_capability[0x8]; 10624 u8 fec_mode_capability[0x18]; 10625 10626 u8 retransmission_support_admin[0x8]; 10627 u8 fec_mode_support_admin[0x18]; 10628 10629 u8 retransmission_request_admin[0x8]; 10630 u8 fec_mode_request_admin[0x18]; 10631 10632 u8 reserved_at_c0[0x80]; 10633 }; 10634 10635 struct mlx5_ifc_plib_reg_bits { 10636 u8 reserved_at_0[0x8]; 10637 u8 local_port[0x8]; 10638 u8 reserved_at_10[0x8]; 10639 u8 ib_port[0x8]; 10640 10641 u8 reserved_at_20[0x60]; 10642 }; 10643 10644 struct mlx5_ifc_plbf_reg_bits { 10645 u8 reserved_at_0[0x8]; 10646 u8 local_port[0x8]; 10647 u8 reserved_at_10[0xd]; 10648 u8 lbf_mode[0x3]; 10649 10650 u8 reserved_at_20[0x20]; 10651 }; 10652 10653 struct mlx5_ifc_pipg_reg_bits { 10654 u8 reserved_at_0[0x8]; 10655 u8 local_port[0x8]; 10656 u8 reserved_at_10[0x10]; 10657 10658 u8 dic[0x1]; 10659 u8 reserved_at_21[0x19]; 10660 u8 ipg[0x4]; 10661 u8 reserved_at_3e[0x2]; 10662 }; 10663 10664 struct mlx5_ifc_pifr_reg_bits { 10665 u8 reserved_at_0[0x8]; 10666 u8 local_port[0x8]; 10667 u8 reserved_at_10[0x10]; 10668 10669 u8 reserved_at_20[0xe0]; 10670 10671 u8 port_filter[8][0x20]; 10672 10673 u8 port_filter_update_en[8][0x20]; 10674 }; 10675 10676 enum { 10677 MLX5_BUF_OWNERSHIP_UNKNOWN = 0x0, 10678 MLX5_BUF_OWNERSHIP_FW_OWNED = 0x1, 10679 MLX5_BUF_OWNERSHIP_SW_OWNED = 0x2, 10680 }; 10681 10682 struct mlx5_ifc_pfcc_reg_bits { 10683 u8 reserved_at_0[0x4]; 10684 u8 buf_ownership[0x2]; 10685 u8 reserved_at_6[0x2]; 10686 u8 local_port[0x8]; 10687 u8 reserved_at_10[0xa]; 10688 u8 cable_length_mask[0x1]; 10689 u8 ppan_mask_n[0x1]; 10690 u8 minor_stall_mask[0x1]; 10691 u8 critical_stall_mask[0x1]; 10692 u8 reserved_at_1e[0x2]; 10693 10694 u8 ppan[0x4]; 10695 u8 reserved_at_24[0x4]; 10696 u8 prio_mask_tx[0x8]; 10697 u8 reserved_at_30[0x8]; 10698 u8 prio_mask_rx[0x8]; 10699 10700 u8 pptx[0x1]; 10701 u8 aptx[0x1]; 10702 u8 pptx_mask_n[0x1]; 10703 u8 reserved_at_43[0x5]; 10704 u8 pfctx[0x8]; 10705 u8 reserved_at_50[0x10]; 10706 10707 u8 pprx[0x1]; 10708 u8 aprx[0x1]; 10709 u8 pprx_mask_n[0x1]; 10710 u8 reserved_at_63[0x5]; 10711 u8 pfcrx[0x8]; 10712 u8 reserved_at_70[0x10]; 10713 10714 u8 device_stall_minor_watermark[0x10]; 10715 u8 device_stall_critical_watermark[0x10]; 10716 10717 u8 reserved_at_a0[0x18]; 10718 u8 cable_length[0x8]; 10719 10720 u8 reserved_at_c0[0x40]; 10721 }; 10722 10723 struct mlx5_ifc_pelc_reg_bits { 10724 u8 op[0x4]; 10725 u8 reserved_at_4[0x4]; 10726 u8 local_port[0x8]; 10727 u8 reserved_at_10[0x10]; 10728 10729 u8 op_admin[0x8]; 10730 u8 op_capability[0x8]; 10731 u8 op_request[0x8]; 10732 u8 op_active[0x8]; 10733 10734 u8 admin[0x40]; 10735 10736 u8 capability[0x40]; 10737 10738 u8 request[0x40]; 10739 10740 u8 active[0x40]; 10741 10742 u8 reserved_at_140[0x80]; 10743 }; 10744 10745 struct mlx5_ifc_peir_reg_bits { 10746 u8 reserved_at_0[0x8]; 10747 u8 local_port[0x8]; 10748 u8 reserved_at_10[0x10]; 10749 10750 u8 reserved_at_20[0xc]; 10751 u8 error_count[0x4]; 10752 u8 reserved_at_30[0x10]; 10753 10754 u8 reserved_at_40[0xc]; 10755 u8 lane[0x4]; 10756 u8 reserved_at_50[0x8]; 10757 u8 error_type[0x8]; 10758 }; 10759 10760 struct mlx5_ifc_mpegc_reg_bits { 10761 u8 reserved_at_0[0x30]; 10762 u8 field_select[0x10]; 10763 10764 u8 tx_overflow_sense[0x1]; 10765 u8 mark_cqe[0x1]; 10766 u8 mark_cnp[0x1]; 10767 u8 reserved_at_43[0x1b]; 10768 u8 tx_lossy_overflow_oper[0x2]; 10769 10770 u8 reserved_at_60[0x100]; 10771 }; 10772 10773 struct mlx5_ifc_mpir_reg_bits { 10774 u8 sdm[0x1]; 10775 u8 reserved_at_1[0x1b]; 10776 u8 host_buses[0x4]; 10777 10778 u8 reserved_at_20[0x20]; 10779 10780 u8 local_port[0x8]; 10781 u8 reserved_at_28[0x18]; 10782 10783 u8 reserved_at_60[0x20]; 10784 }; 10785 10786 enum { 10787 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 10788 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 10789 }; 10790 10791 enum { 10792 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 10793 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 10794 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 10795 }; 10796 10797 struct mlx5_ifc_mtutc_reg_bits { 10798 u8 reserved_at_0[0x5]; 10799 u8 freq_adj_units[0x3]; 10800 u8 reserved_at_8[0x3]; 10801 u8 log_max_freq_adjustment[0x5]; 10802 10803 u8 reserved_at_10[0xc]; 10804 u8 operation[0x4]; 10805 10806 u8 freq_adjustment[0x20]; 10807 10808 u8 reserved_at_40[0x40]; 10809 10810 u8 utc_sec[0x20]; 10811 10812 u8 reserved_at_a0[0x2]; 10813 u8 utc_nsec[0x1e]; 10814 10815 u8 time_adjustment[0x20]; 10816 }; 10817 10818 struct mlx5_ifc_pcam_enhanced_features_bits { 10819 u8 reserved_at_0[0x10]; 10820 u8 ppcnt_recovery_counters[0x1]; 10821 u8 reserved_at_11[0x7]; 10822 u8 cable_length[0x1]; 10823 u8 reserved_at_19[0x4]; 10824 u8 fec_200G_per_lane_in_pplm[0x1]; 10825 u8 reserved_at_1e[0x2a]; 10826 u8 fec_100G_per_lane_in_pplm[0x1]; 10827 u8 reserved_at_49[0xa]; 10828 u8 buffer_ownership[0x1]; 10829 u8 resereved_at_54[0x14]; 10830 u8 fec_50G_per_lane_in_pplm[0x1]; 10831 u8 reserved_at_69[0x4]; 10832 u8 rx_icrc_encapsulated_counter[0x1]; 10833 u8 reserved_at_6e[0x4]; 10834 u8 ptys_extended_ethernet[0x1]; 10835 u8 reserved_at_73[0x3]; 10836 u8 pfcc_mask[0x1]; 10837 u8 reserved_at_77[0x3]; 10838 u8 per_lane_error_counters[0x1]; 10839 u8 rx_buffer_fullness_counters[0x1]; 10840 u8 ptys_connector_type[0x1]; 10841 u8 reserved_at_7d[0x1]; 10842 u8 ppcnt_discard_group[0x1]; 10843 u8 ppcnt_statistical_group[0x1]; 10844 }; 10845 10846 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10847 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10848 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10849 10850 u8 port_access_reg_cap_mask_63[0x1]; 10851 u8 pphcr[0x1]; 10852 u8 port_access_reg_cap_mask_61_to_36[0x1a]; 10853 u8 pplm[0x1]; 10854 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10855 10856 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10857 u8 pbmc[0x1]; 10858 u8 pptb[0x1]; 10859 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10860 u8 ppcnt[0x1]; 10861 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10862 }; 10863 10864 struct mlx5_ifc_pcam_reg_bits { 10865 u8 reserved_at_0[0x8]; 10866 u8 feature_group[0x8]; 10867 u8 reserved_at_10[0x8]; 10868 u8 access_reg_group[0x8]; 10869 10870 u8 reserved_at_20[0x20]; 10871 10872 union { 10873 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10874 u8 reserved_at_0[0x80]; 10875 } port_access_reg_cap_mask; 10876 10877 u8 reserved_at_c0[0x80]; 10878 10879 union { 10880 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10881 u8 reserved_at_0[0x80]; 10882 } feature_cap_mask; 10883 10884 u8 reserved_at_1c0[0xc0]; 10885 }; 10886 10887 struct mlx5_ifc_mcam_enhanced_features_bits { 10888 u8 reserved_at_0[0x50]; 10889 u8 mtutc_freq_adj_units[0x1]; 10890 u8 mtutc_time_adjustment_extended_range[0x1]; 10891 u8 reserved_at_52[0xb]; 10892 u8 mcia_32dwords[0x1]; 10893 u8 out_pulse_duration_ns[0x1]; 10894 u8 npps_period[0x1]; 10895 u8 reserved_at_60[0xa]; 10896 u8 reset_state[0x1]; 10897 u8 ptpcyc2realtime_modify[0x1]; 10898 u8 reserved_at_6c[0x2]; 10899 u8 pci_status_and_power[0x1]; 10900 u8 reserved_at_6f[0x5]; 10901 u8 mark_tx_action_cnp[0x1]; 10902 u8 mark_tx_action_cqe[0x1]; 10903 u8 dynamic_tx_overflow[0x1]; 10904 u8 reserved_at_77[0x4]; 10905 u8 pcie_outbound_stalled[0x1]; 10906 u8 tx_overflow_buffer_pkt[0x1]; 10907 u8 mtpps_enh_out_per_adj[0x1]; 10908 u8 mtpps_fs[0x1]; 10909 u8 pcie_performance_group[0x1]; 10910 }; 10911 10912 struct mlx5_ifc_mcam_access_reg_bits { 10913 u8 reserved_at_0[0x1c]; 10914 u8 mcda[0x1]; 10915 u8 mcc[0x1]; 10916 u8 mcqi[0x1]; 10917 u8 mcqs[0x1]; 10918 10919 u8 regs_95_to_90[0x6]; 10920 u8 mpir[0x1]; 10921 u8 regs_88_to_87[0x2]; 10922 u8 mpegc[0x1]; 10923 u8 mtutc[0x1]; 10924 u8 regs_84_to_68[0x11]; 10925 u8 tracer_registers[0x4]; 10926 10927 u8 regs_63_to_46[0x12]; 10928 u8 mrtc[0x1]; 10929 u8 regs_44_to_41[0x4]; 10930 u8 mfrl[0x1]; 10931 u8 regs_39_to_32[0x8]; 10932 10933 u8 regs_31_to_11[0x15]; 10934 u8 mtmp[0x1]; 10935 u8 regs_9_to_0[0xa]; 10936 }; 10937 10938 struct mlx5_ifc_mcam_access_reg_bits1 { 10939 u8 regs_127_to_96[0x20]; 10940 10941 u8 regs_95_to_64[0x20]; 10942 10943 u8 regs_63_to_32[0x20]; 10944 10945 u8 regs_31_to_0[0x20]; 10946 }; 10947 10948 struct mlx5_ifc_mcam_access_reg_bits2 { 10949 u8 regs_127_to_99[0x1d]; 10950 u8 mirc[0x1]; 10951 u8 regs_97_to_96[0x2]; 10952 10953 u8 regs_95_to_87[0x09]; 10954 u8 synce_registers[0x2]; 10955 u8 regs_84_to_64[0x15]; 10956 10957 u8 regs_63_to_32[0x20]; 10958 10959 u8 regs_31_to_0[0x20]; 10960 }; 10961 10962 struct mlx5_ifc_mcam_access_reg_bits3 { 10963 u8 regs_127_to_96[0x20]; 10964 10965 u8 regs_95_to_64[0x20]; 10966 10967 u8 regs_63_to_32[0x20]; 10968 10969 u8 regs_31_to_3[0x1d]; 10970 u8 mrtcq[0x1]; 10971 u8 mtctr[0x1]; 10972 u8 mtptm[0x1]; 10973 }; 10974 10975 struct mlx5_ifc_mcam_reg_bits { 10976 u8 reserved_at_0[0x8]; 10977 u8 feature_group[0x8]; 10978 u8 reserved_at_10[0x8]; 10979 u8 access_reg_group[0x8]; 10980 10981 u8 reserved_at_20[0x20]; 10982 10983 union { 10984 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10985 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10986 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10987 struct mlx5_ifc_mcam_access_reg_bits3 access_regs3; 10988 u8 reserved_at_0[0x80]; 10989 } mng_access_reg_cap_mask; 10990 10991 u8 reserved_at_c0[0x80]; 10992 10993 union { 10994 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10995 u8 reserved_at_0[0x80]; 10996 } mng_feature_cap_mask; 10997 10998 u8 reserved_at_1c0[0x80]; 10999 }; 11000 11001 struct mlx5_ifc_qcam_access_reg_cap_mask { 11002 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 11003 u8 qpdpm[0x1]; 11004 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 11005 u8 qdpm[0x1]; 11006 u8 qpts[0x1]; 11007 u8 qcap[0x1]; 11008 u8 qcam_access_reg_cap_mask_0[0x1]; 11009 }; 11010 11011 struct mlx5_ifc_qcam_qos_feature_cap_mask { 11012 u8 qcam_qos_feature_cap_mask_127_to_5[0x7B]; 11013 u8 qetcr_qshr_max_bw_val_msb[0x1]; 11014 u8 qcam_qos_feature_cap_mask_3_to_1[0x3]; 11015 u8 qpts_trust_both[0x1]; 11016 }; 11017 11018 struct mlx5_ifc_qcam_reg_bits { 11019 u8 reserved_at_0[0x8]; 11020 u8 feature_group[0x8]; 11021 u8 reserved_at_10[0x8]; 11022 u8 access_reg_group[0x8]; 11023 u8 reserved_at_20[0x20]; 11024 11025 union { 11026 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 11027 u8 reserved_at_0[0x80]; 11028 } qos_access_reg_cap_mask; 11029 11030 u8 reserved_at_c0[0x80]; 11031 11032 union { 11033 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 11034 u8 reserved_at_0[0x80]; 11035 } qos_feature_cap_mask; 11036 11037 u8 reserved_at_1c0[0x80]; 11038 }; 11039 11040 struct mlx5_ifc_core_dump_reg_bits { 11041 u8 reserved_at_0[0x18]; 11042 u8 core_dump_type[0x8]; 11043 11044 u8 reserved_at_20[0x30]; 11045 u8 vhca_id[0x10]; 11046 11047 u8 reserved_at_60[0x8]; 11048 u8 qpn[0x18]; 11049 u8 reserved_at_80[0x180]; 11050 }; 11051 11052 struct mlx5_ifc_pcap_reg_bits { 11053 u8 reserved_at_0[0x8]; 11054 u8 local_port[0x8]; 11055 u8 reserved_at_10[0x10]; 11056 11057 u8 port_capability_mask[4][0x20]; 11058 }; 11059 11060 struct mlx5_ifc_paos_reg_bits { 11061 u8 swid[0x8]; 11062 u8 local_port[0x8]; 11063 u8 reserved_at_10[0x4]; 11064 u8 admin_status[0x4]; 11065 u8 reserved_at_18[0x4]; 11066 u8 oper_status[0x4]; 11067 11068 u8 ase[0x1]; 11069 u8 ee[0x1]; 11070 u8 reserved_at_22[0x1c]; 11071 u8 e[0x2]; 11072 11073 u8 reserved_at_40[0x40]; 11074 }; 11075 11076 struct mlx5_ifc_pamp_reg_bits { 11077 u8 reserved_at_0[0x8]; 11078 u8 opamp_group[0x8]; 11079 u8 reserved_at_10[0xc]; 11080 u8 opamp_group_type[0x4]; 11081 11082 u8 start_index[0x10]; 11083 u8 reserved_at_30[0x4]; 11084 u8 num_of_indices[0xc]; 11085 11086 u8 index_data[18][0x10]; 11087 }; 11088 11089 struct mlx5_ifc_pcmr_reg_bits { 11090 u8 reserved_at_0[0x8]; 11091 u8 local_port[0x8]; 11092 u8 reserved_at_10[0x10]; 11093 11094 u8 entropy_force_cap[0x1]; 11095 u8 entropy_calc_cap[0x1]; 11096 u8 entropy_gre_calc_cap[0x1]; 11097 u8 reserved_at_23[0xf]; 11098 u8 rx_ts_over_crc_cap[0x1]; 11099 u8 reserved_at_33[0xb]; 11100 u8 fcs_cap[0x1]; 11101 u8 reserved_at_3f[0x1]; 11102 11103 u8 entropy_force[0x1]; 11104 u8 entropy_calc[0x1]; 11105 u8 entropy_gre_calc[0x1]; 11106 u8 reserved_at_43[0xf]; 11107 u8 rx_ts_over_crc[0x1]; 11108 u8 reserved_at_53[0xb]; 11109 u8 fcs_chk[0x1]; 11110 u8 reserved_at_5f[0x1]; 11111 }; 11112 11113 struct mlx5_ifc_lane_2_module_mapping_bits { 11114 u8 reserved_at_0[0x4]; 11115 u8 rx_lane[0x4]; 11116 u8 reserved_at_8[0x4]; 11117 u8 tx_lane[0x4]; 11118 u8 reserved_at_10[0x8]; 11119 u8 module[0x8]; 11120 }; 11121 11122 struct mlx5_ifc_bufferx_reg_bits { 11123 u8 reserved_at_0[0x6]; 11124 u8 lossy[0x1]; 11125 u8 epsb[0x1]; 11126 u8 reserved_at_8[0x8]; 11127 u8 size[0x10]; 11128 11129 u8 xoff_threshold[0x10]; 11130 u8 xon_threshold[0x10]; 11131 }; 11132 11133 struct mlx5_ifc_set_node_in_bits { 11134 u8 node_description[64][0x8]; 11135 }; 11136 11137 struct mlx5_ifc_register_power_settings_bits { 11138 u8 reserved_at_0[0x18]; 11139 u8 power_settings_level[0x8]; 11140 11141 u8 reserved_at_20[0x60]; 11142 }; 11143 11144 struct mlx5_ifc_register_host_endianness_bits { 11145 u8 he[0x1]; 11146 u8 reserved_at_1[0x1f]; 11147 11148 u8 reserved_at_20[0x60]; 11149 }; 11150 11151 struct mlx5_ifc_umr_pointer_desc_argument_bits { 11152 u8 reserved_at_0[0x20]; 11153 11154 u8 mkey[0x20]; 11155 11156 u8 addressh_63_32[0x20]; 11157 11158 u8 addressl_31_0[0x20]; 11159 }; 11160 11161 struct mlx5_ifc_ud_adrs_vector_bits { 11162 u8 dc_key[0x40]; 11163 11164 u8 ext[0x1]; 11165 u8 reserved_at_41[0x7]; 11166 u8 destination_qp_dct[0x18]; 11167 11168 u8 static_rate[0x4]; 11169 u8 sl_eth_prio[0x4]; 11170 u8 fl[0x1]; 11171 u8 mlid[0x7]; 11172 u8 rlid_udp_sport[0x10]; 11173 11174 u8 reserved_at_80[0x20]; 11175 11176 u8 rmac_47_16[0x20]; 11177 11178 u8 rmac_15_0[0x10]; 11179 u8 tclass[0x8]; 11180 u8 hop_limit[0x8]; 11181 11182 u8 reserved_at_e0[0x1]; 11183 u8 grh[0x1]; 11184 u8 reserved_at_e2[0x2]; 11185 u8 src_addr_index[0x8]; 11186 u8 flow_label[0x14]; 11187 11188 u8 rgid_rip[16][0x8]; 11189 }; 11190 11191 struct mlx5_ifc_pages_req_event_bits { 11192 u8 reserved_at_0[0x10]; 11193 u8 function_id[0x10]; 11194 11195 u8 num_pages[0x20]; 11196 11197 u8 reserved_at_40[0xa0]; 11198 }; 11199 11200 struct mlx5_ifc_eqe_bits { 11201 u8 reserved_at_0[0x8]; 11202 u8 event_type[0x8]; 11203 u8 reserved_at_10[0x8]; 11204 u8 event_sub_type[0x8]; 11205 11206 u8 reserved_at_20[0xe0]; 11207 11208 union mlx5_ifc_event_auto_bits event_data; 11209 11210 u8 reserved_at_1e0[0x10]; 11211 u8 signature[0x8]; 11212 u8 reserved_at_1f8[0x7]; 11213 u8 owner[0x1]; 11214 }; 11215 11216 enum { 11217 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 11218 }; 11219 11220 struct mlx5_ifc_cmd_queue_entry_bits { 11221 u8 type[0x8]; 11222 u8 reserved_at_8[0x18]; 11223 11224 u8 input_length[0x20]; 11225 11226 u8 input_mailbox_pointer_63_32[0x20]; 11227 11228 u8 input_mailbox_pointer_31_9[0x17]; 11229 u8 reserved_at_77[0x9]; 11230 11231 u8 command_input_inline_data[16][0x8]; 11232 11233 u8 command_output_inline_data[16][0x8]; 11234 11235 u8 output_mailbox_pointer_63_32[0x20]; 11236 11237 u8 output_mailbox_pointer_31_9[0x17]; 11238 u8 reserved_at_1b7[0x9]; 11239 11240 u8 output_length[0x20]; 11241 11242 u8 token[0x8]; 11243 u8 signature[0x8]; 11244 u8 reserved_at_1f0[0x8]; 11245 u8 status[0x7]; 11246 u8 ownership[0x1]; 11247 }; 11248 11249 struct mlx5_ifc_cmd_out_bits { 11250 u8 status[0x8]; 11251 u8 reserved_at_8[0x18]; 11252 11253 u8 syndrome[0x20]; 11254 11255 u8 command_output[0x20]; 11256 }; 11257 11258 struct mlx5_ifc_cmd_in_bits { 11259 u8 opcode[0x10]; 11260 u8 reserved_at_10[0x10]; 11261 11262 u8 reserved_at_20[0x10]; 11263 u8 op_mod[0x10]; 11264 11265 u8 command[][0x20]; 11266 }; 11267 11268 struct mlx5_ifc_cmd_if_box_bits { 11269 u8 mailbox_data[512][0x8]; 11270 11271 u8 reserved_at_1000[0x180]; 11272 11273 u8 next_pointer_63_32[0x20]; 11274 11275 u8 next_pointer_31_10[0x16]; 11276 u8 reserved_at_11b6[0xa]; 11277 11278 u8 block_number[0x20]; 11279 11280 u8 reserved_at_11e0[0x8]; 11281 u8 token[0x8]; 11282 u8 ctrl_signature[0x8]; 11283 u8 signature[0x8]; 11284 }; 11285 11286 struct mlx5_ifc_mtt_bits { 11287 u8 ptag_63_32[0x20]; 11288 11289 u8 ptag_31_8[0x18]; 11290 u8 reserved_at_38[0x6]; 11291 u8 wr_en[0x1]; 11292 u8 rd_en[0x1]; 11293 }; 11294 11295 struct mlx5_ifc_query_wol_rol_out_bits { 11296 u8 status[0x8]; 11297 u8 reserved_at_8[0x18]; 11298 11299 u8 syndrome[0x20]; 11300 11301 u8 reserved_at_40[0x10]; 11302 u8 rol_mode[0x8]; 11303 u8 wol_mode[0x8]; 11304 11305 u8 reserved_at_60[0x20]; 11306 }; 11307 11308 struct mlx5_ifc_query_wol_rol_in_bits { 11309 u8 opcode[0x10]; 11310 u8 reserved_at_10[0x10]; 11311 11312 u8 reserved_at_20[0x10]; 11313 u8 op_mod[0x10]; 11314 11315 u8 reserved_at_40[0x40]; 11316 }; 11317 11318 struct mlx5_ifc_set_wol_rol_out_bits { 11319 u8 status[0x8]; 11320 u8 reserved_at_8[0x18]; 11321 11322 u8 syndrome[0x20]; 11323 11324 u8 reserved_at_40[0x40]; 11325 }; 11326 11327 struct mlx5_ifc_set_wol_rol_in_bits { 11328 u8 opcode[0x10]; 11329 u8 reserved_at_10[0x10]; 11330 11331 u8 reserved_at_20[0x10]; 11332 u8 op_mod[0x10]; 11333 11334 u8 rol_mode_valid[0x1]; 11335 u8 wol_mode_valid[0x1]; 11336 u8 reserved_at_42[0xe]; 11337 u8 rol_mode[0x8]; 11338 u8 wol_mode[0x8]; 11339 11340 u8 reserved_at_60[0x20]; 11341 }; 11342 11343 enum { 11344 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 11345 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 11346 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 11347 MLX5_INITIAL_SEG_NIC_INTERFACE_SW_RESET = 0x7, 11348 }; 11349 11350 enum { 11351 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 11352 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 11353 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 11354 }; 11355 11356 enum { 11357 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 11358 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 11359 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 11360 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 11361 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 11362 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 11363 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 11364 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 11365 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 11366 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 11367 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 11368 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR = 0x12, 11369 MLX5_INITIAL_SEG_HEALTH_SYNDROME_TRUST_LOCKDOWN_ERR = 0x13, 11370 }; 11371 11372 struct mlx5_ifc_initial_seg_bits { 11373 u8 fw_rev_minor[0x10]; 11374 u8 fw_rev_major[0x10]; 11375 11376 u8 cmd_interface_rev[0x10]; 11377 u8 fw_rev_subminor[0x10]; 11378 11379 u8 reserved_at_40[0x40]; 11380 11381 u8 cmdq_phy_addr_63_32[0x20]; 11382 11383 u8 cmdq_phy_addr_31_12[0x14]; 11384 u8 reserved_at_b4[0x2]; 11385 u8 nic_interface[0x2]; 11386 u8 log_cmdq_size[0x4]; 11387 u8 log_cmdq_stride[0x4]; 11388 11389 u8 command_doorbell_vector[0x20]; 11390 11391 u8 reserved_at_e0[0xf00]; 11392 11393 u8 initializing[0x1]; 11394 u8 reserved_at_fe1[0x4]; 11395 u8 nic_interface_supported[0x3]; 11396 u8 embedded_cpu[0x1]; 11397 u8 reserved_at_fe9[0x17]; 11398 11399 struct mlx5_ifc_health_buffer_bits health_buffer; 11400 11401 u8 no_dram_nic_offset[0x20]; 11402 11403 u8 reserved_at_1220[0x6e40]; 11404 11405 u8 reserved_at_8060[0x1f]; 11406 u8 clear_int[0x1]; 11407 11408 u8 health_syndrome[0x8]; 11409 u8 health_counter[0x18]; 11410 11411 u8 reserved_at_80a0[0x17fc0]; 11412 }; 11413 11414 struct mlx5_ifc_mtpps_reg_bits { 11415 u8 reserved_at_0[0xc]; 11416 u8 cap_number_of_pps_pins[0x4]; 11417 u8 reserved_at_10[0x4]; 11418 u8 cap_max_num_of_pps_in_pins[0x4]; 11419 u8 reserved_at_18[0x4]; 11420 u8 cap_max_num_of_pps_out_pins[0x4]; 11421 11422 u8 reserved_at_20[0x13]; 11423 u8 cap_log_min_npps_period[0x5]; 11424 u8 reserved_at_38[0x3]; 11425 u8 cap_log_min_out_pulse_duration_ns[0x5]; 11426 11427 u8 reserved_at_40[0x4]; 11428 u8 cap_pin_3_mode[0x4]; 11429 u8 reserved_at_48[0x4]; 11430 u8 cap_pin_2_mode[0x4]; 11431 u8 reserved_at_50[0x4]; 11432 u8 cap_pin_1_mode[0x4]; 11433 u8 reserved_at_58[0x4]; 11434 u8 cap_pin_0_mode[0x4]; 11435 11436 u8 reserved_at_60[0x4]; 11437 u8 cap_pin_7_mode[0x4]; 11438 u8 reserved_at_68[0x4]; 11439 u8 cap_pin_6_mode[0x4]; 11440 u8 reserved_at_70[0x4]; 11441 u8 cap_pin_5_mode[0x4]; 11442 u8 reserved_at_78[0x4]; 11443 u8 cap_pin_4_mode[0x4]; 11444 11445 u8 field_select[0x20]; 11446 u8 reserved_at_a0[0x20]; 11447 11448 u8 npps_period[0x40]; 11449 11450 u8 enable[0x1]; 11451 u8 reserved_at_101[0xb]; 11452 u8 pattern[0x4]; 11453 u8 reserved_at_110[0x4]; 11454 u8 pin_mode[0x4]; 11455 u8 pin[0x8]; 11456 11457 u8 reserved_at_120[0x2]; 11458 u8 out_pulse_duration_ns[0x1e]; 11459 11460 u8 time_stamp[0x40]; 11461 11462 u8 out_pulse_duration[0x10]; 11463 u8 out_periodic_adjustment[0x10]; 11464 u8 enhanced_out_periodic_adjustment[0x20]; 11465 11466 u8 reserved_at_1c0[0x20]; 11467 }; 11468 11469 struct mlx5_ifc_mtppse_reg_bits { 11470 u8 reserved_at_0[0x18]; 11471 u8 pin[0x8]; 11472 u8 event_arm[0x1]; 11473 u8 reserved_at_21[0x1b]; 11474 u8 event_generation_mode[0x4]; 11475 u8 reserved_at_40[0x40]; 11476 }; 11477 11478 struct mlx5_ifc_mcqs_reg_bits { 11479 u8 last_index_flag[0x1]; 11480 u8 reserved_at_1[0x7]; 11481 u8 fw_device[0x8]; 11482 u8 component_index[0x10]; 11483 11484 u8 reserved_at_20[0x10]; 11485 u8 identifier[0x10]; 11486 11487 u8 reserved_at_40[0x17]; 11488 u8 component_status[0x5]; 11489 u8 component_update_state[0x4]; 11490 11491 u8 last_update_state_changer_type[0x4]; 11492 u8 last_update_state_changer_host_id[0x4]; 11493 u8 reserved_at_68[0x18]; 11494 }; 11495 11496 struct mlx5_ifc_mcqi_cap_bits { 11497 u8 supported_info_bitmask[0x20]; 11498 11499 u8 component_size[0x20]; 11500 11501 u8 max_component_size[0x20]; 11502 11503 u8 log_mcda_word_size[0x4]; 11504 u8 reserved_at_64[0xc]; 11505 u8 mcda_max_write_size[0x10]; 11506 11507 u8 rd_en[0x1]; 11508 u8 reserved_at_81[0x1]; 11509 u8 match_chip_id[0x1]; 11510 u8 match_psid[0x1]; 11511 u8 check_user_timestamp[0x1]; 11512 u8 match_base_guid_mac[0x1]; 11513 u8 reserved_at_86[0x1a]; 11514 }; 11515 11516 struct mlx5_ifc_mcqi_version_bits { 11517 u8 reserved_at_0[0x2]; 11518 u8 build_time_valid[0x1]; 11519 u8 user_defined_time_valid[0x1]; 11520 u8 reserved_at_4[0x14]; 11521 u8 version_string_length[0x8]; 11522 11523 u8 version[0x20]; 11524 11525 u8 build_time[0x40]; 11526 11527 u8 user_defined_time[0x40]; 11528 11529 u8 build_tool_version[0x20]; 11530 11531 u8 reserved_at_e0[0x20]; 11532 11533 u8 version_string[92][0x8]; 11534 }; 11535 11536 struct mlx5_ifc_mcqi_activation_method_bits { 11537 u8 pending_server_ac_power_cycle[0x1]; 11538 u8 pending_server_dc_power_cycle[0x1]; 11539 u8 pending_server_reboot[0x1]; 11540 u8 pending_fw_reset[0x1]; 11541 u8 auto_activate[0x1]; 11542 u8 all_hosts_sync[0x1]; 11543 u8 device_hw_reset[0x1]; 11544 u8 reserved_at_7[0x19]; 11545 }; 11546 11547 union mlx5_ifc_mcqi_reg_data_bits { 11548 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 11549 struct mlx5_ifc_mcqi_version_bits mcqi_version; 11550 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 11551 }; 11552 11553 struct mlx5_ifc_mcqi_reg_bits { 11554 u8 read_pending_component[0x1]; 11555 u8 reserved_at_1[0xf]; 11556 u8 component_index[0x10]; 11557 11558 u8 reserved_at_20[0x20]; 11559 11560 u8 reserved_at_40[0x1b]; 11561 u8 info_type[0x5]; 11562 11563 u8 info_size[0x20]; 11564 11565 u8 offset[0x20]; 11566 11567 u8 reserved_at_a0[0x10]; 11568 u8 data_size[0x10]; 11569 11570 union mlx5_ifc_mcqi_reg_data_bits data[]; 11571 }; 11572 11573 struct mlx5_ifc_mcc_reg_bits { 11574 u8 reserved_at_0[0x4]; 11575 u8 time_elapsed_since_last_cmd[0xc]; 11576 u8 reserved_at_10[0x8]; 11577 u8 instruction[0x8]; 11578 11579 u8 reserved_at_20[0x10]; 11580 u8 component_index[0x10]; 11581 11582 u8 reserved_at_40[0x8]; 11583 u8 update_handle[0x18]; 11584 11585 u8 handle_owner_type[0x4]; 11586 u8 handle_owner_host_id[0x4]; 11587 u8 reserved_at_68[0x1]; 11588 u8 control_progress[0x7]; 11589 u8 error_code[0x8]; 11590 u8 reserved_at_78[0x4]; 11591 u8 control_state[0x4]; 11592 11593 u8 component_size[0x20]; 11594 11595 u8 reserved_at_a0[0x60]; 11596 }; 11597 11598 struct mlx5_ifc_mcda_reg_bits { 11599 u8 reserved_at_0[0x8]; 11600 u8 update_handle[0x18]; 11601 11602 u8 offset[0x20]; 11603 11604 u8 reserved_at_40[0x10]; 11605 u8 size[0x10]; 11606 11607 u8 reserved_at_60[0x20]; 11608 11609 u8 data[][0x20]; 11610 }; 11611 11612 enum { 11613 MLX5_MFRL_REG_PCI_RESET_METHOD_LINK_TOGGLE = 0, 11614 MLX5_MFRL_REG_PCI_RESET_METHOD_HOT_RESET = 1, 11615 }; 11616 11617 enum { 11618 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 11619 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 11620 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 11621 MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3, 11622 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 11623 MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5, 11624 }; 11625 11626 enum { 11627 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 11628 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 11629 }; 11630 11631 enum { 11632 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 11633 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 11634 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 11635 }; 11636 11637 struct mlx5_ifc_mfrl_reg_bits { 11638 u8 reserved_at_0[0x20]; 11639 11640 u8 reserved_at_20[0x2]; 11641 u8 pci_sync_for_fw_update_start[0x1]; 11642 u8 pci_sync_for_fw_update_resp[0x2]; 11643 u8 rst_type_sel[0x3]; 11644 u8 pci_reset_req_method[0x3]; 11645 u8 reserved_at_2b[0x1]; 11646 u8 reset_state[0x4]; 11647 u8 reset_type[0x8]; 11648 u8 reset_level[0x8]; 11649 }; 11650 11651 struct mlx5_ifc_mirc_reg_bits { 11652 u8 reserved_at_0[0x18]; 11653 u8 status_code[0x8]; 11654 11655 u8 reserved_at_20[0x20]; 11656 }; 11657 11658 struct mlx5_ifc_pddr_monitor_opcode_bits { 11659 u8 reserved_at_0[0x10]; 11660 u8 monitor_opcode[0x10]; 11661 }; 11662 11663 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 11664 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11665 u8 reserved_at_0[0x20]; 11666 }; 11667 11668 enum { 11669 /* Monitor opcodes */ 11670 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 11671 }; 11672 11673 struct mlx5_ifc_pddr_troubleshooting_page_bits { 11674 u8 reserved_at_0[0x10]; 11675 u8 group_opcode[0x10]; 11676 11677 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 11678 11679 u8 reserved_at_40[0x20]; 11680 11681 u8 status_message[59][0x20]; 11682 }; 11683 11684 union mlx5_ifc_pddr_reg_page_data_auto_bits { 11685 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11686 u8 reserved_at_0[0x7c0]; 11687 }; 11688 11689 enum { 11690 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 11691 }; 11692 11693 struct mlx5_ifc_pddr_reg_bits { 11694 u8 reserved_at_0[0x8]; 11695 u8 local_port[0x8]; 11696 u8 pnat[0x2]; 11697 u8 reserved_at_12[0xe]; 11698 11699 u8 reserved_at_20[0x18]; 11700 u8 page_select[0x8]; 11701 11702 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 11703 }; 11704 11705 struct mlx5_ifc_mrtc_reg_bits { 11706 u8 time_synced[0x1]; 11707 u8 reserved_at_1[0x1f]; 11708 11709 u8 reserved_at_20[0x20]; 11710 11711 u8 time_h[0x20]; 11712 11713 u8 time_l[0x20]; 11714 }; 11715 11716 struct mlx5_ifc_mtcap_reg_bits { 11717 u8 reserved_at_0[0x19]; 11718 u8 sensor_count[0x7]; 11719 11720 u8 reserved_at_20[0x20]; 11721 11722 u8 sensor_map[0x40]; 11723 }; 11724 11725 struct mlx5_ifc_mtmp_reg_bits { 11726 u8 reserved_at_0[0x14]; 11727 u8 sensor_index[0xc]; 11728 11729 u8 reserved_at_20[0x10]; 11730 u8 temperature[0x10]; 11731 11732 u8 mte[0x1]; 11733 u8 mtr[0x1]; 11734 u8 reserved_at_42[0xe]; 11735 u8 max_temperature[0x10]; 11736 11737 u8 tee[0x2]; 11738 u8 reserved_at_62[0xe]; 11739 u8 temp_threshold_hi[0x10]; 11740 11741 u8 reserved_at_80[0x10]; 11742 u8 temp_threshold_lo[0x10]; 11743 11744 u8 reserved_at_a0[0x20]; 11745 11746 u8 sensor_name_hi[0x20]; 11747 u8 sensor_name_lo[0x20]; 11748 }; 11749 11750 struct mlx5_ifc_mtptm_reg_bits { 11751 u8 reserved_at_0[0x10]; 11752 u8 psta[0x1]; 11753 u8 reserved_at_11[0xf]; 11754 11755 u8 reserved_at_20[0x60]; 11756 }; 11757 11758 enum { 11759 MLX5_MTCTR_REQUEST_NOP = 0x0, 11760 MLX5_MTCTR_REQUEST_PTM_ROOT_CLOCK = 0x1, 11761 MLX5_MTCTR_REQUEST_FREE_RUNNING_COUNTER = 0x2, 11762 MLX5_MTCTR_REQUEST_REAL_TIME_CLOCK = 0x3, 11763 }; 11764 11765 struct mlx5_ifc_mtctr_reg_bits { 11766 u8 first_clock_timestamp_request[0x8]; 11767 u8 second_clock_timestamp_request[0x8]; 11768 u8 reserved_at_10[0x10]; 11769 11770 u8 first_clock_valid[0x1]; 11771 u8 second_clock_valid[0x1]; 11772 u8 reserved_at_22[0x1e]; 11773 11774 u8 first_clock_timestamp[0x40]; 11775 u8 second_clock_timestamp[0x40]; 11776 }; 11777 11778 struct mlx5_ifc_bin_range_layout_bits { 11779 u8 reserved_at_0[0xa]; 11780 u8 high_val[0x6]; 11781 u8 reserved_at_10[0xa]; 11782 u8 low_val[0x6]; 11783 }; 11784 11785 struct mlx5_ifc_pphcr_reg_bits { 11786 u8 active_hist_type[0x4]; 11787 u8 reserved_at_4[0x4]; 11788 u8 local_port[0x8]; 11789 u8 reserved_at_10[0x10]; 11790 11791 u8 reserved_at_20[0x8]; 11792 u8 num_of_bins[0x8]; 11793 u8 reserved_at_30[0x10]; 11794 11795 u8 reserved_at_40[0x40]; 11796 11797 struct mlx5_ifc_bin_range_layout_bits bin_range[16]; 11798 }; 11799 11800 union mlx5_ifc_ports_control_registers_document_bits { 11801 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 11802 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 11803 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 11804 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 11805 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 11806 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 11807 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 11808 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 11809 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 11810 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 11811 struct mlx5_ifc_pamp_reg_bits pamp_reg; 11812 struct mlx5_ifc_paos_reg_bits paos_reg; 11813 struct mlx5_ifc_pcap_reg_bits pcap_reg; 11814 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11815 struct mlx5_ifc_pddr_reg_bits pddr_reg; 11816 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11817 struct mlx5_ifc_peir_reg_bits peir_reg; 11818 struct mlx5_ifc_pelc_reg_bits pelc_reg; 11819 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 11820 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 11821 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 11822 struct mlx5_ifc_pifr_reg_bits pifr_reg; 11823 struct mlx5_ifc_pipg_reg_bits pipg_reg; 11824 struct mlx5_ifc_plbf_reg_bits plbf_reg; 11825 struct mlx5_ifc_plib_reg_bits plib_reg; 11826 struct mlx5_ifc_plpc_reg_bits plpc_reg; 11827 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 11828 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 11829 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 11830 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 11831 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 11832 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 11833 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 11834 struct mlx5_ifc_ppad_reg_bits ppad_reg; 11835 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 11836 struct mlx5_ifc_mpein_reg_bits mpein_reg; 11837 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 11838 struct mlx5_ifc_pplm_reg_bits pplm_reg; 11839 struct mlx5_ifc_pplr_reg_bits pplr_reg; 11840 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 11841 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 11842 struct mlx5_ifc_pspa_reg_bits pspa_reg; 11843 struct mlx5_ifc_ptas_reg_bits ptas_reg; 11844 struct mlx5_ifc_ptys_reg_bits ptys_reg; 11845 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 11846 struct mlx5_ifc_pude_reg_bits pude_reg; 11847 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 11848 struct mlx5_ifc_slrg_reg_bits slrg_reg; 11849 struct mlx5_ifc_sltp_reg_bits sltp_reg; 11850 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 11851 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 11852 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 11853 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 11854 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 11855 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 11856 struct mlx5_ifc_mcc_reg_bits mcc_reg; 11857 struct mlx5_ifc_mcda_reg_bits mcda_reg; 11858 struct mlx5_ifc_mirc_reg_bits mirc_reg; 11859 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 11860 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 11861 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 11862 struct mlx5_ifc_mtcap_reg_bits mtcap_reg; 11863 struct mlx5_ifc_mtmp_reg_bits mtmp_reg; 11864 struct mlx5_ifc_mtptm_reg_bits mtptm_reg; 11865 struct mlx5_ifc_mtctr_reg_bits mtctr_reg; 11866 struct mlx5_ifc_pphcr_reg_bits pphcr_reg; 11867 u8 reserved_at_0[0x60e0]; 11868 }; 11869 11870 union mlx5_ifc_debug_enhancements_document_bits { 11871 struct mlx5_ifc_health_buffer_bits health_buffer; 11872 u8 reserved_at_0[0x200]; 11873 }; 11874 11875 union mlx5_ifc_uplink_pci_interface_document_bits { 11876 struct mlx5_ifc_initial_seg_bits initial_seg; 11877 u8 reserved_at_0[0x20060]; 11878 }; 11879 11880 struct mlx5_ifc_set_flow_table_root_out_bits { 11881 u8 status[0x8]; 11882 u8 reserved_at_8[0x18]; 11883 11884 u8 syndrome[0x20]; 11885 11886 u8 reserved_at_40[0x40]; 11887 }; 11888 11889 struct mlx5_ifc_set_flow_table_root_in_bits { 11890 u8 opcode[0x10]; 11891 u8 reserved_at_10[0x10]; 11892 11893 u8 reserved_at_20[0x10]; 11894 u8 op_mod[0x10]; 11895 11896 u8 other_vport[0x1]; 11897 u8 other_eswitch[0x1]; 11898 u8 reserved_at_42[0xe]; 11899 u8 vport_number[0x10]; 11900 11901 u8 reserved_at_60[0x10]; 11902 u8 eswitch_owner_vhca_id[0x10]; 11903 11904 u8 table_type[0x8]; 11905 u8 reserved_at_88[0x7]; 11906 u8 table_of_other_vport[0x1]; 11907 u8 table_vport_number[0x10]; 11908 11909 u8 reserved_at_a0[0x8]; 11910 u8 table_id[0x18]; 11911 11912 u8 reserved_at_c0[0x8]; 11913 u8 underlay_qpn[0x18]; 11914 u8 table_eswitch_owner_vhca_id_valid[0x1]; 11915 u8 reserved_at_e1[0xf]; 11916 u8 table_eswitch_owner_vhca_id[0x10]; 11917 u8 reserved_at_100[0x100]; 11918 }; 11919 11920 enum { 11921 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 11922 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 11923 }; 11924 11925 struct mlx5_ifc_modify_flow_table_out_bits { 11926 u8 status[0x8]; 11927 u8 reserved_at_8[0x18]; 11928 11929 u8 syndrome[0x20]; 11930 11931 u8 reserved_at_40[0x40]; 11932 }; 11933 11934 struct mlx5_ifc_modify_flow_table_in_bits { 11935 u8 opcode[0x10]; 11936 u8 reserved_at_10[0x10]; 11937 11938 u8 reserved_at_20[0x10]; 11939 u8 op_mod[0x10]; 11940 11941 u8 other_vport[0x1]; 11942 u8 other_eswitch[0x1]; 11943 u8 reserved_at_42[0xe]; 11944 u8 vport_number[0x10]; 11945 11946 u8 reserved_at_60[0x10]; 11947 u8 modify_field_select[0x10]; 11948 11949 u8 table_type[0x8]; 11950 u8 reserved_at_88[0x8]; 11951 u8 eswitch_owner_vhca_id[0x10]; 11952 11953 u8 reserved_at_a0[0x8]; 11954 u8 table_id[0x18]; 11955 11956 struct mlx5_ifc_flow_table_context_bits flow_table_context; 11957 }; 11958 11959 struct mlx5_ifc_ets_tcn_config_reg_bits { 11960 u8 g[0x1]; 11961 u8 b[0x1]; 11962 u8 r[0x1]; 11963 u8 reserved_at_3[0x9]; 11964 u8 group[0x4]; 11965 u8 reserved_at_10[0x9]; 11966 u8 bw_allocation[0x7]; 11967 11968 u8 reserved_at_20[0xc]; 11969 u8 max_bw_units[0x4]; 11970 u8 max_bw_value[0x10]; 11971 }; 11972 11973 struct mlx5_ifc_ets_global_config_reg_bits { 11974 u8 reserved_at_0[0x2]; 11975 u8 r[0x1]; 11976 u8 reserved_at_3[0x1d]; 11977 11978 u8 reserved_at_20[0xc]; 11979 u8 max_bw_units[0x4]; 11980 u8 reserved_at_30[0x8]; 11981 u8 max_bw_value[0x8]; 11982 }; 11983 11984 struct mlx5_ifc_qetc_reg_bits { 11985 u8 reserved_at_0[0x8]; 11986 u8 port_number[0x8]; 11987 u8 reserved_at_10[0x30]; 11988 11989 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 11990 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 11991 }; 11992 11993 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11994 u8 e[0x1]; 11995 u8 reserved_at_01[0x0b]; 11996 u8 prio[0x04]; 11997 }; 11998 11999 struct mlx5_ifc_qpdpm_reg_bits { 12000 u8 reserved_at_0[0x8]; 12001 u8 local_port[0x8]; 12002 u8 reserved_at_10[0x10]; 12003 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 12004 }; 12005 12006 struct mlx5_ifc_qpts_reg_bits { 12007 u8 reserved_at_0[0x8]; 12008 u8 local_port[0x8]; 12009 u8 reserved_at_10[0x2d]; 12010 u8 trust_state[0x3]; 12011 }; 12012 12013 struct mlx5_ifc_pptb_reg_bits { 12014 u8 reserved_at_0[0x2]; 12015 u8 mm[0x2]; 12016 u8 reserved_at_4[0x4]; 12017 u8 local_port[0x8]; 12018 u8 reserved_at_10[0x6]; 12019 u8 cm[0x1]; 12020 u8 um[0x1]; 12021 u8 pm[0x8]; 12022 12023 u8 prio_x_buff[0x20]; 12024 12025 u8 pm_msb[0x8]; 12026 u8 reserved_at_48[0x10]; 12027 u8 ctrl_buff[0x4]; 12028 u8 untagged_buff[0x4]; 12029 }; 12030 12031 struct mlx5_ifc_sbcam_reg_bits { 12032 u8 reserved_at_0[0x8]; 12033 u8 feature_group[0x8]; 12034 u8 reserved_at_10[0x8]; 12035 u8 access_reg_group[0x8]; 12036 12037 u8 reserved_at_20[0x20]; 12038 12039 u8 sb_access_reg_cap_mask[4][0x20]; 12040 12041 u8 reserved_at_c0[0x80]; 12042 12043 u8 sb_feature_cap_mask[4][0x20]; 12044 12045 u8 reserved_at_1c0[0x40]; 12046 12047 u8 cap_total_buffer_size[0x20]; 12048 12049 u8 cap_cell_size[0x10]; 12050 u8 cap_max_pg_buffers[0x8]; 12051 u8 cap_num_pool_supported[0x8]; 12052 12053 u8 reserved_at_240[0x8]; 12054 u8 cap_sbsr_stat_size[0x8]; 12055 u8 cap_max_tclass_data[0x8]; 12056 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 12057 }; 12058 12059 struct mlx5_ifc_pbmc_reg_bits { 12060 u8 reserved_at_0[0x8]; 12061 u8 local_port[0x8]; 12062 u8 reserved_at_10[0x10]; 12063 12064 u8 xoff_timer_value[0x10]; 12065 u8 xoff_refresh[0x10]; 12066 12067 u8 reserved_at_40[0x9]; 12068 u8 fullness_threshold[0x7]; 12069 u8 port_buffer_size[0x10]; 12070 12071 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 12072 12073 u8 reserved_at_2e0[0x80]; 12074 }; 12075 12076 struct mlx5_ifc_sbpr_reg_bits { 12077 u8 desc[0x1]; 12078 u8 snap[0x1]; 12079 u8 reserved_at_2[0x4]; 12080 u8 dir[0x2]; 12081 u8 reserved_at_8[0x14]; 12082 u8 pool[0x4]; 12083 12084 u8 infi_size[0x1]; 12085 u8 reserved_at_21[0x7]; 12086 u8 size[0x18]; 12087 12088 u8 reserved_at_40[0x1c]; 12089 u8 mode[0x4]; 12090 12091 u8 reserved_at_60[0x8]; 12092 u8 buff_occupancy[0x18]; 12093 12094 u8 clr[0x1]; 12095 u8 reserved_at_81[0x7]; 12096 u8 max_buff_occupancy[0x18]; 12097 12098 u8 reserved_at_a0[0x8]; 12099 u8 ext_buff_occupancy[0x18]; 12100 }; 12101 12102 struct mlx5_ifc_sbcm_reg_bits { 12103 u8 desc[0x1]; 12104 u8 snap[0x1]; 12105 u8 reserved_at_2[0x6]; 12106 u8 local_port[0x8]; 12107 u8 pnat[0x2]; 12108 u8 pg_buff[0x6]; 12109 u8 reserved_at_18[0x6]; 12110 u8 dir[0x2]; 12111 12112 u8 reserved_at_20[0x1f]; 12113 u8 exc[0x1]; 12114 12115 u8 reserved_at_40[0x40]; 12116 12117 u8 reserved_at_80[0x8]; 12118 u8 buff_occupancy[0x18]; 12119 12120 u8 clr[0x1]; 12121 u8 reserved_at_a1[0x7]; 12122 u8 max_buff_occupancy[0x18]; 12123 12124 u8 reserved_at_c0[0x8]; 12125 u8 min_buff[0x18]; 12126 12127 u8 infi_max[0x1]; 12128 u8 reserved_at_e1[0x7]; 12129 u8 max_buff[0x18]; 12130 12131 u8 reserved_at_100[0x20]; 12132 12133 u8 reserved_at_120[0x1c]; 12134 u8 pool[0x4]; 12135 }; 12136 12137 struct mlx5_ifc_qtct_reg_bits { 12138 u8 reserved_at_0[0x8]; 12139 u8 port_number[0x8]; 12140 u8 reserved_at_10[0xd]; 12141 u8 prio[0x3]; 12142 12143 u8 reserved_at_20[0x1d]; 12144 u8 tclass[0x3]; 12145 }; 12146 12147 struct mlx5_ifc_mcia_reg_bits { 12148 u8 l[0x1]; 12149 u8 reserved_at_1[0x7]; 12150 u8 module[0x8]; 12151 u8 reserved_at_10[0x8]; 12152 u8 status[0x8]; 12153 12154 u8 i2c_device_address[0x8]; 12155 u8 page_number[0x8]; 12156 u8 device_address[0x10]; 12157 12158 u8 reserved_at_40[0x10]; 12159 u8 size[0x10]; 12160 12161 u8 reserved_at_60[0x20]; 12162 12163 u8 dword_0[0x20]; 12164 u8 dword_1[0x20]; 12165 u8 dword_2[0x20]; 12166 u8 dword_3[0x20]; 12167 u8 dword_4[0x20]; 12168 u8 dword_5[0x20]; 12169 u8 dword_6[0x20]; 12170 u8 dword_7[0x20]; 12171 u8 dword_8[0x20]; 12172 u8 dword_9[0x20]; 12173 u8 dword_10[0x20]; 12174 u8 dword_11[0x20]; 12175 }; 12176 12177 struct mlx5_ifc_dcbx_param_bits { 12178 u8 dcbx_cee_cap[0x1]; 12179 u8 dcbx_ieee_cap[0x1]; 12180 u8 dcbx_standby_cap[0x1]; 12181 u8 reserved_at_3[0x5]; 12182 u8 port_number[0x8]; 12183 u8 reserved_at_10[0xa]; 12184 u8 max_application_table_size[6]; 12185 u8 reserved_at_20[0x15]; 12186 u8 version_oper[0x3]; 12187 u8 reserved_at_38[5]; 12188 u8 version_admin[0x3]; 12189 u8 willing_admin[0x1]; 12190 u8 reserved_at_41[0x3]; 12191 u8 pfc_cap_oper[0x4]; 12192 u8 reserved_at_48[0x4]; 12193 u8 pfc_cap_admin[0x4]; 12194 u8 reserved_at_50[0x4]; 12195 u8 num_of_tc_oper[0x4]; 12196 u8 reserved_at_58[0x4]; 12197 u8 num_of_tc_admin[0x4]; 12198 u8 remote_willing[0x1]; 12199 u8 reserved_at_61[3]; 12200 u8 remote_pfc_cap[4]; 12201 u8 reserved_at_68[0x14]; 12202 u8 remote_num_of_tc[0x4]; 12203 u8 reserved_at_80[0x18]; 12204 u8 error[0x8]; 12205 u8 reserved_at_a0[0x160]; 12206 }; 12207 12208 enum { 12209 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 12210 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 12211 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 12212 }; 12213 12214 struct mlx5_ifc_lagc_bits { 12215 u8 fdb_selection_mode[0x1]; 12216 u8 reserved_at_1[0x14]; 12217 u8 port_select_mode[0x3]; 12218 u8 reserved_at_18[0x5]; 12219 u8 lag_state[0x3]; 12220 12221 u8 reserved_at_20[0xc]; 12222 u8 active_port[0x4]; 12223 u8 reserved_at_30[0x4]; 12224 u8 tx_remap_affinity_2[0x4]; 12225 u8 reserved_at_38[0x4]; 12226 u8 tx_remap_affinity_1[0x4]; 12227 }; 12228 12229 struct mlx5_ifc_create_lag_out_bits { 12230 u8 status[0x8]; 12231 u8 reserved_at_8[0x18]; 12232 12233 u8 syndrome[0x20]; 12234 12235 u8 reserved_at_40[0x40]; 12236 }; 12237 12238 struct mlx5_ifc_create_lag_in_bits { 12239 u8 opcode[0x10]; 12240 u8 reserved_at_10[0x10]; 12241 12242 u8 reserved_at_20[0x10]; 12243 u8 op_mod[0x10]; 12244 12245 struct mlx5_ifc_lagc_bits ctx; 12246 }; 12247 12248 struct mlx5_ifc_modify_lag_out_bits { 12249 u8 status[0x8]; 12250 u8 reserved_at_8[0x18]; 12251 12252 u8 syndrome[0x20]; 12253 12254 u8 reserved_at_40[0x40]; 12255 }; 12256 12257 struct mlx5_ifc_modify_lag_in_bits { 12258 u8 opcode[0x10]; 12259 u8 reserved_at_10[0x10]; 12260 12261 u8 reserved_at_20[0x10]; 12262 u8 op_mod[0x10]; 12263 12264 u8 reserved_at_40[0x20]; 12265 u8 field_select[0x20]; 12266 12267 struct mlx5_ifc_lagc_bits ctx; 12268 }; 12269 12270 struct mlx5_ifc_query_lag_out_bits { 12271 u8 status[0x8]; 12272 u8 reserved_at_8[0x18]; 12273 12274 u8 syndrome[0x20]; 12275 12276 struct mlx5_ifc_lagc_bits ctx; 12277 }; 12278 12279 struct mlx5_ifc_query_lag_in_bits { 12280 u8 opcode[0x10]; 12281 u8 reserved_at_10[0x10]; 12282 12283 u8 reserved_at_20[0x10]; 12284 u8 op_mod[0x10]; 12285 12286 u8 reserved_at_40[0x40]; 12287 }; 12288 12289 struct mlx5_ifc_destroy_lag_out_bits { 12290 u8 status[0x8]; 12291 u8 reserved_at_8[0x18]; 12292 12293 u8 syndrome[0x20]; 12294 12295 u8 reserved_at_40[0x40]; 12296 }; 12297 12298 struct mlx5_ifc_destroy_lag_in_bits { 12299 u8 opcode[0x10]; 12300 u8 reserved_at_10[0x10]; 12301 12302 u8 reserved_at_20[0x10]; 12303 u8 op_mod[0x10]; 12304 12305 u8 reserved_at_40[0x40]; 12306 }; 12307 12308 struct mlx5_ifc_create_vport_lag_out_bits { 12309 u8 status[0x8]; 12310 u8 reserved_at_8[0x18]; 12311 12312 u8 syndrome[0x20]; 12313 12314 u8 reserved_at_40[0x40]; 12315 }; 12316 12317 struct mlx5_ifc_create_vport_lag_in_bits { 12318 u8 opcode[0x10]; 12319 u8 reserved_at_10[0x10]; 12320 12321 u8 reserved_at_20[0x10]; 12322 u8 op_mod[0x10]; 12323 12324 u8 reserved_at_40[0x40]; 12325 }; 12326 12327 struct mlx5_ifc_destroy_vport_lag_out_bits { 12328 u8 status[0x8]; 12329 u8 reserved_at_8[0x18]; 12330 12331 u8 syndrome[0x20]; 12332 12333 u8 reserved_at_40[0x40]; 12334 }; 12335 12336 struct mlx5_ifc_destroy_vport_lag_in_bits { 12337 u8 opcode[0x10]; 12338 u8 reserved_at_10[0x10]; 12339 12340 u8 reserved_at_20[0x10]; 12341 u8 op_mod[0x10]; 12342 12343 u8 reserved_at_40[0x40]; 12344 }; 12345 12346 enum { 12347 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 12348 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 12349 }; 12350 12351 struct mlx5_ifc_modify_memic_in_bits { 12352 u8 opcode[0x10]; 12353 u8 uid[0x10]; 12354 12355 u8 reserved_at_20[0x10]; 12356 u8 op_mod[0x10]; 12357 12358 u8 reserved_at_40[0x20]; 12359 12360 u8 reserved_at_60[0x18]; 12361 u8 memic_operation_type[0x8]; 12362 12363 u8 memic_start_addr[0x40]; 12364 12365 u8 reserved_at_c0[0x140]; 12366 }; 12367 12368 struct mlx5_ifc_modify_memic_out_bits { 12369 u8 status[0x8]; 12370 u8 reserved_at_8[0x18]; 12371 12372 u8 syndrome[0x20]; 12373 12374 u8 reserved_at_40[0x40]; 12375 12376 u8 memic_operation_addr[0x40]; 12377 12378 u8 reserved_at_c0[0x140]; 12379 }; 12380 12381 struct mlx5_ifc_alloc_memic_in_bits { 12382 u8 opcode[0x10]; 12383 u8 reserved_at_10[0x10]; 12384 12385 u8 reserved_at_20[0x10]; 12386 u8 op_mod[0x10]; 12387 12388 u8 reserved_at_30[0x20]; 12389 12390 u8 reserved_at_40[0x18]; 12391 u8 log_memic_addr_alignment[0x8]; 12392 12393 u8 range_start_addr[0x40]; 12394 12395 u8 range_size[0x20]; 12396 12397 u8 memic_size[0x20]; 12398 }; 12399 12400 struct mlx5_ifc_alloc_memic_out_bits { 12401 u8 status[0x8]; 12402 u8 reserved_at_8[0x18]; 12403 12404 u8 syndrome[0x20]; 12405 12406 u8 memic_start_addr[0x40]; 12407 }; 12408 12409 struct mlx5_ifc_dealloc_memic_in_bits { 12410 u8 opcode[0x10]; 12411 u8 reserved_at_10[0x10]; 12412 12413 u8 reserved_at_20[0x10]; 12414 u8 op_mod[0x10]; 12415 12416 u8 reserved_at_40[0x40]; 12417 12418 u8 memic_start_addr[0x40]; 12419 12420 u8 memic_size[0x20]; 12421 12422 u8 reserved_at_e0[0x20]; 12423 }; 12424 12425 struct mlx5_ifc_dealloc_memic_out_bits { 12426 u8 status[0x8]; 12427 u8 reserved_at_8[0x18]; 12428 12429 u8 syndrome[0x20]; 12430 12431 u8 reserved_at_40[0x40]; 12432 }; 12433 12434 struct mlx5_ifc_umem_bits { 12435 u8 reserved_at_0[0x80]; 12436 12437 u8 ats[0x1]; 12438 u8 reserved_at_81[0x1a]; 12439 u8 log_page_size[0x5]; 12440 12441 u8 page_offset[0x20]; 12442 12443 u8 num_of_mtt[0x40]; 12444 12445 struct mlx5_ifc_mtt_bits mtt[]; 12446 }; 12447 12448 struct mlx5_ifc_uctx_bits { 12449 u8 cap[0x20]; 12450 12451 u8 reserved_at_20[0x160]; 12452 }; 12453 12454 struct mlx5_ifc_sw_icm_bits { 12455 u8 modify_field_select[0x40]; 12456 12457 u8 reserved_at_40[0x18]; 12458 u8 log_sw_icm_size[0x8]; 12459 12460 u8 reserved_at_60[0x20]; 12461 12462 u8 sw_icm_start_addr[0x40]; 12463 12464 u8 reserved_at_c0[0x140]; 12465 }; 12466 12467 struct mlx5_ifc_geneve_tlv_option_bits { 12468 u8 modify_field_select[0x40]; 12469 12470 u8 reserved_at_40[0x18]; 12471 u8 geneve_option_fte_index[0x8]; 12472 12473 u8 option_class[0x10]; 12474 u8 option_type[0x8]; 12475 u8 reserved_at_78[0x3]; 12476 u8 option_data_length[0x5]; 12477 12478 u8 reserved_at_80[0x180]; 12479 }; 12480 12481 struct mlx5_ifc_create_umem_in_bits { 12482 u8 opcode[0x10]; 12483 u8 uid[0x10]; 12484 12485 u8 reserved_at_20[0x10]; 12486 u8 op_mod[0x10]; 12487 12488 u8 reserved_at_40[0x40]; 12489 12490 struct mlx5_ifc_umem_bits umem; 12491 }; 12492 12493 struct mlx5_ifc_create_umem_out_bits { 12494 u8 status[0x8]; 12495 u8 reserved_at_8[0x18]; 12496 12497 u8 syndrome[0x20]; 12498 12499 u8 reserved_at_40[0x8]; 12500 u8 umem_id[0x18]; 12501 12502 u8 reserved_at_60[0x20]; 12503 }; 12504 12505 struct mlx5_ifc_destroy_umem_in_bits { 12506 u8 opcode[0x10]; 12507 u8 uid[0x10]; 12508 12509 u8 reserved_at_20[0x10]; 12510 u8 op_mod[0x10]; 12511 12512 u8 reserved_at_40[0x8]; 12513 u8 umem_id[0x18]; 12514 12515 u8 reserved_at_60[0x20]; 12516 }; 12517 12518 struct mlx5_ifc_destroy_umem_out_bits { 12519 u8 status[0x8]; 12520 u8 reserved_at_8[0x18]; 12521 12522 u8 syndrome[0x20]; 12523 12524 u8 reserved_at_40[0x40]; 12525 }; 12526 12527 struct mlx5_ifc_create_uctx_in_bits { 12528 u8 opcode[0x10]; 12529 u8 reserved_at_10[0x10]; 12530 12531 u8 reserved_at_20[0x10]; 12532 u8 op_mod[0x10]; 12533 12534 u8 reserved_at_40[0x40]; 12535 12536 struct mlx5_ifc_uctx_bits uctx; 12537 }; 12538 12539 struct mlx5_ifc_create_uctx_out_bits { 12540 u8 status[0x8]; 12541 u8 reserved_at_8[0x18]; 12542 12543 u8 syndrome[0x20]; 12544 12545 u8 reserved_at_40[0x10]; 12546 u8 uid[0x10]; 12547 12548 u8 reserved_at_60[0x20]; 12549 }; 12550 12551 struct mlx5_ifc_destroy_uctx_in_bits { 12552 u8 opcode[0x10]; 12553 u8 reserved_at_10[0x10]; 12554 12555 u8 reserved_at_20[0x10]; 12556 u8 op_mod[0x10]; 12557 12558 u8 reserved_at_40[0x10]; 12559 u8 uid[0x10]; 12560 12561 u8 reserved_at_60[0x20]; 12562 }; 12563 12564 struct mlx5_ifc_destroy_uctx_out_bits { 12565 u8 status[0x8]; 12566 u8 reserved_at_8[0x18]; 12567 12568 u8 syndrome[0x20]; 12569 12570 u8 reserved_at_40[0x40]; 12571 }; 12572 12573 struct mlx5_ifc_create_sw_icm_in_bits { 12574 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12575 struct mlx5_ifc_sw_icm_bits sw_icm; 12576 }; 12577 12578 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 12579 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12580 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 12581 }; 12582 12583 struct mlx5_ifc_mtrc_string_db_param_bits { 12584 u8 string_db_base_address[0x20]; 12585 12586 u8 reserved_at_20[0x8]; 12587 u8 string_db_size[0x18]; 12588 }; 12589 12590 struct mlx5_ifc_mtrc_cap_bits { 12591 u8 trace_owner[0x1]; 12592 u8 trace_to_memory[0x1]; 12593 u8 reserved_at_2[0x4]; 12594 u8 trc_ver[0x2]; 12595 u8 reserved_at_8[0x14]; 12596 u8 num_string_db[0x4]; 12597 12598 u8 first_string_trace[0x8]; 12599 u8 num_string_trace[0x8]; 12600 u8 reserved_at_30[0x28]; 12601 12602 u8 log_max_trace_buffer_size[0x8]; 12603 12604 u8 reserved_at_60[0x20]; 12605 12606 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 12607 12608 u8 reserved_at_280[0x180]; 12609 }; 12610 12611 struct mlx5_ifc_mtrc_conf_bits { 12612 u8 reserved_at_0[0x1c]; 12613 u8 trace_mode[0x4]; 12614 u8 reserved_at_20[0x18]; 12615 u8 log_trace_buffer_size[0x8]; 12616 u8 trace_mkey[0x20]; 12617 u8 reserved_at_60[0x3a0]; 12618 }; 12619 12620 struct mlx5_ifc_mtrc_stdb_bits { 12621 u8 string_db_index[0x4]; 12622 u8 reserved_at_4[0x4]; 12623 u8 read_size[0x18]; 12624 u8 start_offset[0x20]; 12625 u8 string_db_data[]; 12626 }; 12627 12628 struct mlx5_ifc_mtrc_ctrl_bits { 12629 u8 trace_status[0x2]; 12630 u8 reserved_at_2[0x2]; 12631 u8 arm_event[0x1]; 12632 u8 reserved_at_5[0xb]; 12633 u8 modify_field_select[0x10]; 12634 u8 reserved_at_20[0x2b]; 12635 u8 current_timestamp52_32[0x15]; 12636 u8 current_timestamp31_0[0x20]; 12637 u8 reserved_at_80[0x180]; 12638 }; 12639 12640 struct mlx5_ifc_host_params_context_bits { 12641 u8 host_number[0x8]; 12642 u8 reserved_at_8[0x5]; 12643 u8 host_pf_not_exist[0x1]; 12644 u8 reserved_at_14[0x1]; 12645 u8 host_pf_disabled[0x1]; 12646 u8 host_num_of_vfs[0x10]; 12647 12648 u8 host_total_vfs[0x10]; 12649 u8 host_pci_bus[0x10]; 12650 12651 u8 reserved_at_40[0x10]; 12652 u8 host_pci_device[0x10]; 12653 12654 u8 reserved_at_60[0x10]; 12655 u8 host_pci_function[0x10]; 12656 12657 u8 reserved_at_80[0x180]; 12658 }; 12659 12660 struct mlx5_ifc_query_esw_functions_in_bits { 12661 u8 opcode[0x10]; 12662 u8 reserved_at_10[0x10]; 12663 12664 u8 reserved_at_20[0x10]; 12665 u8 op_mod[0x10]; 12666 12667 u8 reserved_at_40[0x40]; 12668 }; 12669 12670 struct mlx5_ifc_query_esw_functions_out_bits { 12671 u8 status[0x8]; 12672 u8 reserved_at_8[0x18]; 12673 12674 u8 syndrome[0x20]; 12675 12676 u8 reserved_at_40[0x40]; 12677 12678 struct mlx5_ifc_host_params_context_bits host_params_context; 12679 12680 u8 reserved_at_280[0x180]; 12681 u8 host_sf_enable[][0x40]; 12682 }; 12683 12684 struct mlx5_ifc_sf_partition_bits { 12685 u8 reserved_at_0[0x10]; 12686 u8 log_num_sf[0x8]; 12687 u8 log_sf_bar_size[0x8]; 12688 }; 12689 12690 struct mlx5_ifc_query_sf_partitions_out_bits { 12691 u8 status[0x8]; 12692 u8 reserved_at_8[0x18]; 12693 12694 u8 syndrome[0x20]; 12695 12696 u8 reserved_at_40[0x18]; 12697 u8 num_sf_partitions[0x8]; 12698 12699 u8 reserved_at_60[0x20]; 12700 12701 struct mlx5_ifc_sf_partition_bits sf_partition[]; 12702 }; 12703 12704 struct mlx5_ifc_query_sf_partitions_in_bits { 12705 u8 opcode[0x10]; 12706 u8 reserved_at_10[0x10]; 12707 12708 u8 reserved_at_20[0x10]; 12709 u8 op_mod[0x10]; 12710 12711 u8 reserved_at_40[0x40]; 12712 }; 12713 12714 struct mlx5_ifc_dealloc_sf_out_bits { 12715 u8 status[0x8]; 12716 u8 reserved_at_8[0x18]; 12717 12718 u8 syndrome[0x20]; 12719 12720 u8 reserved_at_40[0x40]; 12721 }; 12722 12723 struct mlx5_ifc_dealloc_sf_in_bits { 12724 u8 opcode[0x10]; 12725 u8 reserved_at_10[0x10]; 12726 12727 u8 reserved_at_20[0x10]; 12728 u8 op_mod[0x10]; 12729 12730 u8 reserved_at_40[0x10]; 12731 u8 function_id[0x10]; 12732 12733 u8 reserved_at_60[0x20]; 12734 }; 12735 12736 struct mlx5_ifc_alloc_sf_out_bits { 12737 u8 status[0x8]; 12738 u8 reserved_at_8[0x18]; 12739 12740 u8 syndrome[0x20]; 12741 12742 u8 reserved_at_40[0x40]; 12743 }; 12744 12745 struct mlx5_ifc_alloc_sf_in_bits { 12746 u8 opcode[0x10]; 12747 u8 reserved_at_10[0x10]; 12748 12749 u8 reserved_at_20[0x10]; 12750 u8 op_mod[0x10]; 12751 12752 u8 reserved_at_40[0x10]; 12753 u8 function_id[0x10]; 12754 12755 u8 reserved_at_60[0x20]; 12756 }; 12757 12758 struct mlx5_ifc_affiliated_event_header_bits { 12759 u8 reserved_at_0[0x10]; 12760 u8 obj_type[0x10]; 12761 12762 u8 obj_id[0x20]; 12763 }; 12764 12765 enum { 12766 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 12767 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 12768 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 12769 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 12770 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 12771 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 12772 MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL = 0x53, 12773 MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT = 0x58, 12774 MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15, 12775 }; 12776 12777 enum { 12778 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 12779 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY), 12780 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = 12781 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_IPSEC), 12782 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = 12783 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_SAMPLER), 12784 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 12785 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO), 12786 }; 12787 12788 enum { 12789 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL = 12790 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL - 0x40), 12791 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT = 12792 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT - 0x40), 12793 }; 12794 12795 enum { 12796 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 12797 }; 12798 12799 enum { 12800 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 12801 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 12802 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 12803 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 12804 }; 12805 12806 enum { 12807 MLX5_IPSEC_ASO_MODE = 0x0, 12808 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 12809 MLX5_IPSEC_ASO_INC_SN = 0x2, 12810 }; 12811 12812 enum { 12813 MLX5_IPSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12814 MLX5_IPSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12815 MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12816 MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12817 }; 12818 12819 struct mlx5_ifc_ipsec_aso_bits { 12820 u8 valid[0x1]; 12821 u8 reserved_at_201[0x1]; 12822 u8 mode[0x2]; 12823 u8 window_sz[0x2]; 12824 u8 soft_lft_arm[0x1]; 12825 u8 hard_lft_arm[0x1]; 12826 u8 remove_flow_enable[0x1]; 12827 u8 esn_event_arm[0x1]; 12828 u8 reserved_at_20a[0x16]; 12829 12830 u8 remove_flow_pkt_cnt[0x20]; 12831 12832 u8 remove_flow_soft_lft[0x20]; 12833 12834 u8 reserved_at_260[0x80]; 12835 12836 u8 mode_parameter[0x20]; 12837 12838 u8 replay_protection_window[0x100]; 12839 }; 12840 12841 struct mlx5_ifc_ipsec_obj_bits { 12842 u8 modify_field_select[0x40]; 12843 u8 full_offload[0x1]; 12844 u8 reserved_at_41[0x1]; 12845 u8 esn_en[0x1]; 12846 u8 esn_overlap[0x1]; 12847 u8 reserved_at_44[0x2]; 12848 u8 icv_length[0x2]; 12849 u8 reserved_at_48[0x4]; 12850 u8 aso_return_reg[0x4]; 12851 u8 reserved_at_50[0x10]; 12852 12853 u8 esn_msb[0x20]; 12854 12855 u8 reserved_at_80[0x8]; 12856 u8 dekn[0x18]; 12857 12858 u8 salt[0x20]; 12859 12860 u8 implicit_iv[0x40]; 12861 12862 u8 reserved_at_100[0x8]; 12863 u8 ipsec_aso_access_pd[0x18]; 12864 u8 reserved_at_120[0xe0]; 12865 12866 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 12867 }; 12868 12869 struct mlx5_ifc_create_ipsec_obj_in_bits { 12870 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12871 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12872 }; 12873 12874 enum { 12875 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 12876 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 12877 }; 12878 12879 struct mlx5_ifc_query_ipsec_obj_out_bits { 12880 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12881 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12882 }; 12883 12884 struct mlx5_ifc_modify_ipsec_obj_in_bits { 12885 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12886 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12887 }; 12888 12889 enum { 12890 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 12891 }; 12892 12893 enum { 12894 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12895 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12896 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12897 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12898 }; 12899 12900 #define MLX5_MACSEC_ASO_INC_SN 0x2 12901 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 12902 12903 struct mlx5_ifc_macsec_aso_bits { 12904 u8 valid[0x1]; 12905 u8 reserved_at_1[0x1]; 12906 u8 mode[0x2]; 12907 u8 window_size[0x2]; 12908 u8 soft_lifetime_arm[0x1]; 12909 u8 hard_lifetime_arm[0x1]; 12910 u8 remove_flow_enable[0x1]; 12911 u8 epn_event_arm[0x1]; 12912 u8 reserved_at_a[0x16]; 12913 12914 u8 remove_flow_packet_count[0x20]; 12915 12916 u8 remove_flow_soft_lifetime[0x20]; 12917 12918 u8 reserved_at_60[0x80]; 12919 12920 u8 mode_parameter[0x20]; 12921 12922 u8 replay_protection_window[8][0x20]; 12923 }; 12924 12925 struct mlx5_ifc_macsec_offload_obj_bits { 12926 u8 modify_field_select[0x40]; 12927 12928 u8 confidentiality_en[0x1]; 12929 u8 reserved_at_41[0x1]; 12930 u8 epn_en[0x1]; 12931 u8 epn_overlap[0x1]; 12932 u8 reserved_at_44[0x2]; 12933 u8 confidentiality_offset[0x2]; 12934 u8 reserved_at_48[0x4]; 12935 u8 aso_return_reg[0x4]; 12936 u8 reserved_at_50[0x10]; 12937 12938 u8 epn_msb[0x20]; 12939 12940 u8 reserved_at_80[0x8]; 12941 u8 dekn[0x18]; 12942 12943 u8 reserved_at_a0[0x20]; 12944 12945 u8 sci[0x40]; 12946 12947 u8 reserved_at_100[0x8]; 12948 u8 macsec_aso_access_pd[0x18]; 12949 12950 u8 reserved_at_120[0x60]; 12951 12952 u8 salt[3][0x20]; 12953 12954 u8 reserved_at_1e0[0x20]; 12955 12956 struct mlx5_ifc_macsec_aso_bits macsec_aso; 12957 }; 12958 12959 struct mlx5_ifc_create_macsec_obj_in_bits { 12960 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12961 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12962 }; 12963 12964 struct mlx5_ifc_modify_macsec_obj_in_bits { 12965 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12966 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12967 }; 12968 12969 enum { 12970 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 12971 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 12972 }; 12973 12974 struct mlx5_ifc_query_macsec_obj_out_bits { 12975 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12976 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12977 }; 12978 12979 struct mlx5_ifc_wrapped_dek_bits { 12980 u8 gcm_iv[0x60]; 12981 12982 u8 reserved_at_60[0x20]; 12983 12984 u8 const0[0x1]; 12985 u8 key_size[0x1]; 12986 u8 reserved_at_82[0x2]; 12987 u8 key2_invalid[0x1]; 12988 u8 reserved_at_85[0x3]; 12989 u8 pd[0x18]; 12990 12991 u8 key_purpose[0x5]; 12992 u8 reserved_at_a5[0x13]; 12993 u8 kek_id[0x8]; 12994 12995 u8 reserved_at_c0[0x40]; 12996 12997 u8 key1[0x8][0x20]; 12998 12999 u8 key2[0x8][0x20]; 13000 13001 u8 reserved_at_300[0x40]; 13002 13003 u8 const1[0x1]; 13004 u8 reserved_at_341[0x1f]; 13005 13006 u8 reserved_at_360[0x20]; 13007 13008 u8 auth_tag[0x80]; 13009 }; 13010 13011 struct mlx5_ifc_encryption_key_obj_bits { 13012 u8 modify_field_select[0x40]; 13013 13014 u8 state[0x8]; 13015 u8 sw_wrapped[0x1]; 13016 u8 reserved_at_49[0xb]; 13017 u8 key_size[0x4]; 13018 u8 reserved_at_58[0x4]; 13019 u8 key_purpose[0x4]; 13020 13021 u8 reserved_at_60[0x8]; 13022 u8 pd[0x18]; 13023 13024 u8 reserved_at_80[0x100]; 13025 13026 u8 opaque[0x40]; 13027 13028 u8 reserved_at_1c0[0x40]; 13029 13030 u8 key[8][0x80]; 13031 13032 u8 sw_wrapped_dek[8][0x80]; 13033 13034 u8 reserved_at_a00[0x600]; 13035 }; 13036 13037 struct mlx5_ifc_create_encryption_key_in_bits { 13038 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13039 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 13040 }; 13041 13042 struct mlx5_ifc_modify_encryption_key_in_bits { 13043 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13044 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 13045 }; 13046 13047 enum { 13048 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 13049 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 13050 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 13051 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 13052 }; 13053 13054 struct mlx5_ifc_flow_meter_parameters_bits { 13055 u8 valid[0x1]; 13056 u8 bucket_overflow[0x1]; 13057 u8 start_color[0x2]; 13058 u8 both_buckets_on_green[0x1]; 13059 u8 reserved_at_5[0x1]; 13060 u8 meter_mode[0x2]; 13061 u8 reserved_at_8[0x18]; 13062 13063 u8 reserved_at_20[0x20]; 13064 13065 u8 reserved_at_40[0x3]; 13066 u8 cbs_exponent[0x5]; 13067 u8 cbs_mantissa[0x8]; 13068 u8 reserved_at_50[0x3]; 13069 u8 cir_exponent[0x5]; 13070 u8 cir_mantissa[0x8]; 13071 13072 u8 reserved_at_60[0x20]; 13073 13074 u8 reserved_at_80[0x3]; 13075 u8 ebs_exponent[0x5]; 13076 u8 ebs_mantissa[0x8]; 13077 u8 reserved_at_90[0x3]; 13078 u8 eir_exponent[0x5]; 13079 u8 eir_mantissa[0x8]; 13080 13081 u8 reserved_at_a0[0x60]; 13082 }; 13083 13084 struct mlx5_ifc_flow_meter_aso_obj_bits { 13085 u8 modify_field_select[0x40]; 13086 13087 u8 reserved_at_40[0x40]; 13088 13089 u8 reserved_at_80[0x8]; 13090 u8 meter_aso_access_pd[0x18]; 13091 13092 u8 reserved_at_a0[0x160]; 13093 13094 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 13095 }; 13096 13097 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 13098 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 13099 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 13100 }; 13101 13102 struct mlx5_ifc_int_kek_obj_bits { 13103 u8 modify_field_select[0x40]; 13104 13105 u8 state[0x8]; 13106 u8 auto_gen[0x1]; 13107 u8 reserved_at_49[0xb]; 13108 u8 key_size[0x4]; 13109 u8 reserved_at_58[0x8]; 13110 13111 u8 reserved_at_60[0x8]; 13112 u8 pd[0x18]; 13113 13114 u8 reserved_at_80[0x180]; 13115 u8 key[8][0x80]; 13116 13117 u8 reserved_at_600[0x200]; 13118 }; 13119 13120 struct mlx5_ifc_create_int_kek_obj_in_bits { 13121 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13122 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 13123 }; 13124 13125 struct mlx5_ifc_create_int_kek_obj_out_bits { 13126 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 13127 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 13128 }; 13129 13130 struct mlx5_ifc_sampler_obj_bits { 13131 u8 modify_field_select[0x40]; 13132 13133 u8 table_type[0x8]; 13134 u8 level[0x8]; 13135 u8 reserved_at_50[0xf]; 13136 u8 ignore_flow_level[0x1]; 13137 13138 u8 sample_ratio[0x20]; 13139 13140 u8 reserved_at_80[0x8]; 13141 u8 sample_table_id[0x18]; 13142 13143 u8 reserved_at_a0[0x8]; 13144 u8 default_table_id[0x18]; 13145 13146 u8 sw_steering_icm_address_rx[0x40]; 13147 u8 sw_steering_icm_address_tx[0x40]; 13148 13149 u8 reserved_at_140[0xa0]; 13150 }; 13151 13152 struct mlx5_ifc_create_sampler_obj_in_bits { 13153 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13154 struct mlx5_ifc_sampler_obj_bits sampler_object; 13155 }; 13156 13157 struct mlx5_ifc_query_sampler_obj_out_bits { 13158 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 13159 struct mlx5_ifc_sampler_obj_bits sampler_object; 13160 }; 13161 13162 enum { 13163 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 13164 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 13165 }; 13166 13167 enum { 13168 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 13169 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 13170 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 13171 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_PSP = 0x6, 13172 }; 13173 13174 struct mlx5_ifc_tls_static_params_bits { 13175 u8 const_2[0x2]; 13176 u8 tls_version[0x4]; 13177 u8 const_1[0x2]; 13178 u8 reserved_at_8[0x14]; 13179 u8 encryption_standard[0x4]; 13180 13181 u8 reserved_at_20[0x20]; 13182 13183 u8 initial_record_number[0x40]; 13184 13185 u8 resync_tcp_sn[0x20]; 13186 13187 u8 gcm_iv[0x20]; 13188 13189 u8 implicit_iv[0x40]; 13190 13191 u8 reserved_at_100[0x8]; 13192 u8 dek_index[0x18]; 13193 13194 u8 reserved_at_120[0xe0]; 13195 }; 13196 13197 struct mlx5_ifc_tls_progress_params_bits { 13198 u8 next_record_tcp_sn[0x20]; 13199 13200 u8 hw_resync_tcp_sn[0x20]; 13201 13202 u8 record_tracker_state[0x2]; 13203 u8 auth_state[0x2]; 13204 u8 reserved_at_44[0x4]; 13205 u8 hw_offset_record_number[0x18]; 13206 }; 13207 13208 enum { 13209 MLX5_MTT_PERM_READ = 1 << 0, 13210 MLX5_MTT_PERM_WRITE = 1 << 1, 13211 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 13212 }; 13213 13214 enum { 13215 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 13216 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 13217 }; 13218 13219 struct mlx5_ifc_suspend_vhca_in_bits { 13220 u8 opcode[0x10]; 13221 u8 uid[0x10]; 13222 13223 u8 reserved_at_20[0x10]; 13224 u8 op_mod[0x10]; 13225 13226 u8 reserved_at_40[0x10]; 13227 u8 vhca_id[0x10]; 13228 13229 u8 reserved_at_60[0x20]; 13230 }; 13231 13232 struct mlx5_ifc_suspend_vhca_out_bits { 13233 u8 status[0x8]; 13234 u8 reserved_at_8[0x18]; 13235 13236 u8 syndrome[0x20]; 13237 13238 u8 reserved_at_40[0x40]; 13239 }; 13240 13241 enum { 13242 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 13243 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 13244 }; 13245 13246 struct mlx5_ifc_resume_vhca_in_bits { 13247 u8 opcode[0x10]; 13248 u8 uid[0x10]; 13249 13250 u8 reserved_at_20[0x10]; 13251 u8 op_mod[0x10]; 13252 13253 u8 reserved_at_40[0x10]; 13254 u8 vhca_id[0x10]; 13255 13256 u8 reserved_at_60[0x20]; 13257 }; 13258 13259 struct mlx5_ifc_resume_vhca_out_bits { 13260 u8 status[0x8]; 13261 u8 reserved_at_8[0x18]; 13262 13263 u8 syndrome[0x20]; 13264 13265 u8 reserved_at_40[0x40]; 13266 }; 13267 13268 struct mlx5_ifc_query_vhca_migration_state_in_bits { 13269 u8 opcode[0x10]; 13270 u8 uid[0x10]; 13271 13272 u8 reserved_at_20[0x10]; 13273 u8 op_mod[0x10]; 13274 13275 u8 incremental[0x1]; 13276 u8 chunk[0x1]; 13277 u8 reserved_at_42[0xe]; 13278 u8 vhca_id[0x10]; 13279 13280 u8 reserved_at_60[0x20]; 13281 }; 13282 13283 struct mlx5_ifc_query_vhca_migration_state_out_bits { 13284 u8 status[0x8]; 13285 u8 reserved_at_8[0x18]; 13286 13287 u8 syndrome[0x20]; 13288 13289 u8 reserved_at_40[0x40]; 13290 13291 u8 required_umem_size[0x20]; 13292 13293 u8 reserved_at_a0[0x20]; 13294 13295 u8 remaining_total_size[0x40]; 13296 13297 u8 reserved_at_100[0x100]; 13298 }; 13299 13300 struct mlx5_ifc_save_vhca_state_in_bits { 13301 u8 opcode[0x10]; 13302 u8 uid[0x10]; 13303 13304 u8 reserved_at_20[0x10]; 13305 u8 op_mod[0x10]; 13306 13307 u8 incremental[0x1]; 13308 u8 set_track[0x1]; 13309 u8 reserved_at_42[0xe]; 13310 u8 vhca_id[0x10]; 13311 13312 u8 reserved_at_60[0x20]; 13313 13314 u8 va[0x40]; 13315 13316 u8 mkey[0x20]; 13317 13318 u8 size[0x20]; 13319 }; 13320 13321 struct mlx5_ifc_save_vhca_state_out_bits { 13322 u8 status[0x8]; 13323 u8 reserved_at_8[0x18]; 13324 13325 u8 syndrome[0x20]; 13326 13327 u8 actual_image_size[0x20]; 13328 13329 u8 next_required_umem_size[0x20]; 13330 }; 13331 13332 struct mlx5_ifc_load_vhca_state_in_bits { 13333 u8 opcode[0x10]; 13334 u8 uid[0x10]; 13335 13336 u8 reserved_at_20[0x10]; 13337 u8 op_mod[0x10]; 13338 13339 u8 reserved_at_40[0x10]; 13340 u8 vhca_id[0x10]; 13341 13342 u8 reserved_at_60[0x20]; 13343 13344 u8 va[0x40]; 13345 13346 u8 mkey[0x20]; 13347 13348 u8 size[0x20]; 13349 }; 13350 13351 struct mlx5_ifc_load_vhca_state_out_bits { 13352 u8 status[0x8]; 13353 u8 reserved_at_8[0x18]; 13354 13355 u8 syndrome[0x20]; 13356 13357 u8 reserved_at_40[0x40]; 13358 }; 13359 13360 struct mlx5_ifc_adv_rdma_cap_bits { 13361 u8 rdma_transport_manager[0x1]; 13362 u8 rdma_transport_manager_other_eswitch[0x1]; 13363 u8 reserved_at_2[0x1e]; 13364 13365 u8 rcx_type[0x8]; 13366 u8 reserved_at_28[0x2]; 13367 u8 ps_entry_log_max_value[0x6]; 13368 u8 reserved_at_30[0x6]; 13369 u8 qp_max_ps_num_entry[0xa]; 13370 13371 u8 mp_max_num_queues[0x8]; 13372 u8 ps_user_context_max_log_size[0x8]; 13373 u8 message_based_qp_and_striding_wq[0x8]; 13374 u8 reserved_at_58[0x8]; 13375 13376 u8 max_receive_send_message_size_stride[0x10]; 13377 u8 reserved_at_70[0x10]; 13378 13379 u8 max_receive_send_message_size_byte[0x20]; 13380 13381 u8 reserved_at_a0[0x160]; 13382 13383 struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_rx_flow_table_properties; 13384 13385 struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_tx_flow_table_properties; 13386 13387 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_support_2; 13388 13389 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_support_2; 13390 13391 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_bitmask_support_2; 13392 13393 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_bitmask_support_2; 13394 13395 u8 reserved_at_800[0x3800]; 13396 }; 13397 13398 struct mlx5_ifc_adv_virtualization_cap_bits { 13399 u8 reserved_at_0[0x3]; 13400 u8 pg_track_log_max_num[0x5]; 13401 u8 pg_track_max_num_range[0x8]; 13402 u8 pg_track_log_min_addr_space[0x8]; 13403 u8 pg_track_log_max_addr_space[0x8]; 13404 13405 u8 reserved_at_20[0x3]; 13406 u8 pg_track_log_min_msg_size[0x5]; 13407 u8 reserved_at_28[0x3]; 13408 u8 pg_track_log_max_msg_size[0x5]; 13409 u8 reserved_at_30[0x3]; 13410 u8 pg_track_log_min_page_size[0x5]; 13411 u8 reserved_at_38[0x3]; 13412 u8 pg_track_log_max_page_size[0x5]; 13413 13414 u8 reserved_at_40[0x7c0]; 13415 }; 13416 13417 struct mlx5_ifc_page_track_report_entry_bits { 13418 u8 dirty_address_high[0x20]; 13419 13420 u8 dirty_address_low[0x20]; 13421 }; 13422 13423 enum { 13424 MLX5_PAGE_TRACK_STATE_TRACKING, 13425 MLX5_PAGE_TRACK_STATE_REPORTING, 13426 MLX5_PAGE_TRACK_STATE_ERROR, 13427 }; 13428 13429 struct mlx5_ifc_page_track_range_bits { 13430 u8 start_address[0x40]; 13431 13432 u8 length[0x40]; 13433 }; 13434 13435 struct mlx5_ifc_page_track_bits { 13436 u8 modify_field_select[0x40]; 13437 13438 u8 reserved_at_40[0x10]; 13439 u8 vhca_id[0x10]; 13440 13441 u8 reserved_at_60[0x20]; 13442 13443 u8 state[0x4]; 13444 u8 track_type[0x4]; 13445 u8 log_addr_space_size[0x8]; 13446 u8 reserved_at_90[0x3]; 13447 u8 log_page_size[0x5]; 13448 u8 reserved_at_98[0x3]; 13449 u8 log_msg_size[0x5]; 13450 13451 u8 reserved_at_a0[0x8]; 13452 u8 reporting_qpn[0x18]; 13453 13454 u8 reserved_at_c0[0x18]; 13455 u8 num_ranges[0x8]; 13456 13457 u8 reserved_at_e0[0x20]; 13458 13459 u8 range_start_address[0x40]; 13460 13461 u8 length[0x40]; 13462 13463 struct mlx5_ifc_page_track_range_bits track_range[0]; 13464 }; 13465 13466 struct mlx5_ifc_create_page_track_obj_in_bits { 13467 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13468 struct mlx5_ifc_page_track_bits obj_context; 13469 }; 13470 13471 struct mlx5_ifc_modify_page_track_obj_in_bits { 13472 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13473 struct mlx5_ifc_page_track_bits obj_context; 13474 }; 13475 13476 struct mlx5_ifc_query_page_track_obj_out_bits { 13477 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 13478 struct mlx5_ifc_page_track_bits obj_context; 13479 }; 13480 13481 struct mlx5_ifc_msecq_reg_bits { 13482 u8 reserved_at_0[0x20]; 13483 13484 u8 reserved_at_20[0x12]; 13485 u8 network_option[0x2]; 13486 u8 local_ssm_code[0x4]; 13487 u8 local_enhanced_ssm_code[0x8]; 13488 13489 u8 local_clock_identity[0x40]; 13490 13491 u8 reserved_at_80[0x180]; 13492 }; 13493 13494 enum { 13495 MLX5_MSEES_FIELD_SELECT_ENABLE = BIT(0), 13496 MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS = BIT(1), 13497 MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE = BIT(2), 13498 }; 13499 13500 enum mlx5_msees_admin_status { 13501 MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING = 0x0, 13502 MLX5_MSEES_ADMIN_STATUS_TRACK = 0x1, 13503 }; 13504 13505 enum mlx5_msees_oper_status { 13506 MLX5_MSEES_OPER_STATUS_FREE_RUNNING = 0x0, 13507 MLX5_MSEES_OPER_STATUS_SELF_TRACK = 0x1, 13508 MLX5_MSEES_OPER_STATUS_OTHER_TRACK = 0x2, 13509 MLX5_MSEES_OPER_STATUS_HOLDOVER = 0x3, 13510 MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER = 0x4, 13511 MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING = 0x5, 13512 }; 13513 13514 enum mlx5_msees_failure_reason { 13515 MLX5_MSEES_FAILURE_REASON_UNDEFINED_ERROR = 0x0, 13516 MLX5_MSEES_FAILURE_REASON_PORT_DOWN = 0x1, 13517 MLX5_MSEES_FAILURE_REASON_TOO_HIGH_FREQUENCY_DIFF = 0x2, 13518 MLX5_MSEES_FAILURE_REASON_NET_SYNCHRONIZER_DEVICE_ERROR = 0x3, 13519 MLX5_MSEES_FAILURE_REASON_LACK_OF_RESOURCES = 0x4, 13520 }; 13521 13522 struct mlx5_ifc_msees_reg_bits { 13523 u8 reserved_at_0[0x8]; 13524 u8 local_port[0x8]; 13525 u8 pnat[0x2]; 13526 u8 lp_msb[0x2]; 13527 u8 reserved_at_14[0xc]; 13528 13529 u8 field_select[0x20]; 13530 13531 u8 admin_status[0x4]; 13532 u8 oper_status[0x4]; 13533 u8 ho_acq[0x1]; 13534 u8 reserved_at_49[0xc]; 13535 u8 admin_freq_measure[0x1]; 13536 u8 oper_freq_measure[0x1]; 13537 u8 failure_reason[0x9]; 13538 13539 u8 frequency_diff[0x20]; 13540 13541 u8 reserved_at_80[0x180]; 13542 }; 13543 13544 struct mlx5_ifc_mrtcq_reg_bits { 13545 u8 reserved_at_0[0x40]; 13546 13547 u8 rt_clock_identity[0x40]; 13548 13549 u8 reserved_at_80[0x180]; 13550 }; 13551 13552 struct mlx5_ifc_pcie_cong_event_obj_bits { 13553 u8 modify_select_field[0x40]; 13554 13555 u8 inbound_event_en[0x1]; 13556 u8 outbound_event_en[0x1]; 13557 u8 reserved_at_42[0x1e]; 13558 13559 u8 reserved_at_60[0x1]; 13560 u8 inbound_cong_state[0x3]; 13561 u8 reserved_at_64[0x1]; 13562 u8 outbound_cong_state[0x3]; 13563 u8 reserved_at_68[0x18]; 13564 13565 u8 inbound_cong_low_threshold[0x10]; 13566 u8 inbound_cong_high_threshold[0x10]; 13567 13568 u8 outbound_cong_low_threshold[0x10]; 13569 u8 outbound_cong_high_threshold[0x10]; 13570 13571 u8 reserved_at_e0[0x340]; 13572 }; 13573 13574 struct mlx5_ifc_pcie_cong_event_cmd_in_bits { 13575 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 13576 struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj; 13577 }; 13578 13579 struct mlx5_ifc_pcie_cong_event_cmd_out_bits { 13580 struct mlx5_ifc_general_obj_out_cmd_hdr_bits hdr; 13581 struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj; 13582 }; 13583 13584 enum mlx5e_pcie_cong_event_mod_field { 13585 MLX5_PCIE_CONG_EVENT_MOD_EVENT_EN = BIT(0), 13586 MLX5_PCIE_CONG_EVENT_MOD_THRESH = BIT(2), 13587 }; 13588 13589 struct mlx5_ifc_psp_rotate_key_in_bits { 13590 u8 opcode[0x10]; 13591 u8 uid[0x10]; 13592 13593 u8 reserved_at_20[0x10]; 13594 u8 op_mod[0x10]; 13595 13596 u8 reserved_at_40[0x40]; 13597 }; 13598 13599 struct mlx5_ifc_psp_rotate_key_out_bits { 13600 u8 status[0x8]; 13601 u8 reserved_at_8[0x18]; 13602 13603 u8 syndrome[0x20]; 13604 13605 u8 reserved_at_40[0x40]; 13606 }; 13607 13608 enum mlx5_psp_gen_spi_in_key_size { 13609 MLX5_PSP_GEN_SPI_IN_KEY_SIZE_128 = 0x0, 13610 MLX5_PSP_GEN_SPI_IN_KEY_SIZE_256 = 0x1, 13611 }; 13612 13613 struct mlx5_ifc_key_spi_bits { 13614 u8 spi[0x20]; 13615 13616 u8 reserved_at_20[0x60]; 13617 13618 u8 key[8][0x20]; 13619 }; 13620 13621 struct mlx5_ifc_psp_gen_spi_in_bits { 13622 u8 opcode[0x10]; 13623 u8 uid[0x10]; 13624 13625 u8 reserved_at_20[0x10]; 13626 u8 op_mod[0x10]; 13627 13628 u8 reserved_at_40[0x20]; 13629 13630 u8 key_size[0x2]; 13631 u8 reserved_at_62[0xe]; 13632 u8 num_of_spi[0x10]; 13633 }; 13634 13635 struct mlx5_ifc_psp_gen_spi_out_bits { 13636 u8 status[0x8]; 13637 u8 reserved_at_8[0x18]; 13638 13639 u8 syndrome[0x20]; 13640 13641 u8 reserved_at_40[0x10]; 13642 u8 num_of_spi[0x10]; 13643 13644 u8 reserved_at_60[0x20]; 13645 13646 struct mlx5_ifc_key_spi_bits key_spi[]; 13647 }; 13648 13649 #endif /* MLX5_IFC_H */ 13650