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/linux/drivers/accel/habanalabs/include/gaudi2/
H A Dgaudi2_async_ids_map_extended.h27 int reset; member
32 { .fc_id = 0, .cpu_id = 0, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
34 { .fc_id = 1, .cpu_id = 1, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
36 { .fc_id = 2, .cpu_id = 2, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
38 { .fc_id = 3, .cpu_id = 3, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
40 { .fc_id = 4, .cpu_id = 4, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
42 { .fc_id = 5, .cpu_id = 5, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
44 { .fc_id = 6, .cpu_id = 6, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
46 { .fc_id = 7, .cpu_id = 7, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
48 { .fc_id = 8, .cpu_id = 8, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
[all …]
/linux/Documentation/devicetree/bindings/reset/
H A Dzynq-reset.txt8 - compatible: "xlnx,zynq-reset"
12 - #reset-cells: Must be 1
18 compatible = "xlnx,zynq-reset";
20 #reset-cells = <1>;
25 0 : soft reset
26 32 : ddr reset
27 64 : topsw reset
28 96 : dmac reset
29 128: usb0 reset
30 129: usb1 reset
[all …]
H A Dreset.txt3 This binding is intended to represent the hardware reset signals present
8 Hardware blocks typically receive a reset signal. This signal is generated by
9 a reset provider (e.g. power management or clock module) and received by a
10 reset consumer (the module being reset, or a module managing when a sub-
11 ordinate module is reset). This binding exists to represent the provider and
14 A reset signal is represented by the phandle of the provider, plus a reset
15 specifier - a list of DT cells that represents the reset signal within the
16 provider. The length (number of cells) and semantics of the reset specifier
17 are dictated by the binding of the reset provider, although common schemes
20 A word on where to place reset signal consumers in device tree: It is possible
[all …]
H A Dti-syscon-reset.txt4 Almost all SoCs have hardware modules that require reset control in addition
5 to clock and power control for their functionality. The reset control is
13 and provides reset management functionality for various hardware modules
18 Each of the reset provider/controller nodes should be a child of a syscon
27 "ti,syscon-reset"
28 - #reset-cells : Should be 1. Please see the reset consumer node below
30 - ti,reset-bits : Contains the reset control register information
31 Should contain 7 cells for each reset exposed to
33 Cell #1 : offset of the reset assert control
35 Cell #2 : bit position of the reset in the reset
[all …]
H A Dsnps,hsdk-reset.txt1 Binding for the Synopsys HSDK reset controller
3 This binding uses the common reset binding[1].
5 [1] Documentation/devicetree/bindings/reset/reset.txt
8 - compatible: should be "snps,hsdk-reset".
9 - reg: should always contain 2 pairs address - length: first for reset
10 configuration register and second for corresponding SW reset and status bits
12 - #reset-cells: from common reset binding; Should always be set to 1.
15 reset: reset@880 {
16 compatible = "snps,hsdk-reset";
17 #reset-cells = <1>;
[all …]
H A Dimg,pistachio-reset.txt4 This binding describes a reset controller device that is used to enable and
5 disable individual IP blocks within the Pistachio SoC using "soft reset"
8 The actual action taken when soft reset is asserted is hardware dependent.
13 Please refer to Documentation/devicetree/bindings/reset/reset.txt
14 for common reset controller binding usage.
18 - compatible: Contains "img,pistachio-reset"
20 - #reset-cells: Contains 1
31 pistachio_reset: reset-controller {
32 compatible = "img,pistachio-reset";
33 #reset-cells = <1>;
[all …]
/linux/drivers/reset/
H A DMakefile9 obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
10 obj-$(CONFIG_RESET_ASPEED) += reset-aspeed.o
11 obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
12 obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o
13 obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
14 obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
15 obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o
16 obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o
17 obj-$(CONFIG_RESET_EIC7700) += reset-eic7700.o
18 obj-$(CONFIG_RESET_EIC7700_HSP) += reset-eic7700-hsp.o
[all …]
H A Dreset-sunplus.c113 struct sp_reset *reset = to_sp_reset(rcdev); in sp_reset_update() local
119 writel(val, reset->base + (index * 4)); in sp_reset_update()
139 struct sp_reset *reset = to_sp_reset(rcdev); in sp_reset_status() local
144 reg = readl(reset->base + (index * 4)); in sp_reset_status()
157 struct sp_reset *reset = data->cb_data; in sp_restart() local
159 sp_reset_assert(&reset->rcdev, 0); in sp_restart()
160 sp_reset_deassert(&reset->rcdev, 0); in sp_restart()
168 struct sp_reset *reset; in sp_reset_probe() local
172 reset = devm_kzalloc(dev, sizeof(*reset), GFP_KERNEL); in sp_reset_probe()
173 if (!reset) in sp_reset_probe()
[all …]
H A DKconfig11 This framework is designed to abstract reset handling of devices
12 via GPIOs or SoC-internal reset controller modules.
22 This option enables support for the external reset functions for
30 This enables the reset controller driver for AST2700.
36 This enables the ATH79 reset controller driver that supports the
37 AR71xx SoC reset controller.
43 This enables the reset controller driver for AXS10x.
50 This enables the reset controller driver for BCM6345 SoCs.
57 This enables the reset controller driver for Marvell Berlin SoCs.
60 tristate "Broadcom STB reset controller"
[all …]
/linux/drivers/power/reset/
H A Dat91-reset.c118 struct at91_reset *reset = container_of(this, struct at91_reset, nb); in at91_reset() local
140 : "r" (reset->ramc_base[0]), in at91_reset()
141 "r" (reset->ramc_base[1]), in at91_reset()
142 "r" (reset->rstc_base), in at91_reset()
145 "r" (reset->data->reset_args), in at91_reset()
146 "r" (reset->ramc_lpr) in at91_reset()
152 static const char *at91_reset_reason(struct at91_reset *reset) in at91_reset_reason() argument
154 u32 reg = readl(reset->rstc_base + AT91_RSTC_SR); in at91_reset_reason()
194 struct at91_reset *reset = platform_get_drvdata(pdev); in power_on_reason_show() local
196 return sprintf(buf, "%s\n", at91_reset_reason(reset)); in power_on_reason_show()
[all …]
/linux/drivers/clk/visconti/
H A Dreset.c25 struct visconti_reset *reset = to_visconti_reset(rcdev); in visconti_reset_assert() local
26 const struct visconti_reset_data *data = &reset->resets[id]; in visconti_reset_assert()
31 spin_lock_irqsave(reset->lock, flags); in visconti_reset_assert()
32 ret = regmap_update_bits(reset->regmap, data->rson_offset, rst, rst); in visconti_reset_assert()
33 spin_unlock_irqrestore(reset->lock, flags); in visconti_reset_assert()
40 struct visconti_reset *reset = to_visconti_reset(rcdev); in visconti_reset_deassert() local
41 const struct visconti_reset_data *data = &reset->resets[id]; in visconti_reset_deassert()
46 spin_lock_irqsave(reset->lock, flags); in visconti_reset_deassert()
47 ret = regmap_update_bits(reset->regmap, data->rsoff_offset, rst, rst); in visconti_reset_deassert()
48 spin_unlock_irqrestore(reset->lock, flags); in visconti_reset_deassert()
[all …]
/linux/arch/arm64/boot/dts/apple/
H A Dt8112-pmgr.dtsi14 #reset-cells = <0>;
23 #reset-cells = <0>;
32 #reset-cells = <0>;
41 #reset-cells = <0>;
49 #reset-cells = <0>;
57 #reset-cells = <0>;
66 #reset-cells = <0>;
75 #reset-cells = <0>;
84 #reset-cells = <0>;
93 #reset-cells = <0>;
[all …]
H A Dt8012-pmgr.dtsi13 #reset-cells = <0>;
22 #reset-cells = <0>;
31 #reset-cells = <0>;
40 #reset-cells = <0>;
48 #reset-cells = <0>;
57 #reset-cells = <0>;
65 #reset-cells = <0>;
74 #reset-cells = <0>;
83 #reset-cells = <0>;
91 #reset-cells = <0>;
[all …]
H A Ds8001-pmgr.dtsi13 #reset-cells = <0>;
22 #reset-cells = <0>;
31 #reset-cells = <0>;
40 #reset-cells = <0>;
48 #reset-cells = <0>;
57 #reset-cells = <0>;
66 #reset-cells = <0>;
75 #reset-cells = <0>;
83 #reset-cells = <0>;
91 #reset-cells = <0>;
[all …]
H A Dt8010-pmgr.dtsi13 #reset-cells = <0>;
22 #reset-cells = <0>;
31 #reset-cells = <0>;
40 #reset-cells = <0>;
48 #reset-cells = <0>;
57 #reset-cells = <0>;
66 #reset-cells = <0>;
75 #reset-cells = <0>;
83 #reset-cells = <0>;
91 #reset-cells = <0>;
[all …]
H A Dt8011-pmgr.dtsi13 #reset-cells = <0>;
22 #reset-cells = <0>;
31 #reset-cells = <0>;
40 #reset-cells = <0>;
49 #reset-cells = <0>;
57 #reset-cells = <0>;
66 #reset-cells = <0>;
75 #reset-cells = <0>;
84 #reset-cells = <0>;
92 #reset-cells = <0>;
[all …]
H A Ds800-0-3-pmgr.dtsi13 #reset-cells = <0>;
22 #reset-cells = <0>;
31 #reset-cells = <0>;
40 #reset-cells = <0>;
48 #reset-cells = <0>;
57 #reset-cells = <0>;
66 #reset-cells = <0>;
75 #reset-cells = <0>;
83 #reset-cells = <0>;
91 #reset-cells = <0>;
[all …]
H A Dt7001-pmgr.dtsi13 #reset-cells = <0>;
22 #reset-cells = <0>;
31 #reset-cells = <0>;
40 #reset-cells = <0>;
49 #reset-cells = <0>;
57 #reset-cells = <0>;
66 #reset-cells = <0>;
75 #reset-cells = <0>;
84 #reset-cells = <0>;
92 #reset-cells = <0>;
[all …]
H A Ds5l8960x-pmgr.dtsi13 #reset-cells = <0>;
22 #reset-cells = <0>;
31 #reset-cells = <0>;
40 #reset-cells = <0>;
49 #reset-cells = <0>;
58 #reset-cells = <0>;
67 #reset-cells = <0>;
76 #reset-cells = <0>;
85 #reset-cells = <0>;
93 #reset-cells = <0>;
[all …]
H A Dt7000-pmgr.dtsi12 #reset-cells = <0>;
21 #reset-cells = <0>;
30 #reset-cells = <0>;
39 #reset-cells = <0>;
47 #reset-cells = <0>;
56 #reset-cells = <0>;
65 #reset-cells = <0>;
74 #reset-cells = <0>;
82 #reset-cells = <0>;
90 #reset-cells = <0>;
[all …]
H A Dt600x-pmgr.dtsi13 #reset-cells = <0>;
22 #reset-cells = <0>;
31 #reset-cells = <0>;
40 #reset-cells = <0>;
49 #reset-cells = <0>;
58 #reset-cells = <0>;
67 #reset-cells = <0>;
76 #reset-cells = <0>;
84 #reset-cells = <0>;
92 #reset-cells = <0>;
[all …]
/linux/Documentation/devicetree/bindings/power/
H A Damlogic,meson-gx-pwrc.txt24 - resets: phandles to the reset lines needed for this power demain sequence
25 as described in ../reset/reset.txt
45 resets = <&reset RESET_VIU>,
46 <&reset RESET_VENC>,
47 <&reset RESET_VCBUS>,
48 <&reset RESET_BT656>,
49 <&reset RESET_DVIN_RESET>,
50 <&reset RESET_RDMA>,
51 <&reset RESET_VENCI>,
52 <&reset RESET_VENCP>,
[all …]
/linux/drivers/clk/actions/
H A Dowl-reset.c17 struct owl_reset *reset = to_owl_reset(rcdev); in owl_reset_assert() local
18 const struct owl_reset_map *map = &reset->reset_map[id]; in owl_reset_assert()
20 return regmap_update_bits(reset->regmap, map->reg, map->bit, 0); in owl_reset_assert()
26 struct owl_reset *reset = to_owl_reset(rcdev); in owl_reset_deassert() local
27 const struct owl_reset_map *map = &reset->reset_map[id]; in owl_reset_deassert()
29 return regmap_update_bits(reset->regmap, map->reg, map->bit, map->bit); in owl_reset_deassert()
45 struct owl_reset *reset = to_owl_reset(rcdev); in owl_reset_status() local
46 const struct owl_reset_map *map = &reset->reset_map[id]; in owl_reset_status()
50 ret = regmap_read(reset->regmap, map->reg, &reg); in owl_reset_status()
64 .reset = owl_reset_reset,
/linux/arch/arm/boot/dts/amlogic/
H A Dmeson8m2.dtsi36 resets = <&reset RESET_ETHERNET>;
37 reset-names = "stmmaceth";
66 resets = <&reset RESET_DBLK>,
67 <&reset RESET_PIC_DC>,
68 <&reset RESET_HDMI_APB>,
69 <&reset RESET_HDMI_SYSTEM_RESET>,
70 <&reset RESET_VENCI>,
71 <&reset RESET_VENCP>,
72 <&reset RESET_VDAC_4>,
73 <&reset RESET_VENCL>,
[all …]
/linux/arch/m68k/coldfire/
H A DMakefile19 obj-$(CONFIG_M5206) += m5206.o intc.o reset.o
20 obj-$(CONFIG_M5206e) += m5206.o intc.o reset.o
21 obj-$(CONFIG_M520x) += m520x.o intc-simr.o reset.o
22 obj-$(CONFIG_M523x) += m523x.o dma_timer.o intc-2.o reset.o
23 obj-$(CONFIG_M5249) += m5249.o intc.o intc-5249.o reset.o
24 obj-$(CONFIG_M525x) += m525x.o intc.o intc-525x.o reset.o
25 obj-$(CONFIG_M527x) += m527x.o intc-2.o reset.o
27 obj-$(CONFIG_M528x) += m528x.o intc-2.o reset.o
28 obj-$(CONFIG_M5307) += m5307.o intc.o reset.o
29 obj-$(CONFIG_M53xx) += m53xx.o intc-simr.o reset.o
[all …]

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