1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * 4 * Bluetooth support for Intel PCIe devices 5 * 6 * Copyright (C) 2024 Intel Corporation 7 */ 8 9 /* Control and Status Register(BTINTEL_PCIE_CSR) */ 10 #define BTINTEL_PCIE_CSR_BASE (0x000) 11 #define BTINTEL_PCIE_CSR_FUNC_CTRL_REG (BTINTEL_PCIE_CSR_BASE + 0x024) 12 #define BTINTEL_PCIE_CSR_HW_REV_REG (BTINTEL_PCIE_CSR_BASE + 0x028) 13 #define BTINTEL_PCIE_CSR_RF_ID_REG (BTINTEL_PCIE_CSR_BASE + 0x09C) 14 #define BTINTEL_PCIE_CSR_BOOT_STAGE_REG (BTINTEL_PCIE_CSR_BASE + 0x108) 15 #define BTINTEL_PCIE_CSR_IPC_CONTROL_REG (BTINTEL_PCIE_CSR_BASE + 0x10C) 16 #define BTINTEL_PCIE_CSR_IPC_STATUS_REG (BTINTEL_PCIE_CSR_BASE + 0x110) 17 #define BTINTEL_PCIE_CSR_IPC_SLEEP_CTL_REG (BTINTEL_PCIE_CSR_BASE + 0x114) 18 #define BTINTEL_PCIE_CSR_CI_ADDR_LSB_REG (BTINTEL_PCIE_CSR_BASE + 0x118) 19 #define BTINTEL_PCIE_CSR_CI_ADDR_MSB_REG (BTINTEL_PCIE_CSR_BASE + 0x11C) 20 #define BTINTEL_PCIE_CSR_IMG_RESPONSE_REG (BTINTEL_PCIE_CSR_BASE + 0x12C) 21 #define BTINTEL_PCIE_CSR_IPC_DOORBELL_VEC_REG (BTINTEL_PCIE_CSR_BASE + 0x130) 22 #define BTINTEL_PCIE_CSR_MBOX_1_REG (BTINTEL_PCIE_CSR_BASE + 0x170) 23 #define BTINTEL_PCIE_CSR_MBOX_2_REG (BTINTEL_PCIE_CSR_BASE + 0x174) 24 #define BTINTEL_PCIE_CSR_MBOX_3_REG (BTINTEL_PCIE_CSR_BASE + 0x178) 25 #define BTINTEL_PCIE_CSR_MBOX_4_REG (BTINTEL_PCIE_CSR_BASE + 0x17C) 26 #define BTINTEL_PCIE_CSR_MBOX_STATUS_REG (BTINTEL_PCIE_CSR_BASE + 0x180) 27 #define BTINTEL_PCIE_PRPH_DEV_ADDR_REG (BTINTEL_PCIE_CSR_BASE + 0x440) 28 #define BTINTEL_PCIE_PRPH_DEV_RD_REG (BTINTEL_PCIE_CSR_BASE + 0x458) 29 #define BTINTEL_PCIE_CSR_HBUS_TARG_WRPTR (BTINTEL_PCIE_CSR_BASE + 0x460) 30 31 /* BTINTEL_PCIE_CSR Function Control Register */ 32 #define BTINTEL_PCIE_CSR_FUNC_CTRL_FUNC_ENA (BIT(0)) 33 #define BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_INIT (BIT(6)) 34 #define BTINTEL_PCIE_CSR_FUNC_CTRL_FUNC_INIT (BIT(7)) 35 #define BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_ACCESS_STS (BIT(20)) 36 37 #define BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_ACCESS_REQ (BIT(21)) 38 39 #define BTINTEL_PCIE_CSR_FUNC_CTRL_BUS_MASTER_STS (BIT(28)) 40 #define BTINTEL_PCIE_CSR_FUNC_CTRL_BUS_MASTER_DISCON (BIT(29)) 41 #define BTINTEL_PCIE_CSR_FUNC_CTRL_SW_RESET (BIT(31)) 42 43 /* Value for BTINTEL_PCIE_CSR_BOOT_STAGE register */ 44 #define BTINTEL_PCIE_CSR_BOOT_STAGE_ROM (BIT(0)) 45 #define BTINTEL_PCIE_CSR_BOOT_STAGE_IML (BIT(1)) 46 #define BTINTEL_PCIE_CSR_BOOT_STAGE_OPFW (BIT(2)) 47 #define BTINTEL_PCIE_CSR_BOOT_STAGE_ROM_LOCKDOWN (BIT(10)) 48 #define BTINTEL_PCIE_CSR_BOOT_STAGE_IML_LOCKDOWN (BIT(11)) 49 #define BTINTEL_PCIE_CSR_BOOT_STAGE_DEVICE_WARNING (BIT(12)) 50 #define BTINTEL_PCIE_CSR_BOOT_STAGE_ABORT_HANDLER (BIT(13)) 51 #define BTINTEL_PCIE_CSR_BOOT_STAGE_DEVICE_HALTED (BIT(14)) 52 #define BTINTEL_PCIE_CSR_BOOT_STAGE_MAC_ACCESS_ON (BIT(16)) 53 #define BTINTEL_PCIE_CSR_BOOT_STAGE_ALIVE (BIT(23)) 54 /* Reflects live D-state. Updated by hardware on every D-state transition. */ 55 #define BTINTEL_PCIE_CSR_BOOT_STAGE_D3_STATE_READY (BIT(24)) 56 57 #define BTINTEL_PCIE_CSR_DOORBELL_MBOX_READ_CONFIRM (BIT(4)) 58 59 /* Registers for MSI-X */ 60 #define BTINTEL_PCIE_CSR_MSIX_BASE (0x2000) 61 #define BTINTEL_PCIE_CSR_MSIX_FH_INT_CAUSES (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0800) 62 #define BTINTEL_PCIE_CSR_MSIX_FH_INT_MASK (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0804) 63 #define BTINTEL_PCIE_CSR_MSIX_HW_INT_CAUSES (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0808) 64 #define BTINTEL_PCIE_CSR_MSIX_HW_INT_MASK (BTINTEL_PCIE_CSR_MSIX_BASE + 0x080C) 65 #define BTINTEL_PCIE_CSR_MSIX_AUTOMASK_ST (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0810) 66 #define BTINTEL_PCIE_CSR_MSIX_AUTOMASK_EN (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0814) 67 #define BTINTEL_PCIE_CSR_MSIX_IVAR_BASE (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0880) 68 #define BTINTEL_PCIE_CSR_MSIX_IVAR(cause) (BTINTEL_PCIE_CSR_MSIX_IVAR_BASE + (cause)) 69 70 /* IOSF Debug Register */ 71 #define BTINTEL_PCIE_DBGC_BASE_ADDR (0xf3800300) 72 #define BTINTEL_PCIE_DBGC_CUR_DBGBUFF_STATUS (BTINTEL_PCIE_DBGC_BASE_ADDR + 0x1C) 73 #define BTINTEL_PCIE_DBGC_DBGBUFF_WRAP_ARND (BTINTEL_PCIE_DBGC_BASE_ADDR + 0x2C) 74 75 #define BTINTEL_PCIE_DBGC_BASE_ADDR_SCP (0xf0d5d500) 76 #define BTINTEL_PCIE_DBGC_CUR_DBGBUFF_STATUS_SCP (BTINTEL_PCIE_DBGC_BASE_ADDR_SCP + 0x1C) 77 #define BTINTEL_PCIE_DBGC_DBGBUFF_WRAP_ARND_SCP (BTINTEL_PCIE_DBGC_BASE_ADDR_SCP + 0x2C) 78 #define BTINTEL_PCIE_DBGC_ALLOCATION_OFFSET 0x100 79 80 /* Upper bound for device-supplied debug-region sizes. */ 81 #define BTINTEL_PCIE_REGION_MAX_SIZE (1 * 1024 * 1024) 82 #define BTINTEL_PCIE_DBG_IDX_BIT_MASK 0x0F 83 #define BTINTEL_PCIE_DBGC_DBG_BUF_IDX(data) (((data) >> 24) & BTINTEL_PCIE_DBG_IDX_BIT_MASK) 84 #define BTINTEL_PCIE_DBG_OFFSET_BIT_MASK 0xFFFFFF 85 86 #define BTINTEL_PCIE_TARGET_ACCESS_FRAG_OFFSET 4 87 88 /* The DRAM buffer count, each buffer size, and 89 * fragment buffer size 90 */ 91 #define BTINTEL_PCIE_DBGC_BUFFER_COUNT 16 92 #define BTINTEL_PCIE_DBGC_BUFFER_SIZE (256 * 1024) /* 256 KB */ 93 94 #define BTINTEL_PCIE_DBGC_FRAG_VERSION 1 95 #define BTINTEL_PCIE_DBGC_FRAG_BUFFER_COUNT BTINTEL_PCIE_DBGC_BUFFER_COUNT 96 97 /* Magic number(4), version(4), size of payload length(4) */ 98 #define BTINTEL_PCIE_DBGC_FRAG_HEADER_SIZE 12 99 100 /* Num of alloc Dbg buff (4) + (LSB(4), MSB(4), Size(4)) for each buffer */ 101 #define BTINTEL_PCIE_DBGC_FRAG_PAYLOAD_SIZE 196 102 103 /* dbg_output_mode values for the context info. 104 * BTINTEL_PCIE_DRAM: firmware writes traces to host DRAM DBGC buffers. 105 * BTINTEL_PCIE_WIFI_DBGC: firmware forwards traces to the WiFi DBGC; the 106 * host does NOT need to allocate DBGC fragment/data buffers and must 107 * publish dbgc_addr/size as 0 in the context info. 108 * 109 * Encoding of BTINTEL_PCIE_WIFI_DBGC (0x06): 110 * Bit[0] DBGC O/P : 0 = SRAM (don't care, DBGI selected) 111 * Bit[1] DBGC I/P : 1 = DBGI 112 * Bits[2:3] DBGI O/P : 01 = WiFi DBGC 113 */ 114 #define BTINTEL_PCIE_DRAM 0x01 115 #define BTINTEL_PCIE_FW_MON_MODE_DRAM 0x02 116 #define BTINTEL_PCIE_WIFI_DBGC 0x06 117 118 #define BTINTEL_PCIE_MDBGC_FRAG_VERSION 2 119 120 #define BTINTEL_PCIE_MDBGC_ALLOCATIONID_1 0 121 #define BTINTEL_PCIE_MDBGC_ALLOCATIONID_2 1 122 #define BTINTEL_PCIE_MDBGC_ALLOCATIONID_3 2 123 124 #define BTINTEL_PCIE_DEVICE_ID_NVL_S_SCP2 0x6E74 125 #define BTINTEL_PCIE_DEVICE_ID_NVL_Hx_SCP2 0xD346 126 #define BTINTEL_PCIE_DEVICE_ID_PTL_FMP2 0xE476 127 128 /* Causes for the FH register interrupts */ 129 enum msix_fh_int_causes { 130 BTINTEL_PCIE_MSIX_FH_INT_CAUSES_0 = BIT(0), /* cause 0 */ 131 BTINTEL_PCIE_MSIX_FH_INT_CAUSES_1 = BIT(1), /* cause 1 */ 132 }; 133 134 /* Causes for the HW register interrupts */ 135 enum msix_hw_int_causes { 136 BTINTEL_PCIE_MSIX_HW_INT_CAUSES_GP0 = BIT(0), /* cause 32 */ 137 BTINTEL_PCIE_MSIX_HW_INT_CAUSES_GP1 = BIT(1), /* cause 33 */ 138 BTINTEL_PCIE_MSIX_HW_INT_CAUSES_HWEXP = BIT(3), /* cause 35 */ 139 BTINTEL_PCIE_MSIX_HW_INT_CAUSES_FWTRIG = BIT(5), /* cause 37 */ 140 }; 141 142 /* PCIe device states 143 * Host-Device interface is active 144 * Host-Device interface is inactive(as reflected by IPC_SLEEP_CONTROL_CSR_AD) 145 * Host-Device interface is inactive(as reflected by IPC_SLEEP_CONTROL_CSR_AD) 146 */ 147 enum { 148 BTINTEL_PCIE_STATE_D0 = 0, 149 BTINTEL_PCIE_STATE_D3_HOT = 2, 150 BTINTEL_PCIE_STATE_D3_COLD = 3, 151 }; 152 153 enum { 154 BTINTEL_PCIE_CORE_HALTED, 155 BTINTEL_PCIE_COREDUMP_INPROGRESS, 156 BTINTEL_PCIE_FWTRIGGER_DUMP_INPROGRESS, 157 BTINTEL_PCIE_RECOVERY_IN_PROGRESS, 158 BTINTEL_PCIE_SETUP_DONE, 159 BTINTEL_PCIE_MAIL_BOX_INTR, 160 BTINTEL_PCIE_MBOX_PARSE_PENDING, 161 BTINTEL_PCIE_MBOX_PARSE_READY 162 }; 163 164 enum btintel_pcie_tlv_type { 165 BTINTEL_CNVI_BT, 166 BTINTEL_WRITE_PTR, 167 BTINTEL_WRAP_CTR, 168 BTINTEL_TRIGGER_REASON, 169 BTINTEL_FW_SHA, 170 BTINTEL_CNVR_TOP, 171 BTINTEL_CNVI_TOP, 172 BTINTEL_DUMP_TIME, 173 BTINTEL_FW_BUILD, 174 BTINTEL_VENDOR, 175 BTINTEL_DRIVER, 176 BTINTEL_EVENT_TYPE, 177 BTINTEL_EVENT_ID 178 }; 179 180 /* causes for the MBOX interrupts */ 181 enum msix_mbox_int_causes { 182 BTINTEL_PCIE_CSR_MBOX_STATUS_MBOX1 = BIT(0), /* cause MBOX1 */ 183 BTINTEL_PCIE_CSR_MBOX_STATUS_MBOX2 = BIT(1), /* cause MBOX2 */ 184 BTINTEL_PCIE_CSR_MBOX_STATUS_MBOX3 = BIT(2), /* cause MBOX3 */ 185 BTINTEL_PCIE_CSR_MBOX_STATUS_MBOX4 = BIT(3), /* cause MBOX4 */ 186 }; 187 188 enum btintel_pcie_reset_type { 189 BTINTEL_PCIE_IOSF_PRR_FLR = 0, 190 BTINTEL_PCIE_IOSF_PRR_PLDR = 1, 191 }; 192 193 enum btintel_pcie_mbox_msg { 194 BTINTEL_PCIE_NO_USE = 0, 195 BTINTEL_PCIE_TOP_SILENT_RESET, 196 BTINTEL_PCIE_SB_AUDIO_DEVICE_REPORT, 197 BTINTEL_PCIE_BUILD_SPECIFIC_RESOURCES_MAPPING, 198 BTINTEL_PCIE_LAST_MESSAGE = 4095 199 }; 200 201 #define BTINTEL_PCIE_MSIX_NON_AUTO_CLEAR_CAUSE BIT(7) 202 203 /* Minimum and Maximum number of MSI-X Vector 204 * Intel Bluetooth PCIe support only 1 vector 205 */ 206 #define BTINTEL_PCIE_MSIX_VEC_MAX 1 207 #define BTINTEL_PCIE_MSIX_VEC_MIN 1 208 209 /* Default poll time for MAC access during init */ 210 #define BTINTEL_DEFAULT_MAC_ACCESS_TIMEOUT_US 200000 211 212 /* Default interrupt timeout in msec */ 213 #define BTINTEL_DEFAULT_INTR_TIMEOUT_MS 3000 214 #define BTINTEL_PCIE_MBOX_INTR_TIMEOUT_MS 500 215 216 #define BTINTEL_PCIE_DX_TRANSITION_MAX_RETRIES 3 217 218 /* The number of descriptors in TX queues */ 219 #define BTINTEL_PCIE_TX_DESCS_COUNT 32 220 221 /* The number of descriptors in RX queues */ 222 #define BTINTEL_PCIE_RX_DESCS_COUNT 64 223 224 /* Number of Queue for TX and RX 225 * It indicates the index of the IA(Index Array) 226 */ 227 enum { 228 BTINTEL_PCIE_TXQ_NUM = 0, 229 BTINTEL_PCIE_RXQ_NUM = 1, 230 BTINTEL_PCIE_NUM_QUEUES = 2, 231 }; 232 233 /* The size of DMA buffer for TX and RX in bytes */ 234 #define BTINTEL_PCIE_BUFFER_SIZE 4096 235 236 #define BTINTEL_PCIE_TX_WAIT_TIMEOUT_MS 500 237 238 /* Doorbell vector for TFD */ 239 #define BTINTEL_PCIE_TX_DB_VEC 0 240 241 /* Doorbell vector for FRBD */ 242 #define BTINTEL_PCIE_RX_DB_VEC 513 243 244 /* RBD buffer size mapping */ 245 #define BTINTEL_PCIE_RBD_SIZE_4K 0x04 246 247 #define BTINTEL_PCIE_TLV_TYPE_EXCEPTION_DUMP_ADDRESS 0x04 248 #define BTINTEL_PCIE_TLV_TYPE_DCCM_MEM_ADDRESS 0x05 249 #define BTINTEL_PCIE_TLV_TYPE_SDS_MEM_ADDRESS 0x06 250 #define BTINTEL_PCIE_TLV_TYPE_ECL_MEM_ADDRESS 0x07 251 #define BTINTEL_PCIE_TLV_TYPE_SMEM_ADDRESS 0x08 252 253 /* 254 * Struct for Context Information (v2) 255 * 256 * All members are write-only for host and read-only for device. 257 * 258 * @version: Version of context information 259 * @size: Size of context information 260 * @config: Config with which host wants peripheral to execute 261 * Subset of capability register published by device 262 * @addr_tr_hia: Address of TR Head Index Array 263 * @addr_tr_tia: Address of TR Tail Index Array 264 * @addr_cr_hia: Address of CR Head Index Array 265 * @addr_cr_tia: Address of CR Tail Index Array 266 * @num_tr_ia: Number of entries in TR Index Arrays 267 * @num_cr_ia: Number of entries in CR Index Arrays 268 * @rbd_siz: RBD Size { 0x4=4K } 269 * @addr_tfdq: Address of TFD Queue(tx) 270 * @addr_urbdq0: Address of URBD Queue(tx) 271 * @num_tfdq: Number of TFD in TFD Queue(tx) 272 * @num_urbdq0: Number of URBD in URBD Queue(tx) 273 * @tfdq_db_vec: Queue number of TFD 274 * @urbdq0_db_vec: Queue number of URBD 275 * @addr_frbdq: Address of FRBD Queue(rx) 276 * @addr_urbdq1: Address of URBD Queue(rx) 277 * @num_frbdq: Number of FRBD in FRBD Queue(rx) 278 * @frbdq_db_vec: Queue number of FRBD 279 * @num_urbdq1: Number of URBD in URBD Queue(rx) 280 * @urbdq_db_vec: Queue number of URBDQ1 281 * @tr_msi_vec: Transfer Ring MSI-X Vector 282 * @cr_msi_vec: Completion Ring MSI-X Vector 283 * @dbgc_addr: DBGC first fragment address 284 * @dbgc_size: DBGC buffer size 285 * @early_enable: Enarly debug enable 286 * @dbg_output_mode: Debug output mode 287 * Bit[4] DBGC O/P { 0=SRAM, 1=DRAM(not relevant for NPK) } 288 * Bit[5] DBGC I/P { 0=BDBG, 1=DBGI } 289 * Bits[6:7] DBGI O/P(relevant if bit[5] = 1) 290 * 0=BT DBGC, 1=WiFi DBGC, 2=NPK } 291 * @dbg_preset: Debug preset 292 * @ext_addr: Address of context information extension 293 * @ext_size: Size of context information part 294 * 295 * Total 38 DWords 296 */ 297 struct ctx_info { 298 u16 version; 299 u16 size; 300 u32 config; 301 u32 reserved_dw02; 302 u32 reserved_dw03; 303 u64 addr_tr_hia; 304 u64 addr_tr_tia; 305 u64 addr_cr_hia; 306 u64 addr_cr_tia; 307 u16 num_tr_ia; 308 u16 num_cr_ia; 309 u32 rbd_size:4, 310 reserved_dw13:28; 311 u64 addr_tfdq; 312 u64 addr_urbdq0; 313 u16 num_tfdq; 314 u16 num_urbdq0; 315 u16 tfdq_db_vec; 316 u16 urbdq0_db_vec; 317 u64 addr_frbdq; 318 u64 addr_urbdq1; 319 u16 num_frbdq; 320 u16 frbdq_db_vec; 321 u16 num_urbdq1; 322 u16 urbdq_db_vec; 323 u16 tr_msi_vec; 324 u16 cr_msi_vec; 325 u32 reserved_dw27; 326 u64 dbgc_addr; 327 u32 dbgc_size; 328 u32 early_enable:1, 329 reserved_dw31:3, 330 dbg_output_mode:4, 331 dbg_preset:8, 332 reserved2_dw31:16; 333 u64 ext_addr; 334 u32 ext_size; 335 u32 test_param; 336 u32 reserved_dw36; 337 u32 reserved_dw37; 338 } __packed; 339 340 /* Transfer Descriptor for TX 341 * @type: Not in use. Set to 0x0 342 * @size: Size of data in the buffer 343 * @addr: DMA Address of buffer 344 */ 345 struct tfd { 346 u8 type; 347 u16 size; 348 u8 reserved; 349 u64 addr; 350 u32 reserved1; 351 } __packed; 352 353 /* URB Descriptor for TX 354 * @tfd_index: Index of TFD in TFDQ + 1 355 * @num_txq: Queue index of TFD Queue 356 * @cmpl_count: Completion count. Always 0x01 357 * @immediate_cmpl: Immediate completion flag: Always 0x01 358 */ 359 struct urbd0 { 360 u32 tfd_index:16, 361 num_txq:8, 362 cmpl_count:4, 363 reserved:3, 364 immediate_cmpl:1; 365 } __packed; 366 367 /* FRB Descriptor for RX 368 * @tag: RX buffer tag (index of RX buffer queue) 369 * @addr: Address of buffer 370 */ 371 struct frbd { 372 u32 tag:16, 373 reserved:16; 374 u32 reserved2; 375 u64 addr; 376 } __packed; 377 378 /* URB Descriptor for RX 379 * @frbd_tag: Tag from FRBD 380 * @status: Status 381 */ 382 struct urbd1 { 383 u32 frbd_tag:16, 384 status:1, 385 reserved:14, 386 fixed:1; 387 } __packed; 388 389 /* RFH header in RX packet 390 * @packet_len: Length of the data in the buffer 391 * @rxq: RX Queue number 392 * @cmd_id: Command ID. Not in Use 393 */ 394 struct rfh_hdr { 395 u64 packet_len:16, 396 rxq:6, 397 reserved:10, 398 cmd_id:16, 399 reserved1:16; 400 } __packed; 401 402 /* Internal data buffer 403 * @data: pointer to the data buffer 404 * @p_addr: physical address of data buffer 405 */ 406 struct data_buf { 407 u8 *data; 408 dma_addr_t data_p_addr; 409 }; 410 411 /* Index Array */ 412 struct ia { 413 dma_addr_t tr_hia_p_addr; 414 u16 *tr_hia; 415 dma_addr_t tr_tia_p_addr; 416 u16 *tr_tia; 417 dma_addr_t cr_hia_p_addr; 418 u16 *cr_hia; 419 dma_addr_t cr_tia_p_addr; 420 u16 *cr_tia; 421 }; 422 423 /* Structure for TX Queue 424 * @count: Number of descriptors 425 * @tfds: Array of TFD 426 * @urbd0s: Array of URBD0 427 * @buf: Array of data_buf structure 428 */ 429 struct txq { 430 u16 count; 431 432 dma_addr_t tfds_p_addr; 433 struct tfd *tfds; 434 435 dma_addr_t urbd0s_p_addr; 436 struct urbd0 *urbd0s; 437 438 dma_addr_t buf_p_addr; 439 void *buf_v_addr; 440 struct data_buf *bufs; 441 }; 442 443 /* Structure for RX Queue 444 * @count: Number of descriptors 445 * @frbds: Array of FRBD 446 * @urbd1s: Array of URBD1 447 * @buf: Array of data_buf structure 448 */ 449 struct rxq { 450 u16 count; 451 452 dma_addr_t frbds_p_addr; 453 struct frbd *frbds; 454 455 dma_addr_t urbd1s_p_addr; 456 struct urbd1 *urbd1s; 457 458 dma_addr_t buf_p_addr; 459 void *buf_v_addr; 460 struct data_buf *bufs; 461 }; 462 463 /* Structure for DRAM Buffer 464 * @count: Number of descriptors 465 * @buf: Array of data_buf structure 466 */ 467 struct btintel_pcie_dbgc { 468 u16 count; 469 470 void *frag_v_addr; 471 dma_addr_t frag_p_addr; 472 u16 frag_size; 473 474 dma_addr_t buf_p_addr; 475 void *buf_v_addr; 476 struct data_buf *bufs; 477 }; 478 479 struct btintel_pcie_mdbgc { 480 u32 count; 481 482 void *frag_v_addr; 483 dma_addr_t frag_p_addr; 484 u32 frag_size; 485 486 dma_addr_t buf1_p_addr; 487 void *buf1_v_addr; 488 dma_addr_t buf2_p_addr; 489 void *buf2_v_addr; 490 dma_addr_t buf3_p_addr; 491 void *buf3_v_addr; 492 struct data_buf *buf1; 493 struct data_buf *buf2; 494 struct data_buf *buf3; 495 }; 496 497 struct btintel_pcie_dump_mem_info { 498 u32 exception_dump_addr; 499 u32 exception_dump_len; 500 u32 dccm_addr_start; 501 u32 dccm_size; 502 u32 sds_fixed_rom_addr_start; 503 u32 sds_fixed_rom_size; 504 u32 sds_start_addr_start; 505 u32 sds_start_size; 506 u32 sds_iosf_data_addr_start; 507 u32 sds_iosf_data_size; 508 u32 ecl_addr_start; 509 u32 ecl_size; 510 u32 smem_addr_start; 511 u32 smem_size; 512 }; 513 514 struct btintel_pcie_mbox { 515 u32 mbox_flags; 516 u32 mbox_status; 517 u32 mbox1; 518 u32 mbox2; 519 u32 mbox3; 520 u32 mbox4; 521 }; 522 523 struct btintel_pcie_dump_header { 524 const char *driver_name; 525 u32 cnvi_top; 526 u32 cnvr_top; 527 u16 fw_timestamp; 528 u8 fw_build_type; 529 u32 fw_build_num; 530 u32 fw_sha; 531 u32 cnvi_bt; 532 u32 write_ptr; 533 u32 wrap_ctr; 534 u16 trigger_reason; 535 int state; 536 }; 537 538 /* Per-fragment range descriptor for dump regions. 539 * Binary-compatible with iwl_fw_ini_error_dump_range. 540 */ 541 struct btintel_pcie_dump_range { 542 __le32 range_data_size; 543 union { 544 __le32 internal_base_addr; 545 __le64 dram_base_addr; 546 __le32 page_num; 547 }; 548 __le32 data[]; 549 } __packed; 550 551 /* 552 * INI region types for ini_dump_data.type field. 553 * The unified decoder dispatches parsing logic based on these values. 554 */ 555 #define BTINTEL_PCIE_INI_REGION_INTERNAL_BUFFER 2 556 #define BTINTEL_PCIE_INI_REGION_DRAM_BUFFER 3 557 #define BTINTEL_PCIE_INI_REGION_DEVICE_MEMORY 9 558 559 /* INI region IDs - used in dump header region_id field and regions_mask */ 560 #define BTINTEL_PCIE_INI_ID_EXCEPTION_EVT 7 561 #define BTINTEL_PCIE_INI_ID_SMEM 15 562 #define BTINTEL_PCIE_INI_ID_DCCM 39 563 #define BTINTEL_PCIE_INI_ID_SDS 40 564 #define BTINTEL_PCIE_INI_ID_SDS_IOSF 41 565 #define BTINTEL_PCIE_INI_ID_ECL 42 566 #define BTINTEL_PCIE_INI_ID_DRAM_MONITOR3 61 567 #define BTINTEL_PCIE_INI_ID_DRAM_MONITOR2 62 568 #define BTINTEL_PCIE_INI_ID_DRAM_MONITOR1 63 569 570 /* 571 * INI (Intel INI debug infrastructure) style dump data TLV - wraps each dump 572 * region. INI is the iwlwifi firmware debug format used by the unified decoder. 573 * Compatible with iwl_fw_ini_error_dump_data. 574 */ 575 struct btintel_pcie_ini_dump_data { 576 u8 type; 577 u8 sub_type; 578 u8 sub_type_ver; 579 u8 reserved; 580 __le32 len; 581 u8 data[]; 582 } __packed; 583 584 /* 585 * INI-style region dump header. 586 * Compatible with iwl_fw_ini_error_dump_header. 587 */ 588 #define BTINTEL_PCIE_INI_MAX_NAME 32 589 #define BTINTEL_PCIE_INI_DUMP_VER 1 590 591 struct btintel_pcie_ini_dump_header { 592 __le32 version; 593 __le32 region_id; 594 __le32 num_of_ranges; 595 __le32 name_len; 596 u8 name[BTINTEL_PCIE_INI_MAX_NAME]; 597 }; 598 599 /* 600 * INI-style monitor dump - region header + monitor state. 601 * Compatible with iwl_fw_ini_monitor_dump. 602 */ 603 struct btintel_pcie_ini_monitor_dump { 604 struct btintel_pcie_ini_dump_header header; 605 __le32 write_ptr; 606 __le32 cycle_cnt; 607 __le32 cur_frag; 608 u8 data[]; 609 } __packed; 610 611 /* Linked list entry for modular dump collection */ 612 struct btintel_pcie_dump_entry { 613 struct list_head list; 614 u32 size; 615 u8 data[]; 616 }; 617 618 /* File-level header for coredump output. 619 * Compatible with iwl_fw_ini_dump_file_hdr. 620 * Uses IWL_FW_INI_ERROR_DUMP_BARKER (0x14789633) for decoder compatibility. 621 */ 622 #define BTINTEL_PCIE_INI_ERROR_DUMP_BARKER 0x14789633 623 624 struct btintel_pcie_dump_file_hdr { 625 __le32 barker; 626 __le32 file_len; 627 } __packed; 628 629 /* 630 * Legacy-style dump data wrapper for dump info TLV. 631 * Compatible with iwl_fw_error_dump_data. 632 * Used only for the dump info entry (type=BTINTEL_PCIE_INI_DUMP_INFO_TYPE). 633 */ 634 struct btintel_pcie_error_dump_data { 635 __le32 type; 636 __le32 len; 637 u8 data[]; 638 } __packed; 639 640 /* Use bit 31 as dump info type, matching IWL_INI_DUMP_INFO_TYPE */ 641 #define BTINTEL_PCIE_INI_DUMP_INFO_TYPE BIT(31) 642 643 /* Time point values matching iwl_fw_ini_time_point for fwdump parser */ 644 #define BTINTEL_PCIE_TIME_POINT_FW_ASSERT 4 645 #define BTINTEL_PCIE_TIME_POINT_USER_TRIGGER 9 646 647 /* 648 * Dump info struct - single TLV containing all metadata. 649 * Compatible with iwl_fw_ini_dump_info. 650 * Packs all device/firmware info that the decoder needs. 651 */ 652 struct btintel_pcie_ini_dump_info { 653 __le32 version; 654 __le32 time_point; 655 __le32 trigger_reason; 656 __le32 external_cfg_state; 657 __le32 ver_type; 658 __le32 ver_subtype; 659 __le32 hw_step; 660 __le32 hw_type; 661 __le32 rf_id_flavor; 662 __le32 rf_id_dash; 663 __le32 rf_id_step; 664 __le32 rf_id_type; 665 __le32 lmac_major; 666 __le32 lmac_minor; 667 __le32 umac_major; 668 __le32 umac_minor; 669 __le32 fw_mon_mode; 670 __le64 regions_mask; 671 __le32 build_tag_len; 672 u8 build_tag[64]; 673 __le32 num_of_cfg_names; 674 /* no cfg_names for BT - keep zero-length */ 675 } __packed; 676 677 /* struct btintel_pcie_data 678 * @pdev: pci device 679 * @hdev: hdev device 680 * @flags: driver state 681 * @irq_lock: spinlock for MSI-X 682 * @hci_rx_lock: spinlock for HCI RX flow 683 * @base_addr: pci base address (from BAR) 684 * @msix_entries: array of MSI-X entries 685 * @msix_enabled: true if MSI-X is enabled; 686 * @alloc_vecs: number of interrupt vectors allocated 687 * @def_irq: default irq for all causes 688 * @fh_init_mask: initial unmasked rxq causes 689 * @hw_init_mask: initial unmaksed hw causes 690 * @boot_stage_cache: cached value of boot stage register 691 * @img_resp_cache: cached value of image response register 692 * @dbg_path_cache: cached debug output routing mode (BT DRAM or WiFi DBGC) 693 * @cnvi: CNVi register value 694 * @cnvr: CNVr register value 695 * @gp0_received: condition for gp0 interrupt 696 * @gp0_wait_q: wait_q for gp0 interrupt 697 * @tx_wait_done: condition for tx interrupt 698 * @tx_wait_q: wait_q for tx interrupt 699 * @workqueue: workqueue for RX work 700 * @rx_skb_q: SKB queue for RX packet 701 * @rx_work: RX work struct to process the RX packet in @rx_skb_q 702 * @dump_workqueue: dedicated ordered workqueue serializing the coredump, 703 * hardware exception, and firmware-trigger dump workers 704 * @coredump_work: work struct for DRAM trace coredump collection 705 * @hwexp_work: work struct for hardware exception event read 706 * @fwtrigger_work: work struct for firmware-triggered diagnostic event read 707 * @dma_pool: DMA pool for descriptors, index array and ci 708 * @dma_p_addr: DMA address for pool 709 * @dma_v_addr: address of pool 710 * @ci_p_addr: DMA address for CI struct 711 * @ci: CI struct 712 * @ia: Index Array struct 713 * @txq: TX Queue struct 714 * @rxq: RX Queue struct 715 * @alive_intr_ctxt: Alive interrupt context 716 */ 717 struct btintel_pcie_data { 718 struct pci_dev *pdev; 719 struct hci_dev *hdev; 720 721 unsigned long flags; 722 /* lock used in MSI-X interrupt */ 723 spinlock_t irq_lock; 724 /* lock to serialize rx events */ 725 spinlock_t hci_rx_lock; 726 727 void __iomem *base_addr; 728 729 struct msix_entry msix_entries[BTINTEL_PCIE_MSIX_VEC_MAX]; 730 bool msix_enabled; 731 u32 alloc_vecs; 732 u32 def_irq; 733 734 u32 fh_init_mask; 735 u32 hw_init_mask; 736 737 u32 boot_stage_cache; 738 u32 img_resp_cache; 739 u32 dbg_path_cache; 740 741 u32 cnvi; 742 u32 cnvr; 743 744 bool gp0_received; 745 wait_queue_head_t gp0_wait_q; 746 747 bool tx_wait_done; 748 wait_queue_head_t tx_wait_q; 749 750 struct workqueue_struct *workqueue; 751 struct sk_buff_head rx_skb_q; 752 struct work_struct rx_work; 753 struct work_struct reset_work; 754 755 struct workqueue_struct *dump_workqueue; 756 struct work_struct coredump_work; 757 struct work_struct hwexp_work; 758 struct work_struct fwtrigger_work; 759 struct work_struct mbox_work; 760 761 struct dma_pool *dma_pool; 762 dma_addr_t dma_p_addr; 763 void *dma_v_addr; 764 765 dma_addr_t ci_p_addr; 766 struct ctx_info *ci; 767 struct ia ia; 768 struct txq txq; 769 struct rxq rxq; 770 u32 alive_intr_ctxt; 771 enum btintel_pcie_reset_type reset_type; 772 struct btintel_pcie_dbgc dbgc; 773 struct btintel_pcie_mdbgc mdbgc; 774 struct btintel_pcie_dump_header dmp_hdr; 775 u32 debug_evt_addr; 776 u32 debug_evt_size; 777 dma_addr_t debug_table_addr; 778 u32 debug_table_size; 779 struct btintel_pcie_dump_mem_info dump_info; 780 struct btintel_pcie_mbox mbox; 781 782 /* Wait queue for mbox_worker to wait for GP0 alive interrupt */ 783 wait_queue_head_t mbox_parse_wait_q; 784 /* Timestamp captured in GP1 handler when mbox interrupt is received */ 785 ktime_t mbox_intr_ts; 786 }; 787 788 static inline u32 btintel_pcie_rd_reg32(struct btintel_pcie_data *data, 789 u32 offset) 790 { 791 return ioread32(data->base_addr + offset); 792 } 793 794 static inline void btintel_pcie_wr_reg8(struct btintel_pcie_data *data, 795 u32 offset, u8 val) 796 { 797 iowrite8(val, data->base_addr + offset); 798 } 799 800 static inline void btintel_pcie_wr_reg32(struct btintel_pcie_data *data, 801 u32 offset, u32 val) 802 { 803 iowrite32(val, data->base_addr + offset); 804 } 805 806 static inline void btintel_pcie_set_reg_bits(struct btintel_pcie_data *data, 807 u32 offset, u32 bits) 808 { 809 u32 r; 810 811 r = ioread32(data->base_addr + offset); 812 r |= bits; 813 iowrite32(r, data->base_addr + offset); 814 } 815 816 static inline void btintel_pcie_clr_reg_bits(struct btintel_pcie_data *data, 817 u32 offset, u32 bits) 818 { 819 u32 r; 820 821 r = ioread32(data->base_addr + offset); 822 r &= ~bits; 823 iowrite32(r, data->base_addr + offset); 824 } 825 826 static inline u32 btintel_pcie_rd_dev_mem(struct btintel_pcie_data *data, 827 u32 addr) 828 { 829 btintel_pcie_wr_reg32(data, BTINTEL_PCIE_PRPH_DEV_ADDR_REG, addr); 830 return btintel_pcie_rd_reg32(data, BTINTEL_PCIE_PRPH_DEV_RD_REG); 831 } 832