| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_resource.c | 557 struct resource_context *res_ctx, in resource_unreference_clock_source() argument
564 res_ctx->clock_source_ref_count[i]--; in resource_unreference_clock_source()
567 res_ctx->dp_clock_source_ref_count--; in resource_unreference_clock_source()
571 struct resource_context *res_ctx, in resource_reference_clock_source() argument
578 res_ctx->clock_source_ref_count[i]++; in resource_reference_clock_source()
581 res_ctx->dp_clock_source_ref_count++; in resource_reference_clock_source()
585 struct resource_context *res_ctx, in resource_get_clock_source_reference() argument
592 return res_ctx->clock_source_ref_count[i]; in resource_get_clock_source_reference()
595 return res_ctx->dp_clock_source_ref_count; in resource_get_clock_source_reference()
732 struct resource_context *res_ctx, in resource_find_used_clk_src_for_sharing() argument
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| H A D | dc_stream.c | 257 struct resource_context *res_ctx; in program_cursor_attributes() local
264 res_ctx = &dc->current_state->res_ctx; in program_cursor_attributes()
267 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; in program_cursor_attributes()
404 struct resource_context *res_ctx; in program_cursor_position() local
411 res_ctx = &dc->current_state->res_ctx; in program_cursor_position()
414 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; in program_cursor_position()
504 struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_program_cursor_position()
523 struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_program_cursor_position()
710 struct resource_context *res_ctx = in dc_stream_get_vblank_counter() local
711 &dc->current_state->res_ctx; in dc_stream_get_vblank_counter()
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| H A D | dc.c | 432 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in set_long_vtotal()
496 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_adjust_vmin_vmax()
538 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_get_last_used_drr_vtotal()
604 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_forward_crc_window()
670 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_forward_multiple_crc_window()
720 &dc->current_state->res_ctx, stream); in dc_stream_configure_crc()
795 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_get_crc()
821 if (dc->current_state->res_ctx.pipe_ctx[i].stream in dc_stream_set_dyn_expansion()
823 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_set_dyn_expansion()
843 if (link->dc->current_state->res_ctx.pipe_ctx[i].stream == in dc_stream_set_dither_option()
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| H A D | dc_surface.c | 74 struct pipe_ctx *pipe_ctx = &dc_state->res_ctx.pipe_ctx[i]; in dc_plane_get_pipe_mask()
135 &dc->current_state->res_ctx.pipe_ctx[i]; in dc_plane_get_status()
150 &dc->current_state->res_ctx.pipe_ctx[i]; in dc_plane_get_status()
290 struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_plane_force_dcc_and_tiling_disable()
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| H A D | dc_state.c | 152 struct pipe_ctx *cur_pipe = &dst_state->res_ctx.pipe_ctx[i]; in dc_state_copy_internal()
155 cur_pipe->top_pipe = &dst_state->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx]; in dc_state_copy_internal()
158 cur_pipe->bottom_pipe = &dst_state->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx]; in dc_state_copy_internal()
161 cur_pipe->prev_odm_pipe = &dst_state->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx]; in dc_state_copy_internal()
164 cur_pipe->next_odm_pipe = &dst_state->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx]; in dc_state_copy_internal()
330 memset(&state->res_ctx, 0, sizeof(state->res_ctx)); in dc_state_destruct()
408 &state->res_ctx, stream); in dc_state_remove_stream()
477 &state->res_ctx, stream); in dc_state_add_plane()
924 struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i]; in dc_state_remove_phantom_streams_and_planes()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource_helpers.c | 114 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_merge_pipes_for_subvp()
132 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); in dcn32_merge_pipes_for_subvp()
159 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_all_pipes_have_stream_and_plane()
176 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_subvp_in_use()
201 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_any_surfaces_rotated()
260 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in override_det_for_subvp()
275 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in override_det_for_subvp()
340 if (context->res_ctx.pipe_ctx[j].stream == context->streams[i] && in dcn32_determine_det_override()
348 current_plane = context->res_ctx.pipe_ctx[j].plane_state; in dcn32_determine_det_override()
350 if (k != j && context->res_ctx.pipe_ctx[k].stream == context->streams[i] && in dcn32_determine_det_override()
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| H A D | dcn32_resource.c | 1596 struct resource_context *res_ctx, in dcn32_acquire_post_bldn_3dlut() argument
1608 if (!res_ctx->is_mpc_3dlut_acquired[mpcc_id]) { in dcn32_acquire_post_bldn_3dlut()
1611 res_ctx->is_mpc_3dlut_acquired[mpcc_id] = true; in dcn32_acquire_post_bldn_3dlut()
1618 struct resource_context *res_ctx, in dcn32_release_post_bldn_3dlut() argument
1628 res_ctx->is_mpc_3dlut_acquired[i] = false; in dcn32_release_post_bldn_3dlut()
1646 struct pipe_ctx *curr_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; in dcn32_enable_phantom_plane()
1690 struct pipe_ctx *ref_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; in dcn32_enable_phantom_stream()
1729 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_add_phantom_pipes()
1868 struct resource_context *res_ctx = &context->res_ctx; in dcn32_populate_dml_pipes_from_context() local
1901 pipe = &res_ctx->pipe_ctx[i]; in dcn32_populate_dml_pipes_from_context()
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| /linux/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| H A D | link_dp_panel_replay.c | 60 if (dc->current_state->res_ctx.pipe_ctx[i].stream && in dp_pr_set_static_screen_param()
61 dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) { in dp_pr_set_static_screen_param()
62 struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream; in dp_pr_set_static_screen_param()
128 if (dc->current_state->res_ctx.pipe_ctx[i].stream in dp_setup_panel_replay()
134 dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg->inst + 1; in dp_setup_panel_replay()
219 if (dc->current_state->res_ctx.pipe_ctx[i].stream && in dp_pr_get_panel_inst()
220 dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) { in dp_pr_get_panel_inst()
222 if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg) in dp_pr_get_panel_inst()
223 *inst_out = dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg->inst; in dp_pr_get_panel_inst()
286 if (dc->current_state->res_ctx.pipe_ctx[i].stream && in dp_pr_copy_settings()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| H A D | dcn20_resource.c | 1314 struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream); in dcn20_build_mapped_resource()
1327 struct resource_context *res_ctx, in dcn20_acquire_dsc() argument
1333 …struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_r… in dcn20_acquire_dsc()
1341 res_ctx->is_dsc_acquired[pipe_idx] = true; in dcn20_acquire_dsc()
1346 if (dsc_old && !res_ctx->is_dsc_acquired[dsc_old->inst]) { in dcn20_acquire_dsc()
1348 res_ctx->is_dsc_acquired[dsc_old->inst] = true; in dcn20_acquire_dsc()
1354 if (!res_ctx->is_dsc_acquired[i]) { in dcn20_acquire_dsc()
1356 res_ctx->is_dsc_acquired[i] = true; in dcn20_acquire_dsc()
1361 void dcn20_release_dsc(struct resource_context *res_ctx, in dcn20_release_dsc() argument
1369 res_ctx->is_dsc_acquired[i] = false; in dcn20_release_dsc()
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dmub_replay.c | 125 struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx; in dmub_replay_copy_settings() local
129 if (res_ctx && in dmub_replay_copy_settings()
130 res_ctx->pipe_ctx[i].stream && in dmub_replay_copy_settings()
131 res_ctx->pipe_ctx[i].stream->link && in dmub_replay_copy_settings()
132 res_ctx->pipe_ctx[i].stream->link == link && in dmub_replay_copy_settings()
133 res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) { in dmub_replay_copy_settings()
134 pipe_ctx = &res_ctx->pipe_ctx[i]; in dmub_replay_copy_settings()
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| H A D | dmub_psr.c | 302 struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx; in dmub_psr_copy_settings() local
306 if (res_ctx->pipe_ctx[i].stream && in dmub_psr_copy_settings()
307 res_ctx->pipe_ctx[i].stream->link == link && in dmub_psr_copy_settings()
308 res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) { in dmub_psr_copy_settings()
309 pipe_ctx = &res_ctx->pipe_ctx[i]; in dmub_psr_copy_settings()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 734 *opp_cnt = resource_get_opp_heads_for_otg_master(pipe_ctx, &context->res_ctx, opp_heads); in enable_stream_timing_calc()
1027 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; in disable_link_output_symclk_on_tx_off()
1254 struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[i]; in dcn401_calculate_cab_allocation()
1469 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn401_optimize_bandwidth()
1539 old_otg_master = &dc->current_state->res_ctx.pipe_ctx[otg_master->pipe_idx]; in update_dsc_for_odm_change()
1543 &dc->current_state->res_ctx, in update_dsc_for_odm_change()
1560 new_pipe = &context->res_ctx.pipe_ctx[old_pipe->pipe_idx]; in update_dsc_for_odm_change()
1579 otg_master, &context->res_ctx, opp_heads); in dcn401_update_odm()
1623 old_otg_master = &dc->current_state->res_ctx.pipe_ctx[otg_master->pipe_idx]; in dcn401_add_dsc_sequence_for_odm_change()
1627 &dc->current_state->res_ctx, in dcn401_add_dsc_sequence_for_odm_change()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 1324 struct resource_context *res_ctx = &context->res_ctx; in dcn30_populate_dml_pipes_from_context() local
1331 if (!res_ctx->pipe_ctx[i].stream) in dcn30_populate_dml_pipes_from_context()
1342 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) in dcn30_populate_dml_writeback_from_context() argument
1345 dcn30_fpu_populate_dml_writeback_from_context(dc, res_ctx, pipes); in dcn30_populate_dml_writeback_from_context()
1387 if (!context->res_ctx.pipe_ctx[i].stream) in dcn30_set_mcif_arb_params()
1391 …struct dc_writeback_info *writeback_info = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j]; in dcn30_set_mcif_arb_params()
1408 …wb_arb_params->time_per_pixel = (1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk;… in dcn30_set_mcif_arb_params()
1428 struct resource_context *res_ctx, in dcn30_acquire_post_bldn_3dlut() argument
1443 if (!res_ctx->is_mpc_3dlut_acquired[i]) { in dcn30_acquire_post_bldn_3dlut()
1447 res_ctx->is_mpc_3dlut_acquired[i] = true; in dcn30_acquire_post_bldn_3dlut()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
| H A D | dcn32_hwseq.c | 239 struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[i]; in dcn32_calculate_cab_allocation()
361 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn32_commit_subvp_config()
392 pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_subvp_pipe_control_lock()
413 pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_subvp_pipe_control_lock()
616 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_update_force_pstate()
635 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_update_force_pstate()
636 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dcn32_update_force_pstate()
681 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_update_mall_sel()
741 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_program_mall_pipe_config()
1169 struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; in dcn32_update_odm()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| H A D | dcn20_hwseq.c | 854 opp_cnt = resource_get_opp_heads_for_otg_master(pipe_ctx, &context->res_ctx, opp_heads); in dcn20_enable_stream_timing()
2049 pipe = &context->res_ctx.pipe_ctx[i]; in dcn20_program_front_end_for_ctx()
2061 if (dc->current_state->res_ctx.pipe_ctx[i].plane_state) in dcn20_program_front_end_for_ctx()
2063 if (context->res_ctx.pipe_ctx[i].plane_state) in dcn20_program_front_end_for_ctx()
2076 dcn20_detect_pipe_changes(dc->current_state, context, &dc->current_state->res_ctx.pipe_ctx[i], in dcn20_program_front_end_for_ctx()
2077 &context->res_ctx.pipe_ctx[i]); in dcn20_program_front_end_for_ctx()
2083 struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream; in dcn20_program_front_end_for_ctx()
2085 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dcn20_program_front_end_for_ctx()
2087 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable && stream && in dcn20_program_front_end_for_ctx()
2089 struct timing_generator *tg = dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg; in dcn20_program_front_end_for_ctx()
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| /linux/lib/kunit/ |
| H A D | resource.c | 131 struct kunit_action_ctx *res_ctx = container_of(res, struct kunit_action_ctx, res); in __kunit_action_match() local
138 return (match_ctx->func == res_ctx->func) && (match_ctx->ctx == res_ctx->ctx); in __kunit_action_match()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/ |
| H A D | dce110_hwseq.c | 1083 if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL) in dce110_enable_audio_stream()
1509 struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. in dce110_enable_stream_timing()
1801 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i; in disable_vga_and_power_gate_all_controllers()
1803 &dc->current_state->res_ctx.pipe_ctx[i]); in disable_vga_and_power_gate_all_controllers()
1950 pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, edp_stream); in dce110_enable_accelerated_mode()
2049 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dce110_set_displaymarks()
2078 struct resource_context *res_ctx, in dce110_set_safe_displaymarks() argument
2090 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL) in dce110_set_safe_displaymarks()
2093 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks( in dce110_set_safe_displaymarks()
2094 res_ctx->pipe_ctx[i].plane_res.mi, in dce110_set_safe_displaymarks()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| H A D | dcn315_resource.c | 1637 struct resource_context *res_ctx = &context->res_ctx; in allow_pixel_rate_crb() local
1646 if (!res_ctx->pipe_ctx[i].stream) in allow_pixel_rate_crb()
1650 if (res_ctx->pipe_ctx[i].stream->src.width != res_ctx->pipe_ctx[i].stream->dst.width || in allow_pixel_rate_crb()
1651 res_ctx->pipe_ctx[i].stream->src.height != res_ctx->pipe_ctx[i].stream->dst.height || in allow_pixel_rate_crb()
1652 (res_ctx->pipe_ctx[i].plane_state && (res_ctx->pipe_ctx[i].plane_state->src_rect.width in allow_pixel_rate_crb()
1653 != res_ctx->pipe_ctx[i].plane_state->dst_rect.width || in allow_pixel_rate_crb()
1654 res_ctx->pipe_ctx[i].plane_state->src_rect.height in allow_pixel_rate_crb()
1655 != res_ctx->pipe_ctx[i].plane_state->dst_rect.height))) in allow_pixel_rate_crb()
1658 …if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state != res_ctx->pipe_c… in allow_pixel_rate_crb()
1670 struct resource_context *res_ctx = &context->res_ctx; in dcn315_populate_dml_pipes_from_context() local
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| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| H A D | core_types.h | 174 struct resource_context *res_ctx,
180 struct resource_context *res_ctx,
193 struct resource_context *res_ctx,
200 struct resource_context *res_ctx,
638 struct resource_context res_ctx; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 538 if (!context->res_ctx.pipe_ctx[i].stream) in dcn31_calculate_wm_and_dlg_fp()
541 if (context->res_ctx.pipe_ctx[i].plane_state) in dcn31_calculate_wm_and_dlg_fp()
573 if (context->res_ctx.pipe_ctx[i].stream) in dcn31_calculate_wm_and_dlg_fp()
574 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 0; in dcn31_calculate_wm_and_dlg_fp()
577 if (!context->res_ctx.pipe_ctx[i].stream) in dcn31_calculate_wm_and_dlg_fp()
580 context->res_ctx.pipe_ctx[i].det_buffer_size_kb = in dcn31_calculate_wm_and_dlg_fp()
582 if (context->res_ctx.pipe_ctx[i].det_buffer_size_kb > 384) in dcn31_calculate_wm_and_dlg_fp()
583 context->res_ctx.pipe_ctx[i].det_buffer_size_kb /= 2; in dcn31_calculate_wm_and_dlg_fp()
584 total_det += context->res_ctx.pipe_ctx[i].det_buffer_size_kb; in dcn31_calculate_wm_and_dlg_fp()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn351/ |
| H A D | dcn351_fpu.c | 476 struct resource_context *res_ctx = &context->res_ctx; in dcn351_populate_dml_pipes_from_context_fpu() local
491 if (!res_ctx->pipe_ctx[i].stream) in dcn351_populate_dml_pipes_from_context_fpu()
494 pipe = &res_ctx->pipe_ctx[i]; in dcn351_populate_dml_pipes_from_context_fpu()
590 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn351_populate_dml_pipes_from_context_fpu()
617 if (context->res_ctx.pipe_ctx[i].plane_state) in dcn351_decide_zstate_support()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
| H A D | dcn35_fpu.c | 443 struct resource_context *res_ctx = &context->res_ctx; in dcn35_populate_dml_pipes_from_context_fpu() local
458 if (!res_ctx->pipe_ctx[i].stream) in dcn35_populate_dml_pipes_from_context_fpu()
461 pipe = &res_ctx->pipe_ctx[i]; in dcn35_populate_dml_pipes_from_context_fpu()
557 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn35_populate_dml_pipes_from_context_fpu()
587 if (context->res_ctx.pipe_ctx[i].plane_state) in dcn35_decide_zstate_support()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 275 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn32_update_clocks_update_dtb_dto()
323 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; in dcn32_update_clocks_update_dpp_dto()
325 if (context->res_ctx.pipe_ctx[i].plane_res.dpp) in dcn32_update_clocks_update_dpp_dto()
326 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst; in dcn32_update_clocks_update_dpp_dto()
327 else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) { in dcn32_update_clocks_update_dpp_dto()
332 } else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) { in dcn32_update_clocks_update_dpp_dto()
372 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn32_update_clocks_update_dentist()
426 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn32_update_clocks_update_dentist()
518 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn32_auto_dpm_test_log()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce110/ |
| H A D | dce110_resource.c | 950 struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream); in build_mapped_resource()
983 context->res_ctx.pipe_ctx, in dce110_validate_bandwidth()
1135 struct resource_context *res_ctx = &new_ctx->res_ctx; in dce110_acquire_underlay() local
1137 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx]; in dce110_acquire_underlay()
1139 if (res_ctx->pipe_ctx[underlay_idx].stream) in dce110_acquire_underlay()
1151 if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) { in dce110_acquire_underlay()
1206 struct resource_context *res_ctx, in dce110_find_first_free_match_stream_enc_for_link() argument
1215 if (!res_ctx->is_stream_enc_acquired[i] && in dce110_find_first_free_match_stream_enc_for_link()
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| H A D | dce110_resource.h | 49 struct resource_context *res_ctx,
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