| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_resource.c | 564 struct resource_context *res_ctx, in resource_unreference_clock_source() argument
571 res_ctx->clock_source_ref_count[i]--; in resource_unreference_clock_source()
574 res_ctx->dp_clock_source_ref_count--; in resource_unreference_clock_source()
578 struct resource_context *res_ctx, in resource_reference_clock_source() argument
585 res_ctx->clock_source_ref_count[i]++; in resource_reference_clock_source()
588 res_ctx->dp_clock_source_ref_count++; in resource_reference_clock_source()
592 struct resource_context *res_ctx, in resource_get_clock_source_reference() argument
599 return res_ctx->clock_source_ref_count[i]; in resource_get_clock_source_reference()
602 return res_ctx->dp_clock_source_ref_count; in resource_get_clock_source_reference()
739 struct resource_context *res_ctx, in resource_find_used_clk_src_for_sharing() argument
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| H A D | dc_stream.c | 267 struct resource_context *res_ctx; in program_cursor_attributes() local
274 res_ctx = &dc->current_state->res_ctx; in program_cursor_attributes()
277 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; in program_cursor_attributes()
414 struct resource_context *res_ctx; in program_cursor_position() local
421 res_ctx = &dc->current_state->res_ctx; in program_cursor_position()
424 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; in program_cursor_position()
514 struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_program_cursor_position()
533 struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_program_cursor_position()
722 struct resource_context *res_ctx = in dc_stream_get_vblank_counter() local
723 &dc->current_state->res_ctx; in dc_stream_get_vblank_counter()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | dml2_dc_resource_mgmt.c | 114 …if (state->res_ctx.pipe_ctx[i].stream && state->res_ctx.pipe_ctx[i].stream->stream_id == stream_id… in find_master_pipe_of_stream()
115 if (!state->res_ctx.pipe_ctx[i].prev_odm_pipe && !state->res_ctx.pipe_ctx[i].top_pipe) in find_master_pipe_of_stream()
116 return &state->res_ctx.pipe_ctx[i]; in find_master_pipe_of_stream()
130 …if (state->res_ctx.pipe_ctx[i].plane_state && get_plane_id(ctx, state, state->res_ctx.pipe_ctx[i].… in find_master_pipe_of_plane()
131 state->res_ctx.pipe_ctx[i].stream->stream_id, in find_master_pipe_of_plane()
132 …ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[state->res_ctx.pipe_ctx[i].pip… in find_master_pipe_of_plane()
134 return &state->res_ctx.pipe_ctx[i]; in find_master_pipe_of_plane()
149 struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i]; in find_pipes_assigned_to_plane()
271 …if (existing_state->res_ctx.pipe_ctx[i].stream && existing_state->res_ctx.pipe_ctx[i].stream->stre… in find_preferred_pipe_candidates()
273 resource_is_pipe_type(&existing_state->res_ctx.pipe_ctx[i], DPP_PIPE) ? in find_preferred_pipe_candidates()
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| H A D | dml2_utils.c | 174 if (!context->res_ctx.pipe_ctx[i].stream) in is_dtbclk_required()
176 if (is_dp2p0_output_encoder(&context->res_ctx.pipe_ctx[i])) in is_dtbclk_required()
300 if (!context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream) in dml2_calculate_rq_and_dlg_params()
306 if (get_plane_id(in_ctx, context, context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_state, in dml2_calculate_rq_and_dlg_params()
307 context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream->stream_id, in dml2_calculate_rq_and_dlg_params()
308 …in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[context->res_ctx.pipe_ctx[d… in dml2_calculate_rq_and_dlg_params()
311 …dml_pipe_idx = dml2_helper_find_dml_pipe_idx_by_stream_id(in_ctx, context->res_ctx.pipe_ctx[dc_pip… in dml2_calculate_rq_and_dlg_params()
317 …l_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[dml_pipe_idx] == context->res_ctx.pipe_ctx[dc_pipe_… in dml2_calculate_rq_and_dlg_params()
322 …populate_pipe_ctx_dlg_params_from_dml(&context->res_ctx.pipe_ctx[dc_pipe_ctx_index], &context->bw_… in dml2_calculate_rq_and_dlg_params()
324 …pipe_mall_type = dc_state_get_pipe_subvp_type(context, &context->res_ctx.pipe_ctx[dc_pipe_ctx_inde… in dml2_calculate_rq_and_dlg_params()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 990 struct resource_context *res_ctx, in dcn20_populate_dml_writeback_from_context() argument
998 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0]; in dcn20_populate_dml_writeback_from_context()
1000 if (!res_ctx->pipe_ctx[i].stream) in dcn20_populate_dml_writeback_from_context()
1042 …wb_arb_params->time_per_pixel = 16.0 * 1000 / (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk / … in dcn20_fpu_set_wb_arb_params()
1049 if (!context->res_ctx.pipe_ctx[i].stream) in is_dtbclk_required()
1051 if (dc->link_srv->dp_is_128b_132b_signal(&context->res_ctx.pipe_ctx[i])) in is_dtbclk_required()
1064 if (context->res_ctx.pipe_ctx[i].plane_state) in decide_zstate_support()
1180 if (!context->res_ctx.pipe_ctx[i].stream) in dcn20_calculate_dlg_params()
1182 if (context->res_ctx.pipe_ctx[i].plane_state) in dcn20_calculate_dlg_params()
1189 if (dc_state_get_pipe_subvp_type(context, &context->res_ctx.pipe_ctx[i]) == SUBVP_PHANTOM) { in dcn20_calculate_dlg_params()
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| H A D | dcn20_fpu.h | 32 struct resource_context *res_ctx,
86 struct resource_context *res_ctx,
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| H A D | dcn20_resource.c | 1350 struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream); in dcn20_build_mapped_resource()
1363 struct resource_context *res_ctx, in dcn20_acquire_dsc() argument
1369 …struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_r… in dcn20_acquire_dsc()
1377 res_ctx->is_dsc_acquired[pipe_idx] = true; in dcn20_acquire_dsc()
1382 if (dsc_old && !res_ctx->is_dsc_acquired[dsc_old->inst]) { in dcn20_acquire_dsc()
1384 res_ctx->is_dsc_acquired[dsc_old->inst] = true; in dcn20_acquire_dsc()
1390 if (!res_ctx->is_dsc_acquired[i]) { in dcn20_acquire_dsc()
1392 res_ctx->is_dsc_acquired[i] = true; in dcn20_acquire_dsc()
1397 void dcn20_release_dsc(struct resource_context *res_ctx, in dcn20_release_dsc() argument
1405 res_ctx->is_dsc_acquired[i] = false; in dcn20_release_dsc()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 343 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_helper_populate_phantom_dlg_params()
488 pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_set_phantom_stream_timing()
565 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_get_num_free_pipes()
610 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_assign_subvp_pipe()
644 pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_assign_subvp_pipe()
687 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_enough_pipes_for_subvp()
737 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in subvp_subvp_schedulable()
819 pipe = &context->res_ctx.pipe_ctx[i]; in subvp_drr_schedulable()
836 drr_pipe = &context->res_ctx.pipe_ctx[i]; in subvp_drr_schedulable()
925 pipe = &context->res_ctx.pipe_ctx[i]; in subvp_vblank_schedulable()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/ |
| H A D | dml21_utils.c | 119 …num_pipes = dml_ctx->config.callbacks.get_dpp_pipes_for_plane(dc_main_plane, &context->res_ctx, dc… in dml21_find_dc_pipes_for_plane()
122 …ster_pipe = dml_ctx->config.callbacks.get_otg_master_for_stream(&context->res_ctx, dc_main_stream); in dml21_find_dc_pipes_for_plane()
124 …->config.callbacks.get_opp_heads_for_otg_master(otg_master_pipe, &context->res_ctx, dc_main_pipes); in dml21_find_dc_pipes_for_plane()
138 …dml_ctx->config.callbacks.get_dpp_pipes_for_plane(dc_phantom_plane, &context->res_ctx, dc_phantom_… in dml21_find_dc_pipes_for_plane()
202 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in is_sub_vp_enabled()
435 if (context->res_ctx.pipe_ctx[dc_pipe_idx].stream && in dml21_build_fams2_stream_programming_v2()
436 context->res_ctx.pipe_ctx[dc_pipe_idx].stream->stream_id == stream->stream_id && in dml21_build_fams2_stream_programming_v2()
437 …context->res_ctx.pipe_ctx[dc_pipe_idx].plane_state == context->stream_status[dc_stream_idx].plane_… in dml21_build_fams2_stream_programming_v2()
474 if (context->res_ctx.pipe_ctx[dc_pipe_idx].stream && in dml21_build_fams2_stream_programming_v2()
475 context->res_ctx.pipe_ctx[dc_pipe_idx].stream->stream_id == phantom_stream->stream_id && in dml21_build_fams2_stream_programming_v2()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 629 *opp_cnt = resource_get_opp_heads_for_otg_master(pipe_ctx, &context->res_ctx, opp_heads); in enable_stream_timing_calc()
924 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; in disable_link_output_symclk_on_tx_off()
1170 struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[i]; in dcn401_calculate_cab_allocation()
1385 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn401_optimize_bandwidth()
1456 old_otg_master = &dc->current_state->res_ctx.pipe_ctx[otg_master->pipe_idx]; in update_dsc_for_odm_change()
1460 &dc->current_state->res_ctx, in update_dsc_for_odm_change()
1477 new_pipe = &context->res_ctx.pipe_ctx[old_pipe->pipe_idx]; in update_dsc_for_odm_change()
1496 otg_master, &context->res_ctx, opp_heads); in dcn401_update_odm()
1540 old_otg_master = &dc->current_state->res_ctx.pipe_ctx[otg_master->pipe_idx]; in dcn401_add_dsc_sequence_for_odm_change()
1544 &dc->current_state->res_ctx, in dcn401_add_dsc_sequence_for_odm_change()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 1359 struct resource_context *res_ctx = &context->res_ctx; in dcn30_populate_dml_pipes_from_context() local
1366 if (!res_ctx->pipe_ctx[i].stream) in dcn30_populate_dml_pipes_from_context()
1377 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) in dcn30_populate_dml_writeback_from_context() argument
1380 dcn30_fpu_populate_dml_writeback_from_context(dc, res_ctx, pipes); in dcn30_populate_dml_writeback_from_context()
1422 if (!context->res_ctx.pipe_ctx[i].stream) in dcn30_set_mcif_arb_params()
1426 …struct dc_writeback_info *writeback_info = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j]; in dcn30_set_mcif_arb_params()
1443 …wb_arb_params->time_per_pixel = (1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk;… in dcn30_set_mcif_arb_params()
1463 struct resource_context *res_ctx, in dcn30_acquire_post_bldn_3dlut() argument
1478 if (!res_ctx->is_mpc_3dlut_acquired[i]) { in dcn30_acquire_post_bldn_3dlut()
1482 res_ctx->is_mpc_3dlut_acquired[i] = true; in dcn30_acquire_post_bldn_3dlut()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.c | 1636 struct resource_context *res_ctx, in dcn32_acquire_post_bldn_3dlut() argument
1648 if (!res_ctx->is_mpc_3dlut_acquired[mpcc_id]) { in dcn32_acquire_post_bldn_3dlut()
1651 res_ctx->is_mpc_3dlut_acquired[mpcc_id] = true; in dcn32_acquire_post_bldn_3dlut()
1658 struct resource_context *res_ctx, in dcn32_release_post_bldn_3dlut() argument
1668 res_ctx->is_mpc_3dlut_acquired[i] = false; in dcn32_release_post_bldn_3dlut()
1686 struct pipe_ctx *curr_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; in dcn32_enable_phantom_plane()
1731 struct pipe_ctx *ref_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; in dcn32_enable_phantom_stream()
1770 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_add_phantom_pipes()
1912 struct resource_context *res_ctx = &context->res_ctx; in dcn32_populate_dml_pipes_from_context() local
1945 pipe = &res_ctx->pipe_ctx[i]; in dcn32_populate_dml_pipes_from_context()
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| /linux/lib/kunit/ |
| H A D | resource.c | 131 struct kunit_action_ctx *res_ctx = container_of(res, struct kunit_action_ctx, res); in __kunit_action_match() local
138 return (match_ctx->func == res_ctx->func) && (match_ctx->ctx == res_ctx->ctx); in __kunit_action_match()
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| H A D | kunit-test.c | 509 struct kunit_test_resource_context *res_ctx = (struct kunit_test_resource_context *)ctx; in action_order_1() local
511 KUNIT_RESOURCE_TEST_MARK_ORDER(res_ctx, free_order, 1); in action_order_1()
516 struct kunit_test_resource_context *res_ctx = (struct kunit_test_resource_context *)ctx; in action_order_2() local
518 KUNIT_RESOURCE_TEST_MARK_ORDER(res_ctx, free_order, 2); in action_order_2()
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dmub_psr.c | 302 struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx; in dmub_psr_copy_settings() local
306 if (res_ctx->pipe_ctx[i].stream && in dmub_psr_copy_settings()
307 res_ctx->pipe_ctx[i].stream->link == link && in dmub_psr_copy_settings()
308 res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) { in dmub_psr_copy_settings()
309 pipe_ctx = &res_ctx->pipe_ctx[i]; in dmub_psr_copy_settings()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| H A D | dcn315_resource.c | 1670 struct resource_context *res_ctx = &context->res_ctx; in allow_pixel_rate_crb() local
1679 if (!res_ctx->pipe_ctx[i].stream) in allow_pixel_rate_crb()
1683 if (res_ctx->pipe_ctx[i].stream->src.width != res_ctx->pipe_ctx[i].stream->dst.width || in allow_pixel_rate_crb()
1684 res_ctx->pipe_ctx[i].stream->src.height != res_ctx->pipe_ctx[i].stream->dst.height || in allow_pixel_rate_crb()
1685 (res_ctx->pipe_ctx[i].plane_state && (res_ctx->pipe_ctx[i].plane_state->src_rect.width in allow_pixel_rate_crb()
1686 != res_ctx->pipe_ctx[i].plane_state->dst_rect.width || in allow_pixel_rate_crb()
1687 res_ctx->pipe_ctx[i].plane_state->src_rect.height in allow_pixel_rate_crb()
1688 != res_ctx->pipe_ctx[i].plane_state->dst_rect.height))) in allow_pixel_rate_crb()
1691 …if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state != res_ctx->pipe_c… in allow_pixel_rate_crb()
1703 struct resource_context *res_ctx = &context->res_ctx; in dcn315_populate_dml_pipes_from_context() local
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/ |
| H A D | dce110_hwseq.c | 1147 if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL) in dce110_enable_audio_stream()
1577 struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. in dce110_enable_stream_timing()
1869 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i; in disable_vga_and_power_gate_all_controllers()
1871 &dc->current_state->res_ctx.pipe_ctx[i]); in disable_vga_and_power_gate_all_controllers()
2046 pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, edp_stream); in dce110_enable_accelerated_mode()
2146 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dce110_set_displaymarks()
2175 struct resource_context *res_ctx, in dce110_set_safe_displaymarks() argument
2187 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL) in dce110_set_safe_displaymarks()
2190 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks( in dce110_set_safe_displaymarks()
2191 res_ctx->pipe_ctx[i].plane_res.mi, in dce110_set_safe_displaymarks()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 538 if (!context->res_ctx.pipe_ctx[i].stream) in dcn31_calculate_wm_and_dlg_fp()
541 if (context->res_ctx.pipe_ctx[i].plane_state) in dcn31_calculate_wm_and_dlg_fp()
573 if (context->res_ctx.pipe_ctx[i].stream) in dcn31_calculate_wm_and_dlg_fp()
574 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 0; in dcn31_calculate_wm_and_dlg_fp()
577 if (!context->res_ctx.pipe_ctx[i].stream) in dcn31_calculate_wm_and_dlg_fp()
580 context->res_ctx.pipe_ctx[i].det_buffer_size_kb = in dcn31_calculate_wm_and_dlg_fp()
582 if (context->res_ctx.pipe_ctx[i].det_buffer_size_kb > 384) in dcn31_calculate_wm_and_dlg_fp()
583 context->res_ctx.pipe_ctx[i].det_buffer_size_kb /= 2; in dcn31_calculate_wm_and_dlg_fp()
584 total_det += context->res_ctx.pipe_ctx[i].det_buffer_size_kb; in dcn31_calculate_wm_and_dlg_fp()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce110/ |
| H A D | dce110_resource.c | 952 struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream); in build_mapped_resource()
986 context->res_ctx.pipe_ctx, in dce110_validate_bandwidth()
1141 struct resource_context *res_ctx = &new_ctx->res_ctx; in dce110_acquire_underlay() local
1143 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx]; in dce110_acquire_underlay()
1145 if (res_ctx->pipe_ctx[underlay_idx].stream) in dce110_acquire_underlay()
1157 if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) { in dce110_acquire_underlay()
1212 struct resource_context *res_ctx, in dce110_find_first_free_match_stream_enc_for_link() argument
1221 if (!res_ctx->is_stream_enc_acquired[i] && in dce110_find_first_free_match_stream_enc_for_link()
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| H A D | dce110_resource.h | 49 struct resource_context *res_ctx,
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce112/ |
| H A D | dce112_resource.c | 852 struct resource_context *res_ctx, in find_matching_pll() argument
856 (void)res_ctx; in find_matching_pll()
881 struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream); in build_mapped_resource()
909 context->res_ctx.pipe_ctx, in dce112_validate_bandwidth()
974 &context->res_ctx, stream); in resource_map_phy_clock_resources()
986 &context->res_ctx, dc->res_pool, in resource_map_phy_clock_resources()
994 &context->res_ctx, in resource_map_phy_clock_resources()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| H A D | dcn201_resource.c | 1039 struct resource_context *res_ctx = &new_ctx->res_ctx; in dcn201_acquire_free_pipe_for_layer() local
1040 struct pipe_ctx *head_pipe = resource_get_otg_master_for_stream(res_ctx, opp_head_pipe->stream); in dcn201_acquire_free_pipe_for_layer()
1041 struct pipe_ctx *idle_pipe = resource_find_free_secondary_pipe_legacy(res_ctx, pool, head_pipe); in dcn201_acquire_free_pipe_for_layer()
1074 struct resource_context *res_ctx, in dcn201_populate_dml_writeback_from_context() argument
1078 dcn201_populate_dml_writeback_from_context_fpu(dc, res_ctx, pipes); in dcn201_populate_dml_writeback_from_context()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/ |
| H A D | dcn42_clk_mgr.c | 178 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; in dcn42_update_clocks_update_dpp_dto()
180 if (context->res_ctx.pipe_ctx[i].plane_res.dpp) in dcn42_update_clocks_update_dpp_dto()
181 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst; in dcn42_update_clocks_update_dpp_dto()
182 else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) { in dcn42_update_clocks_update_dpp_dto()
187 } else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) { in dcn42_update_clocks_update_dpp_dto()
204 struct dpp *old_dpp = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.dpp; in dcn42_update_clocks_update_dpp_dto()
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| /linux/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_resource.c | 41 pipe = &link->dc->current_state->res_ctx.pipe_ctx[i]; in link_get_cur_link_res()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| H A D | dcn10_resource.c | 1087 struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream); in build_mapped_resource()
1122 struct resource_context *res_ctx = &new_ctx->res_ctx; in dcn10_acquire_free_pipe_for_layer() local
1123 struct pipe_ctx *head_pipe = resource_get_otg_master_for_stream(res_ctx, opp_head_pipe->stream); in dcn10_acquire_free_pipe_for_layer()
1124 struct pipe_ctx *idle_pipe = resource_find_free_secondary_pipe_legacy(res_ctx, pool, head_pipe); in dcn10_acquire_free_pipe_for_layer()
1265 struct resource_context *res_ctx, in dcn10_find_first_free_match_stream_enc_for_link() argument
1274 if (!res_ctx->is_stream_enc_acquired[i] && in dcn10_find_first_free_match_stream_enc_for_link()
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