| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_resource.c | 598 struct resource_context *res_ctx, in resource_unreference_clock_source() argument
605 res_ctx->clock_source_ref_count[i]--; in resource_unreference_clock_source()
608 res_ctx->dp_clock_source_ref_count--; in resource_unreference_clock_source()
612 struct resource_context *res_ctx, in resource_reference_clock_source() argument
619 res_ctx->clock_source_ref_count[i]++; in resource_reference_clock_source()
622 res_ctx->dp_clock_source_ref_count++; in resource_reference_clock_source()
626 struct resource_context *res_ctx, in resource_get_clock_source_reference() argument
633 return res_ctx->clock_source_ref_count[i]; in resource_get_clock_source_reference()
636 return res_ctx->dp_clock_source_ref_count; in resource_get_clock_source_reference()
773 struct resource_context *res_ctx, in resource_find_used_clk_src_for_sharing() argument
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| H A D | dc.c | 434 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in set_long_vtotal()
471 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_get_last_used_drr_vtotal()
537 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_forward_crc_window()
603 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_forward_multiple_crc_window()
653 &dc->current_state->res_ctx, stream); in dc_stream_configure_crc()
728 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_get_crc()
754 if (dc->current_state->res_ctx.pipe_ctx[i].stream in dc_stream_set_dyn_expansion()
756 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_set_dyn_expansion()
772 struct resource_context *res_ctx = &link->dc->current_state->res_ctx; in dc_stream_set_dither_option() local
778 otg_master = resource_get_otg_master_for_stream(res_ctx, stream); in dc_stream_set_dither_option()
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| H A D | dc_surface.c | 74 struct pipe_ctx *pipe_ctx = &dc_state->res_ctx.pipe_ctx[i]; in dc_plane_get_pipe_mask()
135 &dc->current_state->res_ctx.pipe_ctx[i]; in dc_plane_get_status()
153 &dc->current_state->res_ctx.pipe_ctx[i]; in dc_plane_get_status()
332 struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_plane_force_dcc_and_tiling_disable()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | dml2_dc_resource_mgmt.c | 114 …if (state->res_ctx.pipe_ctx[i].stream && state->res_ctx.pipe_ctx[i].stream->stream_id == stream_id… in find_master_pipe_of_stream()
115 if (!state->res_ctx.pipe_ctx[i].prev_odm_pipe && !state->res_ctx.pipe_ctx[i].top_pipe) in find_master_pipe_of_stream()
116 return &state->res_ctx.pipe_ctx[i]; in find_master_pipe_of_stream()
130 …if (state->res_ctx.pipe_ctx[i].plane_state && get_plane_id(ctx, state, state->res_ctx.pipe_ctx[i].… in find_master_pipe_of_plane()
131 state->res_ctx.pipe_ctx[i].stream->stream_id, in find_master_pipe_of_plane()
132 …ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[state->res_ctx.pipe_ctx[i].pip… in find_master_pipe_of_plane()
134 return &state->res_ctx.pipe_ctx[i]; in find_master_pipe_of_plane()
149 struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i]; in find_pipes_assigned_to_plane()
271 …if (existing_state->res_ctx.pipe_ctx[i].stream && existing_state->res_ctx.pipe_ctx[i].stream->stre… in find_preferred_pipe_candidates()
273 resource_is_pipe_type(&existing_state->res_ctx.pipe_ctx[i], DPP_PIPE) ? in find_preferred_pipe_candidates()
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| H A D | dml2_wrapper_fpu.c | 182 struct pipe_ctx *pipe = &display_state->res_ctx.pipe_ctx[i]; in calculate_lowest_supported_state_for_temp_read()
290 struct pipe_ctx *pipe = &display_state->res_ctx.pipe_ctx[i]; in dml_mode_support_wrapper()
484 …dml2_calculate_rq_and_dlg_params(in_dc, context, &context->res_ctx, dml2, in_dc->res_pool->pipe_co… in dml2_validate_and_build_resource()
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| H A D | dml2_translation_helper.c | 994 struct pipe_ctx *temp_pipe = &context->res_ctx.temp_pipe; in get_scaler_data_for_plane()
999 const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in get_scaler_data_for_plane()
1219 struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i]; in dml2_populate_pipe_to_plane_index_mapping()
1293 current_pipe_context = &context->res_ctx.pipe_ctx[i]; in dml2_map_hpo_stream_encoder_to_hpo_link_encoder_index()
1334 if (context->streams[i] == context->res_ctx.pipe_ctx[k].stream) { in map_dc_state_into_dml_display_cfg()
1335 current_pipe_context = &context->res_ctx.pipe_ctx[k]; in map_dc_state_into_dml_display_cfg()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 1485 struct resource_context *res_ctx = &context->res_ctx; in dcn30_populate_dml_pipes_from_context() local
1492 if (!res_ctx->pipe_ctx[i].stream) in dcn30_populate_dml_pipes_from_context()
1503 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) in dcn30_populate_dml_writeback_from_context() argument
1506 dcn30_fpu_populate_dml_writeback_from_context(dc, res_ctx, pipes); in dcn30_populate_dml_writeback_from_context()
1549 if (!context->res_ctx.pipe_ctx[i].stream) in dcn30_set_mcif_arb_params()
1553 …struct dc_writeback_info *writeback_info = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j]; in dcn30_set_mcif_arb_params()
1570 …wb_arb_params->time_per_pixel = (1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk;… in dcn30_set_mcif_arb_params()
1590 struct resource_context *res_ctx, in dcn30_acquire_post_bldn_3dlut() argument
1605 if (!res_ctx->is_mpc_3dlut_acquired[i]) { in dcn30_acquire_post_bldn_3dlut()
1609 res_ctx->is_mpc_3dlut_acquired[i] = true; in dcn30_acquire_post_bldn_3dlut()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.c | 1766 struct resource_context *res_ctx, in dcn32_acquire_post_bldn_3dlut() argument
1778 if (!res_ctx->is_mpc_3dlut_acquired[mpcc_id]) { in dcn32_acquire_post_bldn_3dlut()
1781 res_ctx->is_mpc_3dlut_acquired[mpcc_id] = true; in dcn32_acquire_post_bldn_3dlut()
1788 struct resource_context *res_ctx, in dcn32_release_post_bldn_3dlut() argument
1798 res_ctx->is_mpc_3dlut_acquired[i] = false; in dcn32_release_post_bldn_3dlut()
1816 struct pipe_ctx *curr_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; in dcn32_enable_phantom_plane()
1861 struct pipe_ctx *ref_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; in dcn32_enable_phantom_stream()
1900 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_add_phantom_pipes()
2043 struct resource_context *res_ctx = &context->res_ctx; in dcn32_populate_dml_pipes_from_context() local
2076 pipe = &res_ctx->pipe_ctx[i]; in dcn32_populate_dml_pipes_from_context()
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| /linux/lib/kunit/ |
| H A D | resource.c | 131 struct kunit_action_ctx *res_ctx = container_of(res, struct kunit_action_ctx, res); in __kunit_action_match() local
138 return (match_ctx->func == res_ctx->func) && (match_ctx->ctx == res_ctx->ctx); in __kunit_action_match()
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| H A D | kunit-test.c | 509 struct kunit_test_resource_context *res_ctx = (struct kunit_test_resource_context *)ctx; in action_order_1() local
511 KUNIT_RESOURCE_TEST_MARK_ORDER(res_ctx, free_order, 1); in action_order_1()
516 struct kunit_test_resource_context *res_ctx = (struct kunit_test_resource_context *)ctx; in action_order_2() local
518 KUNIT_RESOURCE_TEST_MARK_ORDER(res_ctx, free_order, 2); in action_order_2()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.h | 32 struct resource_context *res_ctx,
86 struct resource_context *res_ctx,
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| H A D | dcn315_resource.c | 1799 struct resource_context *res_ctx = &context->res_ctx; in allow_pixel_rate_crb() local
1808 if (!res_ctx->pipe_ctx[i].stream) in allow_pixel_rate_crb()
1812 if (res_ctx->pipe_ctx[i].stream->src.width != res_ctx->pipe_ctx[i].stream->dst.width || in allow_pixel_rate_crb()
1813 res_ctx->pipe_ctx[i].stream->src.height != res_ctx->pipe_ctx[i].stream->dst.height || in allow_pixel_rate_crb()
1814 (res_ctx->pipe_ctx[i].plane_state && (res_ctx->pipe_ctx[i].plane_state->src_rect.width in allow_pixel_rate_crb()
1815 != res_ctx->pipe_ctx[i].plane_state->dst_rect.width || in allow_pixel_rate_crb()
1816 res_ctx->pipe_ctx[i].plane_state->src_rect.height in allow_pixel_rate_crb()
1817 != res_ctx->pipe_ctx[i].plane_state->dst_rect.height))) in allow_pixel_rate_crb()
1820 …if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state != res_ctx->pipe_c… in allow_pixel_rate_crb()
1833 struct resource_context *res_ctx = &context->res_ctx; in dcn315_populate_dml_pipes_from_context() local
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce110/ |
| H A D | dce110_resource.h | 49 struct resource_context *res_ctx,
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.c | 199 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dcn35_disable_otg_wa()
200 struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i]; in dcn35_disable_otg_wa()
204 ? &context->res_ctx.pipe_ctx[i] in dcn35_disable_otg_wa()
205 : &dc->current_state->res_ctx.pipe_ctx[i]; in dcn35_disable_otg_wa()
265 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn35_update_clocks_update_dtb_dto()
305 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; in dcn35_update_clocks_update_dpp_dto()
307 if (context->res_ctx.pipe_ctx[i].plane_res.dpp) in dcn35_update_clocks_update_dpp_dto()
308 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst; in dcn35_update_clocks_update_dpp_dto()
309 else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) { in dcn35_update_clocks_update_dpp_dto()
314 } else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) { in dcn35_update_clocks_update_dpp_dto()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn60/ |
| H A D | dcn60_hwseq.c | 346 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn60_setup_audio_dto()
397 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn60_setup_audio_dto()
479 &dc->current_state->res_ctx.pipe_ctx[i]; in dcn60_apply_ctx_to_hw()
480 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn60_apply_ctx_to_hw()
505 &dc->current_state->res_ctx.pipe_ctx[i]; in dcn60_apply_ctx_to_hw()
506 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn60_apply_ctx_to_hw()
855 otg_pipe = resource_get_otg_master_for_stream(&context->res_ctx, in dcn60_get_ref_tg_for_hubbub_probe()
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| /linux/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_resource.c | 41 pipe = &link->dc->current_state->res_ctx.pipe_ctx[i]; in link_get_cur_link_res()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/ |
| H A D | dcn60_clk_mgr.c | 191 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; in dcn60_update_clocks_update_dpp_dto()
193 if (context->res_ctx.pipe_ctx[i].plane_res.dpp) in dcn60_update_clocks_update_dpp_dto()
194 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst; in dcn60_update_clocks_update_dpp_dto()
195 else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) { in dcn60_update_clocks_update_dpp_dto()
200 } else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) { in dcn60_update_clocks_update_dpp_dto()
253 &context->res_ctx, context->streams[i]); in dcn60_update_clocks_update_dtb_dto()
332 &context->res_ctx, context->streams[i]); in dcn60_build_update_display_clocks_sequence()
840 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn60_auto_dpm_test_log()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce100/ |
| H A D | dce100_resource.c | 854 struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream); in build_mapped_resource()
878 stream = context->res_ctx.pipe_ctx[i].stream; in dce100_validate_bandwidth()
977 struct resource_context *res_ctx, in dce100_find_first_free_match_stream_enc_for_link() argument
993 if (!res_ctx->is_stream_enc_acquired[i] && in dce100_find_first_free_match_stream_enc_for_link()
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_debugfs.c | 1298 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i]; in odm_combine_segments_show()
1579 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; in dp_dsc_clock_en_read()
1681 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; in dp_dsc_clock_en_write()
1765 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; in dp_dsc_slice_width_read()
1865 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; in dp_dsc_slice_width_write()
1949 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; in dp_dsc_slice_height_read()
2049 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; in dp_dsc_slice_height_write()
2129 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; in dp_dsc_bits_per_pixel_read()
2226 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; in dp_dsc_bits_per_pixel_write()
2304 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; in dp_dsc_pic_width_read()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| H A D | dcn31_resource.c | 1807 struct resource_context *res_ctx = &context->res_ctx; in dcn31_populate_dml_pipes_from_context() local
1818 if (!res_ctx->pipe_ctx[i].stream) in dcn31_populate_dml_pipes_from_context()
1820 pipe = &res_ctx->pipe_ctx[i]; in dcn31_populate_dml_pipes_from_context()
1899 struct resource_context *res_ctx, in dcn31_populate_dml_writeback_from_context() argument
1903 dcn30_populate_dml_writeback_from_context(dc, res_ctx, pipes); in dcn31_populate_dml_writeback_from_context()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| H A D | dcn316_resource.c | 1776 struct resource_context *res_ctx = &context->res_ctx; in dcn316_populate_dml_pipes_from_context() local
1787 if (!res_ctx->pipe_ctx[i].stream) in dcn316_populate_dml_pipes_from_context()
1789 pipe = &res_ctx->pipe_ctx[i]; in dcn316_populate_dml_pipes_from_context()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_clk_mgr.c | 159 ? &context->res_ctx.pipe_ctx[i] in dcn314_disable_otg_wa()
160 : &dc->current_state->res_ctx.pipe_ctx[i]; in dcn314_disable_otg_wa()
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| /linux/drivers/gpu/drm/amd/display/dc/pg/dcn42/ |
| H A D | dcn42_pg_cntl.c | 523 struct pipe_ctx *pipe_ctx = &pg_cntl->ctx->dc->current_state->res_ctx.pipe_ctx[i]; in pg_cntl42_plane_otg_pg_control()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
| H A D | dcn30_hwseq.c | 615 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i_pipe]; in dcn30_program_all_writeback_pipes_in_tree()
1218 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dcn30_hardware_release()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| H A D | dcn31_clk_mgr.c | 123 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dcn31_disable_otg_wa()
|