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Searched refs:regs_base (Results 1 – 20 of 20) sorted by relevance

/linux/drivers/spi/
H A Dspi-stm32-ospi.c126 void __iomem *regs_base; member
157 void __iomem *regs_base = ospi->regs_base; in stm32_ospi_abort() local
161 cr = readl_relaxed(regs_base + OSPI_CR) | CR_ABORT; in stm32_ospi_abort()
162 writel_relaxed(cr, regs_base + OSPI_CR); in stm32_ospi_abort()
165 timeout = readl_relaxed_poll_timeout_atomic(regs_base + OSPI_CR, in stm32_ospi_abort()
177 void __iomem *regs_base = ospi->regs_base; in stm32_ospi_poll() local
188 ret = readl_relaxed_poll_timeout_atomic(regs_base + OSPI_SR, in stm32_ospi_poll()
196 fifo(buf++, regs_base + OSPI_DR); in stm32_ospi_poll()
206 return readl_relaxed_poll_timeout_atomic(ospi->regs_base + OSPI_SR, in stm32_ospi_wait_nobusy()
213 void __iomem *regs_base = ospi->regs_base; in stm32_ospi_wait_cmd() local
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H A Dspi-xilinx.c165 void __iomem *regs_base = xspi->regs; in xspi_init_hw() local
169 regs_base + XIPIF_V123B_RESETR_OFFSET); in xspi_init_hw()
174 regs_base + XIPIF_V123B_IIER_OFFSET); in xspi_init_hw()
176 xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET); in xspi_init_hw()
178 xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET); in xspi_init_hw()
183 regs_base + XSPI_CR_OFFSET); in xspi_init_hw()
511 void __iomem *regs_base = xspi->regs; in xilinx_spi_remove() local
516 xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET); in xilinx_spi_remove()
518 xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET); in xilinx_spi_remove()
/linux/drivers/phy/samsung/
H A Dphy-exynos5-usbdrd.c676 void __iomem *regs_base = phy_drd->reg_phy; in exynos5_usbdrd_usbdp_g2_v4_ctrl_pma_ready() local
680 reg = readl(regs_base + EXYNOS850_DRD_CLKRST); in exynos5_usbdrd_usbdp_g2_v4_ctrl_pma_ready()
682 writel(reg, regs_base + EXYNOS850_DRD_CLKRST); in exynos5_usbdrd_usbdp_g2_v4_ctrl_pma_ready()
684 reg = readl(regs_base + EXYNOS850_DRD_SECPMACTL); in exynos5_usbdrd_usbdp_g2_v4_ctrl_pma_ready()
694 writel(reg, regs_base + EXYNOS850_DRD_SECPMACTL); in exynos5_usbdrd_usbdp_g2_v4_ctrl_pma_ready()
698 reg = readl(regs_base + EXYNOS850_DRD_SECPMACTL); in exynos5_usbdrd_usbdp_g2_v4_ctrl_pma_ready()
700 writel(reg, regs_base + EXYNOS850_DRD_SECPMACTL); in exynos5_usbdrd_usbdp_g2_v4_ctrl_pma_ready()
705 reg = readl(regs_base + EXYNOS850_DRD_LINKCTRL); in exynos5_usbdrd_usbdp_g2_v4_ctrl_pma_ready()
707 writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL); in exynos5_usbdrd_usbdp_g2_v4_ctrl_pma_ready()
712 reg = readl(regs_base + EXYNOS850_DRD_SECPMACTL); in exynos5_usbdrd_usbdp_g2_v4_ctrl_pma_ready()
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/linux/drivers/video/fbdev/
H A Dtgafb.c639 void __iomem *regs_base; local
664 regs_base = par->tga_regs_base;
683 __raw_writel(fgcolor, regs_base + TGA_FOREGROUND_REG);
684 __raw_writel(bgcolor, regs_base + TGA_BACKGROUND_REG);
705 regs_base + TGA_MODE_REG);
716 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
735 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
767 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
783 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
797 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
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/linux/drivers/net/ethernet/ezchip/
H A Dnps_enet.h161 void __iomem *regs_base; member
178 iowrite32be(value, priv->regs_base + reg); in nps_enet_reg_set()
190 return ioread32be(priv->regs_base + reg); in nps_enet_reg_get()
/linux/drivers/net/wireless/quantenna/qtnfmac/
H A Dqtn_hw_ids.h28 static inline unsigned int qtnf_chip_id_get(const void __iomem *regs_base) in qtnf_chip_id_get() argument
30 u32 board_rev = readl(regs_base + QTN_REG_SYS_CTRL_CSR); in qtnf_chip_id_get()
/linux/drivers/clk/st/
H A Dclkgen.h44 #define CLKGEN_READ(pll, field) clkgen_read(pll->regs_base, \
47 #define CLKGEN_WRITE(pll, field, val) clkgen_write(pll->regs_base, \
H A Dclkgen-fsyn.c244 void __iomem *regs_base; member
468 pll->regs_base = reg; in st_clk_register_quadfs_pll()
507 void __iomem *regs_base; member
908 fs->regs_base = reg; in st_clk_register_quadfs_fsynth()
H A Dclkgen-pll.c208 void __iomem *regs_base; member
246 void __iomem *base = pll->regs_base; in __clkgen_pll_enable()
671 pll->regs_base = reg; in clkgen_pll_register()
/linux/drivers/dma/bestcomm/
H A Dfec.c123 var->enable = bcom_eng->regs_base + in bcom_fec_rx_reset()
224 var->enable = bcom_eng->regs_base + in bcom_fec_tx_reset()
H A Dgen_bd.c130 var->enable = bcom_eng->regs_base + in bcom_gen_bd_rx_reset()
214 var->enable = bcom_eng->regs_base + in bcom_gen_bd_tx_reset()
H A Data.c79 var->enable = bcom_eng->regs_base + in bcom_ata_init()
/linux/arch/arm/include/asm/
H A Dkexec.h51 : [regs_base] "r" (&newregs->ARM_r0) in crash_setup_regs()
/linux/drivers/media/platform/amphion/
H A Dvpu_windsor.h14 u32 regs_base, void __iomem *regs, u32 core_id);
H A Dvpu_rpc.h57 u32 regs_base, void __iomem *regs, u32 index);
226 static inline int vpu_iface_config_system(struct vpu_core *core, u32 regs_base, void __iomem *regs) in vpu_iface_config_system() argument
233 ops->set_system_cfg(core->iface, regs_base, regs, core->id); in vpu_iface_config_system()
H A Dvpu_malone.h15 u32 regs_base, void __iomem *regs, u32 core_id);
H A Dvpu_windsor.c646 u32 regs_base, void __iomem *regs, u32 core_id) in vpu_windsor_set_system_cfg() argument
651 vpu_imx8q_set_system_cfg_common(config, regs_base, core_id); in vpu_windsor_set_system_cfg()
/linux/include/linux/fsl/bestcomm/
H A Dbestcomm_priv.h71 phys_addr_t regs_base; member
/linux/drivers/media/platform/rockchip/rkisp1/
H A Drkisp1-debug.c124 return rkisp1_debug_dump_regs(rsz->rkisp1, m, rsz->regs_base, registers); in rkisp1_debug_dump_rsz_regs_show()
/linux/drivers/media/platform/chips-media/coda/
H A Dcoda.h86 void __iomem *regs_base; member