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Searched refs:regmap_write (Results 1 – 25 of 862) sorted by relevance

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/linux/drivers/phy/qualcomm/
H A Dphy-qcom-sgmii-eth.c36 regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x01); in qcom_dwmac_sgmii_phy_init_1g()
37 regmap_write(regmap, QSERDES_PCS + QPHY_PCS_POWER_DOWN_CONTROL, 0x01); in qcom_dwmac_sgmii_phy_init_1g()
39 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_IVCO, 0x0F); in qcom_dwmac_sgmii_phy_init_1g()
40 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CP_CTRL_MODE0, 0x06); in qcom_dwmac_sgmii_phy_init_1g()
41 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16); in qcom_dwmac_sgmii_phy_init_1g()
42 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36); in qcom_dwmac_sgmii_phy_init_1g()
43 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1A); in qcom_dwmac_sgmii_phy_init_1g()
44 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0A); in qcom_dwmac_sgmii_phy_init_1g()
45 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1A); in qcom_dwmac_sgmii_phy_init_1g()
46 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_DEC_START_MODE0, 0x82); in qcom_dwmac_sgmii_phy_init_1g()
[all …]
/linux/drivers/gpu/drm/sprd/
H A Dmegacores_pll.c102 regmap_write(regmap, reg_addr[i], reg_val[i]); in dphy_set_pll_reg()
131 regmap_write(regmap, 0x31, val[CLK]); in dphy_set_timing_reg()
132 regmap_write(regmap, 0x41, val[DATA]); in dphy_set_timing_reg()
133 regmap_write(regmap, 0x51, val[DATA]); in dphy_set_timing_reg()
134 regmap_write(regmap, 0x61, val[DATA]); in dphy_set_timing_reg()
135 regmap_write(regmap, 0x71, val[DATA]); in dphy_set_timing_reg()
137 regmap_write(regmap, 0x90, val[CLK]); in dphy_set_timing_reg()
138 regmap_write(regmap, 0xa0, val[DATA]); in dphy_set_timing_reg()
139 regmap_write(regmap, 0xb0, val[DATA]); in dphy_set_timing_reg()
140 regmap_write(regmap, 0xc0, val[DATA]); in dphy_set_timing_reg()
[all …]
/linux/sound/soc/codecs/
H A Des8389.c574 regmap_write(es8389->regmap, ES8389_CLK_DIV1, coeff_div[coeff].Reg0x04); in es8389_pcm_hw_params()
575 regmap_write(es8389->regmap, ES8389_CLK_MUL, coeff_div[coeff].Reg0x05); in es8389_pcm_hw_params()
576 regmap_write(es8389->regmap, ES8389_CLK_MUX1, coeff_div[coeff].Reg0x06); in es8389_pcm_hw_params()
577 regmap_write(es8389->regmap, ES8389_CLK_MUX2, coeff_div[coeff].Reg0x07); in es8389_pcm_hw_params()
578 regmap_write(es8389->regmap, ES8389_CLK_CTL1, coeff_div[coeff].Reg0x08); in es8389_pcm_hw_params()
579 regmap_write(es8389->regmap, ES8389_CLK_CTL2, coeff_div[coeff].Reg0x09); in es8389_pcm_hw_params()
580 regmap_write(es8389->regmap, ES8389_CLK_CTL3, coeff_div[coeff].Reg0x0A); in es8389_pcm_hw_params()
583 regmap_write(es8389->regmap, ES8389_CLK_DIV2, coeff_div[coeff].Reg0x11); in es8389_pcm_hw_params()
584 regmap_write(es8389->regmap, ES8389_ADC_OSR, coeff_div[coeff].Reg0x21); in es8389_pcm_hw_params()
585 regmap_write(es838 in es8389_pcm_hw_params()
[all...]
H A Des8326.c81 regmap_write(es8326->regmap, ES8326_DAC_CROSSTALK, crosstalk_l); in es8326_crosstalk1_set()
119 regmap_write(es8326->regmap, ES8326_DAC_CROSSTALK, crosstalk_l); in es8326_crosstalk2_set()
578 regmap_write(es8326->regmap, ES8326_CLK_DIV1, in es8326_pcm_hw_params()
580 regmap_write(es8326->regmap, ES8326_CLK_DIV2, in es8326_pcm_hw_params()
582 regmap_write(es8326->regmap, ES8326_CLK_DLL, in es8326_pcm_hw_params()
584 regmap_write(es8326->regmap, ES8326_CLK_MUX, in es8326_pcm_hw_params()
586 regmap_write(es8326->regmap, ES8326_CLK_ADC_SEL, in es8326_pcm_hw_params()
588 regmap_write(es8326->regmap, ES8326_CLK_DAC_SEL, in es8326_pcm_hw_params()
590 regmap_write(es8326->regmap, ES8326_CLK_ADC_OSR, in es8326_pcm_hw_params()
592 regmap_write(es832 in es8326_pcm_hw_params()
[all...]
H A Des8375.c324 regmap_write(es8375->regmap, ES8375_CLK_MGR4, in es8375_hw_params()
326 regmap_write(es8375->regmap, ES8375_CLK_MGR5, in es8375_hw_params()
328 regmap_write(es8375->regmap, ES8375_CLK_MGR6, in es8375_hw_params()
330 regmap_write(es8375->regmap, ES8375_CLK_MGR7, in es8375_hw_params()
332 regmap_write(es8375->regmap, ES8375_CLK_MGR8, in es8375_hw_params()
334 regmap_write(es8375->regmap, ES8375_CLK_MGR9, in es8375_hw_params()
336 regmap_write(es8375->regmap, ES8375_CLK_MGR10, in es8375_hw_params()
338 regmap_write(es8375->regmap, ES8375_CLK_MGR11, in es8375_hw_params()
340 regmap_write(es8375->regmap, ES8375_ADC_OSR_GAIN, in es8375_hw_params()
441 regmap_write(es8375->regmap, ES8375_CLK_MGR3, iface); in es8375_set_dai_fmt()
[all …]
H A Drt700.c38 ret = regmap_write(regmap, addr, value); in rt700_index_write()
279 regmap_write(rt700->regmap, in rt700_jack_init()
284 regmap_write(rt700->regmap, in rt700_jack_init()
286 regmap_write(rt700->regmap, in rt700_jack_init()
288 regmap_write(rt700->regmap, in rt700_jack_init()
298 regmap_write(rt700->regmap, in rt700_jack_init()
300 regmap_write(rt700->regmap, in rt700_jack_init()
302 regmap_write(rt700->regmap, in rt700_jack_init()
310 regmap_write(rt700->regmap, in rt700_jack_init()
400 regmap_write(rt70 in rt700_set_amp_gain_put()
[all...]
H A Drt715.c41 ret = regmap_write(regmap, addr, value); in rt715_index_write()
56 ret = regmap_write(regmap, addr, value); in rt715_index_write_nid()
97 regmap_write(regmap, RT715_FUNC_RESET, 0); in rt715_reset()
155 regmap_write(rt715->regmap, in rt715_set_amp_gain_put()
181 regmap_write(rt715->regmap, addr_h, in rt715_set_amp_gain_put()
183 regmap_write(rt715->regmap, addr_l, in rt715_set_amp_gain_put()
188 regmap_write(rt715->regmap, addr_h, in rt715_set_amp_gain_put()
192 regmap_write(rt715->regmap, addr_l, in rt715_set_amp_gain_put()
209 regmap_write(rt715->regmap, in rt715_set_amp_gain_put()
276 regmap_write(rt71 in rt715_set_main_switch_put()
[all...]
H A Drt711.c38 ret = regmap_write(regmap, addr, value); in rt711_index_write()
79 regmap_write(regmap, RT711_FUNC_RESET, 0); in rt711_reset()
93 regmap_write(rt711->regmap, in rt711_calibration()
129 regmap_write(rt711->regmap, in rt711_calibration()
368 regmap_write(rt711->regmap, in rt711_jack_init()
373 regmap_write(rt711->regmap, in rt711_jack_init()
375 regmap_write(rt711->regmap, in rt711_jack_init()
377 regmap_write(rt711->regmap, in rt711_jack_init()
439 regmap_write(rt711->regmap, in rt711_jack_init()
441 regmap_write(rt71 in rt711_jack_init()
[all...]
H A Drt1308-sdw.c115 regmap_write(rt1308->regmap, 0xe0, value); in rt1308_clock_config()
116 regmap_write(rt1308->regmap, 0xf0, value); in rt1308_clock_config()
173 regmap_write(rt1308->regmap, 0xc7f0, 0x04); in rt1308_apply_calib_params()
174 regmap_write(rt1308->regmap, 0xc7f1, 0xfe); in rt1308_apply_calib_params()
176 regmap_write(rt1308->regmap, 0xc7f0, 0x44); in rt1308_apply_calib_params()
178 regmap_write(rt1308->regmap, 0xc240, 0x10); in rt1308_apply_calib_params()
209 regmap_write(rt1308->regmap, reg, data); in rt1308_apply_bq_params()
240 regmap_write(rt1308->regmap, RT1308_SDW_RESET, 0); in rt1308_io_init()
247 regmap_write(rt1308->regmap, 0xc103, 0xc0); in rt1308_io_init()
248 regmap_write(rt1308->regmap, 0xc030, 0x17); in rt1308_io_init()
[all …]
/linux/drivers/gpu/drm/bridge/
H A Dlontium-lt9611.c148 regmap_write(lt9611->regmap, 0x830d, (u8)(v_total / 256)); in lt9611_mipi_video_setup()
149 regmap_write(lt9611->regmap, 0x830e, (u8)(v_total % 256)); in lt9611_mipi_video_setup()
151 regmap_write(lt9611->regmap, 0x830f, (u8)(vactive / 256)); in lt9611_mipi_video_setup()
152 regmap_write(lt9611->regmap, 0x8310, (u8)(vactive % 256)); in lt9611_mipi_video_setup()
154 regmap_write(lt9611->regmap, 0x8311, (u8)(h_total / 256)); in lt9611_mipi_video_setup()
155 regmap_write(lt9611->regmap, 0x8312, (u8)(h_total % 256)); in lt9611_mipi_video_setup()
157 regmap_write(lt9611->regmap, 0x8313, (u8)(hactive / 256)); in lt9611_mipi_video_setup()
158 regmap_write(lt9611->regmap, 0x8314, (u8)(hactive % 256)); in lt9611_mipi_video_setup()
160 regmap_write(lt9611->regmap, 0x8315, (u8)(vsync_len % 256)); in lt9611_mipi_video_setup()
161 regmap_write(lt9611->regmap, 0x8316, (u8)(hsync_len % 256)); in lt9611_mipi_video_setup()
[all …]
H A Dchrontel-ch7033.c338 regmap_write(priv->regmap, 0x03, 0x04); in ch7033_bridge_disable()
346 regmap_write(priv->regmap, 0x03, 0x04); in ch7033_bridge_enable()
363 regmap_write(priv->regmap, 0x03, 0x04); in ch7033_bridge_mode_set()
366 regmap_write(priv->regmap, 0x52, 0x00); in ch7033_bridge_mode_set()
368 regmap_write(priv->regmap, 0x52, RESETIB); in ch7033_bridge_mode_set()
373 regmap_write(priv->regmap, 0x03, 0x00); in ch7033_bridge_mode_set()
383 regmap_write(priv->regmap, 0x0b, (mode->htotal >> 8) << 3 | in ch7033_bridge_mode_set()
385 regmap_write(priv->regmap, 0x0c, mode->hdisplay); in ch7033_bridge_mode_set()
386 regmap_write(priv->regmap, 0x0d, mode->htotal); in ch7033_bridge_mode_set()
387 regmap_write(priv->regmap, 0x0e, (hsynclen >> 8) << 3 | in ch7033_bridge_mode_set()
[all …]
/linux/drivers/media/tuners/
H A Dm88rs6000t.c108 ret = regmap_write(dev->regmap, 0x05, 0x40); in m88rs6000t_set_demod_mclk()
111 ret = regmap_write(dev->regmap, 0x11, 0x08); in m88rs6000t_set_demod_mclk()
114 ret = regmap_write(dev->regmap, 0x15, reg15); in m88rs6000t_set_demod_mclk()
117 ret = regmap_write(dev->regmap, 0x16, reg16); in m88rs6000t_set_demod_mclk()
120 ret = regmap_write(dev->regmap, 0x1D, reg1D); in m88rs6000t_set_demod_mclk()
123 ret = regmap_write(dev->regmap, 0x1E, reg1E); in m88rs6000t_set_demod_mclk()
126 ret = regmap_write(dev->regmap, 0x1F, reg1F); in m88rs6000t_set_demod_mclk()
129 ret = regmap_write(dev->regmap, 0x17, 0xc1); in m88rs6000t_set_demod_mclk()
132 ret = regmap_write(dev->regmap, 0x17, 0x81); in m88rs6000t_set_demod_mclk()
136 ret = regmap_write(dev->regmap, 0x05, 0x00); in m88rs6000t_set_demod_mclk()
[all …]
/linux/drivers/media/dvb-frontends/
H A Drtl2832_sdr.c550 ret = regmap_write(dev->regmap, 0x1b1, u8tmp1); in rtl2832_sdr_set_adc()
554 ret = regmap_write(dev->regmap, 0x008, u8tmp2); in rtl2832_sdr_set_adc()
558 ret = regmap_write(dev->regmap, 0x006, 0x80); in rtl2832_sdr_set_adc()
585 ret = regmap_write(dev->regmap, 0x019, 0x05); in rtl2832_sdr_set_adc()
600 ret = regmap_write(dev->regmap, 0x061, 0x60); in rtl2832_sdr_set_adc()
607 ret = regmap_write(dev->regmap, 0x112, 0x5a); in rtl2832_sdr_set_adc()
608 ret = regmap_write(dev->regmap, 0x102, 0x40); in rtl2832_sdr_set_adc()
609 ret = regmap_write(dev->regmap, 0x103, 0x5a); in rtl2832_sdr_set_adc()
610 ret = regmap_write(dev->regmap, 0x1c7, 0x30); in rtl2832_sdr_set_adc()
611 ret = regmap_write(dev->regmap, 0x104, 0xd0); in rtl2832_sdr_set_adc()
[all …]
H A Dts2020.c68 ret = regmap_write(priv->regmap, u8tmp, 0x00); in ts2020_sleep()
86 regmap_write(priv->regmap, 0x42, 0x73); in ts2020_init()
87 regmap_write(priv->regmap, 0x05, priv->clk_out_div); in ts2020_init()
88 regmap_write(priv->regmap, 0x20, 0x27); in ts2020_init()
89 regmap_write(priv->regmap, 0x07, 0x02); in ts2020_init()
90 regmap_write(priv->regmap, 0x11, 0xff); in ts2020_init()
91 regmap_write(priv->regmap, 0x60, 0xf9); in ts2020_init()
92 regmap_write(priv->regmap, 0x08, 0x01); in ts2020_init()
93 regmap_write(priv->regmap, 0x00, 0x41); in ts2020_init()
109 regmap_write(priv->regmap, 0x00, 0x01); in ts2020_init()
[all …]
H A Dmn88473.c108 ret = regmap_write(dev->regmap[2], 0x05, 0x00); in mn88473_set_frontend()
111 ret = regmap_write(dev->regmap[2], 0xfb, 0x13); in mn88473_set_frontend()
114 ret = regmap_write(dev->regmap[2], 0xef, 0x13); in mn88473_set_frontend()
117 ret = regmap_write(dev->regmap[2], 0xf9, 0x13); in mn88473_set_frontend()
120 ret = regmap_write(dev->regmap[2], 0x00, 0x18); in mn88473_set_frontend()
123 ret = regmap_write(dev->regmap[2], 0x01, 0x01); in mn88473_set_frontend()
126 ret = regmap_write(dev->regmap[2], 0x02, 0x21); in mn88473_set_frontend()
129 ret = regmap_write(dev->regmap[2], 0x03, delivery_system_val); in mn88473_set_frontend()
132 ret = regmap_write(dev->regmap[2], 0x0b, 0x00); in mn88473_set_frontend()
137 ret = regmap_write(dev->regmap[2], 0x10 + i, if_val[i]); in mn88473_set_frontend()
[all …]
H A Dmn88472.c299 ret = regmap_write(dev->regmap[2], 0x00, 0x66); in mn88472_set_frontend()
302 ret = regmap_write(dev->regmap[2], 0x01, 0x00); in mn88472_set_frontend()
305 ret = regmap_write(dev->regmap[2], 0x02, 0x01); in mn88472_set_frontend()
308 ret = regmap_write(dev->regmap[2], 0x03, delivery_system_val); in mn88472_set_frontend()
311 ret = regmap_write(dev->regmap[2], 0x04, bandwidth_val); in mn88472_set_frontend()
321 ret = regmap_write(dev->regmap[2], 0x10 + i, buf[i]); in mn88472_set_frontend()
329 ret = regmap_write(dev->regmap[2], 0x13 + i, in mn88472_set_frontend()
336 ret = regmap_write(dev->regmap[0], 0xb4, reg_bank0_b4_val); in mn88472_set_frontend()
339 ret = regmap_write(dev->regmap[0], 0xcd, reg_bank0_cd_val); in mn88472_set_frontend()
342 ret = regmap_write(dev->regmap[0], 0xd4, reg_bank0_d4_val); in mn88472_set_frontend()
[all …]
/linux/drivers/iio/imu/inv_mpu6050/
H A Dinv_mpu_aux.c32 ret = regmap_write(st->map, st->reg->sample_rate_div, d); in inv_mpu_i2c_master_xfer()
38 ret = regmap_write(st->map, st->reg->user_ctrl, user_ctrl); in inv_mpu_i2c_master_xfer()
47 ret = regmap_write(st->map, st->reg->user_ctrl, user_ctrl); in inv_mpu_i2c_master_xfer()
53 ret = regmap_write(st->map, st->reg->sample_rate_div, d); in inv_mpu_i2c_master_xfer()
58 ret = regmap_write(st->map, INV_MPU6050_REG_I2C_SLV_CTRL(0), 0); in inv_mpu_i2c_master_xfer()
73 regmap_write(st->map, st->reg->user_ctrl, st->chip_config.user_ctrl); in inv_mpu_i2c_master_xfer()
75 regmap_write(st->map, st->reg->sample_rate_div, st->chip_config.divider); in inv_mpu_i2c_master_xfer()
77 regmap_write(st->map, INV_MPU6050_REG_I2C_SLV_CTRL(0), 0); in inv_mpu_i2c_master_xfer()
108 ret = regmap_write(st->map, INV_MPU6050_REG_I2C_MST_CTRL, val); in inv_mpu_aux_init()
113 ret = regmap_write(st->map, INV_MPU6050_REG_I2C_SLV4_CTRL, 0); in inv_mpu_aux_init()
[all …]
/linux/drivers/power/reset/
H A Darm-versatile-reboot.c79 regmap_write(syscon_regmap, INTEGRATOR_HDR_LOCK_OFFSET, in versatile_reboot()
87 regmap_write(syscon_regmap, VERSATILE_SYS_LOCK_OFFSET, in versatile_reboot()
93 regmap_write(syscon_regmap, VERSATILE_SYS_LOCK_OFFSET, in versatile_reboot()
97 regmap_write(syscon_regmap, VERSATILE_SYS_LOCK_OFFSET, in versatile_reboot()
99 regmap_write(syscon_regmap, in versatile_reboot()
103 regmap_write(syscon_regmap, VERSATILE_SYS_LOCK_OFFSET, in versatile_reboot()
105 regmap_write(syscon_regmap, in versatile_reboot()
110 regmap_write(syscon_regmap, VERSATILE_SYS_LOCK_OFFSET, in versatile_reboot()
112 regmap_write(syscon_regmap, VERSATILE_SYS_RESETCTL_OFFSET, in versatile_reboot()
114 regmap_write(syscon_regmap, VERSATILE_SYS_RESETCTL_OFFSET, in versatile_reboot()
[all …]
/linux/drivers/phy/allwinner/
H A Dphy-sun6i-mipi-dphy.c229 regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG, in sun6i_a31_mipi_dphy_tx_power_on()
236 regmap_write(dphy->regs, SUN6I_DPHY_ANA1_REG, in sun6i_a31_mipi_dphy_tx_power_on()
240 regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG, in sun6i_a31_mipi_dphy_tx_power_on()
251 regmap_write(dphy->regs, SUN6I_DPHY_ANA2_REG, in sun6i_a31_mipi_dphy_tx_power_on()
255 regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG, in sun6i_a31_mipi_dphy_tx_power_on()
267 regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG, in sun50i_a100_mipi_dphy_tx_power_on()
287 regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG, in sun50i_a100_mipi_dphy_tx_power_on()
292 regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG, in sun50i_a100_mipi_dphy_tx_power_on()
296 regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG0, in sun50i_a100_mipi_dphy_tx_power_on()
303 regmap_write(dphy->regs, SUN50I_DPHY_PLL_REG0, in sun50i_a100_mipi_dphy_tx_power_on()
[all …]
/linux/drivers/gpu/drm/meson/
H A Dmeson_vclk.c246 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x5800023d); in meson_venci_cvbs_clock_config()
247 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00404e00); in meson_venci_cvbs_clock_config()
248 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091); in meson_venci_cvbs_clock_config()
249 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c); in meson_venci_cvbs_clock_config()
250 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980); in meson_venci_cvbs_clock_config()
251 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55); in meson_venci_cvbs_clock_config()
252 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4800023d); in meson_venci_cvbs_clock_config()
259 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4000027b); in meson_venci_cvbs_clock_config()
260 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb300); in meson_venci_cvbs_clock_config()
261 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0xa6212844); in meson_venci_cvbs_clock_config()
[all …]
/linux/drivers/phy/amlogic/
H A Dphy-meson-axg-mipi-dphy.c229 regmap_write(priv->regmap, MIPI_DSI_PHY_CTRL, 0x1); in phy_meson_axg_mipi_dphy_power_on()
230 regmap_write(priv->regmap, MIPI_DSI_PHY_CTRL, in phy_meson_axg_mipi_dphy_power_on()
247 regmap_write(priv->regmap, MIPI_DSI_CLK_TIM, in phy_meson_axg_mipi_dphy_power_on()
253 regmap_write(priv->regmap, MIPI_DSI_CLK_TIM1, in phy_meson_axg_mipi_dphy_power_on()
256 regmap_write(priv->regmap, MIPI_DSI_HS_TIM, in phy_meson_axg_mipi_dphy_power_on()
262 regmap_write(priv->regmap, MIPI_DSI_LP_TIM, in phy_meson_axg_mipi_dphy_power_on()
268 regmap_write(priv->regmap, MIPI_DSI_ANA_UP_TIM, 0x0100); in phy_meson_axg_mipi_dphy_power_on()
269 regmap_write(priv->regmap, MIPI_DSI_INIT_TIM, in phy_meson_axg_mipi_dphy_power_on()
271 regmap_write(priv->regmap, MIPI_DSI_WAKEUP_TIM, in phy_meson_axg_mipi_dphy_power_on()
273 regmap_write(priv->regmap, MIPI_DSI_LPOK_TIM, 0x7C); in phy_meson_axg_mipi_dphy_power_on()
[all …]
/linux/drivers/phy/lantiq/
H A Dphy-lantiq-vrx200-pcie.c103 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL1, 0x120e); in ltq_vrx200_pcie_phy_common_setup()
106 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL2, 0x39d7); in ltq_vrx200_pcie_phy_common_setup()
107 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL3, 0x0900); in ltq_vrx200_pcie_phy_common_setup()
110 regmap_write(priv->phy_regmap, PCIE_PHY_RX1_EI, 0x0004); in ltq_vrx200_pcie_phy_common_setup()
111 regmap_write(priv->phy_regmap, PCIE_PHY_RX1_A_CTRL, 0x6803); in ltq_vrx200_pcie_phy_common_setup()
118 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_A_CTRL2, 0x0706); in ltq_vrx200_pcie_phy_common_setup()
121 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_CTRL3, 0x1fff); in ltq_vrx200_pcie_phy_common_setup()
124 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_A_CTRL1, 0x0810); in ltq_vrx200_pcie_phy_common_setup()
131 regmap_write(priv->phy_regmap, PCIE_PHY_TX1_CTRL2, 0x2e00); in ltq_vrx200_pcie_phy_common_setup()
134 regmap_write(priv->phy_regmap, PCIE_PHY_TX2_CTRL2, 0x3096); in ltq_vrx200_pcie_phy_common_setup()
[all …]
/linux/drivers/devfreq/event/
H A Dexynos-ppmu.c135 ret = regmap_write(info->regmap, PPMU_CNTENC, in exynos_ppmu_disable()
150 ret = regmap_write(info->regmap, PPMU_PMNC, pmnc); in exynos_ppmu_disable()
173 ret = regmap_write(info->regmap, PPMU_CNTENS, cntens); in exynos_ppmu_set_event()
178 ret = regmap_write(info->regmap, PPMU_BEVTxSEL(id), in exynos_ppmu_set_event()
194 ret = regmap_write(info->regmap, PPMU_PMNC, pmnc); in exynos_ppmu_set_event()
220 ret = regmap_write(info->regmap, PPMU_PMNC, pmnc); in exynos_ppmu_get_event()
261 ret = regmap_write(info->regmap, PPMU_CNTENC, cntenc); in exynos_ppmu_get_event()
289 ret = regmap_write(info->regmap, PPMU_V2_FLAG, clear); in exynos_ppmu_v2_disable()
293 ret = regmap_write(info->regmap, PPMU_V2_INTENC, clear); in exynos_ppmu_v2_disable()
297 ret = regmap_write(info->regmap, PPMU_V2_CNTENC, clear); in exynos_ppmu_v2_disable()
[all …]
/linux/arch/arm/mach-rockchip/
H A Dpm.c102 regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0, in rk3288_slp_mode_set()
111 regmap_write(sgrf_regmap, RK3288_SGRF_CPU_CON0, SGRF_DAPDEVICEEN_WRITE); in rk3288_slp_mode_set()
114 regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR, in rk3288_slp_mode_set()
137 regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1, in rk3288_slp_mode_set()
147 regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 32 * 30); in rk3288_slp_mode_set()
150 regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, in rk3288_slp_mode_set()
160 regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1, in rk3288_slp_mode_set()
164 regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 24000 * 30); in rk3288_slp_mode_set()
167 regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, 0); in rk3288_slp_mode_set()
170 regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON, mode_set); in rk3288_slp_mode_set()
[all …]
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-rk.c133 regmap_write(bsp_priv->grf, reg, val); in rk_set_reg_speed()
178 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M); in rk_gmac_integrated_ephy_powerup()
179 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE); in rk_gmac_integrated_ephy_powerup()
181 regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID); in rk_gmac_integrated_ephy_powerup()
182 regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID); in rk_gmac_integrated_ephy_powerup()
186 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); in rk_gmac_integrated_ephy_powerup()
193 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE); in rk_gmac_integrated_ephy_powerup()
200 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); in rk_gmac_integrated_ephy_powerdown()
217 regmap_write(priv->grf, reg, in rk_gmac_integrated_fephy_powerup()
231 regmap_write(priv->grf, reg, RK_FEPHY_SHUTDOWN); in rk_gmac_integrated_fephy_powerdown()
[all …]

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