1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell RVU Admin Function driver
3 *
4 * Copyright (C) 2018 Marvell.
5 *
6 */
7
8 #ifndef RVU_H
9 #define RVU_H
10
11 #include <linux/pci.h>
12 #include <net/devlink.h>
13 #include <linux/soc/marvell/silicons.h>
14
15 #include "rvu_struct.h"
16 #include "rvu_devlink.h"
17 #include "common.h"
18 #include "mbox.h"
19 #include "npc.h"
20 #include "rvu_reg.h"
21 #include "ptp.h"
22
23 /* PCI device IDs */
24 #define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065
25 #define PCI_DEVID_OCTEONTX2_LBK 0xA061
26
27 /* Subsystem Device ID */
28 #define PCI_SUBSYS_DEVID_98XX 0xB100
29 #define PCI_SUBSYS_DEVID_96XX 0xB200
30 #define PCI_SUBSYS_DEVID_CN10K_A 0xB900
31 #define PCI_SUBSYS_DEVID_CNF10K_A 0xBA00
32 #define PCI_SUBSYS_DEVID_CNF10K_B 0xBC00
33 #define PCI_SUBSYS_DEVID_CN10K_B 0xBD00
34 #define PCI_SUBSYS_DEVID_CN20KA 0xC220
35 #define PCI_SUBSYS_DEVID_CNF20KA 0xC320
36
37 /* PCI BAR nos */
38 #define PCI_AF_REG_BAR_NUM 0
39 #define PCI_PF_REG_BAR_NUM 2
40 #define PCI_MBOX_BAR_NUM 4
41
42 #define NAME_SIZE 32
43 #define MAX_NIX_BLKS 2
44 #define MAX_CPT_BLKS 2
45
46 /* PF_FUNC */
47 #define RVU_OTX2_PFVF_PF_SHIFT 10
48 #define RVU_OTX2_PFVF_PF_MASK 0x3F
49 #define RVU_PFVF_FUNC_SHIFT 0
50 #define RVU_PFVF_FUNC_MASK 0x3FF
51 #define RVU_CN20K_PFVF_PF_SHIFT 9
52 #define RVU_CN20K_PFVF_PF_MASK 0x7F
53
rvu_make_pcifunc(struct pci_dev * pdev,int pf,int func)54 static inline u16 rvu_make_pcifunc(struct pci_dev *pdev, int pf, int func)
55 {
56 if (is_cn20k(pdev))
57 return ((pf & RVU_CN20K_PFVF_PF_MASK) <<
58 RVU_CN20K_PFVF_PF_SHIFT) |
59 ((func & RVU_PFVF_FUNC_MASK) <<
60 RVU_PFVF_FUNC_SHIFT);
61 else
62 return ((pf & RVU_OTX2_PFVF_PF_MASK) <<
63 RVU_OTX2_PFVF_PF_SHIFT) |
64 ((func & RVU_PFVF_FUNC_MASK) <<
65 RVU_PFVF_FUNC_SHIFT);
66 }
67
rvu_pcifunc_pf_mask(struct pci_dev * pdev)68 static inline int rvu_pcifunc_pf_mask(struct pci_dev *pdev)
69 {
70 if (is_cn20k(pdev))
71 return ~(RVU_CN20K_PFVF_PF_MASK << RVU_CN20K_PFVF_PF_SHIFT);
72 else
73 return ~(RVU_OTX2_PFVF_PF_MASK << RVU_OTX2_PFVF_PF_SHIFT);
74 }
75
76 #define RVU_AFPF 25
77
78 #ifdef CONFIG_DEBUG_FS
79
80 struct dump_ctx {
81 int lf;
82 int id;
83 bool all;
84 };
85
86 struct cpt_ctx {
87 int blkaddr;
88 struct rvu *rvu;
89 };
90
91 struct rvu_debugfs {
92 struct dentry *root;
93 struct dentry *cgx_root;
94 struct dentry *cgx;
95 struct dentry *lmac;
96 struct dentry *npa;
97 struct dentry *nix;
98 struct dentry *npc;
99 struct dentry *cpt;
100 struct dentry *mcs_root;
101 struct dentry *mcs;
102 struct dentry *mcs_rx;
103 struct dentry *mcs_tx;
104 struct dump_ctx npa_aura_ctx;
105 struct dump_ctx npa_pool_ctx;
106 struct dump_ctx nix_cq_ctx;
107 struct dump_ctx nix_rq_ctx;
108 struct dump_ctx nix_sq_ctx;
109 struct dump_ctx nix_tm_ctx;
110 struct cpt_ctx cpt_ctx[MAX_CPT_BLKS];
111 int npa_qsize_id;
112 int nix_qsize_id;
113 };
114 #endif
115
116 struct rvu_work {
117 struct work_struct work;
118 struct rvu *rvu;
119 int num_msgs;
120 int up_num_msgs;
121 };
122
123 struct rsrc_bmap {
124 unsigned long *bmap; /* Pointer to resource bitmap */
125 u16 max; /* Max resource id or count */
126 };
127
128 struct rvu_block {
129 struct rsrc_bmap lf;
130 struct admin_queue *aq; /* NIX/NPA AQ */
131 u16 *fn_map; /* LF to pcifunc mapping */
132 bool multislot;
133 bool implemented;
134 u8 addr; /* RVU_BLOCK_ADDR_E */
135 u8 type; /* RVU_BLOCK_TYPE_E */
136 u8 lfshift;
137 u64 lookup_reg;
138 u64 pf_lfcnt_reg;
139 u64 vf_lfcnt_reg;
140 u64 lfcfg_reg;
141 u64 msixcfg_reg;
142 u64 lfreset_reg;
143 unsigned char name[NAME_SIZE];
144 struct rvu *rvu;
145 u64 cpt_flt_eng_map[3];
146 u64 cpt_rcvrd_eng_map[3];
147 };
148
149 struct nix_mcast {
150 struct qmem *mce_ctx;
151 struct qmem *mcast_buf;
152 int replay_pkind;
153 struct rsrc_bmap mce_counter[2];
154 /* Counters for both ingress and egress mcast lists */
155 struct mutex mce_lock; /* Serialize MCE updates */
156 };
157
158 struct nix_mce_list {
159 struct hlist_head head;
160 int count;
161 int max;
162 };
163
164 struct nix_mcast_grp_elem {
165 struct nix_mce_list mcast_mce_list;
166 u32 mcast_grp_idx;
167 u32 pcifunc;
168 int mcam_index;
169 int mce_start_index;
170 struct list_head list;
171 u8 dir;
172 };
173
174 struct nix_mcast_grp {
175 struct list_head mcast_grp_head;
176 int count;
177 int next_grp_index;
178 struct mutex mcast_grp_lock; /* Serialize MCE updates */
179 };
180
181 /* layer metadata to uniquely identify a packet header field */
182 struct npc_layer_mdata {
183 u8 lid;
184 u8 ltype;
185 u8 hdr;
186 u8 key;
187 u8 len;
188 };
189
190 /* Structure to represent a field present in the
191 * generated key. A key field may present anywhere and can
192 * be of any size in the generated key. Once this structure
193 * is populated for fields of interest then field's presence
194 * and location (if present) can be known.
195 */
196 struct npc_key_field {
197 /* Masks where all set bits indicate position
198 * of a field in the key
199 */
200 u64 kw_mask[NPC_KWS_IN_KEY_SZ_MAX];
201 /* Number of words in the key a field spans. If a field is
202 * of 16 bytes and key offset is 4 then the field will use
203 * 4 bytes in KW0, 8 bytes in KW1 and 4 bytes in KW2 and
204 * nr_kws will be 3(KW0, KW1 and KW2).
205 */
206 int nr_kws;
207 /* used by packet header fields */
208 struct npc_layer_mdata layer_mdata;
209 };
210
211 struct npc_mcam {
212 struct rsrc_bmap counters;
213 struct mutex lock; /* MCAM entries and counters update lock */
214 unsigned long *bmap; /* bitmap, 0 => bmap_entries */
215 unsigned long *bmap_reverse; /* Reverse bitmap, bmap_entries => 0 */
216 u16 bmap_entries; /* Number of unreserved MCAM entries */
217 u16 bmap_fcnt; /* MCAM entries free count */
218 u16 *entry2pfvf_map;
219 u16 *entry2cntr_map;
220 u16 *cntr2pfvf_map;
221 u16 *cntr_refcnt;
222 u16 *entry2target_pffunc;
223 u8 keysize; /* MCAM keysize 112/224/448 bits */
224 u8 banks; /* Number of MCAM banks */
225 u8 banks_per_entry;/* Number of keywords in key */
226 u16 banksize; /* Number of MCAM entries in each bank */
227 u16 total_entries; /* Total number of MCAM entries */
228 u16 nixlf_offset; /* Offset of nixlf rsvd uncast entries */
229 u16 pf_offset; /* Offset of PF's rsvd bcast, promisc entries */
230 u16 lprio_count;
231 u16 lprio_start;
232 u16 hprio_count;
233 u16 hprio_end;
234 u16 rx_miss_act_cntr; /* Counter for RX MISS action */
235 /* fields present in the generated key */
236 struct npc_key_field tx_key_fields[NPC_KEY_FIELDS_MAX];
237 struct npc_key_field rx_key_fields[NPC_KEY_FIELDS_MAX];
238 u64 tx_features;
239 u64 rx_features;
240 struct list_head mcam_rules;
241 };
242
243 /* Structure for per RVU func info ie PF/VF */
244 struct rvu_pfvf {
245 bool npalf; /* Only one NPALF per RVU_FUNC */
246 bool nixlf; /* Only one NIXLF per RVU_FUNC */
247 u16 sso;
248 u16 ssow;
249 u16 cptlfs;
250 u16 timlfs;
251 u16 cpt1_lfs;
252 u8 cgx_lmac;
253
254 /* Block LF's MSIX vector info */
255 struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */
256 #define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF))
257 u16 *msix_lfmap; /* Vector to block LF mapping */
258
259 /* NPA contexts */
260 struct qmem *aura_ctx;
261 struct qmem *pool_ctx;
262 struct qmem *npa_qints_ctx;
263 unsigned long *aura_bmap;
264 unsigned long *pool_bmap;
265
266 /* NIX contexts */
267 struct qmem *rq_ctx;
268 struct qmem *sq_ctx;
269 struct qmem *cq_ctx;
270 struct qmem *rss_ctx;
271 struct qmem *cq_ints_ctx;
272 struct qmem *nix_qints_ctx;
273 unsigned long *sq_bmap;
274 unsigned long *rq_bmap;
275 unsigned long *cq_bmap;
276
277 u16 rx_chan_base;
278 u16 tx_chan_base;
279 u8 rx_chan_cnt; /* total number of RX channels */
280 u8 tx_chan_cnt; /* total number of TX channels */
281 u16 maxlen;
282 u16 minlen;
283
284 bool hw_rx_tstamp_en; /* Is rx_tstamp enabled */
285 u8 mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */
286 u8 default_mac[ETH_ALEN]; /* MAC address from FWdata */
287
288 /* Broadcast/Multicast/Promisc pkt replication info */
289 u16 bcast_mce_idx;
290 u16 mcast_mce_idx;
291 u16 promisc_mce_idx;
292 struct nix_mce_list bcast_mce_list;
293 struct nix_mce_list mcast_mce_list;
294 struct nix_mce_list promisc_mce_list;
295 bool use_mce_list;
296
297 struct rvu_npc_mcam_rule *def_ucast_rule;
298
299 bool cgx_in_use; /* this PF/VF using CGX? */
300 int cgx_users; /* number of cgx users - used only by PFs */
301
302 int intf_mode;
303 u8 nix_blkaddr; /* BLKADDR_NIX0/1 assigned to this PF */
304 u8 nix_rx_intf; /* NIX0_RX/NIX1_RX interface to NPC */
305 u8 nix_tx_intf; /* NIX0_TX/NIX1_TX interface to NPC */
306 u8 lbkid; /* NIX0/1 lbk link ID */
307 u64 lmt_base_addr; /* Preseving the pcifunc's lmtst base addr*/
308 u64 lmt_map_ent_w1; /* Preseving the word1 of lmtst map table entry*/
309 unsigned long flags;
310 struct sdp_node_info *sdp_info;
311 u8 hw_prio; /* Hw priority of default rules */
312 };
313
314 enum rvu_pfvf_flags {
315 NIXLF_INITIALIZED = 0,
316 PF_SET_VF_MAC,
317 PF_SET_VF_CFG,
318 PF_SET_VF_TRUSTED,
319 };
320
321 #define RVU_CLEAR_VF_PERM ~GENMASK(PF_SET_VF_TRUSTED, PF_SET_VF_MAC)
322
323 struct nix_bp {
324 struct rsrc_bmap bpids; /* free bpids bitmap */
325 u16 cgx_bpid_cnt;
326 u16 sdp_bpid_cnt;
327 u16 free_pool_base;
328 u16 *fn_map; /* pcifunc mapping */
329 u8 *intf_map; /* interface type map */
330 u8 *ref_cnt;
331 };
332
333 struct nix_txsch {
334 struct rsrc_bmap schq;
335 u8 lvl;
336 #define NIX_TXSCHQ_FREE BIT_ULL(1)
337 #define NIX_TXSCHQ_CFG_DONE BIT_ULL(0)
338 #define TXSCH_MAP_FUNC(__pfvf_map) ((__pfvf_map) & 0xFFFF)
339 #define TXSCH_MAP_FLAGS(__pfvf_map) ((__pfvf_map) >> 16)
340 #define TXSCH_MAP(__func, __flags) (((__func) & 0xFFFF) | ((__flags) << 16))
341 #define TXSCH_SET_FLAG(__pfvf_map, flag) ((__pfvf_map) | ((flag) << 16))
342 u32 *pfvf_map;
343 };
344
345 struct nix_mark_format {
346 u8 total;
347 u8 in_use;
348 u32 *cfg;
349 };
350
351 /* smq(flush) to tl1 cir/pir info */
352 struct nix_smq_tree_ctx {
353 u16 schq;
354 u64 cir_off;
355 u64 cir_val;
356 u64 pir_off;
357 u64 pir_val;
358 };
359
360 /* smq flush context */
361 struct nix_smq_flush_ctx {
362 int smq;
363 struct nix_smq_tree_ctx smq_tree_ctx[NIX_TXSCH_LVL_CNT];
364 };
365
366 struct npc_pkind {
367 struct rsrc_bmap rsrc;
368 u32 *pfchan_map;
369 };
370
371 struct nix_flowkey {
372 #define NIX_FLOW_KEY_ALG_MAX 32
373 u32 flowkey[NIX_FLOW_KEY_ALG_MAX];
374 int in_use;
375 };
376
377 struct nix_lso {
378 u8 total;
379 u8 in_use;
380 };
381
382 struct nix_txvlan {
383 #define NIX_TX_VTAG_DEF_MAX 0x400
384 struct rsrc_bmap rsrc;
385 u16 *entry2pfvf_map;
386 struct mutex rsrc_lock; /* Serialize resource alloc/free */
387 };
388
389 struct nix_ipolicer {
390 struct rsrc_bmap band_prof;
391 u16 *pfvf_map;
392 u16 *match_id;
393 u16 *ref_count;
394 };
395
396 struct nix_hw {
397 int blkaddr;
398 struct rvu *rvu;
399 struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */
400 struct nix_mcast mcast;
401 struct nix_mcast_grp mcast_grp;
402 struct nix_flowkey flowkey;
403 struct nix_mark_format mark_format;
404 struct nix_lso lso;
405 struct nix_txvlan txvlan;
406 struct nix_ipolicer *ipolicer;
407 struct nix_bp bp;
408 u64 *tx_credits;
409 u8 cc_mcs_cnt;
410 };
411
412 /* RVU block's capabilities or functionality,
413 * which vary by silicon version/skew.
414 */
415 struct hw_cap {
416 /* Transmit side supported functionality */
417 u8 nix_tx_aggr_lvl; /* Tx link's traffic aggregation level */
418 u16 nix_txsch_per_cgx_lmac; /* Max Q's transmitting to CGX LMAC */
419 u16 nix_txsch_per_lbk_lmac; /* Max Q's transmitting to LBK LMAC */
420 u16 nix_txsch_per_sdp_lmac; /* Max Q's transmitting to SDP LMAC */
421 bool nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
422 bool nix_shaping; /* Is shaping and coloring supported */
423 bool nix_shaper_toggle_wait; /* Shaping toggle needs poll/wait */
424 bool nix_tx_link_bp; /* Can link backpressure TL queues ? */
425 bool nix_rx_multicast; /* Rx packet replication support */
426 bool nix_common_dwrr_mtu; /* Common DWRR MTU for quantum config */
427 bool per_pf_mbox_regs; /* PF mbox specified in per PF registers ? */
428 bool programmable_chans; /* Channels programmable ? */
429 bool ipolicer;
430 bool nix_multiple_dwrr_mtu; /* Multiple DWRR_MTU to choose from */
431 bool npc_hash_extract; /* Hash extract enabled ? */
432 bool npc_exact_match_enabled; /* Exact match supported ? */
433 bool cpt_rxc; /* Is CPT-RXC supported */
434 };
435
436 struct rvu_hwinfo {
437 u8 total_pfs; /* MAX RVU PFs HW supports */
438 u16 total_vfs; /* Max RVU VFs HW supports */
439 u16 max_vfs_per_pf; /* Max VFs that can be attached to a PF */
440 u8 cgx;
441 u8 lmac_per_cgx;
442 u16 cgx_chan_base; /* CGX base channel number */
443 u16 lbk_chan_base; /* LBK base channel number */
444 u16 sdp_chan_base; /* SDP base channel number */
445 u16 cpt_chan_base; /* CPT base channel number */
446 u8 cgx_links;
447 u8 lbk_links;
448 u8 sdp_links;
449 u8 cpt_links; /* Number of CPT links */
450 u8 npc_kpus; /* No of parser units */
451 u8 npc_kpms; /* Number of enhanced parser units */
452 u8 npc_kex_extr; /* Number of LDATA extractors per KEX */
453 u8 npc_pkinds; /* No of port kinds */
454 u8 npc_intfs; /* No of interfaces */
455 u16 npc_kpu_entries; /* No of KPU entries */
456 u16 npc_counters; /* No of match stats counters */
457 u32 lbk_bufsize; /* FIFO size supported by LBK */
458 bool npc_ext_set; /* Extended register set */
459 u64 npc_stat_ena; /* Match stats enable bit */
460
461 struct hw_cap cap;
462 struct rvu_block block[BLK_COUNT]; /* Block info */
463 struct nix_hw *nix;
464 struct rvu *rvu;
465 struct npc_pkind pkind;
466 struct npc_mcam mcam;
467 struct npc_exact_table *table;
468 };
469
470 struct mbox_wq_info {
471 struct otx2_mbox mbox;
472 struct rvu_work *mbox_wrk;
473
474 struct otx2_mbox mbox_up;
475 struct rvu_work *mbox_wrk_up;
476
477 struct workqueue_struct *mbox_wq;
478 };
479
480 struct rvu_irq_data {
481 u64 intr_status;
482 void (*rvu_queue_work_hdlr)(struct mbox_wq_info *mw, int first,
483 int mdevs, u64 intr);
484 void (*afvf_queue_work_hdlr)(struct mbox_wq_info *mw, int first,
485 int mdevs, u64 intr);
486 struct rvu *rvu;
487 int vec_num;
488 int start;
489 int mdevs;
490 };
491
492 struct mbox_ops {
493 irqreturn_t (*pf_intr_handler)(int irq, void *rvu_irq);
494 irqreturn_t (*afvf_intr_handler)(int irq, void *rvu_irq);
495 };
496
497 struct channel_fwdata {
498 struct sdp_node_info info;
499 u8 valid;
500 #define RVU_CHANL_INFO_RESERVED 379
501 u8 reserved[RVU_CHANL_INFO_RESERVED];
502 };
503
504 struct altaf_intr_notify {
505 unsigned long flr_pf_bmap[2];
506 unsigned long flr_vf_bmap[2];
507 unsigned long gint_paddr;
508 unsigned long gint_iova_addr;
509 unsigned long reserved[6];
510 };
511
512 struct rvu_fwdata {
513 #define RVU_FWDATA_HEADER_MAGIC 0xCFDA /* Custom Firmware Data*/
514 #define RVU_FWDATA_VERSION 0x0001
515 u32 header_magic;
516 u32 version; /* version id */
517
518 /* MAC address */
519 #define PF_MACNUM_MAX 32
520 #define VF_MACNUM_MAX 256
521 u64 pf_macs[PF_MACNUM_MAX];
522 u64 vf_macs[VF_MACNUM_MAX];
523 u64 sclk;
524 u64 rclk;
525 u64 mcam_addr;
526 u64 mcam_sz;
527 u64 msixtr_base;
528 u32 ptp_ext_clk_rate;
529 u32 ptp_ext_tstamp;
530 struct channel_fwdata channel_data;
531 struct altaf_intr_notify altaf_intr_info;
532 #define FWDATA_RESERVED_MEM 946
533 u64 reserved[FWDATA_RESERVED_MEM];
534 #define CGX_MAX 9
535 #define CGX_LMACS_MAX 4
536 #define CGX_LMACS_USX 8
537 #define FWDATA_CGX_LMAC_OFFSET 10536
538 union {
539 struct cgx_lmac_fwdata_s
540 cgx_fw_data[CGX_MAX][CGX_LMACS_MAX];
541 struct cgx_lmac_fwdata_s
542 cgx_fw_data_usx[CGX_MAX][CGX_LMACS_USX];
543 };
544 /* Do not add new fields below this line */
545 };
546
547 struct ptp;
548
549 /* KPU profile adapter structure gathering all KPU configuration data and abstracting out the
550 * source where it came from.
551 */
552 struct npc_kpu_profile_adapter {
553 const char *name;
554 u64 version;
555 const struct npc_lt_def_cfg *lt_def;
556 struct npc_kpu_profile_action *ikpu; /* array[pkinds] */
557 struct npc_kpu_profile_action *ikpu2; /* array[pkinds] */
558 struct npc_kpu_profile *kpu; /* array[kpus] */
559 union npc_mcam_key_prfl {
560 const struct npc_mcam_kex *mkex;
561 /* used for cn9k and cn10k */
562 const struct npc_mcam_kex_extr *mkex_extr; /* used for cn20k */
563 } mcam_kex_prfl;
564 struct npc_mcam_kex_hash *mkex_hash;
565 bool custom;
566 size_t pkinds;
567 size_t kpus;
568 bool from_fs;
569 };
570
571 #define RVU_SWITCH_LBK_CHAN 63
572
573 struct rvu_switch {
574 struct mutex switch_lock; /* Serialize flow installation */
575 u32 used_entries;
576 u16 *entry2pcifunc;
577 u16 mode;
578 u16 start_entry;
579 };
580
581 struct rep_evtq_ent {
582 struct list_head node;
583 struct rep_event event;
584 };
585
586 struct rvu {
587 void __iomem *afreg_base;
588 void __iomem *pfreg_base;
589 struct pci_dev *pdev;
590 struct device *dev;
591 struct rvu_hwinfo *hw;
592 struct rvu_pfvf *pf;
593 struct rvu_pfvf *hwvf;
594 struct mutex rsrc_lock; /* Serialize resource alloc/free */
595 struct mutex alias_lock; /* Serialize bar2 alias access */
596 int vfs; /* Number of VFs attached to RVU */
597 u16 vf_devid; /* VF devices id */
598 bool def_rule_cntr_en;
599 int nix_blkaddr[MAX_NIX_BLKS];
600
601 /* Mbox */
602 struct mbox_wq_info afpf_wq_info;
603 struct mbox_wq_info afvf_wq_info;
604
605 /* PF FLR */
606 struct rvu_work *flr_wrk;
607 struct workqueue_struct *flr_wq;
608 struct mutex flr_lock; /* Serialize FLRs */
609
610 /* MSI-X */
611 u16 num_vec;
612 char *irq_name;
613 bool *irq_allocated;
614 dma_addr_t msix_base_iova;
615 u64 msixtr_base_phy; /* Register reset value */
616
617 /* CGX */
618 #define PF_CGXMAP_BASE 1 /* PF 0 is reserved for RVU PF */
619 u16 cgx_mapped_vfs; /* maximum CGX mapped VFs */
620 u8 cgx_mapped_pfs;
621 u8 cgx_cnt_max; /* CGX port count max */
622 u8 *pf2cgxlmac_map; /* pf to cgx_lmac map */
623 u64 *cgxlmac2pf_map; /* bitmap of mapped pfs for
624 * every cgx lmac port
625 */
626 unsigned long pf_notify_bmap; /* Flags for PF notification */
627 void **cgx_idmap; /* cgx id to cgx data map table */
628 struct work_struct cgx_evh_work;
629 struct workqueue_struct *cgx_evh_wq;
630 spinlock_t cgx_evq_lock; /* cgx event queue lock */
631 struct list_head cgx_evq_head; /* cgx event queue head */
632 struct mutex cgx_cfg_lock; /* serialize cgx configuration */
633
634 char mkex_pfl_name[MKEX_NAME_LEN]; /* Configured MKEX profile name */
635 char kpu_pfl_name[KPU_NAME_LEN]; /* Configured KPU profile name */
636
637 /* Firmware data */
638 struct rvu_fwdata *fwdata;
639 const void *kpu_fwdata;
640 size_t kpu_fwdata_sz;
641 void __iomem *kpu_prfl_addr;
642
643 /* NPC KPU data */
644 struct npc_kpu_profile_adapter kpu;
645
646 struct ptp *ptp;
647
648 int mcs_blk_cnt;
649 int cpt_pf_num;
650
651 #ifdef CONFIG_DEBUG_FS
652 struct rvu_debugfs rvu_dbg;
653 #endif
654 struct rvu_devlink *rvu_dl;
655
656 /* RVU switch implementation over NPC with DMAC rules */
657 struct rvu_switch rswitch;
658
659 struct work_struct mcs_intr_work;
660 struct workqueue_struct *mcs_intr_wq;
661 struct list_head mcs_intrq_head;
662 /* mcs interrupt queue lock */
663 spinlock_t mcs_intrq_lock;
664 /* CPT interrupt lock */
665 spinlock_t cpt_intr_lock;
666
667 struct mutex mbox_lock; /* Serialize mbox up and down msgs */
668 u16 rep_pcifunc;
669 bool altaf_ready;
670 int rep_cnt;
671 u16 *rep2pfvf_map;
672 u8 rep_mode;
673 struct work_struct rep_evt_work;
674 struct workqueue_struct *rep_evt_wq;
675 struct list_head rep_evtq_head;
676 /* Representor event lock */
677 spinlock_t rep_evtq_lock;
678
679 struct ng_rvu *ng_rvu;
680 };
681
rvu_write64(struct rvu * rvu,u64 block,u64 offset,u64 val)682 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val)
683 {
684 writeq(val, rvu->afreg_base + ((block << 28) | offset));
685 }
686
rvu_read64(struct rvu * rvu,u64 block,u64 offset)687 static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset)
688 {
689 return readq(rvu->afreg_base + ((block << 28) | offset));
690 }
691
rvupf_write64(struct rvu * rvu,u64 offset,u64 val)692 static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val)
693 {
694 writeq(val, rvu->pfreg_base + offset);
695 }
696
rvupf_read64(struct rvu * rvu,u64 offset)697 static inline u64 rvupf_read64(struct rvu *rvu, u64 offset)
698 {
699 return readq(rvu->pfreg_base + offset);
700 }
701
rvu_bar2_sel_write64(struct rvu * rvu,u64 block,u64 offset,u64 val)702 static inline void rvu_bar2_sel_write64(struct rvu *rvu, u64 block, u64 offset, u64 val)
703 {
704 /* HW requires read back of RVU_AF_BAR2_SEL register to make sure completion of
705 * write operation.
706 */
707 rvu_write64(rvu, block, offset, val);
708 rvu_read64(rvu, block, offset);
709 /* Barrier to ensure read completes before accessing LF registers */
710 mb();
711 }
712
713 /* Silicon revisions */
is_rvu_pre_96xx_C0(struct rvu * rvu)714 static inline bool is_rvu_pre_96xx_C0(struct rvu *rvu)
715 {
716 struct pci_dev *pdev = rvu->pdev;
717 /* 96XX A0/B0, 95XX A0/A1/B0 chips */
718 return ((pdev->revision == 0x00) || (pdev->revision == 0x01) ||
719 (pdev->revision == 0x10) || (pdev->revision == 0x11) ||
720 (pdev->revision == 0x14));
721 }
722
is_rvu_96xx_A0(struct rvu * rvu)723 static inline bool is_rvu_96xx_A0(struct rvu *rvu)
724 {
725 struct pci_dev *pdev = rvu->pdev;
726
727 return (pdev->revision == 0x00);
728 }
729
is_rvu_96xx_B0(struct rvu * rvu)730 static inline bool is_rvu_96xx_B0(struct rvu *rvu)
731 {
732 struct pci_dev *pdev = rvu->pdev;
733
734 return (pdev->revision == 0x00) || (pdev->revision == 0x01);
735 }
736
is_rvu_95xx_A0(struct rvu * rvu)737 static inline bool is_rvu_95xx_A0(struct rvu *rvu)
738 {
739 struct pci_dev *pdev = rvu->pdev;
740
741 return (pdev->revision == 0x10) || (pdev->revision == 0x11);
742 }
743
744 /* REVID for PCIe devices.
745 * Bits 0..1: minor pass, bit 3..2: major pass
746 * bits 7..4: midr id
747 */
748 #define PCI_REVISION_ID_96XX 0x00
749 #define PCI_REVISION_ID_95XX 0x10
750 #define PCI_REVISION_ID_95XXN 0x20
751 #define PCI_REVISION_ID_98XX 0x30
752 #define PCI_REVISION_ID_95XXMM 0x40
753 #define PCI_REVISION_ID_95XXO 0xE0
754
is_rvu_otx2(struct rvu * rvu)755 static inline bool is_rvu_otx2(struct rvu *rvu)
756 {
757 struct pci_dev *pdev = rvu->pdev;
758
759 u8 midr = pdev->revision & 0xF0;
760
761 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX ||
762 midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX ||
763 midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO);
764 }
765
is_cnf10ka_a0(struct rvu * rvu)766 static inline bool is_cnf10ka_a0(struct rvu *rvu)
767 {
768 struct pci_dev *pdev = rvu->pdev;
769
770 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CNF10K_A &&
771 (pdev->revision & 0x0F) == 0x0)
772 return true;
773 return false;
774 }
775
is_cn10ka_a0(struct rvu * rvu)776 static inline bool is_cn10ka_a0(struct rvu *rvu)
777 {
778 struct pci_dev *pdev = rvu->pdev;
779
780 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_A &&
781 (pdev->revision & 0x0F) == 0x0)
782 return true;
783 return false;
784 }
785
is_cn10ka_a1(struct rvu * rvu)786 static inline bool is_cn10ka_a1(struct rvu *rvu)
787 {
788 struct pci_dev *pdev = rvu->pdev;
789
790 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_A &&
791 (pdev->revision & 0x0F) == 0x1)
792 return true;
793 return false;
794 }
795
is_cn10kb(struct rvu * rvu)796 static inline bool is_cn10kb(struct rvu *rvu)
797 {
798 struct pci_dev *pdev = rvu->pdev;
799
800 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_B)
801 return true;
802 return false;
803 }
804
is_cgx_mapped_to_nix(unsigned short id,u8 cgx_id)805 static inline bool is_cgx_mapped_to_nix(unsigned short id, u8 cgx_id)
806 {
807 /* On CNF10KA and CNF10KB silicons only two CGX blocks are connected
808 * to NIX.
809 */
810 if (id == PCI_SUBSYS_DEVID_CNF10K_A || id == PCI_SUBSYS_DEVID_CNF10K_B)
811 return cgx_id <= 1;
812
813 return !(cgx_id && !(id == PCI_SUBSYS_DEVID_96XX ||
814 id == PCI_SUBSYS_DEVID_98XX ||
815 id == PCI_SUBSYS_DEVID_CN10K_A ||
816 id == PCI_SUBSYS_DEVID_CN10K_B));
817 }
818
is_rvu_npc_hash_extract_en(struct rvu * rvu)819 static inline bool is_rvu_npc_hash_extract_en(struct rvu *rvu)
820 {
821 u64 npc_const3;
822
823 npc_const3 = rvu_read64(rvu, BLKADDR_NPC, NPC_AF_CONST3);
824 if (!(npc_const3 & BIT_ULL(62)))
825 return false;
826
827 return true;
828 }
829
rvu_nix_chan_cgx(struct rvu * rvu,u8 cgxid,u8 lmacid,u8 chan)830 static inline u16 rvu_nix_chan_cgx(struct rvu *rvu, u8 cgxid,
831 u8 lmacid, u8 chan)
832 {
833 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST);
834 u16 cgx_chans = nix_const & 0xFFULL;
835 struct rvu_hwinfo *hw = rvu->hw;
836
837 if (!hw->cap.programmable_chans)
838 return NIX_CHAN_CGX_LMAC_CHX(cgxid, lmacid, chan);
839
840 return rvu->hw->cgx_chan_base +
841 (cgxid * hw->lmac_per_cgx + lmacid) * cgx_chans + chan;
842 }
843
rvu_nix_chan_lbk(struct rvu * rvu,u8 lbkid,u8 chan)844 static inline u16 rvu_nix_chan_lbk(struct rvu *rvu, u8 lbkid,
845 u8 chan)
846 {
847 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST);
848 u16 lbk_chans = (nix_const >> 16) & 0xFFULL;
849 struct rvu_hwinfo *hw = rvu->hw;
850
851 if (!hw->cap.programmable_chans)
852 return NIX_CHAN_LBK_CHX(lbkid, chan);
853
854 return rvu->hw->lbk_chan_base + lbkid * lbk_chans + chan;
855 }
856
rvu_nix_chan_sdp(struct rvu * rvu,u8 chan)857 static inline u16 rvu_nix_chan_sdp(struct rvu *rvu, u8 chan)
858 {
859 struct rvu_hwinfo *hw = rvu->hw;
860
861 if (!hw->cap.programmable_chans)
862 return NIX_CHAN_SDP_CHX(chan);
863
864 return hw->sdp_chan_base + chan;
865 }
866
rvu_nix_chan_cpt(struct rvu * rvu,u8 chan)867 static inline u16 rvu_nix_chan_cpt(struct rvu *rvu, u8 chan)
868 {
869 return rvu->hw->cpt_chan_base + chan;
870 }
871
is_rvu_supports_nix1(struct rvu * rvu)872 static inline bool is_rvu_supports_nix1(struct rvu *rvu)
873 {
874 struct pci_dev *pdev = rvu->pdev;
875
876 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_98XX)
877 return true;
878
879 return false;
880 }
881
882 /* Function Prototypes
883 * RVU
884 */
885 #define RVU_LBK_VF_DEVID 0xA0F8
is_lbk_vf(struct rvu * rvu,u16 pcifunc)886 static inline bool is_lbk_vf(struct rvu *rvu, u16 pcifunc)
887 {
888 return (!(pcifunc & ~RVU_PFVF_FUNC_MASK) &&
889 (rvu->vf_devid == RVU_LBK_VF_DEVID));
890 }
891
is_vf(u16 pcifunc)892 static inline bool is_vf(u16 pcifunc)
893 {
894 return !!(pcifunc & RVU_PFVF_FUNC_MASK);
895 }
896
897 /* check if PF_FUNC is AF */
is_pffunc_af(u16 pcifunc)898 static inline bool is_pffunc_af(u16 pcifunc)
899 {
900 return !pcifunc;
901 }
902
is_rvu_fwdata_valid(struct rvu * rvu)903 static inline bool is_rvu_fwdata_valid(struct rvu *rvu)
904 {
905 return (rvu->fwdata->header_magic == RVU_FWDATA_HEADER_MAGIC) &&
906 (rvu->fwdata->version == RVU_FWDATA_VERSION);
907 }
908
909 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc);
910 void rvu_free_bitmap(struct rsrc_bmap *rsrc);
911 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc);
912 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id);
913 bool is_rsrc_free(struct rsrc_bmap *rsrc, int id);
914 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc);
915 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc);
916 void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start);
917 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc);
918 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr);
919 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc);
920 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf);
921 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr);
922 bool is_pf_func_valid(struct rvu *rvu, u16 pcifunc);
923 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype);
924 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot);
925 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf);
926 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc);
927 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero);
928 int rvu_get_num_lbk_chans(void);
929 int rvu_ndc_sync(struct rvu *rvu, int lfblkid, int lfidx, u64 lfoffset);
930 int rvu_get_blkaddr_from_slot(struct rvu *rvu, int blktype, u16 pcifunc,
931 u16 global_slot, u16 *slot_in_block);
932
933 /* RVU HW reg validation */
934 enum regmap_block {
935 TXSCHQ_HWREGMAP = 0,
936 MAX_HWREGMAP,
937 };
938
939 bool rvu_check_valid_reg(int regmap, int regblk, u64 reg);
940
941 /* NPA/NIX AQ APIs */
942 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue,
943 int qsize, int inst_size, int res_size);
944 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq);
945
946 /* SDP APIs */
947 int rvu_sdp_init(struct rvu *rvu);
948 bool is_sdp_pfvf(struct rvu *rvu, u16 pcifunc);
949 bool is_sdp_pf(struct rvu *rvu, u16 pcifunc);
950 bool is_sdp_vf(struct rvu *rvu, u16 pcifunc);
951
is_rep_dev(struct rvu * rvu,u16 pcifunc)952 static inline bool is_rep_dev(struct rvu *rvu, u16 pcifunc)
953 {
954 if (rvu->rep_pcifunc && rvu->rep_pcifunc == pcifunc)
955 return true;
956
957 return false;
958 }
959
rvu_get_pf(struct pci_dev * pdev,u16 pcifunc)960 static inline int rvu_get_pf(struct pci_dev *pdev, u16 pcifunc)
961 {
962 if (is_cn20k(pdev))
963 return (pcifunc >> RVU_CN20K_PFVF_PF_SHIFT) &
964 RVU_CN20K_PFVF_PF_MASK;
965 else
966 return (pcifunc >> RVU_OTX2_PFVF_PF_SHIFT) &
967 RVU_OTX2_PFVF_PF_MASK;
968 }
969
970 /* CGX APIs */
is_pf_cgxmapped(struct rvu * rvu,u8 pf)971 static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf)
972 {
973 return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs) &&
974 !is_sdp_pf(rvu, rvu_make_pcifunc(rvu->pdev, pf, 0));
975 }
976
rvu_get_cgx_lmac_id(u8 map,u8 * cgx_id,u8 * lmac_id)977 static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id)
978 {
979 *cgx_id = (map >> 4) & 0xF;
980 *lmac_id = (map & 0xF);
981 }
982
is_cgx_vf(struct rvu * rvu,u16 pcifunc)983 static inline bool is_cgx_vf(struct rvu *rvu, u16 pcifunc)
984 {
985 return ((pcifunc & RVU_PFVF_FUNC_MASK) &&
986 is_pf_cgxmapped(rvu, rvu_get_pf(rvu->pdev, pcifunc)));
987 }
988
989 #define M(_name, _id, fn_name, req, rsp) \
990 int rvu_mbox_handler_ ## fn_name(struct rvu *, struct req *, struct rsp *);
991 MBOX_MESSAGES
992 #undef M
993
994 /* Mbox APIs */
995 void rvu_queue_work(struct mbox_wq_info *mw, int first,
996 int mdevs, u64 intr);
997
998 int rvu_cgx_init(struct rvu *rvu);
999 int rvu_cgx_exit(struct rvu *rvu);
1000 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu);
1001 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start);
1002 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable);
1003 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start);
1004 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id, int index,
1005 int rxtxflag, u64 *stat);
1006 void rvu_cgx_disable_dmac_entries(struct rvu *rvu, u16 pcifunc);
1007
1008 /* NPA APIs */
1009 int rvu_npa_init(struct rvu *rvu);
1010 void rvu_npa_freemem(struct rvu *rvu);
1011 void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf);
1012 int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req,
1013 struct npa_aq_enq_rsp *rsp);
1014
1015 /* NIX APIs */
1016 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc);
1017 int rvu_nix_init(struct rvu *rvu);
1018 int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw,
1019 int blkaddr, u32 cfg);
1020 void rvu_nix_freemem(struct rvu *rvu);
1021 int rvu_get_nixlf_count(struct rvu *rvu);
1022 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf);
1023 int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr);
1024 int nix_update_mce_list(struct rvu *rvu, u16 pcifunc,
1025 struct nix_mce_list *mce_list,
1026 int mce_idx, int mcam_index, bool add);
1027 void nix_get_mce_list(struct rvu *rvu, u16 pcifunc, int type,
1028 struct nix_mce_list **mce_list, int *mce_idx);
1029 struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr);
1030 int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr);
1031 void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc);
1032 int nix_get_struct_ptrs(struct rvu *rvu, u16 pcifunc,
1033 struct nix_hw **nix_hw, int *blkaddr);
1034 int rvu_nix_setup_ratelimit_aggr(struct rvu *rvu, u16 pcifunc,
1035 u16 rq_idx, u16 match_id);
1036 int nix_aq_context_read(struct rvu *rvu, struct nix_hw *nix_hw,
1037 struct nix_cn10k_aq_enq_req *aq_req,
1038 struct nix_cn10k_aq_enq_rsp *aq_rsp,
1039 u16 pcifunc, u8 ctype, u32 qidx);
1040 int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc);
1041 int nix_get_dwrr_mtu_reg(struct rvu_hwinfo *hw, int smq_link_type);
1042 u32 convert_dwrr_mtu_to_bytes(u8 dwrr_mtu);
1043 u32 convert_bytes_to_dwrr_mtu(u32 bytes);
1044 void rvu_nix_tx_tl2_cfg(struct rvu *rvu, int blkaddr, u16 pcifunc,
1045 struct nix_txsch *txsch, bool enable);
1046 void rvu_nix_mcast_flr_free_entries(struct rvu *rvu, u16 pcifunc);
1047 int rvu_nix_mcast_get_mce_index(struct rvu *rvu, u16 pcifunc,
1048 u32 mcast_grp_idx);
1049 int rvu_nix_mcast_update_mcam_entry(struct rvu *rvu, u16 pcifunc,
1050 u32 mcast_grp_idx, u16 mcam_index);
1051 void rvu_nix_flr_free_bpids(struct rvu *rvu, u16 pcifunc);
1052 int rvu_alloc_cint_qint_mem(struct rvu *rvu, struct rvu_pfvf *pfvf,
1053 int blkaddr, int nixlf);
1054 void rvu_block_bcast_xon(struct rvu *rvu, int blkaddr);
1055 int rvu_nix_aq_enq_inst(struct rvu *rvu, struct nix_aq_enq_req *req,
1056 struct nix_aq_enq_rsp *rsp);
1057
1058 /* NPC APIs */
1059 void rvu_npc_freemem(struct rvu *rvu);
1060 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf);
1061 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf);
1062 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool en);
1063 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc,
1064 int nixlf, u64 chan, u8 *mac_addr);
1065 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc,
1066 int nixlf, u64 chan, u8 chan_cnt);
1067 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
1068 bool enable);
1069 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc,
1070 int nixlf, u64 chan);
1071 void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
1072 u64 chan);
1073 void rvu_npc_enable_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
1074 bool enable);
1075
1076 void npc_enadis_default_mce_entry(struct rvu *rvu, u16 pcifunc,
1077 int nixlf, int type, bool enable);
1078 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
1079 bool rvu_npc_enable_mcam_by_entry_index(struct rvu *rvu, int entry, int intf, bool enable);
1080 void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
1081 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
1082 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
1083 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf,
1084 int group, int alg_idx, int mcam_index);
1085 void __rvu_mcam_remove_counter_from_rule(struct rvu *rvu, u16 pcifunc,
1086 struct rvu_npc_mcam_rule *rule);
1087 void __rvu_mcam_add_counter_to_rule(struct rvu *rvu, u16 pcifunc,
1088 struct rvu_npc_mcam_rule *rule,
1089 struct npc_install_flow_rsp *rsp);
1090 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc,
1091 int blkaddr, int *alloc_cnt,
1092 int *enable_cnt);
1093 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc,
1094 int blkaddr, int *alloc_cnt,
1095 int *enable_cnt);
1096 void rvu_npc_clear_ucast_entry(struct rvu *rvu, int pcifunc, int nixlf);
1097
1098 bool is_npc_intf_tx(u8 intf);
1099 bool is_npc_intf_rx(u8 intf);
1100 bool is_npc_interface_valid(struct rvu *rvu, u8 intf);
1101 int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena);
1102 int npc_flow_steering_init(struct rvu *rvu, int blkaddr);
1103 const char *npc_get_field_name(u8 hdr);
1104 int npc_get_bank(struct npc_mcam *mcam, int index);
1105 void npc_mcam_enable_flows(struct rvu *rvu, u16 target);
1106 void npc_mcam_disable_flows(struct rvu *rvu, u16 target);
1107 void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
1108 int blkaddr, int index, bool enable);
1109 u64 npc_get_mcam_action(struct rvu *rvu, struct npc_mcam *mcam,
1110 int blkaddr, int index);
1111 void npc_set_mcam_action(struct rvu *rvu, struct npc_mcam *mcam,
1112 int blkaddr, int index, u64 cfg);
1113 void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
1114 int blkaddr, u16 src, struct mcam_entry *entry,
1115 u8 *intf, u8 *ena);
1116 int npc_config_cntr_default_entries(struct rvu *rvu, bool enable);
1117 bool is_cgx_config_permitted(struct rvu *rvu, u16 pcifunc);
1118 bool rvu_cgx_check_permission_and_set_pkind(struct rvu *rvu, u16 pcifunc, int pkind);
1119 bool rvu_cgx_is_pkind_config_permitted(struct rvu *rvu, u16 pcifunc);
1120 bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature);
1121 u32 rvu_cgx_get_fifolen(struct rvu *rvu);
1122 void *rvu_first_cgx_pdata(struct rvu *rvu);
1123 int cgxlmac_to_pf(struct rvu *rvu, int cgx_id, int lmac_id);
1124 int rvu_cgx_config_tx(void *cgxd, int lmac_id, bool enable);
1125 int rvu_cgx_tx_enable(struct rvu *rvu, u16 pcifunc, bool enable);
1126 int rvu_cgx_prio_flow_ctrl_cfg(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause,
1127 u16 pfc_en);
1128 int rvu_cgx_cfg_pause_frm(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause);
1129 void rvu_mac_reset(struct rvu *rvu, u16 pcifunc);
1130 u32 rvu_cgx_get_lmac_fifolen(struct rvu *rvu, int cgx, int lmac);
1131 void cgx_start_linkup(struct rvu *rvu);
1132 int npc_get_nixlf_mcam_index(struct npc_mcam *mcam,
1133 u16 pcifunc, int nixlf, int type);
1134 bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam, int blkaddr,
1135 int index);
1136 int rvu_npc_init(struct rvu *rvu);
1137 int npc_install_mcam_drop_rule(struct rvu *rvu, int mcam_idx, u16 *counter_idx,
1138 u64 chan_val, u64 chan_mask, u64 exact_val, u64 exact_mask,
1139 u64 bcast_mcast_val, u64 bcast_mcast_mask);
1140 void npc_mcam_rsrcs_reserve(struct rvu *rvu, int blkaddr, int entry_idx);
1141 bool npc_is_feature_supported(struct rvu *rvu, u64 features, u8 intf);
1142 int npc_mcam_rsrcs_init(struct rvu *rvu, int blkaddr);
1143 void npc_mcam_rsrcs_deinit(struct rvu *rvu);
1144
1145 /* CPT APIs */
1146 int rvu_cpt_register_interrupts(struct rvu *rvu);
1147 void rvu_cpt_unregister_interrupts(struct rvu *rvu);
1148 int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int lf,
1149 int slot);
1150 int rvu_cpt_ctx_flush(struct rvu *rvu, u16 pcifunc);
1151 int rvu_cpt_init(struct rvu *rvu);
1152 u32 rvu_get_cpt_chan_mask(struct rvu *rvu);
1153
1154 #define NDC_AF_BANK_MASK GENMASK_ULL(7, 0)
1155 #define NDC_AF_BANK_LINE_MASK GENMASK_ULL(31, 16)
1156
1157 /* CN10K RVU */
1158 int rvu_set_channels_base(struct rvu *rvu);
1159 void rvu_program_channels(struct rvu *rvu);
1160
1161 /* CN10K NIX */
1162 void rvu_nix_block_cn10k_init(struct rvu *rvu, struct nix_hw *nix_hw);
1163
1164 /* CN10K RVU - LMT*/
1165 void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc);
1166 void rvu_apr_block_cn10k_init(struct rvu *rvu);
1167
1168 #ifdef CONFIG_DEBUG_FS
1169 void rvu_dbg_init(struct rvu *rvu);
1170 void rvu_dbg_exit(struct rvu *rvu);
1171 #else
rvu_dbg_init(struct rvu * rvu)1172 static inline void rvu_dbg_init(struct rvu *rvu) {}
rvu_dbg_exit(struct rvu * rvu)1173 static inline void rvu_dbg_exit(struct rvu *rvu) {}
1174 #endif
1175
1176 int rvu_ndc_fix_locked_cacheline(struct rvu *rvu, int blkaddr);
1177
1178 /* RVU Switch */
1179 void rvu_switch_enable(struct rvu *rvu);
1180 void rvu_switch_disable(struct rvu *rvu);
1181 void rvu_switch_update_rules(struct rvu *rvu, u16 pcifunc, bool ena);
1182 void rvu_switch_enable_lbk_link(struct rvu *rvu, u16 pcifunc, bool ena);
1183
1184 int rvu_npc_set_parse_mode(struct rvu *rvu, u16 pcifunc, u64 mode, u8 dir,
1185 u64 pkind, u8 var_len_off, u8 var_len_off_mask,
1186 u8 shift_dir, u8 skip_size);
1187 int rvu_get_hwvf(struct rvu *rvu, int pcifunc);
1188
1189 /* CN10K MCS */
1190 int rvu_mcs_init(struct rvu *rvu);
1191 int rvu_mcs_flr_handler(struct rvu *rvu, u16 pcifunc);
1192 void rvu_mcs_ptp_cfg(struct rvu *rvu, u8 rpm_id, u8 lmac_id, bool ena);
1193 void rvu_mcs_exit(struct rvu *rvu);
1194
1195 /* Representor APIs */
1196 int rvu_rep_pf_init(struct rvu *rvu);
1197 int rvu_rep_install_mcam_rules(struct rvu *rvu);
1198 void rvu_rep_update_rules(struct rvu *rvu, u16 pcifunc, bool ena);
1199 int rvu_rep_notify_pfvf_state(struct rvu *rvu, u16 pcifunc, bool enable);
1200 int npc_mcam_verify_entry(struct npc_mcam *mcam, u16 pcifunc, int entry);
1201 #endif /* RVU_H */
1202