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/linux/sound/soc/ux500/
H A Dux500_msp_i2s.c138 writel(temp_reg, msp->registers + MSP_TCF); in set_prot_desc_tx()
166 writel(temp_reg, msp->registers + MSP_RCF); in set_prot_desc_rx()
203 temp_reg = readl(msp->registers + MSP_GCR) & ~TX_CLK_POL_RISING; in configure_protocol()
205 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
206 temp_reg = readl(msp->registers + MSP_GCR) & ~RX_CLK_POL_RISING; in configure_protocol()
208 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
222 reg_val_GCR = readl(msp->registers + MSP_GCR); in setup_bitclk()
223 writel(reg_val_GCR & ~SRG_ENABLE, msp->registers + MSP_GCR); in setup_bitclk()
255 writel(temp_reg, msp->registers + MSP_SRG); in setup_bitclk()
261 reg_val_GCR = readl(msp->registers + MSP_GCR); in setup_bitclk()
[all …]
/linux/drivers/media/radio/si470x/
H A Dradio-si470x-common.c185 radio->registers[SYSCONFIG2] &= ~SYSCONFIG2_BAND; in si470x_set_band()
186 radio->registers[SYSCONFIG2] |= radio->band << 6; in si470x_set_band()
203 if ((radio->registers[POWERCFG] & (POWERCFG_ENABLE|POWERCFG_DMUTE)) in si470x_set_chan()
209 radio->registers[CHANNEL] &= ~CHANNEL_CHAN; in si470x_set_chan()
210 radio->registers[CHANNEL] |= CHANNEL_TUNE | chan; in si470x_set_chan()
222 if ((radio->registers[STATUSRSSI] & STATUSRSSI_STC) == 0) in si470x_set_chan()
229 radio->registers[CHANNEL] &= ~CHANNEL_TUNE; in si470x_set_chan()
242 switch ((radio->registers[SYSCONFIG2] & SYSCONFIG2_SPACE) >> 4) { in si470x_get_step()
265 chan = radio->registers[READCHAN] & READCHAN_READCHAN; in si470x_get_freq()
327 radio->registers[POWERCFG] |= POWERCFG_SEEK; in si470x_set_seek()
[all …]
/linux/drivers/scsi/smartpqi/
H A Dsmartpqi_sis.c110 status = readl(&ctrl_info->registers->sis_firmware_status); in sis_wait_for_ctrl_ready_with_timeout()
116 &ctrl_info->registers->sis_mailbox[7])); in sis_wait_for_ctrl_ready_with_timeout()
151 status = readl(&ctrl_info->registers->sis_firmware_status); in sis_is_firmware_running()
161 readl(&ctrl_info->registers->sis_mailbox[7])); in sis_is_firmware_running()
168 return readl(&ctrl_info->registers->sis_firmware_status) & in sis_is_kernel_up()
174 return readl(&ctrl_info->registers->sis_product_identifier); in sis_get_product_id()
185 struct pqi_ctrl_registers __iomem *registers; in sis_send_sync_cmd() local
191 registers = ctrl_info->registers; in sis_send_sync_cmd()
194 writel(cmd, &registers->sis_mailbox[0]); in sis_send_sync_cmd()
201 writel(params->mailbox[i], &registers->sis_mailbox[i]); in sis_send_sync_cmd()
[all …]
/linux/tools/testing/selftests/vfio/lib/drivers/ioat/
H A Dioat.c67 void *registers = ioat_channel_registers(device); in ioat_clear_errors() local
76 errors = readl(registers + IOAT_CHANERR_OFFSET); in ioat_clear_errors()
77 writel(errors, registers + IOAT_CHANERR_OFFSET); in ioat_clear_errors()
82 void *registers = ioat_channel_registers(device); in ioat_reset() local
88 writeb(IOAT_CHANCMD_RESET, registers + IOAT2_CHANCMD_OFFSET); in ioat_reset()
91 chancmd = readb(registers + IOAT2_CHANCMD_OFFSET); in ioat_reset()
99 VFIO_ASSERT_EQ(ioat_channel_status(registers), IOAT_CHANSTS_HALTED); in ioat_reset()
136 void *registers = ioat_channel_registers(device); in ioat_handle_error() local
142 readl(registers + IOAT_CHANERR_OFFSET), in ioat_handle_error()
151 void *registers = ioat_channel_registers(device); in ioat_memcpy_wait() local
[all …]
/linux/Documentation/driver-api/media/drivers/ccs/
H A Dccs-regs.asc18 # general status registers
51 # frame format description registers
91 # analog gain description registers
110 # data format description registers
122 # general set-up registers
170 # integration time registers
174 # analog gain registers
179 # digital gain registers
182 # hdr control registers
203 # clock set-up registers
[all …]
/linux/Documentation/devicetree/bindings/powerpc/nintendo/
H A Dwii.txt31 - reg : should contain the VI registers location and length
42 - reg : should contain the PI registers location and length
64 - reg : should contain the DSP registers location and length
76 - reg : should contain the SI registers location and length
87 - reg : should contain the AI registers location and length
97 - reg : should contain the EXI registers location and length
107 - reg : should contain the EHCI registers location and length
117 - reg : should contain the SDHCI registers location and length
126 - reg : should contain the IPC registers location and length
138 - reg : should contain the controller registers location and length
[all …]
H A Dgamecube.txt22 - reg : should contain the VI registers location and length
33 - reg : should contain the PI registers location and length
53 - reg : should contain the DSP registers location and length
74 - reg : should contain the DI registers location and length
85 - reg : should contain the AI registers location and length
97 - reg : should contain the SI registers location and length
107 - reg : should contain the EXI registers location and length
/linux/drivers/char/agp/
H A Dsworks-agp.c39 volatile u8 __iomem *registers; member
239 writeb(1, serverworks_private.registers+SVWRKS_POSTFLUSH); in serverworks_tlbflush()
241 while (readb(serverworks_private.registers+SVWRKS_POSTFLUSH) == 1) { in serverworks_tlbflush()
250 writel(1, serverworks_private.registers+SVWRKS_DIRFLUSH); in serverworks_tlbflush()
252 while (readl(serverworks_private.registers+SVWRKS_DIRFLUSH) == 1) { in serverworks_tlbflush()
271 serverworks_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096); in serverworks_configure()
272 if (!serverworks_private.registers) { in serverworks_configure()
277 writeb(0xA, serverworks_private.registers+SVWRKS_GART_CACHE); in serverworks_configure()
278 readb(serverworks_private.registers+SVWRKS_GART_CACHE); /* PCI Posting. */ in serverworks_configure()
280 writel(agp_bridge->gatt_bus_addr, serverworks_private.registers+SVWRKS_GATTBASE); in serverworks_configure()
[all …]
H A Dati-agp.c51 volatile u8 __iomem *registers; member
177 writel(1, ati_generic_private.registers+ATI_GART_CACHE_CNTRL); in ati_tlbflush()
178 readl(ati_generic_private.registers+ATI_GART_CACHE_CNTRL); /* PCI Posting. */ in ati_tlbflush()
198 iounmap((volatile u8 __iomem *)ati_generic_private.registers); in ati_cleanup()
209 ati_generic_private.registers = (volatile u8 __iomem *) ioremap(reg, 4096); in ati_configure()
211 if (!ati_generic_private.registers) in ati_configure()
225 writel(0x60000, ati_generic_private.registers+ATI_GART_FEATURE_ID); in ati_configure()
226 readl(ati_generic_private.registers+ATI_GART_FEATURE_ID); /* PCI Posting.*/ in ati_configure()
233 writel(agp_bridge->gatt_bus_addr, ati_generic_private.registers+ATI_GART_BASE); in ati_configure()
234 readl(ati_generic_private.registers+ATI_GART_BASE); /* PCI Posting. */ in ati_configure()
/linux/Documentation/arch/sh/
H A Dregister-banks.rst17 In the case of this type of banking, banked registers are mapped directly to
19 can still be used to reference the banked registers (as r0_bank ... r7_bank)
21 in mind when writing code that utilizes these banked registers, for obvious
23 be used rather effectively as scratch registers by the kernel.
25 Presently the kernel uses several of these registers.
28 registers when doing exception handling).
/linux/Documentation/devicetree/bindings/arm/marvell/
H A Dcoherency-fabric.txt18 - reg: Should contain coherency fabric registers location and
22 fabric registers, second pair for the per-CPU fabric registers.
25 for the per-CPU fabric registers.
28 for the per-CPU fabric registers.
/linux/drivers/hv/
H A Dmshv_common.c31 struct hv_register_assoc *registers) in hv_call_get_vp_registers() argument
55 input_page->names[i] = registers[i].name; in hv_call_get_vp_registers()
64 registers[i].value = output_page[i]; in hv_call_get_vp_registers()
66 registers += completed; in hv_call_get_vp_registers()
77 struct hv_register_assoc *registers) in hv_call_set_vp_registers() argument
97 memcpy(input_page->elements, registers, in hv_call_set_vp_registers()
106 registers += completed; in hv_call_set_vp_registers()
/linux/drivers/media/platform/rockchip/rkisp1/
H A Drkisp1-debug.c67 static const struct rkisp1_debug_register registers[] = { in rkisp1_debug_dump_core_regs_show() local
83 return rkisp1_debug_dump_regs(rkisp1, m, 0, registers); in rkisp1_debug_dump_core_regs_show()
89 static const struct rkisp1_debug_register registers[] = { in rkisp1_debug_dump_isp_regs_show() local
103 return rkisp1_debug_dump_regs(rkisp1, m, 0, registers); in rkisp1_debug_dump_isp_regs_show()
109 static const struct rkisp1_debug_register registers[] = { in rkisp1_debug_dump_rsz_regs_show() local
124 return rkisp1_debug_dump_regs(rsz->rkisp1, m, rsz->regs_base, registers); in rkisp1_debug_dump_rsz_regs_show()
130 static const struct rkisp1_debug_register registers[] = { in rkisp1_debug_dump_mi_mp_show() local
142 return rkisp1_debug_dump_regs(rkisp1, m, 0, registers); in rkisp1_debug_dump_mi_mp_show()
/linux/Documentation/devicetree/bindings/powerpc/4xx/
H A Dppc440spe-adma.txt16 - reg : <registers mapping>
17 - dcr-reg : <DCR registers range>
35 - reg : <registers mapping>
36 - dcr-reg : <DCR registers range>
65 - reg : <registers mapping>
83 - dcr-reg : <DCR registers range>
/linux/Documentation/bpf/
H A Dclassic_vs_extended.rst12 - Number of registers increase from 2 to 10:
14 The old format had two registers A and X, and a hidden frame pointer. The
15 new layout extends this to be 10 internal registers and a read-only frame
16 pointer. Since 64-bit CPUs are passing arguments to functions via registers
19 function. Natively, x86_64 passes first 6 arguments in registers, aarch64/
20 sparcv9/mips64 have 7 - 8 registers for arguments; x86_64 has 6 callee saved
21 registers, and aarch64/sparcv9/mips64 have 11 or more callee saved registers.
23 Thus, all eBPF registers map one to one to HW registers on x86_64, aarch64,
30 R0 - R5 are scratch registers and eBPF program needs spill/fill them if
38 via 32-bit subregisters. All eBPF registers are 64-bit with 32-bit lower
[all …]
/linux/drivers/media/platform/nxp/imx8-isi/
H A Dimx8-isi-debug.c29 static const struct debug_regs registers[] = { in mxc_isi_debug_dump_regs_show() local
90 for (i = 0; i < ARRAY_SIZE(registers); ++i) in mxc_isi_debug_dump_regs_show()
92 registers[i].name, registers[i].offset, in mxc_isi_debug_dump_regs_show()
93 mxc_isi_read(pipe, registers[i].offset)); in mxc_isi_debug_dump_regs_show()
/linux/drivers/usb/storage/
H A Dshuttle_usbat.c515 unsigned char *registers, in usbat_hp8200e_rw_block_test() argument
592 data[j<<1] = registers[j]; in usbat_hp8200e_rw_block_test()
678 unsigned char *registers, in usbat_multiple_write() argument
709 data[i<<1] = registers[i]; in usbat_multiple_write()
1054 unsigned char registers[3] = { in usbat_flash_get_sector_count() local
1072 rc = usbat_multiple_write(us, registers, command, 3); in usbat_flash_get_sector_count()
1112 unsigned char registers[7] = { in usbat_flash_read_data() local
1168 result = usbat_multiple_write(us, registers, command, 7); in usbat_flash_read_data()
1203 unsigned char registers[7] = { in usbat_flash_write_data() local
1263 result = usbat_multiple_write(us, registers, command, 7); in usbat_flash_write_data()
[all …]
/linux/Documentation/devicetree/bindings/mips/
H A Dmscc.txt14 The SoC has a few registers (DEVCPU_GCB:CHIP_REGS) handling miscellaneous
20 - reg : Should contain registers location and length
30 The SoC has a few registers (HSIO) handling miscellaneous functionalities:
36 - reg : Should contain registers location and length
/linux/drivers/char/xillybus/
H A Dxillybus_core.c147 ep->registers + fpga_msg_ctrl_reg); in xillybus_isr()
280 iowrite32(0x03, ep->registers + fpga_msg_ctrl_reg); /* Message ACK */ in xillybus_isr()
401 ep->registers + fpga_dma_bufaddr_lowaddr_reg); in xilly_get_dma_buffers()
403 ep->registers + fpga_dma_bufaddr_highaddr_reg); in xilly_get_dma_buffers()
411 ep->registers + fpga_dma_bufno_reg); in xilly_get_dma_buffers()
418 ep->registers + fpga_dma_bufno_reg); in xilly_get_dma_buffers()
644 endpoint->registers + fpga_buf_ctrl_reg); in xilly_obtain_idt()
803 channel->endpoint->registers + in xillybus_read()
888 channel->endpoint->registers + in xillybus_read()
894 channel->endpoint->registers + in xillybus_read()
[all …]
/linux/Documentation/virt/kvm/loongarch/
H A Dhypercalls.rst8 number is put in a0. Up to five arguments may be placed in registers a1 - a5.
34 five generic registers (a1 - a5) used as input parameters. The FP (Floating-
35 point) and vector registers are not utilized as input registers and must
83 bitmap contained in the first two input registers (a1 and a2).
89 and SWI is used for PV IPI inject since there is no VM-exits accessing SWI registers.
/linux/Documentation/virt/kvm/arm/
H A Dvcpu-features.rst19 ID registers.
26 the guest's ID registers to the maximum set of CPU features supported by the
31 registers by writing values to them via the ``KVM_SET_ONE_REG`` ioctl. The ID
32 registers are mutable until the VM has started, i.e. userspace has called
34 are mutable in the ID registers using the ``KVM_ARM_GET_REG_WRITABLE_MASKS``.
/linux/Documentation/devicetree/bindings/sound/
H A Dbrcm,cygnus-audio.txt7 - reg : Should contain audio registers location and length
8 - reg-names: names of the registers listed in "reg" property
10 set of DMA, I2S_OUT and SPDIF registers. "i2s_in" contains
11 a set of I2S_IN registers.
/linux/Documentation/devicetree/bindings/mips/lantiq/
H A Drcu.txt5 where each sub-device has its own set of registers.
8 uses one or multiple register exclusively, but for some registers some
10 With this patch all accesses to the RCU registers will go through
18 - reg : The address and length of the system control registers
/linux/drivers/thermal/ti-soc-thermal/
H A Ddra752-thermal-data.c334 .registers = &dra752_mpu_temp_sensor_registers,
343 .registers = &dra752_gpu_temp_sensor_registers,
350 .registers = &dra752_core_temp_sensor_registers,
357 .registers = &dra752_dspeve_temp_sensor_registers,
364 .registers = &dra752_iva_temp_sensor_registers,
/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dmpic-msgr.txt12 the MPIC containing the message registers.
25 - mpic-msgr-receive-mask: Specifies what registers in the containing block
29 be <u32>. If not present, then all of the message registers in the block
50 // Message registers 0 and 2 in this block can receive interrupts on
59 // Message registers 0 and 2 in this block can receive interrupts on

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