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Searched refs:reg_offset (Results 1 – 25 of 320) sorted by relevance

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/linux/drivers/mfd/
H A Dsec-irq.c21 .reg_offset = 0,
25 .reg_offset = 0,
29 .reg_offset = 0,
33 .reg_offset = 0,
37 .reg_offset = 0,
41 .reg_offset = 0,
45 .reg_offset = 0,
49 .reg_offset = 0,
53 .reg_offset = 1,
57 .reg_offset = 1,
[all …]
H A Dda9052-irq.c37 .reg_offset = 0,
41 .reg_offset = 0,
45 .reg_offset = 0,
49 .reg_offset = 0,
53 .reg_offset = 0,
57 .reg_offset = 0,
61 .reg_offset = 0,
65 .reg_offset = 0,
69 .reg_offset = 1,
73 .reg_offset = 1,
[all …]
H A Dwm5110-tables.c310 [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
311 [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },
312 [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
313 [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
316 .reg_offset = 1, .mask = ARIZONA_DSP4_RAM_RDY_EINT1
319 .reg_offset = 1, .mask = ARIZONA_DSP3_RAM_RDY_EINT1
322 .reg_offset = 1, .mask = ARIZONA_DSP2_RAM_RDY_EINT1
325 .reg_offset = 1, .mask = ARIZONA_DSP1_RAM_RDY_EINT1
328 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ8_EINT1
331 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ7_EINT1
[all …]
H A Dtps65910.c54 .reg_offset = 0,
58 .reg_offset = 0,
62 .reg_offset = 0,
66 .reg_offset = 0,
70 .reg_offset = 0,
74 .reg_offset = 0,
78 .reg_offset = 0,
82 .reg_offset = 0,
88 .reg_offset = 1,
92 .reg_offset = 1,
[all …]
H A Dpalmas.c74 .reg_offset = 1,
78 .reg_offset = 1,
82 .reg_offset = 1,
86 .reg_offset = 1,
90 .reg_offset = 1,
94 .reg_offset = 1,
98 .reg_offset = 1,
102 .reg_offset = 1,
107 .reg_offset = 2,
111 .reg_offset = 2,
[all …]
H A Dcs47l24-tables.c36 [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
37 [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
40 .reg_offset = 1, .mask = ARIZONA_DSP3_RAM_RDY_EINT1
43 .reg_offset = 1, .mask = ARIZONA_DSP2_RAM_RDY_EINT1
46 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ8_EINT1
49 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ7_EINT1
52 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ6_EINT1
55 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ5_EINT1
58 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ4_EINT1
61 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ3_EINT1
[all …]
H A Dmax8907.c115 { .reg_offset = 0, .mask = 1 << 0, },
116 { .reg_offset = 0, .mask = 1 << 1, },
117 { .reg_offset = 0, .mask = 1 << 2, },
118 { .reg_offset = 1, .mask = 1 << 0, },
119 { .reg_offset = 1, .mask = 1 << 1, },
120 { .reg_offset = 1, .mask = 1 << 2, },
121 { .reg_offset = 1, .mask = 1 << 3, },
122 { .reg_offset = 1, .mask = 1 << 4, },
123 { .reg_offset = 1, .mask = 1 << 5, },
124 { .reg_offset = 1, .mask = 1 << 6, },
[all …]
H A Dmax14577.c195 { .reg_offset = 0, .mask = MAX14577_INT1_ADC_MASK, },
196 { .reg_offset = 0, .mask = MAX14577_INT1_ADCLOW_MASK, },
197 { .reg_offset = 0, .mask = MAX14577_INT1_ADCERR_MASK, },
199 { .reg_offset = 1, .mask = MAX14577_INT2_CHGTYP_MASK, },
200 { .reg_offset = 1, .mask = MAX14577_INT2_CHGDETRUN_MASK, },
201 { .reg_offset = 1, .mask = MAX14577_INT2_DCDTMR_MASK, },
202 { .reg_offset = 1, .mask = MAX14577_INT2_DBCHG_MASK, },
203 { .reg_offset = 1, .mask = MAX14577_INT2_VBVOLT_MASK, },
205 { .reg_offset = 2, .mask = MAX14577_INT3_EOC_MASK, },
206 { .reg_offset = 2, .mask = MAX14577_INT3_CGMBC_MASK, },
[all …]
H A Das3722.c89 .reg_offset = 1,
93 .reg_offset = 1,
97 .reg_offset = 1,
101 .reg_offset = 1,
105 .reg_offset = 1,
109 .reg_offset = 1,
113 .reg_offset = 1,
117 .reg_offset = 1,
123 .reg_offset = 2,
127 .reg_offset = 2,
[all …]
H A Dwm8994-irq.c28 .reg_offset = 1,
32 .reg_offset = 1,
36 .reg_offset = 1,
40 .reg_offset = 1,
44 .reg_offset = 1,
48 .reg_offset = 1,
52 .reg_offset = 1,
56 .reg_offset = 1,
60 .reg_offset = 1,
64 .reg_offset = 1,
[all …]
H A Dwm8998-tables.c76 [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
77 [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },
78 [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
79 [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
82 .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1
85 .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1
88 .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1
91 .reg_offset = 2, .mask = ARIZONA_MICDET_EINT1
94 .reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1
97 .reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1
[all …]
H A Dwm5102-tables.c124 [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
125 [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },
126 [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
127 [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
130 .reg_offset = 1, .mask = ARIZONA_DSP1_RAM_RDY_EINT1
133 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1
136 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ1_EINT1
140 .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1
143 .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1
146 .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1
[all …]
H A Dwm8997-tables.c60 [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
61 [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },
62 [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
63 [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
66 .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1
69 .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1
72 .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1
75 .reg_offset = 2, .mask = ARIZONA_MICDET_EINT1
78 .reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1
81 .reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1
[all …]
H A Drk8xx-core.c289 .reg_offset = 0,
293 .reg_offset = 0,
297 .reg_offset = 0,
301 .reg_offset = 0,
305 .reg_offset = 0,
309 .reg_offset = 0,
313 .reg_offset = 0,
317 .reg_offset = 0,
346 .reg_offset = 0,
350 .reg_offset = 0,
[all …]
H A Dda9150-core.c258 .reg_offset = 0,
262 .reg_offset = 0,
266 .reg_offset = 0,
270 .reg_offset = 0,
274 .reg_offset = 0,
278 .reg_offset = 1,
282 .reg_offset = 1,
286 .reg_offset = 1,
290 .reg_offset = 1,
294 .reg_offset = 1,
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Darct_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in arct_reg_base_init()
35 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in arct_reg_base_init()
36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in arct_reg_base_init()
37 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); in arct_reg_base_init()
38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i])); in arct_reg_base_init()
39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in arct_reg_base_init()
40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in arct_reg_base_init()
41 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); in arct_reg_base_init()
42 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); in arct_reg_base_init()
43 adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); in arct_reg_base_init()
[all …]
H A Daldebaran_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in aldebaran_reg_base_init()
35 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in aldebaran_reg_base_init()
36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in aldebaran_reg_base_init()
37 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); in aldebaran_reg_base_init()
38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in aldebaran_reg_base_init()
39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in aldebaran_reg_base_init()
40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in aldebaran_reg_base_init()
41 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); in aldebaran_reg_base_init()
42 adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); in aldebaran_reg_base_init()
43 adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i])); in aldebaran_reg_base_init()
[all …]
H A Ddimgrey_cavefish_reg_init.c35 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
36 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
37 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
38 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
39 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
40 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
41 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
42 adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN0_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
43 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
44 adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
[all …]
H A Dvega10_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega10_reg_base_init()
35 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in vega10_reg_base_init()
36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in vega10_reg_base_init()
37 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); in vega10_reg_base_init()
38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in vega10_reg_base_init()
39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in vega10_reg_base_init()
40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in vega10_reg_base_init()
41 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); in vega10_reg_base_init()
42 adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i])); in vega10_reg_base_init()
43 adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i])); in vega10_reg_base_init()
[all …]
H A Dvega20_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega20_reg_base_init()
35 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in vega20_reg_base_init()
36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in vega20_reg_base_init()
37 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); in vega20_reg_base_init()
38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in vega20_reg_base_init()
39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in vega20_reg_base_init()
40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in vega20_reg_base_init()
41 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); in vega20_reg_base_init()
42 adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i])); in vega20_reg_base_init()
43 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); in vega20_reg_base_init()
[all …]
H A Dsoc15_common.h36 #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
38 (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)+(offset))
51 __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
53 adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
59 …__WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name, …
61 adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name, \
67 __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
75 __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
79 __RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)) + \
83 __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), \
[all …]
H A Dmmsch_v1_0.h61 uint32_t reg_offset : 28; member
66 uint32_t reg_offset : 20; member
99 uint32_t reg_offset, in mmsch_v1_0_insert_direct_wt() argument
102 direct_wt->cmd_header.reg_offset = reg_offset; in mmsch_v1_0_insert_direct_wt()
109 uint32_t reg_offset, in mmsch_v1_0_insert_direct_rd_mod_wt() argument
112 direct_rd_mod_wt->cmd_header.reg_offset = reg_offset; in mmsch_v1_0_insert_direct_rd_mod_wt()
121 uint32_t reg_offset, in mmsch_v1_0_insert_direct_poll() argument
124 direct_poll->cmd_header.reg_offset = reg_offset; in mmsch_v1_0_insert_direct_poll()
H A Dsdma_v4_4.c40 uint32_t sdma_base = adev->reg_offset[SDMA0_HWIP][0][0]; in sdma_v4_4_get_reg_offset()
167 uint32_t reg_offset, in sdma_v4_4_get_ras_error_count() argument
177 if (sdma_v4_4_ras_fields[i].reg_offset != reg_offset) in sdma_v4_4_get_ras_error_count()
202 uint32_t reg_offset = 0; in sdma_v4_4_query_ras_error_count_by_instance() local
204 reg_offset = sdma_v4_4_get_reg_offset(adev, instance, regSDMA0_EDC_COUNTER); in sdma_v4_4_query_ras_error_count_by_instance()
205 reg_value = RREG32(reg_offset); in sdma_v4_4_query_ras_error_count_by_instance()
211 reg_offset = sdma_v4_4_get_reg_offset(adev, instance, regSDMA0_EDC_COUNTER2); in sdma_v4_4_query_ras_error_count_by_instance()
212 reg_value = RREG32(reg_offset); in sdma_v4_4_query_ras_error_count_by_instance()
239 uint32_t reg_offset; in sdma_v4_4_reset_ras_error_count() local
244 reg_offset = sdma_v4_4_get_reg_offset(adev, i, regSDMA0_EDC_COUNTER); in sdma_v4_4_reset_ras_error_count()
[all …]
/linux/drivers/input/misc/
H A Diqs7222.c797 int reg_offset; member
811 .reg_offset = 0,
819 .reg_offset = 0,
827 .reg_offset = 1,
835 .reg_offset = 1,
842 .reg_offset = 1,
849 .reg_offset = 1,
856 .reg_offset = 1,
865 .reg_offset = 2,
872 .reg_offset = 2,
[all …]
/linux/drivers/phy/rockchip/
H A Dphy-rockchip-emmc.c85 unsigned int reg_offset; member
107 rk_phy->reg_offset + GRF_EMMCPHY_CON6, in rockchip_emmc_phy_power()
112 rk_phy->reg_offset + GRF_EMMCPHY_CON6, in rockchip_emmc_phy_power()
165 rk_phy->reg_offset + GRF_EMMCPHY_CON6, in rockchip_emmc_phy_power()
178 rk_phy->reg_offset + GRF_EMMCPHY_STATUS, in rockchip_emmc_phy_power()
188 rk_phy->reg_offset + GRF_EMMCPHY_CON0, in rockchip_emmc_phy_power()
194 rk_phy->reg_offset + GRF_EMMCPHY_CON6, in rockchip_emmc_phy_power()
226 rk_phy->reg_offset + GRF_EMMCPHY_STATUS, in rockchip_emmc_phy_power()
289 rk_phy->reg_offset + GRF_EMMCPHY_CON6, in rockchip_emmc_phy_power_on()
296 rk_phy->reg_offset + GRF_EMMCPHY_CON0, in rockchip_emmc_phy_power_on()
[all …]

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