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Searched refs:reg_idx (Results 1 – 25 of 83) sorted by relevance

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/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_lib.c24 u16 reg_idx, pool; in ixgbe_cache_ring_dcb_sriov() local
36 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
37 for (i = 0, pool = 0; i < adapter->num_rx_queues; i++, reg_idx++) { in ixgbe_cache_ring_dcb_sriov()
39 if ((reg_idx & ~vmdq->mask) >= tcs) { in ixgbe_cache_ring_dcb_sriov()
41 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
43 adapter->rx_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_dcb_sriov()
47 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
48 for (i = 0; i < adapter->num_tx_queues; i++, reg_idx++) { in ixgbe_cache_ring_dcb_sriov()
50 if ((reg_idx & ~vmdq->mask) >= tcs) in ixgbe_cache_ring_dcb_sriov()
51 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
[all …]
H A Dixgbe_main.c1223 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), in ixgbe_pf_handle_tx_hang()
1224 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), in ixgbe_pf_handle_tx_hang()
1495 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); in ixgbe_update_tx_dca()
1499 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); in ixgbe_update_tx_dca()
1525 u8 reg_idx = rx_ring->reg_idx; in ixgbe_update_rx_dca() local
1548 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); in ixgbe_update_rx_dca()
2676 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); in ixgbe_configure_msix()
2679 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); in ixgbe_configure_msix()
3910 u8 reg_idx = ring->reg_idx; in ixgbe_configure_tx_ring() local
3917 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); in ixgbe_configure_tx_ring()
[all …]
/linux/drivers/pmdomain/renesas/
H A Drcar-gen4-sysc.c91 static int clear_irq_flags(unsigned int reg_idx, unsigned int isr_mask) in clear_irq_flags() argument
96 iowrite32(isr_mask, rcar_gen4_sysc_base + SYSCISCR(reg_idx)); in clear_irq_flags()
98 ret = readl_poll_timeout_atomic(rcar_gen4_sysc_base + SYSCISCR(reg_idx), in clear_irq_flags()
112 unsigned int reg_idx, bit_idx; in rcar_gen4_sysc_power() local
121 reg_idx = pdr / NUM_DOMAINS_EACH_REG; in rcar_gen4_sysc_power()
130 iowrite32(ioread32(rcar_gen4_sysc_base + SYSCIER(reg_idx)) | isr_mask, in rcar_gen4_sysc_power()
131 rcar_gen4_sysc_base + SYSCIER(reg_idx)); in rcar_gen4_sysc_power()
132 iowrite32(ioread32(rcar_gen4_sysc_base + SYSCIMR(reg_idx)) | isr_mask, in rcar_gen4_sysc_power()
133 rcar_gen4_sysc_base + SYSCIMR(reg_idx)); in rcar_gen4_sysc_power()
135 ret = clear_irq_flags(reg_idx, isr_mask); in rcar_gen4_sysc_power()
[all …]
/linux/drivers/i2c/
H A Di2c-slave-testunit.c47 u8 reg_idx; member
86 bool is_proc_call = tu->reg_idx == 3 && tu->regs[TU_REG_DATAL] == 1 && in i2c_slave_testunit_slave_cb()
88 bool is_get_version = tu->reg_idx == 3 && in i2c_slave_testunit_slave_cb()
100 tu->reg_idx = 0; in i2c_slave_testunit_slave_cb()
110 if (tu->reg_idx < TU_NUM_REGS) in i2c_slave_testunit_slave_cb()
111 tu->regs[tu->reg_idx] = *val; in i2c_slave_testunit_slave_cb()
115 if (tu->reg_idx <= TU_NUM_REGS) in i2c_slave_testunit_slave_cb()
116 tu->reg_idx++; in i2c_slave_testunit_slave_cb()
125 if (tu->reg_idx == TU_NUM_REGS) { in i2c_slave_testunit_slave_cb()
136 tu->reg_idx = 0; in i2c_slave_testunit_slave_cb()
/linux/drivers/irqchip/
H A Dirq-mvebu-sei.c61 u32 reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_ack_irq() local
64 sei->base + GICP_SECR(reg_idx)); in mvebu_sei_ack_irq()
70 u32 reg, reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_mask_irq() local
75 reg = readl_relaxed(sei->base + GICP_SEMR(reg_idx)); in mvebu_sei_mask_irq()
77 writel_relaxed(reg, sei->base + GICP_SEMR(reg_idx)); in mvebu_sei_mask_irq()
84 u32 reg, reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_unmask_irq() local
89 reg = readl_relaxed(sei->base + GICP_SEMR(reg_idx)); in mvebu_sei_unmask_irq()
91 writel_relaxed(reg, sei->base + GICP_SEMR(reg_idx)); in mvebu_sei_unmask_irq()
342 u32 reg_idx; in mvebu_sei_reset() local
345 for (reg_idx = 0; reg_idx < SEI_IRQ_REG_COUNT; reg_idx++) { in mvebu_sei_reset()
[all …]
H A Dirq-pruss-intc.c181 u8 ch, host, reg_idx; in pruss_intc_map() local
193 reg_idx = hwirq / 32; in pruss_intc_map()
197 pruss_intc_write_reg(intc, PRU_INTC_ESR(reg_idx), val); in pruss_intc_map()
198 pruss_intc_write_reg(intc, PRU_INTC_SECR(reg_idx), val); in pruss_intc_map()
224 u8 ch, host, reg_idx; in pruss_intc_unmap() local
241 reg_idx = hwirq / 32; in pruss_intc_unmap()
245 pruss_intc_write_reg(intc, PRU_INTC_ECR(reg_idx), val); in pruss_intc_unmap()
247 pruss_intc_write_reg(intc, PRU_INTC_SECR(reg_idx), val); in pruss_intc_unmap()
/linux/drivers/net/ethernet/wangxun/libwx/
H A Dwx_hw.c1604 j = ring->reg_idx; in wx_vlan_strip_control()
1612 u32 vlnctrl, i, vind, bits, reg_idx; in wx_vlan_promisc_enable() local
1633 reg_idx = WX_VF_REG_OFFSET(VMDQ_P(0)); in wx_vlan_promisc_enable()
1634 bits = rd32(wx, WX_PSR_VLAN_SWC_VM(reg_idx)); in wx_vlan_promisc_enable()
1636 wr32(wx, WX_PSR_VLAN_SWC_VM(reg_idx), bits); in wx_vlan_promisc_enable()
1645 u32 i, vid, bits, vfta, vind, vlvf, reg_idx; in wx_scrub_vfta() local
1659 reg_idx = WX_VF_REG_OFFSET(VMDQ_P(0)); in wx_scrub_vfta()
1660 bits = rd32(wx, WX_PSR_VLAN_SWC_VM(reg_idx)); in wx_scrub_vfta()
1662 wr32(wx, WX_PSR_VLAN_SWC_VM(reg_idx), bits); in wx_scrub_vfta()
1830 u8 reg_idx = ring->reg_idx; in wx_disable_rx_queue() local
[all …]
H A Dwx_lib.c2007 u16 reg_idx; in wx_cache_ring_vmdq() local
2016 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); in wx_cache_ring_vmdq()
2017 for (i = 0; i < wx->num_rx_queues; i++, reg_idx++) { in wx_cache_ring_vmdq()
2019 if ((reg_idx & ~vmdq->mask) >= rss->indices) in wx_cache_ring_vmdq()
2020 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); in wx_cache_ring_vmdq()
2021 wx->rx_ring[i]->reg_idx = reg_idx; in wx_cache_ring_vmdq()
2023 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); in wx_cache_ring_vmdq()
2024 for (i = 0; i < wx->num_tx_queues; i++, reg_idx++) { in wx_cache_ring_vmdq()
2026 if ((reg_idx & rss->mask) >= rss->indices) in wx_cache_ring_vmdq()
2027 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); in wx_cache_ring_vmdq()
[all …]
/linux/drivers/accel/habanalabs/goya/
H A Dgoya_coresight.c236 if (params->reg_idx >= ARRAY_SIZE(debug_stm_regs)) { in goya_config_stm()
241 base_reg = debug_stm_regs[params->reg_idx] - CFG_BASE; in goya_config_stm()
309 if (params->reg_idx >= ARRAY_SIZE(debug_etf_regs)) { in goya_config_etf()
314 base_reg = debug_etf_regs[params->reg_idx] - CFG_BASE; in goya_config_etf()
489 if (params->reg_idx >= ARRAY_SIZE(debug_funnel_regs)) { in goya_config_funnel()
494 base_reg = debug_funnel_regs[params->reg_idx] - CFG_BASE; in goya_config_funnel()
510 if (params->reg_idx >= ARRAY_SIZE(debug_bmon_regs)) { in goya_config_bmon()
515 base_reg = debug_bmon_regs[params->reg_idx] - CFG_BASE; in goya_config_bmon()
539 if (params->reg_idx != GOYA_BMON_PCIE_MSTR_RD && in goya_config_bmon()
540 params->reg_idx != GOYA_BMON_PCIE_MSTR_WR && in goya_config_bmon()
[all …]
/linux/drivers/sh/intc/
H A Dhandle.c41 unsigned int *reg_idx, in _intc_mask_data() argument
48 while (mr && enum_id && *reg_idx < desc->hw.nr_mask_regs) { in _intc_mask_data()
49 mr = desc->hw.mask_regs + *reg_idx; in _intc_mask_data()
82 (*reg_idx)++; in _intc_mask_data()
109 unsigned int *reg_idx, in _intc_prio_data() argument
116 while (pr && enum_id && *reg_idx < desc->hw.nr_prio_regs) { in _intc_prio_data()
117 pr = desc->hw.prio_regs + *reg_idx; in _intc_prio_data()
151 (*reg_idx)++; in _intc_prio_data()
/linux/drivers/clocksource/
H A Dtimer-mediatek-cpux.c37 static u32 mtk_cpux_readl(u32 reg_idx, struct timer_of *to) in mtk_cpux_readl() argument
39 writel(reg_idx, timer_of_base(to) + CPUX_IDX_REG); in mtk_cpux_readl()
43 static void mtk_cpux_writel(u32 val, u32 reg_idx, struct timer_of *to) in mtk_cpux_writel() argument
45 writel(reg_idx, timer_of_base(to) + CPUX_IDX_REG); in mtk_cpux_writel()
/linux/drivers/net/ethernet/intel/ixgbevf/
H A Dixgbevf_main.c204 u32 head = IXGBE_READ_REG(hw, IXGBE_VFTDH(ring->reg_idx)); in ixgbevf_get_tx_pending()
205 u32 tail = IXGBE_READ_REG(hw, IXGBE_VFTDT(ring->reg_idx)); in ixgbevf_get_tx_pending()
389 IXGBE_READ_REG(hw, IXGBE_VFTDH(tx_ring->reg_idx)), in ixgbevf_clean_tx_irq()
390 IXGBE_READ_REG(hw, IXGBE_VFTDT(tx_ring->reg_idx)), in ixgbevf_clean_tx_irq()
1366 ixgbevf_set_ivar(adapter, 0, ring->reg_idx, v_idx); in ixgbevf_configure_msix()
1369 ixgbevf_set_ivar(adapter, 1, ring->reg_idx, v_idx); in ixgbevf_configure_msix()
1692 u8 reg_idx = ring->reg_idx; in ixgbevf_configure_tx_ring() local
1695 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); in ixgbevf_configure_tx_ring()
1698 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(reg_idx), tdba & DMA_BIT_MASK(32)); in ixgbevf_configure_tx_ring()
1699 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(reg_idx), tdba >> 32); in ixgbevf_configure_tx_ring()
[all …]
/linux/drivers/media/platform/mediatek/vcodec/common/
H A Dmtk_vcodec_util.c24 void __iomem *mtk_vcodec_get_reg_addr(void __iomem **reg_base, unsigned int reg_idx) in mtk_vcodec_get_reg_addr() argument
26 if (reg_idx >= NUM_MAX_VCODEC_REG_BASE) { in mtk_vcodec_get_reg_addr()
27 pr_err(MTK_DBG_V4L2_STR "Invalid arguments, reg_idx=%d", reg_idx); in mtk_vcodec_get_reg_addr()
30 return reg_base[reg_idx]; in mtk_vcodec_get_reg_addr()
/linux/drivers/accel/habanalabs/gaudi/
H A Dgaudi_coresight.c398 if (params->reg_idx >= ARRAY_SIZE(debug_stm_regs)) { in gaudi_config_stm()
403 base_reg = debug_stm_regs[params->reg_idx] - CFG_BASE; in gaudi_config_stm()
476 if (params->reg_idx >= ARRAY_SIZE(debug_etf_regs)) { in gaudi_config_etf()
481 base_reg = debug_etf_regs[params->reg_idx] - CFG_BASE; in gaudi_config_etf()
703 if (params->reg_idx >= ARRAY_SIZE(debug_funnel_regs)) { in gaudi_config_funnel()
708 base_reg = debug_funnel_regs[params->reg_idx] - CFG_BASE; in gaudi_config_funnel()
723 if (params->reg_idx >= ARRAY_SIZE(debug_bmon_regs)) { in gaudi_config_bmon()
728 base_reg = debug_bmon_regs[params->reg_idx] - CFG_BASE; in gaudi_config_bmon()
791 if (params->reg_idx >= ARRAY_SIZE(debug_spmu_regs)) { in gaudi_config_spmu()
796 base_reg = debug_spmu_regs[params->reg_idx] - CFG_BASE; in gaudi_config_spmu()
[all …]
/linux/drivers/bus/
H A Dimx-weim.c145 int reg_idx, num_regs; in weim_timing_setup() local
174 for (reg_idx = 0; reg_idx < num_regs; reg_idx++) { in weim_timing_setup()
177 reg_idx * OF_REG_SIZE, &cs_idx); in weim_timing_setup()
/linux/sound/soc/codecs/
H A Dmt6351.c325 int idx, old_idx, offset, reg_idx; in hp_gain_ramp_set() local
342 reg_idx = old_idx; in hp_gain_ramp_set()
345 reg_idx = idx > old_idx ? reg_idx + 1 : reg_idx - 1; in hp_gain_ramp_set()
348 if ((reg_idx >= 0 && reg_idx <= 0x12) || reg_idx == 0x1f) { in hp_gain_ramp_set()
352 (reg_idx << 7) | reg_idx); in hp_gain_ramp_set()
/linux/drivers/net/ethernet/intel/i40e/
H A Di40e_virtchnl_pf.c379 u32 reg, reg_idx; in i40e_config_irq_link_list() local
385 reg_idx = I40E_VPINT_LNKLST0(vf->vf_id); in i40e_config_irq_link_list()
387 reg_idx = I40E_VPINT_LNKLSTN( in i40e_config_irq_link_list()
393 wr32(hw, reg_idx, I40E_VPINT_LNKLST0_FIRSTQ_INDX_MASK); in i40e_config_irq_link_list()
418 wr32(hw, reg_idx, reg); in i40e_config_irq_link_list()
423 reg_idx = I40E_QINT_RQCTL(pf_queue_id); in i40e_config_irq_link_list()
427 reg_idx = I40E_QINT_TQCTL(pf_queue_id); in i40e_config_irq_link_list()
452 wr32(hw, reg_idx, reg); in i40e_config_irq_link_list()
491 u32 v_idx, reg_idx, reg; in i40e_release_rdma_qvlist() local
499 reg_idx = (msix_vf - 1) * vf->vf_id + qv_info->ceq_idx; in i40e_release_rdma_qvlist()
[all …]
H A Di40e_client.c149 u32 reg_idx; in i40e_client_release_qvlist() local
152 reg_idx = I40E_PFINT_LNKLSTN(qv_info->v_idx - 1); in i40e_client_release_qvlist()
153 wr32(&pf->hw, reg_idx, I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK); in i40e_client_release_qvlist()
567 u32 v_idx, i, reg_idx, reg; in i40e_client_setup_qvlist() local
585 reg_idx = I40E_PFINT_LNKLSTN(v_idx - 1); in i40e_client_setup_qvlist()
589 wr32(hw, reg_idx, I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK); in i40e_client_setup_qvlist()
595 wr32(hw, reg_idx, reg); in i40e_client_setup_qvlist()
/linux/drivers/regulator/
H A Dda9121-regulator.c641 int reg_idx = item->reg_index; in da9121_status_poll_on() local
644 bool persisting = (chip->persistent[reg_idx] & item->event_bit); in da9121_status_poll_on()
645 bool now_cleared = !(status[reg_idx] & item->status_bit); in da9121_status_poll_on()
648 clear[reg_idx] |= item->mask_bit; in da9121_status_poll_on()
649 chip->persistent[reg_idx] &= ~item->event_bit; in da9121_status_poll_on()
712 int reg_idx = item->reg_index; in da9121_irq_handler() local
714 bool enabled = !(mask[reg_idx] & item->mask_bit); in da9121_irq_handler()
715 bool active = (event[reg_idx] & item->event_bit); in da9121_irq_handler()
720 chip->persistent[reg_idx] |= item->event_bit; in da9121_irq_handler()
724 handled[reg_idx] |= item->event_bit; in da9121_irq_handler()
/linux/drivers/net/ethernet/intel/igc/
H A Digc_tsn.c380 int reg_idx = adapter->tx_ring[i]->reg_idx; in igc_tsn_disable_offload() local
387 txdctl = rd32(IGC_TXDCTL(reg_idx)); in igc_tsn_disable_offload()
389 wr32(IGC_TXDCTL(reg_idx), txdctl); in igc_tsn_disable_offload()
470 u32 txdctl = rd32(IGC_TXDCTL(ring->reg_idx)); in igc_tsn_enable_offload()
518 wr32(IGC_TXDCTL(ring->reg_idx), txdctl); in igc_tsn_enable_offload()
/linux/drivers/gpio/
H A Dgpio-graniterapids.c180 unsigned int reg_idx = gpio / GNR_PINS_PER_REG; in gnr_gpio_irq_ack() local
182 void __iomem *addr = gnr_gpio_get_reg_addr(priv, GNR_GPI_STATUS_OFFSET, reg_idx); in gnr_gpio_irq_ack()
195 unsigned int reg_idx = gpio / GNR_PINS_PER_REG; in gnr_gpio_irq_mask_unmask() local
197 void __iomem *addr = gnr_gpio_get_reg_addr(priv, GNR_GPI_ENABLE_OFFSET, reg_idx); in gnr_gpio_irq_mask_unmask()
/linux/drivers/hwmon/
H A Dw83791d.c772 u8 reg_idx = 0; in store_pwmenable() local
785 reg_idx = 0; in store_pwmenable()
790 reg_idx = 0; in store_pwmenable()
795 reg_idx = 1; in store_pwmenable()
801 reg_cfg_tmp = w83791d_read(client, W83791D_REG_FAN_CFG[reg_idx]); in store_pwmenable()
805 w83791d_write(client, W83791D_REG_FAN_CFG[reg_idx], reg_cfg_tmp); in store_pwmenable()
879 u8 reg_idx = 0; in store_temp_tolerance() local
888 reg_idx = 0; in store_temp_tolerance()
893 reg_idx = 0; in store_temp_tolerance()
898 reg_idx = 1; in store_temp_tolerance()
[all …]
/linux/drivers/net/ethernet/intel/ice/
H A Dice_sriov.c171 u32 reg_idx, bit_idx; in ice_free_vfs() local
173 reg_idx = (hw->func_caps.vf_base_id + vf->vf_id) / 32; in ice_free_vfs()
175 wr32(hw, GLGEN_VFLRSTAT(reg_idx), BIT(bit_idx)); in ice_free_vfs()
346 q_vector->reg_idx = vf->first_vector_idx + q_vector->vf_reg_idx; in ice_calc_vf_reg_idx()
568 u32 reg, reg_idx, bit_idx; in ice_sriov_trigger_reset_register() local
588 reg_idx = (vf_abs_id) / 32; in ice_sriov_trigger_reset_register()
590 wr32(hw, GLGEN_VFLRSTAT(reg_idx), BIT(bit_idx)); in ice_sriov_trigger_reset_register()
1086 u32 reg_idx, bit_idx; in ice_process_vflr_event() local
1088 reg_idx = (hw->func_caps.vf_base_id + vf->vf_id) / 32; in ice_process_vflr_event()
1091 reg = rd32(hw, GLGEN_VFLRSTAT(reg_idx)); in ice_process_vflr_event()
H A Dice_xsk.c59 reg = rx_ring->reg_idx; in ice_qvec_dis_irq()
65 wr32(hw, GLINT_DYN_CTL(q_vector->reg_idx), 0); in ice_qvec_dis_irq()
80 u16 reg_idx = q_vector->reg_idx; in ice_qvec_cfg_msix() local
88 ice_cfg_txq_interrupt(vsi, _qid, reg_idx, q_vector->tx.itr_idx); in ice_qvec_cfg_msix()
95 ice_cfg_rxq_interrupt(vsi, _qid, reg_idx, q_vector->rx.itr_idx); in ice_qvec_cfg_msix()
/linux/drivers/perf/hisilicon/
H A Dhisi_uncore_l3c_pmu.c223 u32 reg, reg_idx, shift, val; in hisi_l3c_pmu_write_ds() local
234 reg_idx = idx % 4; in hisi_l3c_pmu_write_ds()
235 shift = 8 * reg_idx; in hisi_l3c_pmu_write_ds()
384 u32 reg, reg_idx, shift, val; in hisi_l3c_pmu_write_evtype() local
396 reg_idx = idx % 4; in hisi_l3c_pmu_write_evtype()
397 shift = 8 * reg_idx; in hisi_l3c_pmu_write_evtype()

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