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Searched refs:reg_idx (Results 1 – 25 of 107) sorted by relevance

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/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_lib.c24 u16 reg_idx, pool; in ixgbe_cache_ring_dcb_sriov() local
36 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
37 for (i = 0, pool = 0; i < adapter->num_rx_queues; i++, reg_idx++) { in ixgbe_cache_ring_dcb_sriov()
39 if ((reg_idx & ~vmdq->mask) >= tcs) { in ixgbe_cache_ring_dcb_sriov()
41 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
43 adapter->rx_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_dcb_sriov()
47 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
48 for (i = 0; i < adapter->num_tx_queues; i++, reg_idx++) { in ixgbe_cache_ring_dcb_sriov()
50 if ((reg_idx & ~vmdq->mask) >= tcs) in ixgbe_cache_ring_dcb_sriov()
51 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
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H A Dixgbe_main.c1264 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), in ixgbe_clean_tx_irq()
1265 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), in ixgbe_clean_tx_irq()
1313 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); in ixgbe_update_tx_dca()
1317 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); in ixgbe_update_tx_dca()
1343 u8 reg_idx = rx_ring->reg_idx; in ixgbe_update_rx_dca() local
1366 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); in ixgbe_update_rx_dca()
2499 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); in ixgbe_configure_msix()
2502 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); in ixgbe_configure_msix()
3495 u8 reg_idx = ring->reg_idx; in ixgbe_configure_tx_ring() local
3502 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); in ixgbe_configure_tx_ring()
[all …]
/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_interrupts.c244 int reg_idx; in dpu_core_irq() local
255 for (reg_idx = 0; reg_idx < MDP_INTR_MAX; reg_idx++) { in dpu_core_irq()
256 if (!test_bit(reg_idx, &intr->irq_mask)) in dpu_core_irq()
260 irq_status = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].status_off); in dpu_core_irq()
263 enable_mask = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].en_off); in dpu_core_irq()
267 DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off, in dpu_core_irq()
280 irq_idx = DPU_IRQ_IDX(reg_idx, bit - 1); in dpu_core_irq()
304 int reg_idx; in dpu_hw_intr_enable_irq_locked() local
325 reg_idx = DPU_IRQ_REG(irq_idx); in dpu_hw_intr_enable_irq_locked()
326 reg = &intr->intr_set[reg_idx]; in dpu_hw_intr_enable_irq_locked()
[all …]
H A Ddpu_hw_interrupts.h39 #define DPU_IRQ_IDX(reg_idx, offset) (1 + reg_idx * 32 + offset) argument
/linux/drivers/staging/media/atomisp/pci/css_2401_system/host/
H A Disys_irq_private.h69 const unsigned int reg_idx, in isys_irqc_reg_store() argument
75 assert(reg_idx <= ISYS_IRQ_LEVEL_NO_REG_IDX); in isys_irqc_reg_store()
77 reg_addr = ISYS_IRQ_BASE[isys_irqc_id] + (reg_idx * sizeof(hrt_data)); in isys_irqc_reg_store()
86 const unsigned int reg_idx) in isys_irqc_reg_load() argument
92 assert(reg_idx <= ISYS_IRQ_LEVEL_NO_REG_IDX); in isys_irqc_reg_load()
94 reg_addr = ISYS_IRQ_BASE[isys_irqc_id] + (reg_idx * sizeof(hrt_data)); in isys_irqc_reg_load()
H A Disys_stream2mmio_private.h139 const uint32_t reg_idx) in stream2mmio_reg_load() argument
147 (reg_bank_offset + reg_idx) * sizeof(hrt_data)); in stream2mmio_reg_load()
/linux/drivers/pmdomain/renesas/
H A Drcar-gen4-sysc.c91 static int clear_irq_flags(unsigned int reg_idx, unsigned int isr_mask) in clear_irq_flags() argument
96 iowrite32(isr_mask, rcar_gen4_sysc_base + SYSCISCR(reg_idx)); in clear_irq_flags()
98 ret = readl_poll_timeout_atomic(rcar_gen4_sysc_base + SYSCISCR(reg_idx), in clear_irq_flags()
112 unsigned int reg_idx, bit_idx; in rcar_gen4_sysc_power() local
121 reg_idx = pdr / NUM_DOMAINS_EACH_REG; in rcar_gen4_sysc_power()
130 iowrite32(ioread32(rcar_gen4_sysc_base + SYSCIER(reg_idx)) | isr_mask, in rcar_gen4_sysc_power()
131 rcar_gen4_sysc_base + SYSCIER(reg_idx)); in rcar_gen4_sysc_power()
132 iowrite32(ioread32(rcar_gen4_sysc_base + SYSCIMR(reg_idx)) | isr_mask, in rcar_gen4_sysc_power()
133 rcar_gen4_sysc_base + SYSCIMR(reg_idx)); in rcar_gen4_sysc_power()
135 ret = clear_irq_flags(reg_idx, isr_mask); in rcar_gen4_sysc_power()
[all …]
/linux/drivers/i2c/
H A Di2c-slave-testunit.c46 u8 reg_idx; member
85 bool is_proc_call = tu->reg_idx == 3 && tu->regs[TU_REG_DATAL] == 1 && in i2c_slave_testunit_slave_cb()
87 bool is_get_version = tu->reg_idx == 3 && in i2c_slave_testunit_slave_cb()
97 tu->reg_idx = 0; in i2c_slave_testunit_slave_cb()
105 if (tu->reg_idx < TU_NUM_REGS) in i2c_slave_testunit_slave_cb()
106 tu->regs[tu->reg_idx] = *val; in i2c_slave_testunit_slave_cb()
110 if (tu->reg_idx <= TU_NUM_REGS) in i2c_slave_testunit_slave_cb()
111 tu->reg_idx++; in i2c_slave_testunit_slave_cb()
120 if (tu->reg_idx == TU_NUM_REGS) { in i2c_slave_testunit_slave_cb()
131 tu->reg_idx = 0; in i2c_slave_testunit_slave_cb()
/linux/drivers/irqchip/
H A Dirq-mvebu-sei.c61 u32 reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_ack_irq() local
64 sei->base + GICP_SECR(reg_idx)); in mvebu_sei_ack_irq()
70 u32 reg, reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_mask_irq() local
75 reg = readl_relaxed(sei->base + GICP_SEMR(reg_idx)); in mvebu_sei_mask_irq()
77 writel_relaxed(reg, sei->base + GICP_SEMR(reg_idx)); in mvebu_sei_mask_irq()
84 u32 reg, reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_unmask_irq() local
89 reg = readl_relaxed(sei->base + GICP_SEMR(reg_idx)); in mvebu_sei_unmask_irq()
91 writel_relaxed(reg, sei->base + GICP_SEMR(reg_idx)); in mvebu_sei_unmask_irq()
342 u32 reg_idx; in mvebu_sei_reset() local
345 for (reg_idx = 0; reg_idx < SEI_IRQ_REG_COUNT; reg_idx++) { in mvebu_sei_reset()
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H A Dirq-pruss-intc.c181 u8 ch, host, reg_idx; in pruss_intc_map() local
193 reg_idx = hwirq / 32; in pruss_intc_map()
197 pruss_intc_write_reg(intc, PRU_INTC_ESR(reg_idx), val); in pruss_intc_map()
198 pruss_intc_write_reg(intc, PRU_INTC_SECR(reg_idx), val); in pruss_intc_map()
224 u8 ch, host, reg_idx; in pruss_intc_unmap() local
241 reg_idx = hwirq / 32; in pruss_intc_unmap()
245 pruss_intc_write_reg(intc, PRU_INTC_ECR(reg_idx), val); in pruss_intc_unmap()
247 pruss_intc_write_reg(intc, PRU_INTC_SECR(reg_idx), val); in pruss_intc_unmap()
/linux/drivers/net/ethernet/wangxun/libwx/
H A Dwx_hw.c1303 j = ring->reg_idx; in wx_vlan_strip_control()
1430 u8 reg_idx = ring->reg_idx; in wx_disable_rx_queue() local
1435 wr32m(wx, WX_PX_RR_CFG(reg_idx), in wx_disable_rx_queue()
1440 10, 100, true, wx, WX_PX_RR_CFG(reg_idx)); in wx_disable_rx_queue()
1446 reg_idx); in wx_disable_rx_queue()
1453 u8 reg_idx = ring->reg_idx; in wx_enable_rx_queue() local
1458 1000, 10000, true, wx, WX_PX_RR_CFG(reg_idx)); in wx_enable_rx_queue()
1464 reg_idx); in wx_enable_rx_queue()
1471 u16 reg_idx = rx_ring->reg_idx; in wx_configure_srrctl() local
1474 srrctl = rd32(wx, WX_PX_RR_CFG(reg_idx)); in wx_configure_srrctl()
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/linux/drivers/accel/habanalabs/goya/
H A Dgoya_coresight.c236 if (params->reg_idx >= ARRAY_SIZE(debug_stm_regs)) { in goya_config_stm()
241 base_reg = debug_stm_regs[params->reg_idx] - CFG_BASE; in goya_config_stm()
309 if (params->reg_idx >= ARRAY_SIZE(debug_etf_regs)) { in goya_config_etf()
314 base_reg = debug_etf_regs[params->reg_idx] - CFG_BASE; in goya_config_etf()
489 if (params->reg_idx >= ARRAY_SIZE(debug_funnel_regs)) { in goya_config_funnel()
494 base_reg = debug_funnel_regs[params->reg_idx] - CFG_BASE; in goya_config_funnel()
510 if (params->reg_idx >= ARRAY_SIZE(debug_bmon_regs)) { in goya_config_bmon()
515 base_reg = debug_bmon_regs[params->reg_idx] - CFG_BASE; in goya_config_bmon()
539 if (params->reg_idx != GOYA_BMON_PCIE_MSTR_RD && in goya_config_bmon()
540 params->reg_idx != GOYA_BMON_PCIE_MSTR_WR && in goya_config_bmon()
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/linux/drivers/clocksource/
H A Dtimer-mediatek-cpux.c37 static u32 mtk_cpux_readl(u32 reg_idx, struct timer_of *to) in mtk_cpux_readl() argument
39 writel(reg_idx, timer_of_base(to) + CPUX_IDX_REG); in mtk_cpux_readl()
43 static void mtk_cpux_writel(u32 val, u32 reg_idx, struct timer_of *to) in mtk_cpux_writel() argument
45 writel(reg_idx, timer_of_base(to) + CPUX_IDX_REG); in mtk_cpux_writel()
/linux/drivers/sh/intc/
H A Dhandle.c41 unsigned int *reg_idx, in _intc_mask_data() argument
48 while (mr && enum_id && *reg_idx < desc->hw.nr_mask_regs) { in _intc_mask_data()
49 mr = desc->hw.mask_regs + *reg_idx; in _intc_mask_data()
82 (*reg_idx)++; in _intc_mask_data()
109 unsigned int *reg_idx, in _intc_prio_data() argument
116 while (pr && enum_id && *reg_idx < desc->hw.nr_prio_regs) { in _intc_prio_data()
117 pr = desc->hw.prio_regs + *reg_idx; in _intc_prio_data()
151 (*reg_idx)++; in _intc_prio_data()
/linux/drivers/net/ethernet/intel/fm10k/
H A Dfm10k_pci.c875 u8 reg_idx = ring->reg_idx; in fm10k_configure_tx_ring() local
878 fm10k_write_reg(hw, FM10K_TXDCTL(reg_idx), 0); in fm10k_configure_tx_ring()
884 fm10k_write_reg(hw, FM10K_TDBAL(reg_idx), tdba & DMA_BIT_MASK(32)); in fm10k_configure_tx_ring()
885 fm10k_write_reg(hw, FM10K_TDBAH(reg_idx), tdba >> 32); in fm10k_configure_tx_ring()
886 fm10k_write_reg(hw, FM10K_TDLEN(reg_idx), size); in fm10k_configure_tx_ring()
889 fm10k_write_reg(hw, FM10K_TDH(reg_idx), 0); in fm10k_configure_tx_ring()
890 fm10k_write_reg(hw, FM10K_TDT(reg_idx), 0); in fm10k_configure_tx_ring()
893 ring->tail = &interface->uc_addr[FM10K_TDT(reg_idx)]; in fm10k_configure_tx_ring()
905 fm10k_write_reg(hw, FM10K_TXINT(reg_idx), txint); in fm10k_configure_tx_ring()
908 fm10k_write_reg(hw, FM10K_PFVTCTL(reg_idx), in fm10k_configure_tx_ring()
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/linux/drivers/net/ethernet/intel/ixgbevf/
H A Dixgbevf_main.c199 u32 head = IXGBE_READ_REG(hw, IXGBE_VFTDH(ring->reg_idx)); in ixgbevf_get_tx_pending()
200 u32 tail = IXGBE_READ_REG(hw, IXGBE_VFTDT(ring->reg_idx)); in ixgbevf_get_tx_pending()
384 IXGBE_READ_REG(hw, IXGBE_VFTDH(tx_ring->reg_idx)), in ixgbevf_clean_tx_irq()
385 IXGBE_READ_REG(hw, IXGBE_VFTDT(tx_ring->reg_idx)), in ixgbevf_clean_tx_irq()
1364 ixgbevf_set_ivar(adapter, 0, ring->reg_idx, v_idx); in ixgbevf_configure_msix()
1367 ixgbevf_set_ivar(adapter, 1, ring->reg_idx, v_idx); in ixgbevf_configure_msix()
1690 u8 reg_idx = ring->reg_idx; in ixgbevf_configure_tx_ring() local
1693 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); in ixgbevf_configure_tx_ring()
1696 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(reg_idx), tdba & DMA_BIT_MASK(32)); in ixgbevf_configure_tx_ring()
1697 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(reg_idx), tdba >> 32); in ixgbevf_configure_tx_ring()
[all …]
/linux/drivers/media/platform/mediatek/vcodec/common/
H A Dmtk_vcodec_util.c24 void __iomem *mtk_vcodec_get_reg_addr(void __iomem **reg_base, unsigned int reg_idx) in mtk_vcodec_get_reg_addr() argument
26 if (reg_idx >= NUM_MAX_VCODEC_REG_BASE) { in mtk_vcodec_get_reg_addr()
27 pr_err(MTK_DBG_V4L2_STR "Invalid arguments, reg_idx=%d", reg_idx); in mtk_vcodec_get_reg_addr()
30 return reg_base[reg_idx]; in mtk_vcodec_get_reg_addr()
/linux/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/
H A Disys_irq_public.h30 const unsigned int reg_idx,
34 const unsigned int reg_idx);
/linux/drivers/accel/habanalabs/gaudi/
H A Dgaudi_coresight.c398 if (params->reg_idx >= ARRAY_SIZE(debug_stm_regs)) { in gaudi_config_stm()
403 base_reg = debug_stm_regs[params->reg_idx] - CFG_BASE; in gaudi_config_stm()
476 if (params->reg_idx >= ARRAY_SIZE(debug_etf_regs)) { in gaudi_config_etf()
481 base_reg = debug_etf_regs[params->reg_idx] - CFG_BASE; in gaudi_config_etf()
703 if (params->reg_idx >= ARRAY_SIZE(debug_funnel_regs)) { in gaudi_config_funnel()
708 base_reg = debug_funnel_regs[params->reg_idx] - CFG_BASE; in gaudi_config_funnel()
723 if (params->reg_idx >= ARRAY_SIZE(debug_bmon_regs)) { in gaudi_config_bmon()
728 base_reg = debug_bmon_regs[params->reg_idx] - CFG_BASE; in gaudi_config_bmon()
791 if (params->reg_idx >= ARRAY_SIZE(debug_spmu_regs)) { in gaudi_config_spmu()
796 base_reg = debug_spmu_regs[params->reg_idx] - CFG_BASE; in gaudi_config_spmu()
[all …]
/linux/drivers/bus/
H A Dimx-weim.c145 int reg_idx, num_regs; in weim_timing_setup() local
174 for (reg_idx = 0; reg_idx < num_regs; reg_idx++) { in weim_timing_setup()
177 reg_idx * OF_REG_SIZE, &cs_idx); in weim_timing_setup()
/linux/sound/soc/codecs/
H A Dmt6351.c325 int idx, old_idx, offset, reg_idx; in hp_gain_ramp_set() local
342 reg_idx = old_idx; in hp_gain_ramp_set()
345 reg_idx = idx > old_idx ? reg_idx + 1 : reg_idx - 1; in hp_gain_ramp_set()
348 if ((reg_idx >= 0 && reg_idx <= 0x12) || reg_idx == 0x1f) { in hp_gain_ramp_set()
352 (reg_idx << 7) | reg_idx); in hp_gain_ramp_set()
/linux/include/linux/soc/mediatek/
H A Dmtk-cmdq.h147 u16 reg_idx);
328 int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value);
436 u16 addr_low, u16 reg_idx) in cmdq_pkt_read_s() argument
492 static inline int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value) in cmdq_pkt_assign() argument
/linux/drivers/hwtracing/coresight/
H A Dcoresight-cti-sysfs.c798 int used = 0, reg_idx; in chan_xtrigs_in_show() local
802 for (reg_idx = 0; reg_idx < nr_trig_max; reg_idx++) { in chan_xtrigs_in_show()
803 if (chan_mask & cfg->ctiinen[reg_idx]) in chan_xtrigs_in_show()
804 used += sprintf(buf + used, "%d ", reg_idx); in chan_xtrigs_in_show()
818 int used = 0, reg_idx; in chan_xtrigs_out_show() local
822 for (reg_idx = 0; reg_idx < nr_trig_max; reg_idx++) { in chan_xtrigs_out_show()
823 if (chan_mask & cfg->ctiouten[reg_idx]) in chan_xtrigs_out_show()
824 used += sprintf(buf + used, "%d ", reg_idx); in chan_xtrigs_out_show()
/linux/drivers/perf/hisilicon/
H A Dhisi_uncore_l3c_pmu.c109 u32 reg, reg_idx, shift, val; in hisi_l3c_pmu_write_ds() local
120 reg_idx = idx % 4; in hisi_l3c_pmu_write_ds()
121 shift = 8 * reg_idx; in hisi_l3c_pmu_write_ds()
248 u32 reg, reg_idx, shift, val; in hisi_l3c_pmu_write_evtype() local
258 reg_idx = idx % 4; in hisi_l3c_pmu_write_evtype()
259 shift = 8 * reg_idx; in hisi_l3c_pmu_write_evtype()
/linux/drivers/net/ethernet/intel/i40e/
H A Di40e_client.c149 u32 reg_idx; in i40e_client_release_qvlist() local
152 reg_idx = I40E_PFINT_LNKLSTN(qv_info->v_idx - 1); in i40e_client_release_qvlist()
153 wr32(&pf->hw, reg_idx, I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK); in i40e_client_release_qvlist()
567 u32 v_idx, i, reg_idx, reg; in i40e_client_setup_qvlist() local
585 reg_idx = I40E_PFINT_LNKLSTN(v_idx - 1); in i40e_client_setup_qvlist()
589 wr32(hw, reg_idx, I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK); in i40e_client_setup_qvlist()
595 wr32(hw, reg_idx, reg); in i40e_client_setup_qvlist()

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