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Searched refs:regMMMC_VM_MX_L1_TLB_CNTL (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmmhub_v3_0_2.c207 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_2_init_tlb_regs()
219 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); in mmhub_v3_0_2_init_tlb_regs()
402 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_2_gart_disable()
406 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); in mmhub_v3_0_2_gart_disable()
H A Dmmhub_v3_0_1.c214 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_1_init_tlb_regs()
226 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); in mmhub_v3_0_1_init_tlb_regs()
397 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_1_gart_disable()
401 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); in mmhub_v3_0_1_gart_disable()
H A Dmmhub_v3_0.c215 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_init_tlb_regs()
227 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); in mmhub_v3_0_init_tlb_regs()
410 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_gart_disable()
414 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); in mmhub_v3_0_gart_disable()
H A Dmmhub_v3_3.c210 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_3_init_tlb_regs()
222 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); in mmhub_v3_3_init_tlb_regs()
443 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_3_gart_disable()
447 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); in mmhub_v3_3_gart_disable()
H A Dmmhub_v4_1_0.c216 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v4_1_0_init_tlb_regs()
228 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); in mmhub_v4_1_0_init_tlb_regs()
411 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v4_1_0_gart_disable()
415 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); in mmhub_v4_1_0_gart_disable()
H A Dimu_v12_0.c315 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in imu_v12_init_gfxhub_settings()
/linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_3_3_0_offset.h1304 #define regMMMC_VM_MX_L1_TLB_CNTL … macro
H A Dmmhub_4_1_0_offset.h874 #define regMMMC_VM_MX_L1_TLB_CNTL … macro
H A Dmmhub_3_0_2_offset.h1410 #define regMMMC_VM_MX_L1_TLB_CNTL … macro
H A Dmmhub_3_0_0_offset.h1444 #define regMMMC_VM_MX_L1_TLB_CNTL … macro
H A Dmmhub_3_0_1_offset.h1682 #define regMMMC_VM_MX_L1_TLB_CNTL … macro