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Searched refs:regMMMC_VM_MX_L1_TLB_CNTL (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmmhub_v3_0_2.c206 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_2_init_tlb_regs()
218 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); in mmhub_v3_0_2_init_tlb_regs()
401 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_2_gart_disable()
405 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); in mmhub_v3_0_2_gart_disable()
H A Dmmhub_v3_0_1.c212 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_1_init_tlb_regs()
224 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); in mmhub_v3_0_1_init_tlb_regs()
395 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_1_gart_disable()
399 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); in mmhub_v3_0_1_gart_disable()
H A Dmmhub_v3_0.c207 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_init_tlb_regs()
219 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); in mmhub_v3_0_init_tlb_regs()
402 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_gart_disable()
406 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); in mmhub_v3_0_gart_disable()
H A Dmmhub_v4_1_0.c201 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v4_1_0_init_tlb_regs()
213 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); in mmhub_v4_1_0_init_tlb_regs()
396 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v4_1_0_gart_disable()
400 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); in mmhub_v4_1_0_gart_disable()
H A Dmmhub_v4_2_0.c338 regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v4_2_0_mid_init_tlb_regs()
351 regMMMC_VM_MX_L1_TLB_CNTL, tmp); in mmhub_v4_2_0_mid_init_tlb_regs()
601 regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v4_2_0_mid_gart_disable()
607 regMMMC_VM_MX_L1_TLB_CNTL, tmp); in mmhub_v4_2_0_mid_gart_disable()
H A Dimu_v12_0.c321 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in imu_v12_init_gfxhub_settings()
/linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_3_3_0_offset.h1304 #define regMMMC_VM_MX_L1_TLB_CNTL … macro
H A Dmmhub_4_1_0_offset.h874 #define regMMMC_VM_MX_L1_TLB_CNTL … macro
H A Dmmhub_3_0_2_offset.h1410 #define regMMMC_VM_MX_L1_TLB_CNTL … macro
H A Dmmhub_3_0_0_offset.h1444 #define regMMMC_VM_MX_L1_TLB_CNTL … macro
H A Dmmhub_3_0_1_offset.h1682 #define regMMMC_VM_MX_L1_TLB_CNTL … macro