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Searched refs:regGRBM_GFX_INDEX (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v12.c172 WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX), gfx_index_val); in wave_control_execute_v12()
182 WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX), data); in wave_control_execute_v12()
H A Damdgpu_amdkfd_gfx_v12_1.c175 WREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regGRBM_GFX_INDEX), gfx_index_val); in wave_control_execute_v12_1()
185 WREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regGRBM_GFX_INDEX), data); in wave_control_execute_v12_1()
H A Damdgpu_amdkfd_gfx_v11.c583 WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX), gfx_index_val); in wave_control_execute_v11()
593 WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX), data); in wave_control_execute_v11()
H A Dgfx_v9_4_3.c712 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); in gfx_v9_4_3_xcc_select_se_sh()
1383 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1627 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)},
H A Dmes_v11_0.c648 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, in mes_v11_0_reset_queue_mmio()
H A Dmes_v12_0.c603 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, in mes_v12_0_reset_queue_mmio()
H A Dgfx_v12_1.c660 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); in gfx_v12_1_init_rlcg_reg_access_ctrl()
1632 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); in gfx_v12_1_xcc_select_se_sh()
H A Dgfx_v12_0.c749 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); in gfx_v12_0_init_rlcg_reg_access_ctrl()
1709 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); in gfx_v12_0_select_se_sh()
H A Dgfx_v11_0.c920 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); in gfx_v11_0_init_rlcg_reg_access_ctrl()
2034 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); in gfx_v11_0_select_se_sh()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h5308 #define regGRBM_GFX_INDEX … macro
H A Dgc_9_4_2_offset.h3076 #define regGRBM_GFX_INDEX … macro
H A Dgc_12_0_0_offset.h4566 #define regGRBM_GFX_INDEX … macro
H A Dgc_11_0_3_offset.h7476 #define regGRBM_GFX_INDEX … macro
H A Dgc_11_0_0_offset.h7170 #define regGRBM_GFX_INDEX … macro