| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | imu_v12_0.c | 207 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0xe0000000, 0x1c0000),
211 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000000, 0x1c0000),
213 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000001, 0x1c0000),
215 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000100, 0x1c0000),
217 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000101, 0x1c0000),
219 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0xe0000000, 0x1c0000),
351 if (reg == SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX)) { in program_imu_rlc_ram()
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| H A D | amdgpu_amdkfd_gfx_v12.c | 171 WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX), gfx_index_val); in wave_control_execute_v12()
181 WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX), data); in wave_control_execute_v12()
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| H A D | amdgpu_amdkfd_gfx_v11.c | 582 WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX), gfx_index_val); in wave_control_execute_v11()
592 WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX), data); in wave_control_execute_v11()
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| H A D | gfx_v9_4_3.c | 732 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); in gfx_v9_4_3_xcc_select_se_sh()
1438 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1682 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)},
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| H A D | mes_v11_0.c | 381 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, in mes_v11_0_reset_queue_mmio()
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| H A D | mes_v12_0.c | 403 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, in mes_v12_0_reset_queue_mmio()
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| H A D | gfx_v9_4_2.c | 871 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, 0, regGRBM_GFX_INDEX, data); in gfx_v9_4_2_select_se_sh()
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| H A D | gfx_v12_0.c | 706 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); in gfx_v12_0_init_rlcg_reg_access_ctrl()
1592 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); in gfx_v12_0_select_se_sh()
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| H A D | gfx_v11_0.c | 885 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); in gfx_v11_0_init_rlcg_reg_access_ctrl()
1852 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); in gfx_v11_0_select_se_sh()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_4_3_offset.h | 5308 #define regGRBM_GFX_INDEX … macro
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| H A D | gc_9_4_2_offset.h | 3076 #define regGRBM_GFX_INDEX … macro
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| H A D | gc_11_5_0_offset.h | 5943 #define regGRBM_GFX_INDEX … macro
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| H A D | gc_12_0_0_offset.h | 4566 #define regGRBM_GFX_INDEX … macro
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| H A D | gc_11_0_3_offset.h | 7476 #define regGRBM_GFX_INDEX … macro
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| H A D | gc_11_0_0_offset.h | 7170 #define regGRBM_GFX_INDEX … macro
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