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Searched refs:regGRBM_GFX_INDEX (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dimu_v12_0.c212 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0xe0000000, 0x1c0000),
216 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000000, 0x1c0000),
218 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000001, 0x1c0000),
220 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000100, 0x1c0000),
222 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000101, 0x1c0000),
224 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0xe0000000, 0x1c0000),
356 if (reg == SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX)) { in program_imu_rlc_ram()
H A Dmes_v11_0.c408 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, in mes_v11_0_reset_queue_mmio()
H A Dmes_v12_0.c433 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, in mes_v12_0_reset_queue_mmio()
H A Dgfx_v12_0.c740 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); in gfx_v12_0_init_rlcg_reg_access_ctrl()
1685 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); in gfx_v12_0_select_se_sh()
H A Dgfx_v11_0.c897 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); in gfx_v11_0_init_rlcg_reg_access_ctrl()
1971 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); in gfx_v11_0_select_se_sh()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h5308 #define regGRBM_GFX_INDEX … macro
H A Dgc_9_4_2_offset.h3076 #define regGRBM_GFX_INDEX … macro
H A Dgc_12_0_0_offset.h4566 #define regGRBM_GFX_INDEX … macro
H A Dgc_11_0_3_offset.h7476 #define regGRBM_GFX_INDEX … macro
H A Dgc_11_0_0_offset.h7170 #define regGRBM_GFX_INDEX … macro