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Searched refs:regGCVM_L2_PROTECTION_FAULT_CNTL (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v3_0_3.c413 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v3_0_3_set_fault_enable_default()
443 WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, tmp); in gfxhub_v3_0_3_set_fault_enable_default()
472 SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v3_0_3_init()
H A Dgfxhub_v11_5_0.c428 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v11_5_0_set_fault_enable_default()
458 WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, tmp); in gfxhub_v11_5_0_set_fault_enable_default()
487 SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v11_5_0_init()
H A Dgfxhub_v3_0.c425 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v3_0_set_fault_enable_default()
455 WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, tmp); in gfxhub_v3_0_set_fault_enable_default()
484 SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v3_0_init()
H A Dgfxhub_v12_0.c433 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v12_0_set_fault_enable_default()
463 WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, tmp); in gfxhub_v12_0_set_fault_enable_default()
492 SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v12_0_init()
H A Dimu_v11_0.c220 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, 0x00001ffc, 0xe0000000),
302 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, 0x00001ffc, 0xe0000000),
H A Dimu_v11_0_3.c81 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, 0x00001ffc, 0xe0000000),
H A Dimu_v12_0.c240 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, 0x00001ffc, 0x1c0000),
H A Dgfx_v12_0.c123 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL),
H A Dgfx_v11_0.c168 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL),
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_5_0_offset.h1875 #define regGCVM_L2_PROTECTION_FAULT_CNTL 0x15c8 macro
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H A Dgc_12_0_0_offset.h2782 #define regGCVM_L2_PROTECTION_FAULT_CNTL … macro
H A Dgc_11_0_3_offset.h2888 #define regGCVM_L2_PROTECTION_FAULT_CNTL … macro
H A Dgc_11_0_0_offset.h2746 #define regGCVM_L2_PROTECTION_FAULT_CNTL … macro