Searched refs:regGCVM_L2_CNTL5 (Results 1 – 11 of 11) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | imu_v11_0.c | 223 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL5, 0x00003fe0, 0xe0000000),
306 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL5, 0x00003fe0, 0xe0000000),
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| H A D | imu_v11_0_3.c | 86 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL5, 0x00003fe0, 0xe0000000),
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| H A D | imu_v12_0.c | 244 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL5, 0x00003fe0, 0x1c0000),
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| H A D | gfxhub_v3_0_3.c | 257 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL5, tmp); in gfxhub_v3_0_3_init_cache_regs()
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| H A D | gfxhub_v11_5_0.c | 255 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL5, tmp); in gfxhub_v11_5_0_init_cache_regs()
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| H A D | gfxhub_v3_0.c | 252 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL5, tmp); in gfxhub_v3_0_init_cache_regs()
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| H A D | gfxhub_v12_0.c | 260 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL5, tmp); in gfxhub_v12_0_init_cache_regs()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_11_5_0_offset.h | 1917 #define regGCVM_L2_CNTL5 … macro
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| H A D | gc_12_0_0_offset.h | 2826 #define regGCVM_L2_CNTL5 … macro
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| H A D | gc_11_0_3_offset.h | 2930 #define regGCVM_L2_CNTL5 … macro
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| H A D | gc_11_0_0_offset.h | 2788 #define regGCVM_L2_CNTL5 … macro
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