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Searched refs:regGCVM_L2_CNTL3 (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dimu_v11_0.c222 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL3, 0x00100003, 0xe0000000),
305 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL3, 0x00100003, 0xe0000000),
H A Dgfxhub_v3_0_3.c248 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp); in gfxhub_v3_0_3_init_cache_regs()
393 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, 0); in gfxhub_v3_0_3_gart_disable()
H A Dimu_v11_0_3.c85 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL3, 0x00100003, 0xe0000000),
H A Dgfxhub_v11_5_0.c246 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp); in gfxhub_v11_5_0_init_cache_regs()
403 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, 0); in gfxhub_v11_5_0_gart_disable()
H A Dgfxhub_v3_0.c243 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp); in gfxhub_v3_0_init_cache_regs()
400 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, 0); in gfxhub_v3_0_gart_disable()
H A Dgfxhub_v12_0.c251 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp); in gfxhub_v12_0_init_cache_regs()
408 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, 0); in gfxhub_v12_0_gart_disable()
H A Dimu_v12_0.c243 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL3, 0x00100003, 0x1c0000),
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_5_0_offset.h1863 #define regGCVM_L2_CNTL3 … macro
H A Dgc_12_0_0_offset.h2770 #define regGCVM_L2_CNTL3 … macro
H A Dgc_11_0_3_offset.h2876 #define regGCVM_L2_CNTL3 … macro
H A Dgc_11_0_0_offset.h2734 #define regGCVM_L2_CNTL3 … macro