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Searched refs:regGCVM_CONTEXT1_CNTL (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dimu_v11_0.c215 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT1_CNTL, 0x00000000, 0xe0000000),
227 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT1_CNTL, 0x00000001, 0xe0000000),
293 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT1_CNTL, 0x00000000, 0xe0000000),
310 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT1_CNTL, 0x00000001, 0xe0000000),
H A Dimu_v11_0_3.c77 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT1_CNTL, 0x00000000, 0xe0000000),
89 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT1_CNTL, 0x00000001, 0xe0000000),
H A Dgfxhub_v3_0_3.c302 tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i * hub->ctx_distance); in gfxhub_v3_0_3_setup_vmid_config()
327 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, in gfxhub_v3_0_3_setup_vmid_config()
474 hub->ctx_distance = regGCVM_CONTEXT1_CNTL - regGCVM_CONTEXT0_CNTL; in gfxhub_v3_0_3_init()
H A Dgfxhub_v11_5_0.c300 tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i * hub->ctx_distance); in gfxhub_v11_5_0_setup_vmid_config()
325 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, in gfxhub_v11_5_0_setup_vmid_config()
489 hub->ctx_distance = regGCVM_CONTEXT1_CNTL - regGCVM_CONTEXT0_CNTL; in gfxhub_v11_5_0_init()
H A Dgfxhub_v3_0.c297 tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i * hub->ctx_distance); in gfxhub_v3_0_setup_vmid_config()
322 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, in gfxhub_v3_0_setup_vmid_config()
486 hub->ctx_distance = regGCVM_CONTEXT1_CNTL - regGCVM_CONTEXT0_CNTL; in gfxhub_v3_0_init()
H A Dgfxhub_v12_0.c305 tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i); in gfxhub_v12_0_setup_vmid_config()
330 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, in gfxhub_v12_0_setup_vmid_config()
494 hub->ctx_distance = regGCVM_CONTEXT1_CNTL - regGCVM_CONTEXT0_CNTL; in gfxhub_v12_0_init()
H A Dimu_v12_0.c233 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT1_CNTL, 0x00000000, 0x1c0000),
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_5_0_offset.h2017 #define regGCVM_CONTEXT1_CNTL … macro
H A Dgc_12_0_0_offset.h2894 #define regGCVM_CONTEXT1_CNTL … macro
H A Dgc_11_0_3_offset.h3026 #define regGCVM_CONTEXT1_CNTL … macro
H A Dgc_11_0_0_offset.h2852 #define regGCVM_CONTEXT1_CNTL … macro