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Searched refs:regGCVM_CONTEXT0_CNTL (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v3_0_3.c264 tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL); in gfxhub_v3_0_3_enable_system_domain()
269 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL, tmp); in gfxhub_v3_0_3_enable_system_domain()
381 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL, in gfxhub_v3_0_3_gart_disable()
468 SOC15_REG_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL); in gfxhub_v3_0_3_init()
474 hub->ctx_distance = regGCVM_CONTEXT1_CNTL - regGCVM_CONTEXT0_CNTL; in gfxhub_v3_0_3_init()
H A Dgfxhub_v11_5_0.c262 tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL); in gfxhub_v11_5_0_enable_system_domain()
267 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL, tmp); in gfxhub_v11_5_0_enable_system_domain()
391 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL, in gfxhub_v11_5_0_gart_disable()
483 SOC15_REG_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL); in gfxhub_v11_5_0_init()
489 hub->ctx_distance = regGCVM_CONTEXT1_CNTL - regGCVM_CONTEXT0_CNTL; in gfxhub_v11_5_0_init()
H A Dgfxhub_v3_0.c259 tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL); in gfxhub_v3_0_enable_system_domain()
264 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL, tmp); in gfxhub_v3_0_enable_system_domain()
388 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL, in gfxhub_v3_0_gart_disable()
480 SOC15_REG_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL); in gfxhub_v3_0_init()
486 hub->ctx_distance = regGCVM_CONTEXT1_CNTL - regGCVM_CONTEXT0_CNTL; in gfxhub_v3_0_init()
H A Dgfxhub_v12_0.c267 tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL); in gfxhub_v12_0_enable_system_domain()
272 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL, tmp); in gfxhub_v12_0_enable_system_domain()
396 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL, in gfxhub_v12_0_gart_disable()
488 SOC15_REG_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL); in gfxhub_v12_0_init()
494 hub->ctx_distance = regGCVM_CONTEXT1_CNTL - regGCVM_CONTEXT0_CNTL; in gfxhub_v12_0_init()
H A Dimu_v11_0.c213 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT0_CNTL, 0x00000000, 0xe0000000),
224 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT0_CNTL, 0x00000001, 0xe0000000),
291 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT0_CNTL, 0x00000000, 0xe0000000),
307 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT0_CNTL, 0x00000001, 0xe0000000),
H A Dimu_v11_0_3.c76 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT0_CNTL, 0x00000000, 0xe0000000),
87 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT0_CNTL, 0x00000001, 0xe0000000),
H A Dimu_v12_0.c231 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT0_CNTL, 0x00000000, 0x1c0000),
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_5_0_offset.h2015 #define regGCVM_CONTEXT0_CNTL … macro
H A Dgc_12_0_0_offset.h2892 #define regGCVM_CONTEXT0_CNTL … macro
H A Dgc_11_0_3_offset.h3024 #define regGCVM_CONTEXT0_CNTL … macro
H A Dgc_11_0_0_offset.h2850 #define regGCVM_CONTEXT0_CNTL … macro