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Searched refs:regCP_RB_WPTR_POLL_CNTL (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dimu_v12_0.c188 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCP_RB_WPTR_POLL_CNTL, 0x600100, 0x1c0000),
H A Dgfx_v12_1.c3113 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL); in gfx_v12_1_xcc_update_coarse_grain_clock_gating()
3121 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data); in gfx_v12_1_xcc_update_coarse_grain_clock_gating()
H A Dgfx_v12_0.c4145 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); in gfx_v12_0_update_coarse_grain_clock_gating()
4152 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); in gfx_v12_0_update_coarse_grain_clock_gating()
H A Dgfx_v11_0.c5561 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); in gfx_v11_0_update_coarse_grain_clock_gating()
5568 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h216 #define regCP_RB_WPTR_POLL_CNTL … macro
H A Dgc_9_4_2_offset.h259 #define regCP_RB_WPTR_POLL_CNTL … macro
H A Dgc_12_0_0_offset.h2154 #define regCP_RB_WPTR_POLL_CNTL … macro
H A Dgc_11_0_3_offset.h2062 #define regCP_RB_WPTR_POLL_CNTL … macro
H A Dgc_11_0_0_offset.h2000 #define regCP_RB_WPTR_POLL_CNTL … macro