1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef _nbio_7_9_0_OFFSET_HEADER 24 #define _nbio_7_9_0_OFFSET_HEADER 25 26 27 28 // addressBlock: aid_nbio_nbif0_bif_bx_SYSDEC 29 // base address: 0x0 30 #define regBIF_BX0_PCIE_INDEX 0x000c 31 #define regBIF_BX0_PCIE_INDEX_BASE_IDX 0 32 #define regBIF_BX0_PCIE_DATA 0x000d 33 #define regBIF_BX0_PCIE_DATA_BASE_IDX 0 34 #define regBIF_BX0_PCIE_INDEX2 0x000e 35 #define regBIF_BX0_PCIE_INDEX2_BASE_IDX 0 36 #define regBIF_BX0_PCIE_DATA2 0x000f 37 #define regBIF_BX0_PCIE_DATA2_BASE_IDX 0 38 #define regBIF_BX0_PCIE_INDEX_HI 0x0010 39 #define regBIF_BX0_PCIE_INDEX_HI_BASE_IDX 0 40 #define regBIF_BX0_PCIE_INDEX2_HI 0x0011 41 #define regBIF_BX0_PCIE_INDEX2_HI_BASE_IDX 0 42 #define regBIF_BX0_SBIOS_SCRATCH_0 0x0034 43 #define regBIF_BX0_SBIOS_SCRATCH_0_BASE_IDX 1 44 #define regBIF_BX0_SBIOS_SCRATCH_1 0x0035 45 #define regBIF_BX0_SBIOS_SCRATCH_1_BASE_IDX 1 46 #define regBIF_BX0_SBIOS_SCRATCH_2 0x0036 47 #define regBIF_BX0_SBIOS_SCRATCH_2_BASE_IDX 1 48 #define regBIF_BX0_SBIOS_SCRATCH_3 0x0037 49 #define regBIF_BX0_SBIOS_SCRATCH_3_BASE_IDX 1 50 #define regBIF_BX0_BIOS_SCRATCH_0 0x0038 51 #define regBIF_BX0_BIOS_SCRATCH_0_BASE_IDX 1 52 #define regBIF_BX0_BIOS_SCRATCH_1 0x0039 53 #define regBIF_BX0_BIOS_SCRATCH_1_BASE_IDX 1 54 #define regBIF_BX0_BIOS_SCRATCH_2 0x003a 55 #define regBIF_BX0_BIOS_SCRATCH_2_BASE_IDX 1 56 #define regBIF_BX0_BIOS_SCRATCH_3 0x003b 57 #define regBIF_BX0_BIOS_SCRATCH_3_BASE_IDX 1 58 #define regBIF_BX0_BIOS_SCRATCH_4 0x003c 59 #define regBIF_BX0_BIOS_SCRATCH_4_BASE_IDX 1 60 #define regBIF_BX0_BIOS_SCRATCH_5 0x003d 61 #define regBIF_BX0_BIOS_SCRATCH_5_BASE_IDX 1 62 #define regBIF_BX0_BIOS_SCRATCH_6 0x003e 63 #define regBIF_BX0_BIOS_SCRATCH_6_BASE_IDX 1 64 #define regBIF_BX0_BIOS_SCRATCH_7 0x003f 65 #define regBIF_BX0_BIOS_SCRATCH_7_BASE_IDX 1 66 #define regBIF_BX0_BIOS_SCRATCH_8 0x0040 67 #define regBIF_BX0_BIOS_SCRATCH_8_BASE_IDX 1 68 #define regBIF_BX0_BIOS_SCRATCH_9 0x0041 69 #define regBIF_BX0_BIOS_SCRATCH_9_BASE_IDX 1 70 #define regBIF_BX0_BIOS_SCRATCH_10 0x0042 71 #define regBIF_BX0_BIOS_SCRATCH_10_BASE_IDX 1 72 #define regBIF_BX0_BIOS_SCRATCH_11 0x0043 73 #define regBIF_BX0_BIOS_SCRATCH_11_BASE_IDX 1 74 #define regBIF_BX0_BIOS_SCRATCH_12 0x0044 75 #define regBIF_BX0_BIOS_SCRATCH_12_BASE_IDX 1 76 #define regBIF_BX0_BIOS_SCRATCH_13 0x0045 77 #define regBIF_BX0_BIOS_SCRATCH_13_BASE_IDX 1 78 #define regBIF_BX0_BIOS_SCRATCH_14 0x0046 79 #define regBIF_BX0_BIOS_SCRATCH_14_BASE_IDX 1 80 #define regBIF_BX0_BIOS_SCRATCH_15 0x0047 81 #define regBIF_BX0_BIOS_SCRATCH_15_BASE_IDX 1 82 #define regBIF_BX0_BIF_RLC_INTR_CNTL 0x004c 83 #define regBIF_BX0_BIF_RLC_INTR_CNTL_BASE_IDX 1 84 #define regBIF_BX0_BIF_VCE_INTR_CNTL 0x004d 85 #define regBIF_BX0_BIF_VCE_INTR_CNTL_BASE_IDX 1 86 #define regBIF_BX0_BIF_UVD_INTR_CNTL 0x004e 87 #define regBIF_BX0_BIF_UVD_INTR_CNTL_BASE_IDX 1 88 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR0 0x006c 89 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR0_BASE_IDX 1 90 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0 0x006d 91 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 1 92 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR1 0x006e 93 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR1_BASE_IDX 1 94 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1 0x006f 95 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 1 96 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR2 0x0070 97 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR2_BASE_IDX 1 98 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2 0x0071 99 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 1 100 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR3 0x0072 101 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR3_BASE_IDX 1 102 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3 0x0073 103 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 1 104 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR4 0x0074 105 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR4_BASE_IDX 1 106 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4 0x0075 107 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 1 108 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR5 0x0076 109 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR5_BASE_IDX 1 110 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5 0x0077 111 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 1 112 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR6 0x0078 113 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR6_BASE_IDX 1 114 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6 0x0079 115 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 1 116 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR7 0x007a 117 #define regBIF_BX0_GFX_MMIOREG_CAM_ADDR7_BASE_IDX 1 118 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7 0x007b 119 #define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 1 120 #define regBIF_BX0_GFX_MMIOREG_CAM_CNTL 0x007c 121 #define regBIF_BX0_GFX_MMIOREG_CAM_CNTL_BASE_IDX 1 122 #define regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL 0x007d 123 #define regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 1 124 #define regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL 0x007e 125 #define regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 1 126 #define regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x007f 127 #define regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 1 128 #define regBIF_BX0_DRIVER_SCRATCH_0 0x0080 129 #define regBIF_BX0_DRIVER_SCRATCH_0_BASE_IDX 1 130 #define regBIF_BX0_DRIVER_SCRATCH_1 0x0081 131 #define regBIF_BX0_DRIVER_SCRATCH_1_BASE_IDX 1 132 #define regBIF_BX0_DRIVER_SCRATCH_2 0x0082 133 #define regBIF_BX0_DRIVER_SCRATCH_2_BASE_IDX 1 134 #define regBIF_BX0_DRIVER_SCRATCH_3 0x0083 135 #define regBIF_BX0_DRIVER_SCRATCH_3_BASE_IDX 1 136 #define regBIF_BX0_DRIVER_SCRATCH_4 0x0084 137 #define regBIF_BX0_DRIVER_SCRATCH_4_BASE_IDX 1 138 #define regBIF_BX0_DRIVER_SCRATCH_5 0x0085 139 #define regBIF_BX0_DRIVER_SCRATCH_5_BASE_IDX 1 140 #define regBIF_BX0_DRIVER_SCRATCH_6 0x0086 141 #define regBIF_BX0_DRIVER_SCRATCH_6_BASE_IDX 1 142 #define regBIF_BX0_DRIVER_SCRATCH_7 0x0087 143 #define regBIF_BX0_DRIVER_SCRATCH_7_BASE_IDX 1 144 #define regBIF_BX0_DRIVER_SCRATCH_8 0x0088 145 #define regBIF_BX0_DRIVER_SCRATCH_8_BASE_IDX 1 146 #define regBIF_BX0_DRIVER_SCRATCH_9 0x0089 147 #define regBIF_BX0_DRIVER_SCRATCH_9_BASE_IDX 1 148 #define regBIF_BX0_DRIVER_SCRATCH_10 0x008a 149 #define regBIF_BX0_DRIVER_SCRATCH_10_BASE_IDX 1 150 #define regBIF_BX0_DRIVER_SCRATCH_11 0x008b 151 #define regBIF_BX0_DRIVER_SCRATCH_11_BASE_IDX 1 152 #define regBIF_BX0_DRIVER_SCRATCH_12 0x008c 153 #define regBIF_BX0_DRIVER_SCRATCH_12_BASE_IDX 1 154 #define regBIF_BX0_DRIVER_SCRATCH_13 0x008d 155 #define regBIF_BX0_DRIVER_SCRATCH_13_BASE_IDX 1 156 #define regBIF_BX0_DRIVER_SCRATCH_14 0x008e 157 #define regBIF_BX0_DRIVER_SCRATCH_14_BASE_IDX 1 158 #define regBIF_BX0_DRIVER_SCRATCH_15 0x008f 159 #define regBIF_BX0_DRIVER_SCRATCH_15_BASE_IDX 1 160 #define regBIF_BX0_FW_SCRATCH_0 0x0090 161 #define regBIF_BX0_FW_SCRATCH_0_BASE_IDX 1 162 #define regBIF_BX0_FW_SCRATCH_1 0x0091 163 #define regBIF_BX0_FW_SCRATCH_1_BASE_IDX 1 164 #define regBIF_BX0_FW_SCRATCH_2 0x0092 165 #define regBIF_BX0_FW_SCRATCH_2_BASE_IDX 1 166 #define regBIF_BX0_FW_SCRATCH_3 0x0093 167 #define regBIF_BX0_FW_SCRATCH_3_BASE_IDX 1 168 #define regBIF_BX0_FW_SCRATCH_4 0x0094 169 #define regBIF_BX0_FW_SCRATCH_4_BASE_IDX 1 170 #define regBIF_BX0_FW_SCRATCH_5 0x0095 171 #define regBIF_BX0_FW_SCRATCH_5_BASE_IDX 1 172 #define regBIF_BX0_FW_SCRATCH_6 0x0096 173 #define regBIF_BX0_FW_SCRATCH_6_BASE_IDX 1 174 #define regBIF_BX0_FW_SCRATCH_7 0x0097 175 #define regBIF_BX0_FW_SCRATCH_7_BASE_IDX 1 176 #define regBIF_BX0_FW_SCRATCH_8 0x0098 177 #define regBIF_BX0_FW_SCRATCH_8_BASE_IDX 1 178 #define regBIF_BX0_FW_SCRATCH_9 0x0099 179 #define regBIF_BX0_FW_SCRATCH_9_BASE_IDX 1 180 #define regBIF_BX0_FW_SCRATCH_10 0x009a 181 #define regBIF_BX0_FW_SCRATCH_10_BASE_IDX 1 182 #define regBIF_BX0_FW_SCRATCH_11 0x009b 183 #define regBIF_BX0_FW_SCRATCH_11_BASE_IDX 1 184 #define regBIF_BX0_FW_SCRATCH_12 0x009c 185 #define regBIF_BX0_FW_SCRATCH_12_BASE_IDX 1 186 #define regBIF_BX0_FW_SCRATCH_13 0x009d 187 #define regBIF_BX0_FW_SCRATCH_13_BASE_IDX 1 188 #define regBIF_BX0_FW_SCRATCH_14 0x009e 189 #define regBIF_BX0_FW_SCRATCH_14_BASE_IDX 1 190 #define regBIF_BX0_FW_SCRATCH_15 0x009f 191 #define regBIF_BX0_FW_SCRATCH_15_BASE_IDX 1 192 #define regBIF_BX0_SBIOS_SCRATCH_4 0x00a0 193 #define regBIF_BX0_SBIOS_SCRATCH_4_BASE_IDX 1 194 #define regBIF_BX0_SBIOS_SCRATCH_5 0x00a1 195 #define regBIF_BX0_SBIOS_SCRATCH_5_BASE_IDX 1 196 #define regBIF_BX0_SBIOS_SCRATCH_6 0x00a2 197 #define regBIF_BX0_SBIOS_SCRATCH_6_BASE_IDX 1 198 #define regBIF_BX0_SBIOS_SCRATCH_7 0x00a3 199 #define regBIF_BX0_SBIOS_SCRATCH_7_BASE_IDX 1 200 #define regBIF_BX0_SBIOS_SCRATCH_8 0x00a4 201 #define regBIF_BX0_SBIOS_SCRATCH_8_BASE_IDX 1 202 #define regBIF_BX0_SBIOS_SCRATCH_9 0x00a5 203 #define regBIF_BX0_SBIOS_SCRATCH_9_BASE_IDX 1 204 #define regBIF_BX0_SBIOS_SCRATCH_10 0x00a6 205 #define regBIF_BX0_SBIOS_SCRATCH_10_BASE_IDX 1 206 #define regBIF_BX0_SBIOS_SCRATCH_11 0x00a7 207 #define regBIF_BX0_SBIOS_SCRATCH_11_BASE_IDX 1 208 #define regBIF_BX0_SBIOS_SCRATCH_12 0x00a8 209 #define regBIF_BX0_SBIOS_SCRATCH_12_BASE_IDX 1 210 #define regBIF_BX0_SBIOS_SCRATCH_13 0x00a9 211 #define regBIF_BX0_SBIOS_SCRATCH_13_BASE_IDX 1 212 #define regBIF_BX0_SBIOS_SCRATCH_14 0x00aa 213 #define regBIF_BX0_SBIOS_SCRATCH_14_BASE_IDX 1 214 #define regBIF_BX0_SBIOS_SCRATCH_15 0x00ab 215 #define regBIF_BX0_SBIOS_SCRATCH_15_BASE_IDX 1 216 217 218 // addressBlock: aid_nbio_nbif0_rcc_dwn_dev0_BIFDEC1 219 // base address: 0x0 220 #define regRCC_DWN_DEV0_0_DN_PCIE_RESERVED 0x0060 221 #define regRCC_DWN_DEV0_0_DN_PCIE_RESERVED_BASE_IDX 2 222 #define regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH 0x0061 223 #define regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH_BASE_IDX 2 224 #define regRCC_DWN_DEV0_0_DN_PCIE_CNTL 0x0063 225 #define regRCC_DWN_DEV0_0_DN_PCIE_CNTL_BASE_IDX 2 226 #define regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL 0x0064 227 #define regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL_BASE_IDX 2 228 #define regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2 0x0065 229 #define regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2_BASE_IDX 2 230 #define regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL 0x0066 231 #define regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL_BASE_IDX 2 232 #define regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL 0x0067 233 #define regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL_BASE_IDX 2 234 #define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0 0x0068 235 #define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0_BASE_IDX 2 236 #define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC 0x0069 237 #define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC_BASE_IDX 2 238 #define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2 0x006a 239 #define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2_BASE_IDX 2 240 241 242 // addressBlock: aid_nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 243 // base address: 0x0 244 #define regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL 0x006c 245 #define regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL_BASE_IDX 2 246 #define regRCC_DWNP_DEV0_0_PCIE_RX_CNTL 0x006d 247 #define regRCC_DWNP_DEV0_0_PCIE_RX_CNTL_BASE_IDX 2 248 #define regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL 0x006e 249 #define regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL_BASE_IDX 2 250 #define regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2 0x006f 251 #define regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2_BASE_IDX 2 252 #define regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC 0x0070 253 #define regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC_BASE_IDX 2 254 #define regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP 0x0071 255 #define regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP_BASE_IDX 2 256 257 258 // addressBlock: aid_nbio_nbif0_rcc_ep_dev0_BIFDEC1 259 // base address: 0x0 260 #define regRCC_EP_DEV0_0_EP_PCIE_SCRATCH 0x0040 261 #define regRCC_EP_DEV0_0_EP_PCIE_SCRATCH_BASE_IDX 2 262 #define regRCC_EP_DEV0_0_EP_PCIE_CNTL 0x0042 263 #define regRCC_EP_DEV0_0_EP_PCIE_CNTL_BASE_IDX 2 264 #define regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL 0x0043 265 #define regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL_BASE_IDX 2 266 #define regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS 0x0044 267 #define regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS_BASE_IDX 2 268 #define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2 0x0045 269 #define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2_BASE_IDX 2 270 #define regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL 0x0046 271 #define regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL_BASE_IDX 2 272 #define regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL 0x0047 273 #define regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL_BASE_IDX 2 274 #define regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL 0x0049 275 #define regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL_BASE_IDX 2 276 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x004a 277 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 278 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x004a 279 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 280 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x004a 281 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 282 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x004a 283 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 284 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x004b 285 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 286 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x004b 287 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 288 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x004b 289 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 290 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x004b 291 #define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 292 #define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC 0x004c 293 #define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC_BASE_IDX 2 294 #define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2 0x004d 295 #define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2_BASE_IDX 2 296 #define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP 0x004f 297 #define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP_BASE_IDX 2 298 #define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0x0050 299 #define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 2 300 #define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL 0x0050 301 #define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL_BASE_IDX 2 302 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x0050 303 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 304 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x0051 305 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 306 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x0051 307 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 308 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x0051 309 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 310 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x0051 311 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 312 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x0052 313 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 314 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x0052 315 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 316 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x0052 317 #define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 318 #define regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL 0x0052 319 #define regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL_BASE_IDX 2 320 #define regRCC_EP_DEV0_0_EP_PCIEP_RESERVED 0x0053 321 #define regRCC_EP_DEV0_0_EP_PCIEP_RESERVED_BASE_IDX 2 322 #define regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL 0x0055 323 #define regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL_BASE_IDX 2 324 #define regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID 0x0056 325 #define regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 2 326 #define regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL 0x0057 327 #define regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL_BASE_IDX 2 328 #define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL 0x0058 329 #define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL_BASE_IDX 2 330 #define regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL 0x0059 331 #define regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 2 332 333 334 // addressBlock: aid_nbio_nbif0_bif_bx_pf_SYSPFVFDEC 335 // base address: 0x0 336 #define regBIF_BX_PF0_MM_INDEX 0x0000 337 #define regBIF_BX_PF0_MM_INDEX_BASE_IDX 0 338 #define regBIF_BX_PF0_MM_DATA 0x0001 339 #define regBIF_BX_PF0_MM_DATA_BASE_IDX 0 340 #define regBIF_BX_PF0_MM_INDEX_HI 0x0006 341 #define regBIF_BX_PF0_MM_INDEX_HI_BASE_IDX 0 342 #define regBIF_BX_PF0_RSMU_INDEX 0x0000 343 #define regBIF_BX_PF0_RSMU_INDEX_BASE_IDX 1 344 #define regBIF_BX_PF0_RSMU_DATA 0x0001 345 #define regBIF_BX_PF0_RSMU_DATA_BASE_IDX 1 346 #define regBIF_BX_PF0_RSMU_INDEX_HI 0x0002 347 #define regBIF_BX_PF0_RSMU_INDEX_HI_BASE_IDX 1 348 349 350 // addressBlock: aid_nbio_nbif0_bif_bx_BIFDEC1 351 // base address: 0x0 352 #define regBIF_BX0_CC_BIF_BX_STRAP0 0x00e2 353 #define regBIF_BX0_CC_BIF_BX_STRAP0_BASE_IDX 2 354 #define regBIF_BX0_CC_BIF_BX_PINSTRAP0 0x00e4 355 #define regBIF_BX0_CC_BIF_BX_PINSTRAP0_BASE_IDX 2 356 #define regBIF_BX0_BIF_MM_INDACCESS_CNTL 0x00e6 357 #define regBIF_BX0_BIF_MM_INDACCESS_CNTL_BASE_IDX 2 358 #define regBIF_BX0_BUS_CNTL 0x00e7 359 #define regBIF_BX0_BUS_CNTL_BASE_IDX 2 360 #define regBIF_BX0_BIF_SCRATCH0 0x00e8 361 #define regBIF_BX0_BIF_SCRATCH0_BASE_IDX 2 362 #define regBIF_BX0_BIF_SCRATCH1 0x00e9 363 #define regBIF_BX0_BIF_SCRATCH1_BASE_IDX 2 364 #define regBIF_BX0_BX_RESET_EN 0x00ed 365 #define regBIF_BX0_BX_RESET_EN_BASE_IDX 2 366 #define regBIF_BX0_MM_CFGREGS_CNTL 0x00ee 367 #define regBIF_BX0_MM_CFGREGS_CNTL_BASE_IDX 2 368 #define regBIF_BX0_BX_RESET_CNTL 0x00f0 369 #define regBIF_BX0_BX_RESET_CNTL_BASE_IDX 2 370 #define regBIF_BX0_INTERRUPT_CNTL 0x00f1 371 #define regBIF_BX0_INTERRUPT_CNTL_BASE_IDX 2 372 #define regBIF_BX0_INTERRUPT_CNTL2 0x00f2 373 #define regBIF_BX0_INTERRUPT_CNTL2_BASE_IDX 2 374 #define regBIF_BX0_CLKREQB_PAD_CNTL 0x00f8 375 #define regBIF_BX0_CLKREQB_PAD_CNTL_BASE_IDX 2 376 #define regBIF_BX0_BIF_FEATURES_CONTROL_MISC 0x00fb 377 #define regBIF_BX0_BIF_FEATURES_CONTROL_MISC_BASE_IDX 2 378 #define regBIF_BX0_HDP_ATOMIC_CONTROL_MISC 0x00fc 379 #define regBIF_BX0_HDP_ATOMIC_CONTROL_MISC_BASE_IDX 2 380 #define regBIF_BX0_BIF_DOORBELL_CNTL 0x00fd 381 #define regBIF_BX0_BIF_DOORBELL_CNTL_BASE_IDX 2 382 #define regBIF_BX0_BIF_DOORBELL_INT_CNTL 0x00fe 383 #define regBIF_BX0_BIF_DOORBELL_INT_CNTL_BASE_IDX 2 384 #define regBIF_BX0_BIF_FB_EN 0x0100 385 #define regBIF_BX0_BIF_FB_EN_BASE_IDX 2 386 #define regBIF_BX0_BIF_INTR_CNTL 0x0101 387 #define regBIF_BX0_BIF_INTR_CNTL_BASE_IDX 2 388 #define regBIF_BX0_BIF_MST_TRANS_PENDING_VF 0x0109 389 #define regBIF_BX0_BIF_MST_TRANS_PENDING_VF_BASE_IDX 2 390 #define regBIF_BX0_BIF_SLV_TRANS_PENDING_VF 0x010a 391 #define regBIF_BX0_BIF_SLV_TRANS_PENDING_VF_BASE_IDX 2 392 #define regBIF_BX0_BACO_CNTL 0x010b 393 #define regBIF_BX0_BACO_CNTL_BASE_IDX 2 394 #define regBIF_BX0_BIF_BACO_EXIT_TIME0 0x010c 395 #define regBIF_BX0_BIF_BACO_EXIT_TIME0_BASE_IDX 2 396 #define regBIF_BX0_BIF_BACO_EXIT_TIMER1 0x010d 397 #define regBIF_BX0_BIF_BACO_EXIT_TIMER1_BASE_IDX 2 398 #define regBIF_BX0_BIF_BACO_EXIT_TIMER2 0x010e 399 #define regBIF_BX0_BIF_BACO_EXIT_TIMER2_BASE_IDX 2 400 #define regBIF_BX0_BIF_BACO_EXIT_TIMER3 0x010f 401 #define regBIF_BX0_BIF_BACO_EXIT_TIMER3_BASE_IDX 2 402 #define regBIF_BX0_BIF_BACO_EXIT_TIMER4 0x0110 403 #define regBIF_BX0_BIF_BACO_EXIT_TIMER4_BASE_IDX 2 404 #define regBIF_BX0_MEM_TYPE_CNTL 0x0111 405 #define regBIF_BX0_MEM_TYPE_CNTL_BASE_IDX 2 406 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_CNTL 0x0113 407 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX 2 408 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_0 0x0114 409 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_0_BASE_IDX 2 410 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_1 0x0115 411 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_1_BASE_IDX 2 412 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_2 0x0116 413 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_2_BASE_IDX 2 414 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_3 0x0117 415 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_3_BASE_IDX 2 416 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_4 0x0118 417 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_4_BASE_IDX 2 418 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_5 0x0119 419 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_5_BASE_IDX 2 420 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_6 0x011a 421 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_6_BASE_IDX 2 422 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_7 0x011b 423 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_7_BASE_IDX 2 424 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_8 0x011c 425 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_8_BASE_IDX 2 426 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_9 0x011d 427 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_9_BASE_IDX 2 428 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_10 0x011e 429 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_10_BASE_IDX 2 430 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_11 0x011f 431 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_11_BASE_IDX 2 432 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_12 0x0120 433 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_12_BASE_IDX 2 434 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_13 0x0121 435 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_13_BASE_IDX 2 436 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_14 0x0122 437 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_14_BASE_IDX 2 438 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_15 0x0123 439 #define regBIF_BX0_NBIF_GFX_ADDR_LUT_15_BASE_IDX 2 440 #define regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL 0x012d 441 #define regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 2 442 #define regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL 0x012e 443 #define regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 2 444 #define regBIF_BX0_BIF_RB_CNTL 0x012f 445 #define regBIF_BX0_BIF_RB_CNTL_BASE_IDX 2 446 #define regBIF_BX0_BIF_RB_BASE 0x0130 447 #define regBIF_BX0_BIF_RB_BASE_BASE_IDX 2 448 #define regBIF_BX0_BIF_RB_RPTR 0x0131 449 #define regBIF_BX0_BIF_RB_RPTR_BASE_IDX 2 450 #define regBIF_BX0_BIF_RB_WPTR 0x0132 451 #define regBIF_BX0_BIF_RB_WPTR_BASE_IDX 2 452 #define regBIF_BX0_BIF_RB_WPTR_ADDR_HI 0x0133 453 #define regBIF_BX0_BIF_RB_WPTR_ADDR_HI_BASE_IDX 2 454 #define regBIF_BX0_BIF_RB_WPTR_ADDR_LO 0x0134 455 #define regBIF_BX0_BIF_RB_WPTR_ADDR_LO_BASE_IDX 2 456 #define regBIF_BX0_MAILBOX_INDEX 0x0135 457 #define regBIF_BX0_MAILBOX_INDEX_BASE_IDX 2 458 #define regBIF_BX0_BIF_MP1_INTR_CTRL 0x0142 459 #define regBIF_BX0_BIF_MP1_INTR_CTRL_BASE_IDX 2 460 #define regBIF_BX0_BIF_PERSTB_PAD_CNTL 0x0146 461 #define regBIF_BX0_BIF_PERSTB_PAD_CNTL_BASE_IDX 2 462 #define regBIF_BX0_BIF_PX_EN_PAD_CNTL 0x0147 463 #define regBIF_BX0_BIF_PX_EN_PAD_CNTL_BASE_IDX 2 464 #define regBIF_BX0_BIF_REFPADKIN_PAD_CNTL 0x0148 465 #define regBIF_BX0_BIF_REFPADKIN_PAD_CNTL_BASE_IDX 2 466 #define regBIF_BX0_BIF_CLKREQB_PAD_CNTL 0x0149 467 #define regBIF_BX0_BIF_CLKREQB_PAD_CNTL_BASE_IDX 2 468 #define regBIF_BX0_BIF_PWRBRK_PAD_CNTL 0x014a 469 #define regBIF_BX0_BIF_PWRBRK_PAD_CNTL_BASE_IDX 2 470 471 472 // addressBlock: aid_nbio_nbif0_rcc_dev0_BIFDEC1 473 // base address: 0x0 474 #define regRCC_DEV0_0_RCC_ERR_INT_CNTL 0x0086 475 #define regRCC_DEV0_0_RCC_ERR_INT_CNTL_BASE_IDX 2 476 #define regRCC_DEV0_0_RCC_BACO_CNTL_MISC 0x0087 477 #define regRCC_DEV0_0_RCC_BACO_CNTL_MISC_BASE_IDX 2 478 #define regRCC_DEV0_0_RCC_RESET_EN 0x0088 479 #define regRCC_DEV0_0_RCC_RESET_EN_BASE_IDX 2 480 #define regRCC_DEV0_0_RCC_VDM_SUPPORT 0x0089 481 #define regRCC_DEV0_0_RCC_VDM_SUPPORT_BASE_IDX 2 482 #define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0 0x008a 483 #define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 2 484 #define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1 0x008b 485 #define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 2 486 #define regRCC_DEV0_0_RCC_GPUIOV_REGION 0x008c 487 #define regRCC_DEV0_0_RCC_GPUIOV_REGION_BASE_IDX 2 488 #define regRCC_DEV0_0_RCC_GPU_HOSTVM_EN 0x008d 489 #define regRCC_DEV0_0_RCC_GPU_HOSTVM_EN_BASE_IDX 2 490 #define regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL 0x008e 491 #define regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX 2 492 #define regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET 0x008f 493 #define regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX 2 494 #define regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE 0x008f 495 #define regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX 2 496 #define regRCC_DEV0_0_RCC_PEER_REG_RANGE0 0x00be 497 #define regRCC_DEV0_0_RCC_PEER_REG_RANGE0_BASE_IDX 2 498 #define regRCC_DEV0_0_RCC_PEER_REG_RANGE1 0x00bf 499 #define regRCC_DEV0_0_RCC_PEER_REG_RANGE1_BASE_IDX 2 500 #define regRCC_DEV0_0_RCC_BUS_CNTL 0x00c1 501 #define regRCC_DEV0_0_RCC_BUS_CNTL_BASE_IDX 2 502 #define regRCC_DEV0_0_RCC_CONFIG_CNTL 0x00c2 503 #define regRCC_DEV0_0_RCC_CONFIG_CNTL_BASE_IDX 2 504 #define regRCC_DEV0_0_RCC_CONFIG_F0_BASE 0x00c6 505 #define regRCC_DEV0_0_RCC_CONFIG_F0_BASE_BASE_IDX 2 506 #define regRCC_DEV0_0_RCC_CONFIG_APER_SIZE 0x00c7 507 #define regRCC_DEV0_0_RCC_CONFIG_APER_SIZE_BASE_IDX 2 508 #define regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE 0x00c8 509 #define regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE_BASE_IDX 2 510 #define regRCC_DEV0_0_RCC_XDMA_LO 0x00c9 511 #define regRCC_DEV0_0_RCC_XDMA_LO_BASE_IDX 2 512 #define regRCC_DEV0_0_RCC_XDMA_HI 0x00ca 513 #define regRCC_DEV0_0_RCC_XDMA_HI_BASE_IDX 2 514 #define regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC 0x00cb 515 #define regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC_BASE_IDX 2 516 #define regRCC_DEV0_0_RCC_BUSNUM_CNTL1 0x00cc 517 #define regRCC_DEV0_0_RCC_BUSNUM_CNTL1_BASE_IDX 2 518 #define regRCC_DEV0_0_RCC_BUSNUM_LIST0 0x00cd 519 #define regRCC_DEV0_0_RCC_BUSNUM_LIST0_BASE_IDX 2 520 #define regRCC_DEV0_0_RCC_BUSNUM_LIST1 0x00ce 521 #define regRCC_DEV0_0_RCC_BUSNUM_LIST1_BASE_IDX 2 522 #define regRCC_DEV0_0_RCC_BUSNUM_CNTL2 0x00cf 523 #define regRCC_DEV0_0_RCC_BUSNUM_CNTL2_BASE_IDX 2 524 #define regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM 0x00d0 525 #define regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX 2 526 #define regRCC_DEV0_0_RCC_HOST_BUSNUM 0x00d1 527 #define regRCC_DEV0_0_RCC_HOST_BUSNUM_BASE_IDX 2 528 #define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI 0x00d2 529 #define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI_BASE_IDX 2 530 #define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO 0x00d3 531 #define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO_BASE_IDX 2 532 #define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI 0x00d4 533 #define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI_BASE_IDX 2 534 #define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO 0x00d5 535 #define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO_BASE_IDX 2 536 #define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI 0x00d6 537 #define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI_BASE_IDX 2 538 #define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO 0x00d7 539 #define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO_BASE_IDX 2 540 #define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI 0x00d8 541 #define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI_BASE_IDX 2 542 #define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO 0x00d9 543 #define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO_BASE_IDX 2 544 #define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0 0x00da 545 #define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0_BASE_IDX 2 546 #define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1 0x00db 547 #define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1_BASE_IDX 2 548 #define regRCC_DEV0_0_RCC_DEV0_LINK_CNTL 0x00dd 549 #define regRCC_DEV0_0_RCC_DEV0_LINK_CNTL_BASE_IDX 2 550 #define regRCC_DEV0_0_RCC_CMN_LINK_CNTL 0x00de 551 #define regRCC_DEV0_0_RCC_CMN_LINK_CNTL_BASE_IDX 2 552 #define regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE 0x00df 553 #define regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 2 554 #define regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL 0x00e0 555 #define regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL_BASE_IDX 2 556 #define regRCC_DEV0_0_RCC_MH_ARB_CNTL 0x00e1 557 #define regRCC_DEV0_0_RCC_MH_ARB_CNTL_BASE_IDX 2 558 559 560 // addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_BIFDEC2 561 // base address: 0x0 562 #define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO 0x0400 563 #define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 564 #define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI 0x0401 565 #define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 566 #define regRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA 0x0402 567 #define regRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 568 #define regRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL 0x0403 569 #define regRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 570 #define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO 0x0404 571 #define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 572 #define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI 0x0405 573 #define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 574 #define regRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA 0x0406 575 #define regRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 576 #define regRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL 0x0407 577 #define regRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 578 #define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO 0x0408 579 #define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 580 #define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI 0x0409 581 #define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 582 #define regRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA 0x040a 583 #define regRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 584 #define regRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL 0x040b 585 #define regRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 586 #define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO 0x040c 587 #define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 588 #define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI 0x040d 589 #define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 590 #define regRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA 0x040e 591 #define regRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 592 #define regRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL 0x040f 593 #define regRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 594 #define regRCC_DEV0_EPF0_GFXMSIX_PBA 0x0800 595 #define regRCC_DEV0_EPF0_GFXMSIX_PBA_BASE_IDX 4 596 597 598 // addressBlock: aid_nbio_nbif0_rcc_strap_BIFDEC1 599 // base address: 0x0 600 #define regRCC_STRAP0_RCC_BIF_STRAP0 0x0000 601 #define regRCC_STRAP0_RCC_BIF_STRAP0_BASE_IDX 2 602 #define regRCC_STRAP0_RCC_BIF_STRAP1 0x0001 603 #define regRCC_STRAP0_RCC_BIF_STRAP1_BASE_IDX 2 604 #define regRCC_STRAP0_RCC_BIF_STRAP2 0x0002 605 #define regRCC_STRAP0_RCC_BIF_STRAP2_BASE_IDX 2 606 #define regRCC_STRAP0_RCC_BIF_STRAP3 0x0003 607 #define regRCC_STRAP0_RCC_BIF_STRAP3_BASE_IDX 2 608 #define regRCC_STRAP0_RCC_BIF_STRAP4 0x0004 609 #define regRCC_STRAP0_RCC_BIF_STRAP4_BASE_IDX 2 610 #define regRCC_STRAP0_RCC_BIF_STRAP5 0x0005 611 #define regRCC_STRAP0_RCC_BIF_STRAP5_BASE_IDX 2 612 #define regRCC_STRAP0_RCC_BIF_STRAP6 0x0006 613 #define regRCC_STRAP0_RCC_BIF_STRAP6_BASE_IDX 2 614 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP0 0x0007 615 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP0_BASE_IDX 2 616 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP1 0x0008 617 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP1_BASE_IDX 2 618 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP10 0x0009 619 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP10_BASE_IDX 2 620 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP11 0x000a 621 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP11_BASE_IDX 2 622 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP12 0x000b 623 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP12_BASE_IDX 2 624 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP13 0x000c 625 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP13_BASE_IDX 2 626 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP14 0x000d 627 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP14_BASE_IDX 2 628 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP2 0x000e 629 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP2_BASE_IDX 2 630 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP3 0x000f 631 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP3_BASE_IDX 2 632 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP4 0x0010 633 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP4_BASE_IDX 2 634 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP5 0x0011 635 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP5_BASE_IDX 2 636 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP6 0x0012 637 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP6_BASE_IDX 2 638 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP7 0x0013 639 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP7_BASE_IDX 2 640 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP8 0x0014 641 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP8_BASE_IDX 2 642 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP9 0x0015 643 #define regRCC_STRAP0_RCC_DEV0_PORT_STRAP9_BASE_IDX 2 644 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0 0x0016 645 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_BASE_IDX 2 646 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1 0x0017 647 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1_BASE_IDX 2 648 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13 0x0018 649 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13_BASE_IDX 2 650 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14 0x0019 651 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14_BASE_IDX 2 652 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15 0x001a 653 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15_BASE_IDX 2 654 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16 0x001b 655 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16_BASE_IDX 2 656 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17 0x001c 657 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17_BASE_IDX 2 658 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18 0x001d 659 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18_BASE_IDX 2 660 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2 0x001e 661 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2_BASE_IDX 2 662 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP26 0x001f 663 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP26_BASE_IDX 2 664 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3 0x0020 665 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3_BASE_IDX 2 666 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4 0x0021 667 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4_BASE_IDX 2 668 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5 0x0022 669 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5_BASE_IDX 2 670 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8 0x0024 671 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8_BASE_IDX 2 672 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9 0x0025 673 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9_BASE_IDX 2 674 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0 0x0026 675 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0_BASE_IDX 2 676 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2 0x0032 677 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2_BASE_IDX 2 678 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP20 0x0033 679 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP20_BASE_IDX 2 680 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP21 0x0034 681 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP21_BASE_IDX 2 682 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP22 0x0035 683 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP22_BASE_IDX 2 684 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP23 0x0036 685 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP23_BASE_IDX 2 686 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP24 0x0037 687 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP24_BASE_IDX 2 688 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP25 0x0038 689 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP25_BASE_IDX 2 690 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3 0x0039 691 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3_BASE_IDX 2 692 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4 0x003a 693 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4_BASE_IDX 2 694 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5 0x003b 695 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5_BASE_IDX 2 696 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6 0x003c 697 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6_BASE_IDX 2 698 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7 0x003d 699 #define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7_BASE_IDX 2 700 701 702 // addressBlock: aid_nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 703 // base address: 0x0 704 #define regBIF_BX_PF0_BIF_BME_STATUS 0x00eb 705 #define regBIF_BX_PF0_BIF_BME_STATUS_BASE_IDX 2 706 #define regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG 0x00ec 707 #define regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 708 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 709 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 710 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 711 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 712 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 713 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 714 #define regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 715 #define regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 716 #define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 717 #define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 718 #define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 719 #define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 720 #define regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 721 #define regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 722 #define regBIF_BX_PF0_GPU_HDP_FLUSH_REQ 0x0106 723 #define regBIF_BX_PF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2 724 #define regBIF_BX_PF0_GPU_HDP_FLUSH_DONE 0x0107 725 #define regBIF_BX_PF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2 726 #define regBIF_BX_PF0_BIF_TRANS_PENDING 0x0108 727 #define regBIF_BX_PF0_BIF_TRANS_PENDING_BASE_IDX 2 728 #define regBIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 729 #define regBIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 730 #define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0 0x0136 731 #define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 732 #define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1 0x0137 733 #define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 734 #define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2 0x0138 735 #define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 736 #define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3 0x0139 737 #define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 738 #define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0 0x013a 739 #define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 740 #define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1 0x013b 741 #define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 742 #define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2 0x013c 743 #define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 744 #define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3 0x013d 745 #define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 746 #define regBIF_BX_PF0_MAILBOX_CONTROL 0x013e 747 #define regBIF_BX_PF0_MAILBOX_CONTROL_BASE_IDX 2 748 #define regBIF_BX_PF0_MAILBOX_INT_CNTL 0x013f 749 #define regBIF_BX_PF0_MAILBOX_INT_CNTL_BASE_IDX 2 750 #define regBIF_BX_PF0_BIF_VMHV_MAILBOX 0x0140 751 #define regBIF_BX_PF0_BIF_VMHV_MAILBOX_BASE_IDX 2 752 #define regBIF_BX_PF0_PARTITION_COMPUTE_CAP 0x0161 753 #define regBIF_BX_PF0_PARTITION_COMPUTE_CAP_BASE_IDX 2 754 #define regBIF_BX_PF0_PARTITION_MEM_CAP 0x0162 755 #define regBIF_BX_PF0_PARTITION_MEM_CAP_BASE_IDX 2 756 #define regBIF_BX_PF0_PARTITION_COMPUTE_STATUS 0x0163 757 #define regBIF_BX_PF0_PARTITION_COMPUTE_STATUS_BASE_IDX 2 758 #define regBIF_BX_PF0_PARTITION_MEM_STATUS 0x0164 759 #define regBIF_BX_PF0_PARTITION_MEM_STATUS_BASE_IDX 2 760 761 762 // addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975] 763 // base address: 0x3480 764 #define regRCC_DEV0_EPF0_RCC_ERR_LOG 0x0085 765 #define regRCC_DEV0_EPF0_RCC_ERR_LOG_BASE_IDX 2 766 #define regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN 0x00c0 767 #define regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN_BASE_IDX 2 768 #define regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE 0x00c3 769 #define regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE_BASE_IDX 2 770 #define regRCC_DEV0_EPF0_RCC_CONFIG_RESERVED 0x00c4 771 #define regRCC_DEV0_EPF0_RCC_CONFIG_RESERVED_BASE_IDX 2 772 #define regRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER 0x00c5 773 #define regRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 774 775 776 // addressBlock: aid_nbio_nbif0_gdc_GDCDEC 777 // base address: 0x0 778 #define regGDC0_A2S_CNTL_CL0 0x0000 779 #define regGDC0_A2S_CNTL_CL0_BASE_IDX 3 780 #define regGDC0_A2S_CNTL_CL1 0x0001 781 #define regGDC0_A2S_CNTL_CL1_BASE_IDX 3 782 #define regGDC0_A2S_CNTL3_CL0 0x0018 783 #define regGDC0_A2S_CNTL3_CL0_BASE_IDX 3 784 #define regGDC0_A2S_CNTL3_CL1 0x0019 785 #define regGDC0_A2S_CNTL3_CL1_BASE_IDX 3 786 #define regGDC0_A2S_CNTL_SW0 0x0030 787 #define regGDC0_A2S_CNTL_SW0_BASE_IDX 3 788 #define regGDC0_A2S_CNTL_SW1 0x0031 789 #define regGDC0_A2S_CNTL_SW1_BASE_IDX 3 790 #define regGDC0_A2S_CNTL_SW2 0x0032 791 #define regGDC0_A2S_CNTL_SW2_BASE_IDX 3 792 #define regGDC0_A2S_TAG_ALLOC_0 0x003d 793 #define regGDC0_A2S_TAG_ALLOC_0_BASE_IDX 3 794 #define regGDC0_A2S_TAG_ALLOC_1 0x003e 795 #define regGDC0_A2S_TAG_ALLOC_1_BASE_IDX 3 796 #define regGDC0_A2S_MISC_CNTL 0x0041 797 #define regGDC0_A2S_MISC_CNTL_BASE_IDX 3 798 #define regGDC0_SHUB_REGS_IF_CTL 0x0043 799 #define regGDC0_SHUB_REGS_IF_CTL_BASE_IDX 3 800 #define regGDC0_NGDC_MGCG_CTRL 0x004a 801 #define regGDC0_NGDC_MGCG_CTRL_BASE_IDX 3 802 #define regGDC0_NGDC_RESERVED_0 0x004b 803 #define regGDC0_NGDC_RESERVED_0_BASE_IDX 3 804 #define regGDC0_NGDC_RESERVED_1 0x004c 805 #define regGDC0_NGDC_RESERVED_1_BASE_IDX 3 806 #define regGDC0_NBIF_GFX_DOORBELL_STATUS 0x004f 807 #define regGDC0_NBIF_GFX_DOORBELL_STATUS_BASE_IDX 3 808 #define regGDC0_ATDMA_MISC_CNTL 0x005d 809 #define regGDC0_ATDMA_MISC_CNTL_BASE_IDX 3 810 #define regGDC0_S2A_MISC_CNTL 0x005f 811 #define regGDC0_S2A_MISC_CNTL_BASE_IDX 3 812 #define regGDC0_NGDC_PG_MISC_CTRL 0x0078 813 #define regGDC0_NGDC_PG_MISC_CTRL_BASE_IDX 3 814 #define regGDC0_NGDC_PGMST_CTRL 0x0079 815 #define regGDC0_NGDC_PGMST_CTRL_BASE_IDX 3 816 #define regGDC0_NGDC_PGSLV_CTRL 0x007a 817 #define regGDC0_NGDC_PGSLV_CTRL_BASE_IDX 3 818 819 820 // addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp 821 // base address: 0x0 822 #define cfgBIF_CFG_DEV0_EPF0_VENDOR_ID 0x0000 823 #define cfgBIF_CFG_DEV0_EPF0_DEVICE_ID 0x0002 824 #define cfgBIF_CFG_DEV0_EPF0_COMMAND 0x0004 825 #define cfgBIF_CFG_DEV0_EPF0_STATUS 0x0006 826 #define cfgBIF_CFG_DEV0_EPF0_REVISION_ID 0x0008 827 #define cfgBIF_CFG_DEV0_EPF0_PROG_INTERFACE 0x0009 828 #define cfgBIF_CFG_DEV0_EPF0_SUB_CLASS 0x000a 829 #define cfgBIF_CFG_DEV0_EPF0_BASE_CLASS 0x000b 830 #define cfgBIF_CFG_DEV0_EPF0_CACHE_LINE 0x000c 831 #define cfgBIF_CFG_DEV0_EPF0_LATENCY 0x000d 832 #define cfgBIF_CFG_DEV0_EPF0_HEADER 0x000e 833 #define cfgBIF_CFG_DEV0_EPF0_BIST 0x000f 834 #define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_1 0x0010 835 #define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_2 0x0014 836 #define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_3 0x0018 837 #define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_4 0x001c 838 #define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_5 0x0020 839 #define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_6 0x0024 840 #define cfgBIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR 0x0028 841 #define cfgBIF_CFG_DEV0_EPF0_ADAPTER_ID 0x002c 842 #define cfgBIF_CFG_DEV0_EPF0_ROM_BASE_ADDR 0x0030 843 #define cfgBIF_CFG_DEV0_EPF0_CAP_PTR 0x0034 844 #define cfgBIF_CFG_DEV0_EPF0_INTERRUPT_LINE 0x003c 845 #define cfgBIF_CFG_DEV0_EPF0_INTERRUPT_PIN 0x003d 846 #define cfgBIF_CFG_DEV0_EPF0_MIN_GRANT 0x003e 847 #define cfgBIF_CFG_DEV0_EPF0_MAX_LATENCY 0x003f 848 #define cfgBIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST 0x0048 849 #define cfgBIF_CFG_DEV0_EPF0_ADAPTER_ID_W 0x004c 850 #define cfgBIF_CFG_DEV0_EPF0_PMI_CAP_LIST 0x0050 851 #define cfgBIF_CFG_DEV0_EPF0_PMI_CAP 0x0052 852 #define cfgBIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL 0x0054 853 #define cfgBIF_CFG_DEV0_EPF0_PCIE_CAP_LIST 0x0064 854 #define cfgBIF_CFG_DEV0_EPF0_PCIE_CAP 0x0066 855 #define cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP 0x0068 856 #define cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL 0x006c 857 #define cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS 0x006e 858 #define cfgBIF_CFG_DEV0_EPF0_LINK_CAP 0x0070 859 #define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL 0x0074 860 #define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS 0x0076 861 #define cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP2 0x0088 862 #define cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 0x008c 863 #define cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS2 0x008e 864 #define cfgBIF_CFG_DEV0_EPF0_LINK_CAP2 0x0090 865 #define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL2 0x0094 866 #define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS2 0x0096 867 #define cfgBIF_CFG_DEV0_EPF0_MSI_CAP_LIST 0x00a0 868 #define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_CNTL 0x00a2 869 #define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO 0x00a4 870 #define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI 0x00a8 871 #define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA 0x00a8 872 #define cfgBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA 0x00aa 873 #define cfgBIF_CFG_DEV0_EPF0_MSI_MASK 0x00ac 874 #define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64 0x00ac 875 #define cfgBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64 0x00ae 876 #define cfgBIF_CFG_DEV0_EPF0_MSI_MASK_64 0x00b0 877 #define cfgBIF_CFG_DEV0_EPF0_MSI_PENDING 0x00b0 878 #define cfgBIF_CFG_DEV0_EPF0_MSI_PENDING_64 0x00b4 879 #define cfgBIF_CFG_DEV0_EPF0_MSIX_CAP_LIST 0x00c0 880 #define cfgBIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL 0x00c2 881 #define cfgBIF_CFG_DEV0_EPF0_MSIX_TABLE 0x00c4 882 #define cfgBIF_CFG_DEV0_EPF0_MSIX_PBA 0x00c8 883 #define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 884 #define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 885 #define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1 0x0108 886 #define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2 0x010c 887 #define cfgBIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST 0x0110 888 #define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1 0x0114 889 #define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2 0x0118 890 #define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL 0x011c 891 #define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS 0x011e 892 #define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP 0x0120 893 #define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL 0x0124 894 #define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS 0x012a 895 #define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP 0x012c 896 #define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL 0x0130 897 #define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS 0x0136 898 #define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 899 #define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 900 #define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 901 #define cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 902 #define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS 0x0154 903 #define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK 0x0158 904 #define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY 0x015c 905 #define cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS 0x0160 906 #define cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK 0x0164 907 #define cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL 0x0168 908 #define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0 0x016c 909 #define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1 0x0170 910 #define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2 0x0174 911 #define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3 0x0178 912 #define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0 0x0188 913 #define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1 0x018c 914 #define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2 0x0190 915 #define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3 0x0194 916 #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST 0x0200 917 #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP 0x0204 918 #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL 0x0208 919 #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP 0x020c 920 #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL 0x0210 921 #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP 0x0214 922 #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL 0x0218 923 #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP 0x021c 924 #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL 0x0220 925 #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP 0x0224 926 #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL 0x0228 927 #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP 0x022c 928 #define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL 0x0230 929 #define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 930 #define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 931 #define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA 0x0248 932 #define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP 0x024c 933 #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST 0x0250 934 #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_CAP 0x0254 935 #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR 0x0258 936 #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS 0x025c 937 #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL 0x025e 938 #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 939 #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 940 #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 941 #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 942 #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 943 #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 944 #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 945 #define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 946 #define cfgBIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 947 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3 0x0274 948 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS 0x0278 949 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 950 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 951 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 952 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 953 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 954 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 955 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 956 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 957 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 958 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 959 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 960 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 961 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 962 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 963 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 964 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 965 #define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST 0x02a0 966 #define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CAP 0x02a4 967 #define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL 0x02a6 968 #define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST 0x02b0 969 #define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_CAP 0x02b4 970 #define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL 0x02b6 971 #define cfgPCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0 972 #define cfgPCIE_PAGE_REQ_CNTL 0x02c4 973 #define cfgPCIE_PAGE_REQ_STATUS 0x02c6 974 #define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8 975 #define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc 976 #define cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST 0x02d0 977 #define cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_CAP 0x02d4 978 #define cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL 0x02d6 979 #define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST 0x02f0 980 #define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_CAP 0x02f4 981 #define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_CNTL 0x02f6 982 #define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0 0x02f8 983 #define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1 0x02fc 984 #define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_RCV0 0x0300 985 #define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_RCV1 0x0304 986 #define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0 0x0308 987 #define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1 0x030c 988 #define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 989 #define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 990 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST 0x0320 991 #define cfgBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP 0x0324 992 #define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST 0x0328 993 #define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CAP 0x032c 994 #define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL 0x032e 995 #define cfgPCIE_SRIOV_ENH_CAP_LIST 0x0330 996 #define cfgPCIE_SRIOV_CAP 0x0334 997 #define cfgPCIE_SRIOV_CONTROL 0x0338 998 #define cfgPCIE_SRIOV_STATUS 0x033a 999 #define cfgPCIE_SRIOV_INITIAL_VFS 0x033c 1000 #define cfgPCIE_SRIOV_TOTAL_VFS 0x033e 1001 #define cfgPCIE_SRIOV_NUM_VFS 0x0340 1002 #define cfgPCIE_SRIOV_FUNC_DEP_LINK 0x0342 1003 #define cfgPCIE_SRIOV_FIRST_VF_OFFSET 0x0344 1004 #define cfgPCIE_SRIOV_VF_STRIDE 0x0346 1005 #define cfgPCIE_SRIOV_VF_DEVICE_ID 0x034a 1006 #define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c 1007 #define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 1008 #define cfgPCIE_SRIOV_VF_BASE_ADDR_0 0x0354 1009 #define cfgPCIE_SRIOV_VF_BASE_ADDR_1 0x0358 1010 #define cfgPCIE_SRIOV_VF_BASE_ADDR_2 0x035c 1011 #define cfgPCIE_SRIOV_VF_BASE_ADDR_3 0x0360 1012 #define cfgPCIE_SRIOV_VF_BASE_ADDR_4 0x0364 1013 #define cfgPCIE_SRIOV_VF_BASE_ADDR_5 0x0368 1014 #define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c 1015 #define cfgBIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST 0x0400 1016 #define cfgBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP 0x0404 1017 #define cfgBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS 0x0408 1018 #define cfgBIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 1019 #define cfgBIF_CFG_DEV0_EPF0_LINK_CAP_16GT 0x0414 1020 #define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL_16GT 0x0418 1021 #define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS_16GT 0x041c 1022 #define cfgBIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 1023 #define cfgBIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 1024 #define cfgBIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 1025 #define cfgBIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 1026 #define cfgBIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 1027 #define cfgBIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 1028 #define cfgBIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 1029 #define cfgBIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 1030 #define cfgBIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 1031 #define cfgBIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 1032 #define cfgBIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 1033 #define cfgBIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 1034 #define cfgBIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 1035 #define cfgBIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT 0x043a 1036 #define cfgBIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT 0x043b 1037 #define cfgBIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT 0x043c 1038 #define cfgBIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT 0x043d 1039 #define cfgBIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT 0x043e 1040 #define cfgBIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT 0x043f 1041 #define cfgBIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST 0x0450 1042 #define cfgBIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP 0x0454 1043 #define cfgBIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS 0x0456 1044 #define cfgBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL 0x0458 1045 #define cfgBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS 0x045a 1046 #define cfgBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL 0x045c 1047 #define cfgBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS 0x045e 1048 #define cfgBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL 0x0460 1049 #define cfgBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS 0x0462 1050 #define cfgBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL 0x0464 1051 #define cfgBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS 0x0466 1052 #define cfgBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL 0x0468 1053 #define cfgBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS 0x046a 1054 #define cfgBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL 0x046c 1055 #define cfgBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS 0x046e 1056 #define cfgBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL 0x0470 1057 #define cfgBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS 0x0472 1058 #define cfgBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL 0x0474 1059 #define cfgBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS 0x0476 1060 #define cfgBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL 0x0478 1061 #define cfgBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS 0x047a 1062 #define cfgBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL 0x047c 1063 #define cfgBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS 0x047e 1064 #define cfgBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL 0x0480 1065 #define cfgBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS 0x0482 1066 #define cfgBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL 0x0484 1067 #define cfgBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS 0x0486 1068 #define cfgBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL 0x0488 1069 #define cfgBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS 0x048a 1070 #define cfgBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL 0x048c 1071 #define cfgBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS 0x048e 1072 #define cfgBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL 0x0490 1073 #define cfgBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS 0x0492 1074 #define cfgBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL 0x0494 1075 #define cfgBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS 0x0496 1076 #define cfgBIF_CFG_DEV0_EPF0_LINK_CAP_32GT 0x0504 1077 #define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL_32GT 0x0508 1078 #define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS_32GT 0x050c 1079 #define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0700 1080 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0704 1081 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0708 1082 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x070c 1083 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0710 1084 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0714 1085 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0718 1086 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x071c 1087 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0720 1088 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0724 1089 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0728 1090 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION 0x0730 1091 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 0x0734 1092 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0738 1093 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x073c 1094 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x0740 1095 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x0744 1096 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0748 1097 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x074c 1098 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x0750 1099 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x0754 1100 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0758 1101 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x075c 1102 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x0760 1103 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x0764 1104 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0768 1105 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x076c 1106 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x0770 1107 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x0774 1108 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 0x0778 1109 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 0x077c 1110 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 0x0780 1111 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 0x0784 1112 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 0x0788 1113 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 0x078c 1114 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 0x0790 1115 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 0x0794 1116 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 0x0798 1117 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 0x079c 1118 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 0x07a0 1119 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 0x07a4 1120 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 0x07a8 1121 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 0x07ac 1122 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 0x07b0 1123 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x07c0 1124 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1 0x07c4 1125 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2 0x07c8 1126 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3 0x07cc 1127 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4 0x07d0 1128 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0 0x07f0 1129 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1 0x07f4 1130 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2 0x07f8 1131 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3 0x07fc 1132 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4 0x0800 1133 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5 0x0804 1134 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6 0x0808 1135 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7 0x080c 1136 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8 0x0810 1137 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 0x0820 1138 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 0x0824 1139 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 0x0828 1140 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 0x082c 1141 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 0x0830 1142 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 0x0834 1143 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 0x0838 1144 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 0x083c 1145 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 0x0840 1146 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0 0x0850 1147 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1 0x0854 1148 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2 0x0858 1149 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3 0x085c 1150 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4 0x0860 1151 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5 0x0864 1152 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6 0x0868 1153 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7 0x086c 1154 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8 0x0870 1155 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0 0x0880 1156 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1 0x0884 1157 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2 0x0888 1158 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3 0x088c 1159 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4 0x0890 1160 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5 0x0894 1161 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6 0x0898 1162 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7 0x089c 1163 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8 0x08a0 1164 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0 0x08b0 1165 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1 0x08b4 1166 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2 0x08b8 1167 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3 0x08bc 1168 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4 0x08c0 1169 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5 0x08c4 1170 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6 0x08c8 1171 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7 0x08cc 1172 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8 0x08d0 1173 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0 0x08e0 1174 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1 0x08e4 1175 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2 0x08e8 1176 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3 0x08ec 1177 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4 0x08f0 1178 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5 0x08f4 1179 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6 0x08f8 1180 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7 0x08fc 1181 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8 0x0900 1182 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0 0x0910 1183 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1 0x0914 1184 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2 0x0918 1185 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3 0x091c 1186 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4 0x0920 1187 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5 0x0924 1188 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6 0x0928 1189 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7 0x092c 1190 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8 0x0930 1191 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0 0x0940 1192 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1 0x0944 1193 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2 0x0948 1194 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3 0x094c 1195 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4 0x0950 1196 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5 0x0954 1197 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6 0x0958 1198 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7 0x095c 1199 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8 0x0960 1200 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0 0x0970 1201 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1 0x0974 1202 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2 0x0978 1203 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3 0x097c 1204 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4 0x0980 1205 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5 0x0984 1206 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6 0x0988 1207 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7 0x098c 1208 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8 0x0990 1209 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0 0x09a0 1210 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1 0x09a4 1211 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2 0x09a8 1212 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3 0x09ac 1213 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4 0x09b0 1214 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5 0x09b4 1215 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6 0x09b8 1216 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7 0x09bc 1217 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8 0x09c0 1218 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0 0x09d0 1219 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1 0x09d4 1220 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2 0x09d8 1221 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3 0x09dc 1222 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4 0x09e0 1223 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5 0x09e4 1224 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6 0x09e8 1225 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7 0x09ec 1226 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8 0x09f0 1227 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0 0x0a00 1228 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1 0x0a04 1229 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2 0x0a08 1230 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3 0x0a0c 1231 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4 0x0a10 1232 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5 0x0a14 1233 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6 0x0a18 1234 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7 0x0a1c 1235 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8 0x0a20 1236 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0 0x0a30 1237 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1 0x0a34 1238 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2 0x0a38 1239 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3 0x0a3c 1240 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4 0x0a40 1241 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5 0x0a44 1242 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6 0x0a48 1243 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7 0x0a4c 1244 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8 0x0a50 1245 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0 0x0a60 1246 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1 0x0a64 1247 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2 0x0a68 1248 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3 0x0a6c 1249 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4 0x0a70 1250 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5 0x0a74 1251 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6 0x0a78 1252 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7 0x0a7c 1253 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8 0x0a80 1254 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0 0x0a90 1255 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1 0x0a94 1256 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2 0x0a98 1257 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3 0x0a9c 1258 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4 0x0aa0 1259 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5 0x0aa4 1260 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6 0x0aa8 1261 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7 0x0aac 1262 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8 0x0ab0 1263 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0 0x0ac0 1264 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1 0x0ac4 1265 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2 0x0ac8 1266 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3 0x0acc 1267 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4 0x0ad0 1268 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5 0x0ad4 1269 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6 0x0ad8 1270 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7 0x0adc 1271 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8 0x0ae0 1272 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0 0x0af0 1273 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1 0x0af4 1274 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2 0x0af8 1275 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3 0x0afc 1276 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4 0x0b00 1277 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5 0x0b04 1278 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6 0x0b08 1279 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7 0x0b0c 1280 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8 0x0b10 1281 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0 0x0b20 1282 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1 0x0b24 1283 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2 0x0b28 1284 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3 0x0b2c 1285 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4 0x0b30 1286 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5 0x0b34 1287 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6 0x0b38 1288 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7 0x0b3c 1289 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8 0x0b40 1290 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0 0x0b50 1291 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1 0x0b54 1292 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2 0x0b58 1293 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3 0x0b5c 1294 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4 0x0b60 1295 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5 0x0b64 1296 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6 0x0b68 1297 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7 0x0b6c 1298 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8 0x0b70 1299 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0 0x0b80 1300 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1 0x0b84 1301 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2 0x0b88 1302 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3 0x0b8c 1303 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4 0x0b90 1304 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5 0x0b94 1305 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6 0x0b98 1306 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7 0x0b9c 1307 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8 0x0ba0 1308 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE 0x0c00 1309 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_ENABLE 0x0c04 1310 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE 0x0c08 1311 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE 0x0c0c 1312 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS 0x0c10 1313 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_STATUS 0x0c14 1314 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS 0x0c18 1315 #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS 0x0c1c 1316 1317 1318 // addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp 1319 // base address: 0x0 1320 #define cfgBIF_CFG_DEV0_EPF1_VENDOR_ID 0x0000 1321 #define cfgBIF_CFG_DEV0_EPF1_DEVICE_ID 0x0002 1322 #define cfgBIF_CFG_DEV0_EPF1_COMMAND 0x0004 1323 #define cfgBIF_CFG_DEV0_EPF1_STATUS 0x0006 1324 #define cfgBIF_CFG_DEV0_EPF1_REVISION_ID 0x0008 1325 #define cfgBIF_CFG_DEV0_EPF1_PROG_INTERFACE 0x0009 1326 #define cfgBIF_CFG_DEV0_EPF1_SUB_CLASS 0x000a 1327 #define cfgBIF_CFG_DEV0_EPF1_BASE_CLASS 0x000b 1328 #define cfgBIF_CFG_DEV0_EPF1_CACHE_LINE 0x000c 1329 #define cfgBIF_CFG_DEV0_EPF1_LATENCY 0x000d 1330 #define cfgBIF_CFG_DEV0_EPF1_HEADER 0x000e 1331 #define cfgBIF_CFG_DEV0_EPF1_BIST 0x000f 1332 #define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_1 0x0010 1333 #define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_2 0x0014 1334 #define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_3 0x0018 1335 #define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_4 0x001c 1336 #define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_5 0x0020 1337 #define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_6 0x0024 1338 #define cfgBIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR 0x0028 1339 #define cfgBIF_CFG_DEV0_EPF1_ADAPTER_ID 0x002c 1340 #define cfgBIF_CFG_DEV0_EPF1_ROM_BASE_ADDR 0x0030 1341 #define cfgBIF_CFG_DEV0_EPF1_CAP_PTR 0x0034 1342 #define cfgBIF_CFG_DEV0_EPF1_INTERRUPT_LINE 0x003c 1343 #define cfgBIF_CFG_DEV0_EPF1_INTERRUPT_PIN 0x003d 1344 #define cfgBIF_CFG_DEV0_EPF1_MIN_GRANT 0x003e 1345 #define cfgBIF_CFG_DEV0_EPF1_MAX_LATENCY 0x003f 1346 #define cfgBIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST 0x0048 1347 #define cfgBIF_CFG_DEV0_EPF1_ADAPTER_ID_W 0x004c 1348 #define cfgBIF_CFG_DEV0_EPF1_PMI_CAP_LIST 0x0050 1349 #define cfgBIF_CFG_DEV0_EPF1_PMI_CAP 0x0052 1350 #define cfgBIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL 0x0054 1351 #define cfgBIF_CFG_DEV0_EPF1_PCIE_CAP_LIST 0x0064 1352 #define cfgBIF_CFG_DEV0_EPF1_PCIE_CAP 0x0066 1353 #define cfgBIF_CFG_DEV0_EPF1_DEVICE_CAP 0x0068 1354 #define cfgBIF_CFG_DEV0_EPF1_DEVICE_CNTL 0x006c 1355 #define cfgBIF_CFG_DEV0_EPF1_DEVICE_STATUS 0x006e 1356 #define cfgBIF_CFG_DEV0_EPF1_LINK_CAP 0x0070 1357 #define cfgBIF_CFG_DEV0_EPF1_LINK_CNTL 0x0074 1358 #define cfgBIF_CFG_DEV0_EPF1_LINK_STATUS 0x0076 1359 #define cfgBIF_CFG_DEV0_EPF1_DEVICE_CAP2 0x0088 1360 #define cfgBIF_CFG_DEV0_EPF1_DEVICE_CNTL2 0x008c 1361 #define cfgBIF_CFG_DEV0_EPF1_DEVICE_STATUS2 0x008e 1362 #define cfgBIF_CFG_DEV0_EPF1_LINK_CAP2 0x0090 1363 #define cfgBIF_CFG_DEV0_EPF1_LINK_CNTL2 0x0094 1364 #define cfgBIF_CFG_DEV0_EPF1_LINK_STATUS2 0x0096 1365 #define cfgBIF_CFG_DEV0_EPF1_MSI_CAP_LIST 0x00a0 1366 #define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_CNTL 0x00a2 1367 #define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO 0x00a4 1368 #define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI 0x00a8 1369 #define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_DATA 0x00a8 1370 #define cfgBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA 0x00aa 1371 #define cfgBIF_CFG_DEV0_EPF1_MSI_MASK 0x00ac 1372 #define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64 0x00ac 1373 #define cfgBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64 0x00ae 1374 #define cfgBIF_CFG_DEV0_EPF1_MSI_MASK_64 0x00b0 1375 #define cfgBIF_CFG_DEV0_EPF1_MSI_PENDING 0x00b0 1376 #define cfgBIF_CFG_DEV0_EPF1_MSI_PENDING_64 0x00b4 1377 #define cfgBIF_CFG_DEV0_EPF1_MSIX_CAP_LIST 0x00c0 1378 #define cfgBIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL 0x00c2 1379 #define cfgBIF_CFG_DEV0_EPF1_MSIX_TABLE 0x00c4 1380 #define cfgBIF_CFG_DEV0_EPF1_MSIX_PBA 0x00c8 1381 #define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 1382 #define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 1383 #define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1 0x0108 1384 #define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2 0x010c 1385 #define cfgBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 1386 #define cfgBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS 0x0154 1387 #define cfgBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK 0x0158 1388 #define cfgBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY 0x015c 1389 #define cfgBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS 0x0160 1390 #define cfgBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK 0x0164 1391 #define cfgBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL 0x0168 1392 #define cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0 0x016c 1393 #define cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1 0x0170 1394 #define cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2 0x0174 1395 #define cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3 0x0178 1396 #define cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0 0x0188 1397 #define cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1 0x018c 1398 #define cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2 0x0190 1399 #define cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3 0x0194 1400 #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST 0x0200 1401 #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP 0x0204 1402 #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL 0x0208 1403 #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP 0x020c 1404 #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL 0x0210 1405 #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP 0x0214 1406 #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL 0x0218 1407 #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP 0x021c 1408 #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL 0x0220 1409 #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP 0x0224 1410 #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL 0x0228 1411 #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP 0x022c 1412 #define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL 0x0230 1413 #define cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 1414 #define cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 1415 #define cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA 0x0248 1416 #define cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP 0x024c 1417 #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST 0x0250 1418 #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_CAP 0x0254 1419 #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR 0x0258 1420 #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS 0x025c 1421 #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL 0x025e 1422 #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 1423 #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 1424 #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 1425 #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 1426 #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 1427 #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 1428 #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 1429 #define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 1430 #define cfgBIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST 0x02a0 1431 #define cfgBIF_CFG_DEV0_EPF1_PCIE_ACS_CAP 0x02a4 1432 #define cfgBIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL 0x02a6 1433 #define cfgBIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST 0x02d0 1434 #define cfgBIF_CFG_DEV0_EPF1_PCIE_PASID_CAP 0x02d4 1435 #define cfgBIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL 0x02d6 1436 #define cfgBIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST 0x0328 1437 #define cfgBIF_CFG_DEV0_EPF1_PCIE_ARI_CAP 0x032c 1438 #define cfgBIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL 0x032e 1439 1440 1441 // addressBlock: aid_nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp 1442 // base address: 0x10100000 1443 #define regBIF_CFG_DEV0_RC0_VENDOR_ID 0x0000 1444 #define regBIF_CFG_DEV0_RC0_VENDOR_ID_BASE_IDX 8 1445 #define regBIF_CFG_DEV0_RC0_DEVICE_ID 0x0000 1446 #define regBIF_CFG_DEV0_RC0_DEVICE_ID_BASE_IDX 8 1447 #define regBIF_CFG_DEV0_RC0_COMMAND 0x0001 1448 #define regBIF_CFG_DEV0_RC0_COMMAND_BASE_IDX 8 1449 #define regBIF_CFG_DEV0_RC0_STATUS 0x0001 1450 #define regBIF_CFG_DEV0_RC0_STATUS_BASE_IDX 8 1451 #define regBIF_CFG_DEV0_RC0_REVISION_ID 0x0002 1452 #define regBIF_CFG_DEV0_RC0_REVISION_ID_BASE_IDX 8 1453 #define regBIF_CFG_DEV0_RC0_PROG_INTERFACE 0x0002 1454 #define regBIF_CFG_DEV0_RC0_PROG_INTERFACE_BASE_IDX 8 1455 #define regBIF_CFG_DEV0_RC0_SUB_CLASS 0x0002 1456 #define regBIF_CFG_DEV0_RC0_SUB_CLASS_BASE_IDX 8 1457 #define regBIF_CFG_DEV0_RC0_BASE_CLASS 0x0002 1458 #define regBIF_CFG_DEV0_RC0_BASE_CLASS_BASE_IDX 8 1459 #define regBIF_CFG_DEV0_RC0_CACHE_LINE 0x0003 1460 #define regBIF_CFG_DEV0_RC0_CACHE_LINE_BASE_IDX 8 1461 #define regBIF_CFG_DEV0_RC0_LATENCY 0x0003 1462 #define regBIF_CFG_DEV0_RC0_LATENCY_BASE_IDX 8 1463 #define regBIF_CFG_DEV0_RC0_HEADER 0x0003 1464 #define regBIF_CFG_DEV0_RC0_HEADER_BASE_IDX 8 1465 #define regBIF_CFG_DEV0_RC0_BIST 0x0003 1466 #define regBIF_CFG_DEV0_RC0_BIST_BASE_IDX 8 1467 #define regBIF_CFG_DEV0_RC0_BASE_ADDR_1 0x0004 1468 #define regBIF_CFG_DEV0_RC0_BASE_ADDR_1_BASE_IDX 8 1469 #define regBIF_CFG_DEV0_RC0_BASE_ADDR_2 0x0005 1470 #define regBIF_CFG_DEV0_RC0_BASE_ADDR_2_BASE_IDX 8 1471 #define regBIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY 0x0006 1472 #define regBIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY_BASE_IDX 8 1473 #define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT 0x0007 1474 #define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_BASE_IDX 8 1475 #define regBIF_CFG_DEV0_RC0_SECONDARY_STATUS 0x0007 1476 #define regBIF_CFG_DEV0_RC0_SECONDARY_STATUS_BASE_IDX 8 1477 #define regBIF_CFG_DEV0_RC0_MEM_BASE_LIMIT 0x0008 1478 #define regBIF_CFG_DEV0_RC0_MEM_BASE_LIMIT_BASE_IDX 8 1479 #define regBIF_CFG_DEV0_RC0_PREF_BASE_LIMIT 0x0009 1480 #define regBIF_CFG_DEV0_RC0_PREF_BASE_LIMIT_BASE_IDX 8 1481 #define regBIF_CFG_DEV0_RC0_PREF_BASE_UPPER 0x000a 1482 #define regBIF_CFG_DEV0_RC0_PREF_BASE_UPPER_BASE_IDX 8 1483 #define regBIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER 0x000b 1484 #define regBIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER_BASE_IDX 8 1485 #define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI 0x000c 1486 #define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI_BASE_IDX 8 1487 #define regBIF_CFG_DEV0_RC0_CAP_PTR 0x000d 1488 #define regBIF_CFG_DEV0_RC0_CAP_PTR_BASE_IDX 8 1489 #define regBIF_CFG_DEV0_RC0_ROM_BASE_ADDR 0x000e 1490 #define regBIF_CFG_DEV0_RC0_ROM_BASE_ADDR_BASE_IDX 8 1491 #define regBIF_CFG_DEV0_RC0_INTERRUPT_LINE 0x000f 1492 #define regBIF_CFG_DEV0_RC0_INTERRUPT_LINE_BASE_IDX 8 1493 #define regBIF_CFG_DEV0_RC0_INTERRUPT_PIN 0x000f 1494 #define regBIF_CFG_DEV0_RC0_INTERRUPT_PIN_BASE_IDX 8 1495 #define regBIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL 0x000f 1496 #define regBIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL_BASE_IDX 8 1497 #define regBIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL 0x0010 1498 #define regBIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL_BASE_IDX 8 1499 #define regBIF_CFG_DEV0_RC0_PMI_CAP_LIST 0x0014 1500 #define regBIF_CFG_DEV0_RC0_PMI_CAP_LIST_BASE_IDX 8 1501 #define regBIF_CFG_DEV0_RC0_PMI_CAP 0x0014 1502 #define regBIF_CFG_DEV0_RC0_PMI_CAP_BASE_IDX 8 1503 #define regBIF_CFG_DEV0_RC0_PMI_STATUS_CNTL 0x0015 1504 #define regBIF_CFG_DEV0_RC0_PMI_STATUS_CNTL_BASE_IDX 8 1505 #define regBIF_CFG_DEV0_RC0_PCIE_CAP_LIST 0x0016 1506 #define regBIF_CFG_DEV0_RC0_PCIE_CAP_LIST_BASE_IDX 8 1507 #define regBIF_CFG_DEV0_RC0_PCIE_CAP 0x0016 1508 #define regBIF_CFG_DEV0_RC0_PCIE_CAP_BASE_IDX 8 1509 #define regBIF_CFG_DEV0_RC0_DEVICE_CAP 0x0017 1510 #define regBIF_CFG_DEV0_RC0_DEVICE_CAP_BASE_IDX 8 1511 #define regBIF_CFG_DEV0_RC0_DEVICE_CNTL 0x0018 1512 #define regBIF_CFG_DEV0_RC0_DEVICE_CNTL_BASE_IDX 8 1513 #define regBIF_CFG_DEV0_RC0_DEVICE_STATUS 0x0018 1514 #define regBIF_CFG_DEV0_RC0_DEVICE_STATUS_BASE_IDX 8 1515 #define regBIF_CFG_DEV0_RC0_LINK_CAP 0x0019 1516 #define regBIF_CFG_DEV0_RC0_LINK_CAP_BASE_IDX 8 1517 #define regBIF_CFG_DEV0_RC0_LINK_CNTL 0x001a 1518 #define regBIF_CFG_DEV0_RC0_LINK_CNTL_BASE_IDX 8 1519 #define regBIF_CFG_DEV0_RC0_LINK_STATUS 0x001a 1520 #define regBIF_CFG_DEV0_RC0_LINK_STATUS_BASE_IDX 8 1521 #define regBIF_CFG_DEV0_RC0_SLOT_CAP 0x001b 1522 #define regBIF_CFG_DEV0_RC0_SLOT_CAP_BASE_IDX 8 1523 #define regBIF_CFG_DEV0_RC0_SLOT_CNTL 0x001c 1524 #define regBIF_CFG_DEV0_RC0_SLOT_CNTL_BASE_IDX 8 1525 #define regBIF_CFG_DEV0_RC0_SLOT_STATUS 0x001c 1526 #define regBIF_CFG_DEV0_RC0_SLOT_STATUS_BASE_IDX 8 1527 #define regBIF_CFG_DEV0_RC0_ROOT_CNTL 0x001d 1528 #define regBIF_CFG_DEV0_RC0_ROOT_CNTL_BASE_IDX 8 1529 #define regBIF_CFG_DEV0_RC0_ROOT_CAP 0x001d 1530 #define regBIF_CFG_DEV0_RC0_ROOT_CAP_BASE_IDX 8 1531 #define regBIF_CFG_DEV0_RC0_ROOT_STATUS 0x001e 1532 #define regBIF_CFG_DEV0_RC0_ROOT_STATUS_BASE_IDX 8 1533 #define regBIF_CFG_DEV0_RC0_DEVICE_CAP2 0x001f 1534 #define regBIF_CFG_DEV0_RC0_DEVICE_CAP2_BASE_IDX 8 1535 #define regBIF_CFG_DEV0_RC0_DEVICE_CNTL2 0x0020 1536 #define regBIF_CFG_DEV0_RC0_DEVICE_CNTL2_BASE_IDX 8 1537 #define regBIF_CFG_DEV0_RC0_DEVICE_STATUS2 0x0020 1538 #define regBIF_CFG_DEV0_RC0_DEVICE_STATUS2_BASE_IDX 8 1539 #define regBIF_CFG_DEV0_RC0_LINK_CAP2 0x0021 1540 #define regBIF_CFG_DEV0_RC0_LINK_CAP2_BASE_IDX 8 1541 #define regBIF_CFG_DEV0_RC0_LINK_CNTL2 0x0022 1542 #define regBIF_CFG_DEV0_RC0_LINK_CNTL2_BASE_IDX 8 1543 #define regBIF_CFG_DEV0_RC0_LINK_STATUS2 0x0022 1544 #define regBIF_CFG_DEV0_RC0_LINK_STATUS2_BASE_IDX 8 1545 #define regBIF_CFG_DEV0_RC0_SLOT_CAP2 0x0023 1546 #define regBIF_CFG_DEV0_RC0_SLOT_CAP2_BASE_IDX 8 1547 #define regBIF_CFG_DEV0_RC0_SLOT_CNTL2 0x0024 1548 #define regBIF_CFG_DEV0_RC0_SLOT_CNTL2_BASE_IDX 8 1549 #define regBIF_CFG_DEV0_RC0_SLOT_STATUS2 0x0024 1550 #define regBIF_CFG_DEV0_RC0_SLOT_STATUS2_BASE_IDX 8 1551 #define regBIF_CFG_DEV0_RC0_MSI_CAP_LIST 0x0028 1552 #define regBIF_CFG_DEV0_RC0_MSI_CAP_LIST_BASE_IDX 8 1553 #define regBIF_CFG_DEV0_RC0_MSI_MSG_CNTL 0x0028 1554 #define regBIF_CFG_DEV0_RC0_MSI_MSG_CNTL_BASE_IDX 8 1555 #define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO 0x0029 1556 #define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO_BASE_IDX 8 1557 #define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI 0x002a 1558 #define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI_BASE_IDX 8 1559 #define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA 0x002a 1560 #define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_BASE_IDX 8 1561 #define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA 0x002a 1562 #define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_BASE_IDX 8 1563 #define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_64 0x002b 1564 #define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_64_BASE_IDX 8 1565 #define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64 0x002b 1566 #define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64_BASE_IDX 8 1567 #define regBIF_CFG_DEV0_RC0_SSID_CAP_LIST 0x0030 1568 #define regBIF_CFG_DEV0_RC0_SSID_CAP_LIST_BASE_IDX 8 1569 #define regBIF_CFG_DEV0_RC0_SSID_CAP 0x0031 1570 #define regBIF_CFG_DEV0_RC0_SSID_CAP_BASE_IDX 8 1571 #define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0040 1572 #define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 8 1573 #define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR 0x0041 1574 #define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 8 1575 #define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1 0x0042 1576 #define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 8 1577 #define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2 0x0043 1578 #define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 8 1579 #define regBIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST 0x0044 1580 #define regBIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST_BASE_IDX 8 1581 #define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1 0x0045 1582 #define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1_BASE_IDX 8 1583 #define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2 0x0046 1584 #define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2_BASE_IDX 8 1585 #define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL 0x0047 1586 #define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL_BASE_IDX 8 1587 #define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS 0x0047 1588 #define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS_BASE_IDX 8 1589 #define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP 0x0048 1590 #define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP_BASE_IDX 8 1591 #define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL 0x0049 1592 #define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 8 1593 #define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS 0x004a 1594 #define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 8 1595 #define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP 0x004b 1596 #define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP_BASE_IDX 8 1597 #define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL 0x004c 1598 #define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 8 1599 #define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS 0x004d 1600 #define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 8 1601 #define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0050 1602 #define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 8 1603 #define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1 0x0051 1604 #define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 8 1605 #define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2 0x0052 1606 #define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 8 1607 #define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0054 1608 #define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 8 1609 #define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS 0x0055 1610 #define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 8 1611 #define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK 0x0056 1612 #define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK_BASE_IDX 8 1613 #define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY 0x0057 1614 #define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 8 1615 #define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS 0x0058 1616 #define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS_BASE_IDX 8 1617 #define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK 0x0059 1618 #define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK_BASE_IDX 8 1619 #define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL 0x005a 1620 #define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 8 1621 #define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG0 0x005b 1622 #define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG0_BASE_IDX 8 1623 #define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG1 0x005c 1624 #define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG1_BASE_IDX 8 1625 #define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG2 0x005d 1626 #define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG2_BASE_IDX 8 1627 #define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG3 0x005e 1628 #define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG3_BASE_IDX 8 1629 #define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD 0x005f 1630 #define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD_BASE_IDX 8 1631 #define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS 0x0060 1632 #define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS_BASE_IDX 8 1633 #define regBIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID 0x0061 1634 #define regBIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID_BASE_IDX 8 1635 #define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0 0x0062 1636 #define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 8 1637 #define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1 0x0063 1638 #define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 8 1639 #define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2 0x0064 1640 #define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 8 1641 #define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3 0x0065 1642 #define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 8 1643 #define regBIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST 0x009c 1644 #define regBIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 8 1645 #define regBIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3 0x009d 1646 #define regBIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3_BASE_IDX 8 1647 #define regBIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS 0x009e 1648 #define regBIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS_BASE_IDX 8 1649 #define regBIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL 0x009f 1650 #define regBIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 8 1651 #define regBIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL 0x009f 1652 #define regBIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 8 1653 #define regBIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL 0x00a0 1654 #define regBIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 8 1655 #define regBIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL 0x00a0 1656 #define regBIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 8 1657 #define regBIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL 0x00a1 1658 #define regBIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 8 1659 #define regBIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL 0x00a1 1660 #define regBIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 8 1661 #define regBIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL 0x00a2 1662 #define regBIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 8 1663 #define regBIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL 0x00a2 1664 #define regBIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 8 1665 #define regBIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL 0x00a3 1666 #define regBIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 8 1667 #define regBIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL 0x00a3 1668 #define regBIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 8 1669 #define regBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL 0x00a4 1670 #define regBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 8 1671 #define regBIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL 0x00a4 1672 #define regBIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 8 1673 #define regBIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL 0x00a5 1674 #define regBIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 8 1675 #define regBIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL 0x00a5 1676 #define regBIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 8 1677 #define regBIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL 0x00a6 1678 #define regBIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 8 1679 #define regBIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL 0x00a6 1680 #define regBIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 8 1681 #define regBIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST 0x00a8 1682 #define regBIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 8 1683 #define regBIF_CFG_DEV0_RC0_PCIE_ACS_CAP 0x00a9 1684 #define regBIF_CFG_DEV0_RC0_PCIE_ACS_CAP_BASE_IDX 8 1685 #define regBIF_CFG_DEV0_RC0_PCIE_ACS_CNTL 0x00a9 1686 #define regBIF_CFG_DEV0_RC0_PCIE_ACS_CNTL_BASE_IDX 8 1687 #define regBIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST 0x0100 1688 #define regBIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 8 1689 #define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP 0x0101 1690 #define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP_BASE_IDX 8 1691 #define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS 0x0102 1692 #define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS_BASE_IDX 8 1693 #define regBIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST 0x0104 1694 #define regBIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 8 1695 #define regBIF_CFG_DEV0_RC0_LINK_CAP_16GT 0x0105 1696 #define regBIF_CFG_DEV0_RC0_LINK_CAP_16GT_BASE_IDX 8 1697 #define regBIF_CFG_DEV0_RC0_LINK_CNTL_16GT 0x0106 1698 #define regBIF_CFG_DEV0_RC0_LINK_CNTL_16GT_BASE_IDX 8 1699 #define regBIF_CFG_DEV0_RC0_LINK_STATUS_16GT 0x0107 1700 #define regBIF_CFG_DEV0_RC0_LINK_STATUS_16GT_BASE_IDX 8 1701 #define regBIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0108 1702 #define regBIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 8 1703 #define regBIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0109 1704 #define regBIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 8 1705 #define regBIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x010a 1706 #define regBIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 8 1707 #define regBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT 0x010c 1708 #define regBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 8 1709 #define regBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT 0x010c 1710 #define regBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 8 1711 #define regBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT 0x010c 1712 #define regBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 8 1713 #define regBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT 0x010c 1714 #define regBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 8 1715 #define regBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT 0x010d 1716 #define regBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 8 1717 #define regBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT 0x010d 1718 #define regBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 8 1719 #define regBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT 0x010d 1720 #define regBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 8 1721 #define regBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT 0x010d 1722 #define regBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 8 1723 #define regBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT 0x010e 1724 #define regBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 8 1725 #define regBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT 0x010e 1726 #define regBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 8 1727 #define regBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT 0x010e 1728 #define regBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 8 1729 #define regBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT 0x010e 1730 #define regBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 8 1731 #define regBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT 0x010f 1732 #define regBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 8 1733 #define regBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT 0x010f 1734 #define regBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 8 1735 #define regBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT 0x010f 1736 #define regBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 8 1737 #define regBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT 0x010f 1738 #define regBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 8 1739 #define regBIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST 0x0114 1740 #define regBIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 8 1741 #define regBIF_CFG_DEV0_RC0_MARGINING_PORT_CAP 0x0115 1742 #define regBIF_CFG_DEV0_RC0_MARGINING_PORT_CAP_BASE_IDX 8 1743 #define regBIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS 0x0115 1744 #define regBIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS_BASE_IDX 8 1745 #define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL 0x0116 1746 #define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 8 1747 #define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS 0x0116 1748 #define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 8 1749 #define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL 0x0117 1750 #define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 8 1751 #define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS 0x0117 1752 #define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 8 1753 #define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL 0x0118 1754 #define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 8 1755 #define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS 0x0118 1756 #define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 8 1757 #define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL 0x0119 1758 #define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 8 1759 #define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS 0x0119 1760 #define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 8 1761 #define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL 0x011a 1762 #define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 8 1763 #define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS 0x011a 1764 #define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 8 1765 #define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL 0x011b 1766 #define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 8 1767 #define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS 0x011b 1768 #define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 8 1769 #define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL 0x011c 1770 #define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 8 1771 #define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS 0x011c 1772 #define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 8 1773 #define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL 0x011d 1774 #define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 8 1775 #define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS 0x011d 1776 #define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 8 1777 #define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL 0x011e 1778 #define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 8 1779 #define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS 0x011e 1780 #define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 8 1781 #define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL 0x011f 1782 #define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 8 1783 #define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS 0x011f 1784 #define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 8 1785 #define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL 0x0120 1786 #define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 8 1787 #define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS 0x0120 1788 #define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 8 1789 #define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL 0x0121 1790 #define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 8 1791 #define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS 0x0121 1792 #define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 8 1793 #define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL 0x0122 1794 #define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 8 1795 #define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS 0x0122 1796 #define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 8 1797 #define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL 0x0123 1798 #define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 8 1799 #define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS 0x0123 1800 #define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 8 1801 #define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL 0x0124 1802 #define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 8 1803 #define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS 0x0124 1804 #define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 8 1805 #define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL 0x0125 1806 #define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 8 1807 #define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS 0x0125 1808 #define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 8 1809 #define regBIF_CFG_DEV0_RC0_LINK_CAP_32GT 0x0141 1810 #define regBIF_CFG_DEV0_RC0_LINK_CAP_32GT_BASE_IDX 8 1811 #define regBIF_CFG_DEV0_RC0_LINK_CNTL_32GT 0x0142 1812 #define regBIF_CFG_DEV0_RC0_LINK_CNTL_32GT_BASE_IDX 8 1813 #define regBIF_CFG_DEV0_RC0_LINK_STATUS_32GT 0x0143 1814 #define regBIF_CFG_DEV0_RC0_LINK_STATUS_32GT_BASE_IDX 8 1815 1816 1817 // addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp 1818 // base address: 0x10140000 1819 #define regBIF_CFG_DEV0_EPF0_0_VENDOR_ID 0x10000 1820 #define regBIF_CFG_DEV0_EPF0_0_VENDOR_ID_BASE_IDX 8 1821 #define regBIF_CFG_DEV0_EPF0_0_DEVICE_ID 0x10000 1822 #define regBIF_CFG_DEV0_EPF0_0_DEVICE_ID_BASE_IDX 8 1823 #define regBIF_CFG_DEV0_EPF0_0_COMMAND 0x10001 1824 #define regBIF_CFG_DEV0_EPF0_0_COMMAND_BASE_IDX 8 1825 #define regBIF_CFG_DEV0_EPF0_0_STATUS 0x10001 1826 #define regBIF_CFG_DEV0_EPF0_0_STATUS_BASE_IDX 8 1827 #define regBIF_CFG_DEV0_EPF0_0_REVISION_ID 0x10002 1828 #define regBIF_CFG_DEV0_EPF0_0_REVISION_ID_BASE_IDX 8 1829 #define regBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE 0x10002 1830 #define regBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE_BASE_IDX 8 1831 #define regBIF_CFG_DEV0_EPF0_0_SUB_CLASS 0x10002 1832 #define regBIF_CFG_DEV0_EPF0_0_SUB_CLASS_BASE_IDX 8 1833 #define regBIF_CFG_DEV0_EPF0_0_BASE_CLASS 0x10002 1834 #define regBIF_CFG_DEV0_EPF0_0_BASE_CLASS_BASE_IDX 8 1835 #define regBIF_CFG_DEV0_EPF0_0_CACHE_LINE 0x10003 1836 #define regBIF_CFG_DEV0_EPF0_0_CACHE_LINE_BASE_IDX 8 1837 #define regBIF_CFG_DEV0_EPF0_0_LATENCY 0x10003 1838 #define regBIF_CFG_DEV0_EPF0_0_LATENCY_BASE_IDX 8 1839 #define regBIF_CFG_DEV0_EPF0_0_HEADER 0x10003 1840 #define regBIF_CFG_DEV0_EPF0_0_HEADER_BASE_IDX 8 1841 #define regBIF_CFG_DEV0_EPF0_0_BIST 0x10003 1842 #define regBIF_CFG_DEV0_EPF0_0_BIST_BASE_IDX 8 1843 #define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1 0x10004 1844 #define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1_BASE_IDX 8 1845 #define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2 0x10005 1846 #define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2_BASE_IDX 8 1847 #define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3 0x10006 1848 #define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3_BASE_IDX 8 1849 #define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4 0x10007 1850 #define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4_BASE_IDX 8 1851 #define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5 0x10008 1852 #define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5_BASE_IDX 8 1853 #define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6 0x10009 1854 #define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6_BASE_IDX 8 1855 #define regBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR 0x1000a 1856 #define regBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR_BASE_IDX 8 1857 #define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID 0x1000b 1858 #define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_BASE_IDX 8 1859 #define regBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR 0x1000c 1860 #define regBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR_BASE_IDX 8 1861 #define regBIF_CFG_DEV0_EPF0_0_CAP_PTR 0x1000d 1862 #define regBIF_CFG_DEV0_EPF0_0_CAP_PTR_BASE_IDX 8 1863 #define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE 0x1000f 1864 #define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE_BASE_IDX 8 1865 #define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN 0x1000f 1866 #define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN_BASE_IDX 8 1867 #define regBIF_CFG_DEV0_EPF0_0_MIN_GRANT 0x1000f 1868 #define regBIF_CFG_DEV0_EPF0_0_MIN_GRANT_BASE_IDX 8 1869 #define regBIF_CFG_DEV0_EPF0_0_MAX_LATENCY 0x1000f 1870 #define regBIF_CFG_DEV0_EPF0_0_MAX_LATENCY_BASE_IDX 8 1871 #define regBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST 0x10012 1872 #define regBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST_BASE_IDX 8 1873 #define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W 0x10013 1874 #define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W_BASE_IDX 8 1875 #define regBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST 0x10014 1876 #define regBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST_BASE_IDX 8 1877 #define regBIF_CFG_DEV0_EPF0_0_PMI_CAP 0x10014 1878 #define regBIF_CFG_DEV0_EPF0_0_PMI_CAP_BASE_IDX 8 1879 #define regBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL 0x10015 1880 #define regBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL_BASE_IDX 8 1881 #define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST 0x10019 1882 #define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST_BASE_IDX 8 1883 #define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP 0x10019 1884 #define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_BASE_IDX 8 1885 #define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP 0x1001a 1886 #define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP_BASE_IDX 8 1887 #define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL 0x1001b 1888 #define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL_BASE_IDX 8 1889 #define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS 0x1001b 1890 #define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS_BASE_IDX 8 1891 #define regBIF_CFG_DEV0_EPF0_0_LINK_CAP 0x1001c 1892 #define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_BASE_IDX 8 1893 #define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL 0x1001d 1894 #define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_BASE_IDX 8 1895 #define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS 0x1001d 1896 #define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_BASE_IDX 8 1897 #define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2 0x10022 1898 #define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2_BASE_IDX 8 1899 #define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2 0x10023 1900 #define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2_BASE_IDX 8 1901 #define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2 0x10023 1902 #define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2_BASE_IDX 8 1903 #define regBIF_CFG_DEV0_EPF0_0_LINK_CAP2 0x10024 1904 #define regBIF_CFG_DEV0_EPF0_0_LINK_CAP2_BASE_IDX 8 1905 #define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL2 0x10025 1906 #define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL2_BASE_IDX 8 1907 #define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS2 0x10025 1908 #define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS2_BASE_IDX 8 1909 #define regBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST 0x10028 1910 #define regBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST_BASE_IDX 8 1911 #define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL 0x10028 1912 #define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL_BASE_IDX 8 1913 #define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO 0x10029 1914 #define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO_BASE_IDX 8 1915 #define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI 0x1002a 1916 #define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI_BASE_IDX 8 1917 #define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA 0x1002a 1918 #define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_BASE_IDX 8 1919 #define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA 0x1002a 1920 #define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_BASE_IDX 8 1921 #define regBIF_CFG_DEV0_EPF0_0_MSI_MASK 0x1002b 1922 #define regBIF_CFG_DEV0_EPF0_0_MSI_MASK_BASE_IDX 8 1923 #define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64 0x1002b 1924 #define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64_BASE_IDX 8 1925 #define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64 0x1002b 1926 #define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64_BASE_IDX 8 1927 #define regBIF_CFG_DEV0_EPF0_0_MSI_MASK_64 0x1002c 1928 #define regBIF_CFG_DEV0_EPF0_0_MSI_MASK_64_BASE_IDX 8 1929 #define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING 0x1002c 1930 #define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_BASE_IDX 8 1931 #define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64 0x1002d 1932 #define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64_BASE_IDX 8 1933 #define regBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST 0x10030 1934 #define regBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST_BASE_IDX 8 1935 #define regBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL 0x10030 1936 #define regBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL_BASE_IDX 8 1937 #define regBIF_CFG_DEV0_EPF0_0_MSIX_TABLE 0x10031 1938 #define regBIF_CFG_DEV0_EPF0_0_MSIX_TABLE_BASE_IDX 8 1939 #define regBIF_CFG_DEV0_EPF0_0_MSIX_PBA 0x10032 1940 #define regBIF_CFG_DEV0_EPF0_0_MSIX_PBA_BASE_IDX 8 1941 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040 1942 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 8 1943 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR 0x10041 1944 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 8 1945 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1 0x10042 1946 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 8 1947 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2 0x10043 1948 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 8 1949 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST 0x10044 1950 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST_BASE_IDX 8 1951 #define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1 0x10045 1952 #define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1_BASE_IDX 8 1953 #define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2 0x10046 1954 #define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2_BASE_IDX 8 1955 #define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL 0x10047 1956 #define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL_BASE_IDX 8 1957 #define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS 0x10047 1958 #define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS_BASE_IDX 8 1959 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP 0x10048 1960 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP_BASE_IDX 8 1961 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL 0x10049 1962 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 8 1963 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS 0x1004a 1964 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 8 1965 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP 0x1004b 1966 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP_BASE_IDX 8 1967 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL 0x1004c 1968 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 8 1969 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS 0x1004d 1970 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 8 1971 #define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x10050 1972 #define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 8 1973 #define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1 0x10051 1974 #define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 8 1975 #define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2 0x10052 1976 #define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 8 1977 #define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10054 1978 #define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 8 1979 #define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS 0x10055 1980 #define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 8 1981 #define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK 0x10056 1982 #define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK_BASE_IDX 8 1983 #define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY 0x10057 1984 #define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 8 1985 #define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS 0x10058 1986 #define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS_BASE_IDX 8 1987 #define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK 0x10059 1988 #define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK_BASE_IDX 8 1989 #define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL 0x1005a 1990 #define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 8 1991 #define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0 0x1005b 1992 #define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0_BASE_IDX 8 1993 #define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1 0x1005c 1994 #define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1_BASE_IDX 8 1995 #define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2 0x1005d 1996 #define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2_BASE_IDX 8 1997 #define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3 0x1005e 1998 #define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3_BASE_IDX 8 1999 #define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0 0x10062 2000 #define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 8 2001 #define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1 0x10063 2002 #define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 8 2003 #define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2 0x10064 2004 #define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 8 2005 #define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3 0x10065 2006 #define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 8 2007 #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST 0x10080 2008 #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 8 2009 #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP 0x10081 2010 #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP_BASE_IDX 8 2011 #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL 0x10082 2012 #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL_BASE_IDX 8 2013 #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP 0x10083 2014 #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP_BASE_IDX 8 2015 #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL 0x10084 2016 #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL_BASE_IDX 8 2017 #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP 0x10085 2018 #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP_BASE_IDX 8 2019 #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL 0x10086 2020 #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL_BASE_IDX 8 2021 #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP 0x10087 2022 #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP_BASE_IDX 8 2023 #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL 0x10088 2024 #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL_BASE_IDX 8 2025 #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP 0x10089 2026 #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP_BASE_IDX 8 2027 #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL 0x1008a 2028 #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL_BASE_IDX 8 2029 #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP 0x1008b 2030 #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP_BASE_IDX 8 2031 #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL 0x1008c 2032 #define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL_BASE_IDX 8 2033 #define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x10090 2034 #define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 8 2035 #define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT 0x10091 2036 #define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 8 2037 #define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA 0x10092 2038 #define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_BASE_IDX 8 2039 #define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP 0x10093 2040 #define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP_BASE_IDX 8 2041 #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST 0x10094 2042 #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 8 2043 #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP 0x10095 2044 #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP_BASE_IDX 8 2045 #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR 0x10096 2046 #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 8 2047 #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS 0x10097 2048 #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS_BASE_IDX 8 2049 #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL 0x10097 2050 #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL_BASE_IDX 8 2051 #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x10098 2052 #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 8 2053 #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x10098 2054 #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 8 2055 #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x10098 2056 #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 8 2057 #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x10098 2058 #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 8 2059 #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x10099 2060 #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 8 2061 #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x10099 2062 #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 8 2063 #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x10099 2064 #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 8 2065 #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x10099 2066 #define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 8 2067 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST 0x1009c 2068 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 8 2069 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3 0x1009d 2070 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3_BASE_IDX 8 2071 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS 0x1009e 2072 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS_BASE_IDX 8 2073 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x1009f 2074 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 8 2075 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x1009f 2076 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 8 2077 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x100a0 2078 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 8 2079 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x100a0 2080 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 8 2081 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x100a1 2082 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 8 2083 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x100a1 2084 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 8 2085 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x100a2 2086 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 8 2087 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x100a2 2088 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 8 2089 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x100a3 2090 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 8 2091 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x100a3 2092 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 8 2093 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x100a4 2094 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 8 2095 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x100a4 2096 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 8 2097 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x100a5 2098 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 8 2099 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x100a5 2100 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 8 2101 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x100a6 2102 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 8 2103 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x100a6 2104 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 8 2105 #define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST 0x100a8 2106 #define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 8 2107 #define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP 0x100a9 2108 #define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP_BASE_IDX 8 2109 #define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL 0x100a9 2110 #define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL_BASE_IDX 8 2111 #define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST 0x100ac 2112 #define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST_BASE_IDX 8 2113 #define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP 0x100ad 2114 #define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP_BASE_IDX 8 2115 #define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL 0x100ad 2116 #define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL_BASE_IDX 8 2117 #define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x100b0 2118 #define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST_BASE_IDX 8 2119 #define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL 0x100b1 2120 #define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL_BASE_IDX 8 2121 #define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS 0x100b1 2122 #define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS_BASE_IDX 8 2123 #define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x100b2 2124 #define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_BASE_IDX 8 2125 #define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x100b3 2126 #define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX 8 2127 #define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST 0x100b4 2128 #define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 8 2129 #define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP 0x100b5 2130 #define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP_BASE_IDX 8 2131 #define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL 0x100b5 2132 #define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL_BASE_IDX 8 2133 #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST 0x100bc 2134 #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST_BASE_IDX 8 2135 #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP 0x100bd 2136 #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP_BASE_IDX 8 2137 #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL 0x100bd 2138 #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL_BASE_IDX 8 2139 #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0 0x100be 2140 #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0_BASE_IDX 8 2141 #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1 0x100bf 2142 #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1_BASE_IDX 8 2143 #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0 0x100c0 2144 #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0_BASE_IDX 8 2145 #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1 0x100c1 2146 #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1_BASE_IDX 8 2147 #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0 0x100c2 2148 #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0_BASE_IDX 8 2149 #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1 0x100c3 2150 #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1_BASE_IDX 8 2151 #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x100c4 2152 #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX 8 2153 #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x100c5 2154 #define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX 8 2155 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST 0x100c8 2156 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST_BASE_IDX 8 2157 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP 0x100c9 2158 #define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP_BASE_IDX 8 2159 #define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST 0x100ca 2160 #define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 8 2161 #define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP 0x100cb 2162 #define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP_BASE_IDX 8 2163 #define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL 0x100cb 2164 #define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL_BASE_IDX 8 2165 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST 0x100cc 2166 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX 8 2167 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP 0x100cd 2168 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP_BASE_IDX 8 2169 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL 0x100ce 2170 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL_BASE_IDX 8 2171 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS 0x100ce 2172 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS_BASE_IDX 8 2173 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS 0x100cf 2174 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS_BASE_IDX 8 2175 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS 0x100cf 2176 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS_BASE_IDX 8 2177 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS 0x100d0 2178 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS_BASE_IDX 8 2179 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK 0x100d0 2180 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX 8 2181 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET 0x100d1 2182 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX 8 2183 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE 0x100d1 2184 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE_BASE_IDX 8 2185 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID 0x100d2 2186 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX 8 2187 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x100d3 2188 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX 8 2189 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x100d4 2190 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX 8 2191 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0 0x100d5 2192 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX 8 2193 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1 0x100d6 2194 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX 8 2195 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2 0x100d7 2196 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX 8 2197 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3 0x100d8 2198 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX 8 2199 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4 0x100d9 2200 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX 8 2201 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5 0x100da 2202 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX 8 2203 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x100db 2204 #define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX 8 2205 #define regBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST 0x10100 2206 #define regBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 8 2207 #define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP 0x10101 2208 #define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP_BASE_IDX 8 2209 #define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS 0x10102 2210 #define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS_BASE_IDX 8 2211 #define regBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST 0x10104 2212 #define regBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 8 2213 #define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT 0x10105 2214 #define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT_BASE_IDX 8 2215 #define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT 0x10106 2216 #define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT_BASE_IDX 8 2217 #define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT 0x10107 2218 #define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT_BASE_IDX 8 2219 #define regBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x10108 2220 #define regBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 8 2221 #define regBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x10109 2222 #define regBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 8 2223 #define regBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x1010a 2224 #define regBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 8 2225 #define regBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT 0x1010c 2226 #define regBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 8 2227 #define regBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT 0x1010c 2228 #define regBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 8 2229 #define regBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT 0x1010c 2230 #define regBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 8 2231 #define regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT 0x1010c 2232 #define regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 8 2233 #define regBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT 0x1010d 2234 #define regBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 8 2235 #define regBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT 0x1010d 2236 #define regBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 8 2237 #define regBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT 0x1010d 2238 #define regBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 8 2239 #define regBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT 0x1010d 2240 #define regBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 8 2241 #define regBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT 0x1010e 2242 #define regBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 8 2243 #define regBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT 0x1010e 2244 #define regBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 8 2245 #define regBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT 0x1010e 2246 #define regBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 8 2247 #define regBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT 0x1010e 2248 #define regBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 8 2249 #define regBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT 0x1010f 2250 #define regBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 8 2251 #define regBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT 0x1010f 2252 #define regBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 8 2253 #define regBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT 0x1010f 2254 #define regBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 8 2255 #define regBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT 0x1010f 2256 #define regBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 8 2257 #define regBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST 0x10114 2258 #define regBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 8 2259 #define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP 0x10115 2260 #define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP_BASE_IDX 8 2261 #define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS 0x10115 2262 #define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS_BASE_IDX 8 2263 #define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL 0x10116 2264 #define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 8 2265 #define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS 0x10116 2266 #define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 8 2267 #define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL 0x10117 2268 #define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 8 2269 #define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS 0x10117 2270 #define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 8 2271 #define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL 0x10118 2272 #define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 8 2273 #define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS 0x10118 2274 #define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 8 2275 #define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL 0x10119 2276 #define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 8 2277 #define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS 0x10119 2278 #define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 8 2279 #define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL 0x1011a 2280 #define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 8 2281 #define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS 0x1011a 2282 #define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 8 2283 #define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL 0x1011b 2284 #define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 8 2285 #define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS 0x1011b 2286 #define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 8 2287 #define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL 0x1011c 2288 #define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 8 2289 #define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS 0x1011c 2290 #define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 8 2291 #define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL 0x1011d 2292 #define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 8 2293 #define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS 0x1011d 2294 #define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 8 2295 #define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL 0x1011e 2296 #define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 8 2297 #define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS 0x1011e 2298 #define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 8 2299 #define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL 0x1011f 2300 #define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 8 2301 #define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS 0x1011f 2302 #define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 8 2303 #define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL 0x10120 2304 #define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 8 2305 #define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS 0x10120 2306 #define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 8 2307 #define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL 0x10121 2308 #define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 8 2309 #define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS 0x10121 2310 #define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 8 2311 #define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL 0x10122 2312 #define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 8 2313 #define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS 0x10122 2314 #define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 8 2315 #define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL 0x10123 2316 #define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 8 2317 #define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS 0x10123 2318 #define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 8 2319 #define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL 0x10124 2320 #define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 8 2321 #define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS 0x10124 2322 #define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 8 2323 #define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL 0x10125 2324 #define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 8 2325 #define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS 0x10125 2326 #define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 8 2327 #define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT 0x10141 2328 #define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT_BASE_IDX 8 2329 #define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT 0x10142 2330 #define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT_BASE_IDX 8 2331 #define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT 0x10143 2332 #define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT_BASE_IDX 8 2333 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x101c0 2334 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_BASE_IDX 8 2335 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x101c1 2336 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_BASE_IDX 8 2337 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x101c2 2338 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x101c3 2339 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_BASE_IDX 8 2340 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x101c4 2341 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_BASE_IDX 8 2342 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x101c5 2343 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_BASE_IDX 8 2344 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x101c6 2345 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_BASE_IDX 8 2346 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x101c7 2347 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_BASE_IDX 8 2348 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x101c8 2349 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_BASE_IDX 8 2350 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x101c9 2351 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_BASE_IDX 8 2352 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x101ca 2353 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_BASE_IDX 8 2354 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION 0x101cc 2355 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION_BASE_IDX 8 2356 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 0x101cd 2357 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE_BASE_IDX 8 2358 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x101ce 2359 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_BASE_IDX 8 2360 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x101cf 2361 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_BASE_IDX 8 2362 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x101d0 2363 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_BASE_IDX 8 2364 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x101d1 2365 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_BASE_IDX 8 2366 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x101d2 2367 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_BASE_IDX 8 2368 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x101d3 2369 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_BASE_IDX 8 2370 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x101d4 2371 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_BASE_IDX 8 2372 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x101d5 2373 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_BASE_IDX 8 2374 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x101d6 2375 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_BASE_IDX 8 2376 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x101d7 2377 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_BASE_IDX 8 2378 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x101d8 2379 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_BASE_IDX 8 2380 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x101d9 2381 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_BASE_IDX 8 2382 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x101da 2383 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_BASE_IDX 8 2384 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x101db 2385 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_BASE_IDX 8 2386 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x101dc 2387 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_BASE_IDX 8 2388 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x101dd 2389 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_BASE_IDX 8 2390 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 0x101de 2391 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB_BASE_IDX 8 2392 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 0x101df 2393 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB_BASE_IDX 8 2394 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 0x101e0 2395 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB_BASE_IDX 8 2396 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 0x101e1 2397 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB_BASE_IDX 8 2398 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 0x101e2 2399 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB_BASE_IDX 8 2400 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 0x101e3 2401 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB_BASE_IDX 8 2402 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 0x101e4 2403 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB_BASE_IDX 8 2404 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 0x101e5 2405 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB_BASE_IDX 8 2406 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 0x101e6 2407 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB_BASE_IDX 8 2408 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 0x101e7 2409 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB_BASE_IDX 8 2410 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 0x101e8 2411 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB_BASE_IDX 8 2412 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 0x101e9 2413 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB_BASE_IDX 8 2414 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 0x101ea 2415 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB_BASE_IDX 8 2416 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 0x101eb 2417 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB_BASE_IDX 8 2418 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 0x101ec 2419 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB_BASE_IDX 8 2420 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x101f0 2421 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_BASE_IDX 8 2422 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1 0x101f1 2423 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1_BASE_IDX 8 2424 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2 0x101f2 2425 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2_BASE_IDX 8 2426 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3 0x101f3 2427 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3_BASE_IDX 8 2428 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4 0x101f4 2429 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4_BASE_IDX 8 2430 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0 0x101fc 2431 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0_BASE_IDX 8 2432 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1 0x101fd 2433 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1_BASE_IDX 8 2434 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2 0x101fe 2435 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2_BASE_IDX 8 2436 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3 0x101ff 2437 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3_BASE_IDX 8 2438 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4 0x10200 2439 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4_BASE_IDX 8 2440 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5 0x10201 2441 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5_BASE_IDX 8 2442 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6 0x10202 2443 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6_BASE_IDX 8 2444 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7 0x10203 2445 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7_BASE_IDX 8 2446 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8 0x10204 2447 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8_BASE_IDX 8 2448 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 0x10208 2449 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0_BASE_IDX 8 2450 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 0x10209 2451 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1_BASE_IDX 8 2452 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 0x1020a 2453 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2_BASE_IDX 8 2454 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 0x1020b 2455 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3_BASE_IDX 8 2456 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 0x1020c 2457 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4_BASE_IDX 8 2458 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 0x1020d 2459 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5_BASE_IDX 8 2460 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 0x1020e 2461 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6_BASE_IDX 8 2462 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 0x1020f 2463 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7_BASE_IDX 8 2464 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 0x10210 2465 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8_BASE_IDX 8 2466 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0 0x10214 2467 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0_BASE_IDX 8 2468 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1 0x10215 2469 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1_BASE_IDX 8 2470 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2 0x10216 2471 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2_BASE_IDX 8 2472 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3 0x10217 2473 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3_BASE_IDX 8 2474 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4 0x10218 2475 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4_BASE_IDX 8 2476 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5 0x10219 2477 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5_BASE_IDX 8 2478 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6 0x1021a 2479 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6_BASE_IDX 8 2480 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7 0x1021b 2481 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7_BASE_IDX 8 2482 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8 0x1021c 2483 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8_BASE_IDX 8 2484 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0 0x10220 2485 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0_BASE_IDX 8 2486 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1 0x10221 2487 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1_BASE_IDX 8 2488 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2 0x10222 2489 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2_BASE_IDX 8 2490 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3 0x10223 2491 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3_BASE_IDX 8 2492 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4 0x10224 2493 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4_BASE_IDX 8 2494 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5 0x10225 2495 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5_BASE_IDX 8 2496 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6 0x10226 2497 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6_BASE_IDX 8 2498 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7 0x10227 2499 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7_BASE_IDX 8 2500 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8 0x10228 2501 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8_BASE_IDX 8 2502 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0 0x1022c 2503 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0_BASE_IDX 8 2504 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1 0x1022d 2505 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1_BASE_IDX 8 2506 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2 0x1022e 2507 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2_BASE_IDX 8 2508 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3 0x1022f 2509 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3_BASE_IDX 8 2510 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4 0x10230 2511 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4_BASE_IDX 8 2512 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5 0x10231 2513 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5_BASE_IDX 8 2514 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6 0x10232 2515 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6_BASE_IDX 8 2516 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7 0x10233 2517 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7_BASE_IDX 8 2518 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8 0x10234 2519 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8_BASE_IDX 8 2520 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0 0x10238 2521 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0_BASE_IDX 8 2522 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1 0x10239 2523 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1_BASE_IDX 8 2524 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2 0x1023a 2525 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2_BASE_IDX 8 2526 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3 0x1023b 2527 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3_BASE_IDX 8 2528 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4 0x1023c 2529 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4_BASE_IDX 8 2530 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5 0x1023d 2531 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5_BASE_IDX 8 2532 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6 0x1023e 2533 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6_BASE_IDX 8 2534 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7 0x1023f 2535 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7_BASE_IDX 8 2536 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8 0x10240 2537 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8_BASE_IDX 8 2538 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0 0x10244 2539 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0_BASE_IDX 8 2540 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1 0x10245 2541 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1_BASE_IDX 8 2542 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2 0x10246 2543 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2_BASE_IDX 8 2544 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3 0x10247 2545 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3_BASE_IDX 8 2546 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4 0x10248 2547 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4_BASE_IDX 8 2548 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5 0x10249 2549 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5_BASE_IDX 8 2550 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6 0x1024a 2551 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6_BASE_IDX 8 2552 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7 0x1024b 2553 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7_BASE_IDX 8 2554 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8 0x1024c 2555 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8_BASE_IDX 8 2556 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0 0x10250 2557 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0_BASE_IDX 8 2558 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1 0x10251 2559 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1_BASE_IDX 8 2560 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2 0x10252 2561 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2_BASE_IDX 8 2562 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3 0x10253 2563 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3_BASE_IDX 8 2564 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4 0x10254 2565 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4_BASE_IDX 8 2566 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5 0x10255 2567 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5_BASE_IDX 8 2568 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6 0x10256 2569 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6_BASE_IDX 8 2570 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7 0x10257 2571 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7_BASE_IDX 8 2572 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8 0x10258 2573 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8_BASE_IDX 8 2574 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0 0x1025c 2575 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0_BASE_IDX 8 2576 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1 0x1025d 2577 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1_BASE_IDX 8 2578 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2 0x1025e 2579 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2_BASE_IDX 8 2580 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3 0x1025f 2581 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3_BASE_IDX 8 2582 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4 0x10260 2583 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4_BASE_IDX 8 2584 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5 0x10261 2585 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5_BASE_IDX 8 2586 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6 0x10262 2587 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6_BASE_IDX 8 2588 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7 0x10263 2589 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7_BASE_IDX 8 2590 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8 0x10264 2591 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8_BASE_IDX 8 2592 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0 0x10268 2593 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0_BASE_IDX 8 2594 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1 0x10269 2595 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1_BASE_IDX 8 2596 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2 0x1026a 2597 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2_BASE_IDX 8 2598 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3 0x1026b 2599 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3_BASE_IDX 8 2600 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4 0x1026c 2601 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4_BASE_IDX 8 2602 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5 0x1026d 2603 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5_BASE_IDX 8 2604 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6 0x1026e 2605 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6_BASE_IDX 8 2606 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7 0x1026f 2607 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7_BASE_IDX 8 2608 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8 0x10270 2609 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8_BASE_IDX 8 2610 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0 0x10274 2611 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0_BASE_IDX 8 2612 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1 0x10275 2613 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1_BASE_IDX 8 2614 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2 0x10276 2615 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2_BASE_IDX 8 2616 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3 0x10277 2617 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3_BASE_IDX 8 2618 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4 0x10278 2619 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4_BASE_IDX 8 2620 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5 0x10279 2621 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5_BASE_IDX 8 2622 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6 0x1027a 2623 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6_BASE_IDX 8 2624 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7 0x1027b 2625 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7_BASE_IDX 8 2626 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8 0x1027c 2627 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8_BASE_IDX 8 2628 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0 0x10280 2629 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0_BASE_IDX 8 2630 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1 0x10281 2631 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1_BASE_IDX 8 2632 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2 0x10282 2633 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2_BASE_IDX 8 2634 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3 0x10283 2635 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3_BASE_IDX 8 2636 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4 0x10284 2637 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4_BASE_IDX 8 2638 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5 0x10285 2639 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5_BASE_IDX 8 2640 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6 0x10286 2641 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6_BASE_IDX 8 2642 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7 0x10287 2643 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7_BASE_IDX 8 2644 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8 0x10288 2645 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8_BASE_IDX 8 2646 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0 0x1028c 2647 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0_BASE_IDX 8 2648 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1 0x1028d 2649 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1_BASE_IDX 8 2650 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2 0x1028e 2651 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2_BASE_IDX 8 2652 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3 0x1028f 2653 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3_BASE_IDX 8 2654 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4 0x10290 2655 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4_BASE_IDX 8 2656 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5 0x10291 2657 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5_BASE_IDX 8 2658 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6 0x10292 2659 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6_BASE_IDX 8 2660 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7 0x10293 2661 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7_BASE_IDX 8 2662 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8 0x10294 2663 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8_BASE_IDX 8 2664 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0 0x10298 2665 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0_BASE_IDX 8 2666 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1 0x10299 2667 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1_BASE_IDX 8 2668 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2 0x1029a 2669 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2_BASE_IDX 8 2670 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3 0x1029b 2671 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3_BASE_IDX 8 2672 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4 0x1029c 2673 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4_BASE_IDX 8 2674 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5 0x1029d 2675 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5_BASE_IDX 8 2676 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6 0x1029e 2677 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6_BASE_IDX 8 2678 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7 0x1029f 2679 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7_BASE_IDX 8 2680 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8 0x102a0 2681 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8_BASE_IDX 8 2682 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0 0x102a4 2683 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0_BASE_IDX 8 2684 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1 0x102a5 2685 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1_BASE_IDX 8 2686 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2 0x102a6 2687 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2_BASE_IDX 8 2688 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3 0x102a7 2689 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3_BASE_IDX 8 2690 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4 0x102a8 2691 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4_BASE_IDX 8 2692 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5 0x102a9 2693 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5_BASE_IDX 8 2694 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6 0x102aa 2695 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6_BASE_IDX 8 2696 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7 0x102ab 2697 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7_BASE_IDX 8 2698 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8 0x102ac 2699 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8_BASE_IDX 8 2700 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0 0x102b0 2701 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0_BASE_IDX 8 2702 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1 0x102b1 2703 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1_BASE_IDX 8 2704 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2 0x102b2 2705 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2_BASE_IDX 8 2706 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3 0x102b3 2707 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3_BASE_IDX 8 2708 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4 0x102b4 2709 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4_BASE_IDX 8 2710 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5 0x102b5 2711 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5_BASE_IDX 8 2712 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6 0x102b6 2713 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6_BASE_IDX 8 2714 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7 0x102b7 2715 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7_BASE_IDX 8 2716 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8 0x102b8 2717 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8_BASE_IDX 8 2718 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0 0x102bc 2719 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0_BASE_IDX 8 2720 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1 0x102bd 2721 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1_BASE_IDX 8 2722 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2 0x102be 2723 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2_BASE_IDX 8 2724 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3 0x102bf 2725 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3_BASE_IDX 8 2726 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4 0x102c0 2727 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4_BASE_IDX 8 2728 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5 0x102c1 2729 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5_BASE_IDX 8 2730 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6 0x102c2 2731 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6_BASE_IDX 8 2732 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7 0x102c3 2733 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7_BASE_IDX 8 2734 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8 0x102c4 2735 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8_BASE_IDX 8 2736 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0 0x102c8 2737 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0_BASE_IDX 8 2738 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1 0x102c9 2739 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1_BASE_IDX 8 2740 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2 0x102ca 2741 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2_BASE_IDX 8 2742 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3 0x102cb 2743 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3_BASE_IDX 8 2744 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4 0x102cc 2745 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4_BASE_IDX 8 2746 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5 0x102cd 2747 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5_BASE_IDX 8 2748 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6 0x102ce 2749 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6_BASE_IDX 8 2750 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7 0x102cf 2751 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7_BASE_IDX 8 2752 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8 0x102d0 2753 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8_BASE_IDX 8 2754 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0 0x102d4 2755 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0_BASE_IDX 8 2756 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1 0x102d5 2757 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1_BASE_IDX 8 2758 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2 0x102d6 2759 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2_BASE_IDX 8 2760 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3 0x102d7 2761 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3_BASE_IDX 8 2762 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4 0x102d8 2763 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4_BASE_IDX 8 2764 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5 0x102d9 2765 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5_BASE_IDX 8 2766 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6 0x102da 2767 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6_BASE_IDX 8 2768 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7 0x102db 2769 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7_BASE_IDX 8 2770 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8 0x102dc 2771 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8_BASE_IDX 8 2772 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0 0x102e0 2773 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0_BASE_IDX 8 2774 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1 0x102e1 2775 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1_BASE_IDX 8 2776 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2 0x102e2 2777 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2_BASE_IDX 8 2778 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3 0x102e3 2779 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3_BASE_IDX 8 2780 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4 0x102e4 2781 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4_BASE_IDX 8 2782 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5 0x102e5 2783 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5_BASE_IDX 8 2784 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6 0x102e6 2785 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6_BASE_IDX 8 2786 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7 0x102e7 2787 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7_BASE_IDX 8 2788 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8 0x102e8 2789 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8_BASE_IDX 8 2790 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE 0x10300 2791 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE_BASE_IDX 8 2792 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_ENABLE 0x10301 2793 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_ENABLE_BASE_IDX 8 2794 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE 0x10302 2795 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE_BASE_IDX 8 2796 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE 0x10303 2797 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE_BASE_IDX 8 2798 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS 0x10304 2799 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS_BASE_IDX 8 2800 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_STATUS 0x10305 2801 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_STATUS_BASE_IDX 8 2802 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS 0x10306 2803 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS_BASE_IDX 8 2804 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS 0x10307 2805 #define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS_BASE_IDX 8 2806 2807 2808 // addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp 2809 // base address: 0x10141000 2810 #define regBIF_CFG_DEV0_EPF1_0_VENDOR_ID 0x10400 2811 #define regBIF_CFG_DEV0_EPF1_0_VENDOR_ID_BASE_IDX 8 2812 #define regBIF_CFG_DEV0_EPF1_0_DEVICE_ID 0x10400 2813 #define regBIF_CFG_DEV0_EPF1_0_DEVICE_ID_BASE_IDX 8 2814 #define regBIF_CFG_DEV0_EPF1_0_COMMAND 0x10401 2815 #define regBIF_CFG_DEV0_EPF1_0_COMMAND_BASE_IDX 8 2816 #define regBIF_CFG_DEV0_EPF1_0_STATUS 0x10401 2817 #define regBIF_CFG_DEV0_EPF1_0_STATUS_BASE_IDX 8 2818 #define regBIF_CFG_DEV0_EPF1_0_REVISION_ID 0x10402 2819 #define regBIF_CFG_DEV0_EPF1_0_REVISION_ID_BASE_IDX 8 2820 #define regBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE 0x10402 2821 #define regBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE_BASE_IDX 8 2822 #define regBIF_CFG_DEV0_EPF1_0_SUB_CLASS 0x10402 2823 #define regBIF_CFG_DEV0_EPF1_0_SUB_CLASS_BASE_IDX 8 2824 #define regBIF_CFG_DEV0_EPF1_0_BASE_CLASS 0x10402 2825 #define regBIF_CFG_DEV0_EPF1_0_BASE_CLASS_BASE_IDX 8 2826 #define regBIF_CFG_DEV0_EPF1_0_CACHE_LINE 0x10403 2827 #define regBIF_CFG_DEV0_EPF1_0_CACHE_LINE_BASE_IDX 8 2828 #define regBIF_CFG_DEV0_EPF1_0_LATENCY 0x10403 2829 #define regBIF_CFG_DEV0_EPF1_0_LATENCY_BASE_IDX 8 2830 #define regBIF_CFG_DEV0_EPF1_0_HEADER 0x10403 2831 #define regBIF_CFG_DEV0_EPF1_0_HEADER_BASE_IDX 8 2832 #define regBIF_CFG_DEV0_EPF1_0_BIST 0x10403 2833 #define regBIF_CFG_DEV0_EPF1_0_BIST_BASE_IDX 8 2834 #define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1 0x10404 2835 #define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1_BASE_IDX 8 2836 #define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2 0x10405 2837 #define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2_BASE_IDX 8 2838 #define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3 0x10406 2839 #define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3_BASE_IDX 8 2840 #define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4 0x10407 2841 #define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4_BASE_IDX 8 2842 #define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5 0x10408 2843 #define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5_BASE_IDX 8 2844 #define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6 0x10409 2845 #define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6_BASE_IDX 8 2846 #define regBIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR 0x1040a 2847 #define regBIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR_BASE_IDX 8 2848 #define regBIF_CFG_DEV0_EPF1_0_ADAPTER_ID 0x1040b 2849 #define regBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_BASE_IDX 8 2850 #define regBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR 0x1040c 2851 #define regBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR_BASE_IDX 8 2852 #define regBIF_CFG_DEV0_EPF1_0_CAP_PTR 0x1040d 2853 #define regBIF_CFG_DEV0_EPF1_0_CAP_PTR_BASE_IDX 8 2854 #define regBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE 0x1040f 2855 #define regBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE_BASE_IDX 8 2856 #define regBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN 0x1040f 2857 #define regBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN_BASE_IDX 8 2858 #define regBIF_CFG_DEV0_EPF1_0_MIN_GRANT 0x1040f 2859 #define regBIF_CFG_DEV0_EPF1_0_MIN_GRANT_BASE_IDX 8 2860 #define regBIF_CFG_DEV0_EPF1_0_MAX_LATENCY 0x1040f 2861 #define regBIF_CFG_DEV0_EPF1_0_MAX_LATENCY_BASE_IDX 8 2862 #define regBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST 0x10412 2863 #define regBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST_BASE_IDX 8 2864 #define regBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W 0x10413 2865 #define regBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W_BASE_IDX 8 2866 #define regBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST 0x10414 2867 #define regBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST_BASE_IDX 8 2868 #define regBIF_CFG_DEV0_EPF1_0_PMI_CAP 0x10414 2869 #define regBIF_CFG_DEV0_EPF1_0_PMI_CAP_BASE_IDX 8 2870 #define regBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL 0x10415 2871 #define regBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL_BASE_IDX 8 2872 #define regBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST 0x10419 2873 #define regBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST_BASE_IDX 8 2874 #define regBIF_CFG_DEV0_EPF1_0_PCIE_CAP 0x10419 2875 #define regBIF_CFG_DEV0_EPF1_0_PCIE_CAP_BASE_IDX 8 2876 #define regBIF_CFG_DEV0_EPF1_0_DEVICE_CAP 0x1041a 2877 #define regBIF_CFG_DEV0_EPF1_0_DEVICE_CAP_BASE_IDX 8 2878 #define regBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL 0x1041b 2879 #define regBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL_BASE_IDX 8 2880 #define regBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS 0x1041b 2881 #define regBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS_BASE_IDX 8 2882 #define regBIF_CFG_DEV0_EPF1_0_LINK_CAP 0x1041c 2883 #define regBIF_CFG_DEV0_EPF1_0_LINK_CAP_BASE_IDX 8 2884 #define regBIF_CFG_DEV0_EPF1_0_LINK_CNTL 0x1041d 2885 #define regBIF_CFG_DEV0_EPF1_0_LINK_CNTL_BASE_IDX 8 2886 #define regBIF_CFG_DEV0_EPF1_0_LINK_STATUS 0x1041d 2887 #define regBIF_CFG_DEV0_EPF1_0_LINK_STATUS_BASE_IDX 8 2888 #define regBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2 0x10422 2889 #define regBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2_BASE_IDX 8 2890 #define regBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2 0x10423 2891 #define regBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2_BASE_IDX 8 2892 #define regBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2 0x10423 2893 #define regBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2_BASE_IDX 8 2894 #define regBIF_CFG_DEV0_EPF1_0_LINK_CAP2 0x10424 2895 #define regBIF_CFG_DEV0_EPF1_0_LINK_CAP2_BASE_IDX 8 2896 #define regBIF_CFG_DEV0_EPF1_0_LINK_CNTL2 0x10425 2897 #define regBIF_CFG_DEV0_EPF1_0_LINK_CNTL2_BASE_IDX 8 2898 #define regBIF_CFG_DEV0_EPF1_0_LINK_STATUS2 0x10425 2899 #define regBIF_CFG_DEV0_EPF1_0_LINK_STATUS2_BASE_IDX 8 2900 #define regBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST 0x10428 2901 #define regBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST_BASE_IDX 8 2902 #define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL 0x10428 2903 #define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL_BASE_IDX 8 2904 #define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO 0x10429 2905 #define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO_BASE_IDX 8 2906 #define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI 0x1042a 2907 #define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI_BASE_IDX 8 2908 #define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA 0x1042a 2909 #define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_BASE_IDX 8 2910 #define regBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA 0x1042a 2911 #define regBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_BASE_IDX 8 2912 #define regBIF_CFG_DEV0_EPF1_0_MSI_MASK 0x1042b 2913 #define regBIF_CFG_DEV0_EPF1_0_MSI_MASK_BASE_IDX 8 2914 #define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64 0x1042b 2915 #define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64_BASE_IDX 8 2916 #define regBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64 0x1042b 2917 #define regBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64_BASE_IDX 8 2918 #define regBIF_CFG_DEV0_EPF1_0_MSI_MASK_64 0x1042c 2919 #define regBIF_CFG_DEV0_EPF1_0_MSI_MASK_64_BASE_IDX 8 2920 #define regBIF_CFG_DEV0_EPF1_0_MSI_PENDING 0x1042c 2921 #define regBIF_CFG_DEV0_EPF1_0_MSI_PENDING_BASE_IDX 8 2922 #define regBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64 0x1042d 2923 #define regBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64_BASE_IDX 8 2924 #define regBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST 0x10430 2925 #define regBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST_BASE_IDX 8 2926 #define regBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL 0x10430 2927 #define regBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL_BASE_IDX 8 2928 #define regBIF_CFG_DEV0_EPF1_0_MSIX_TABLE 0x10431 2929 #define regBIF_CFG_DEV0_EPF1_0_MSIX_TABLE_BASE_IDX 8 2930 #define regBIF_CFG_DEV0_EPF1_0_MSIX_PBA 0x10432 2931 #define regBIF_CFG_DEV0_EPF1_0_MSIX_PBA_BASE_IDX 8 2932 #define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10440 2933 #define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 8 2934 #define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR 0x10441 2935 #define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 8 2936 #define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1 0x10442 2937 #define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 8 2938 #define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2 0x10443 2939 #define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 8 2940 #define regBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10454 2941 #define regBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 8 2942 #define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS 0x10455 2943 #define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 8 2944 #define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK 0x10456 2945 #define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK_BASE_IDX 8 2946 #define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY 0x10457 2947 #define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 8 2948 #define regBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS 0x10458 2949 #define regBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS_BASE_IDX 8 2950 #define regBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK 0x10459 2951 #define regBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK_BASE_IDX 8 2952 #define regBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL 0x1045a 2953 #define regBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 8 2954 #define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0 0x1045b 2955 #define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0_BASE_IDX 8 2956 #define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1 0x1045c 2957 #define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1_BASE_IDX 8 2958 #define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2 0x1045d 2959 #define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2_BASE_IDX 8 2960 #define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3 0x1045e 2961 #define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3_BASE_IDX 8 2962 #define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0 0x10462 2963 #define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 8 2964 #define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1 0x10463 2965 #define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 8 2966 #define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2 0x10464 2967 #define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 8 2968 #define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3 0x10465 2969 #define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 8 2970 #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST 0x10480 2971 #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 8 2972 #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP 0x10481 2973 #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP_BASE_IDX 8 2974 #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL 0x10482 2975 #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL_BASE_IDX 8 2976 #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP 0x10483 2977 #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP_BASE_IDX 8 2978 #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL 0x10484 2979 #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL_BASE_IDX 8 2980 #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP 0x10485 2981 #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP_BASE_IDX 8 2982 #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL 0x10486 2983 #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL_BASE_IDX 8 2984 #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP 0x10487 2985 #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP_BASE_IDX 8 2986 #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL 0x10488 2987 #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL_BASE_IDX 8 2988 #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP 0x10489 2989 #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP_BASE_IDX 8 2990 #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL 0x1048a 2991 #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL_BASE_IDX 8 2992 #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP 0x1048b 2993 #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP_BASE_IDX 8 2994 #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL 0x1048c 2995 #define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL_BASE_IDX 8 2996 #define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x10490 2997 #define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 8 2998 #define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT 0x10491 2999 #define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 8 3000 #define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA 0x10492 3001 #define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_BASE_IDX 8 3002 #define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP 0x10493 3003 #define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP_BASE_IDX 8 3004 #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST 0x10494 3005 #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 8 3006 #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP 0x10495 3007 #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP_BASE_IDX 8 3008 #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR 0x10496 3009 #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 8 3010 #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS 0x10497 3011 #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS_BASE_IDX 8 3012 #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL 0x10497 3013 #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL_BASE_IDX 8 3014 #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x10498 3015 #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 8 3016 #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x10498 3017 #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 8 3018 #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x10498 3019 #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 8 3020 #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x10498 3021 #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 8 3022 #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x10499 3023 #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 8 3024 #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x10499 3025 #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 8 3026 #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x10499 3027 #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 8 3028 #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x10499 3029 #define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 8 3030 #define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST 0x104a8 3031 #define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 8 3032 #define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP 0x104a9 3033 #define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP_BASE_IDX 8 3034 #define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL 0x104a9 3035 #define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL_BASE_IDX 8 3036 #define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST 0x104b4 3037 #define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 8 3038 #define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP 0x104b5 3039 #define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP_BASE_IDX 8 3040 #define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL 0x104b5 3041 #define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL_BASE_IDX 8 3042 #define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST 0x104ca 3043 #define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 8 3044 #define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP 0x104cb 3045 #define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP_BASE_IDX 8 3046 #define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL 0x104cb 3047 #define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL_BASE_IDX 8 3048 3049 3050 // addressBlock: aid_nbio_nbif0_rcc_dev0_RCCPORTDEC 3051 // base address: 0x10131000 3052 #define regRCC_DEV0_1_RCC_VDM_SUPPORT 0xc440 3053 #define regRCC_DEV0_1_RCC_VDM_SUPPORT_BASE_IDX 8 3054 #define regRCC_DEV0_1_RCC_BUS_CNTL 0xc441 3055 #define regRCC_DEV0_1_RCC_BUS_CNTL_BASE_IDX 8 3056 #define regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC 0xc442 3057 #define regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC_BASE_IDX 8 3058 #define regRCC_DEV0_1_RCC_DEV0_LINK_CNTL 0xc443 3059 #define regRCC_DEV0_1_RCC_DEV0_LINK_CNTL_BASE_IDX 8 3060 #define regRCC_DEV0_1_RCC_CMN_LINK_CNTL 0xc444 3061 #define regRCC_DEV0_1_RCC_CMN_LINK_CNTL_BASE_IDX 8 3062 #define regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE 0xc445 3063 #define regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 8 3064 #define regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL 0xc446 3065 #define regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL_BASE_IDX 8 3066 #define regRCC_DEV0_1_RCC_MH_ARB_CNTL 0xc447 3067 #define regRCC_DEV0_1_RCC_MH_ARB_CNTL_BASE_IDX 8 3068 #define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0 0xc448 3069 #define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 8 3070 #define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1 0xc449 3071 #define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 8 3072 3073 3074 // addressBlock: aid_nbio_nbif0_rcc_ep_dev0_RCCPORTDEC 3075 // base address: 0x10131000 3076 #define regRCC_EP_DEV0_1_EP_PCIE_SCRATCH 0xc44c 3077 #define regRCC_EP_DEV0_1_EP_PCIE_SCRATCH_BASE_IDX 8 3078 #define regRCC_EP_DEV0_1_EP_PCIE_CNTL 0xc44e 3079 #define regRCC_EP_DEV0_1_EP_PCIE_CNTL_BASE_IDX 8 3080 #define regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL 0xc44f 3081 #define regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL_BASE_IDX 8 3082 #define regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS 0xc450 3083 #define regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS_BASE_IDX 8 3084 #define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2 0xc451 3085 #define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2_BASE_IDX 8 3086 #define regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL 0xc452 3087 #define regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL_BASE_IDX 8 3088 #define regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL 0xc453 3089 #define regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL_BASE_IDX 8 3090 #define regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL 0xc454 3091 #define regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL_BASE_IDX 8 3092 #define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC 0xc455 3093 #define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC_BASE_IDX 8 3094 #define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2 0xc456 3095 #define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2_BASE_IDX 8 3096 #define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP 0xc457 3097 #define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP_BASE_IDX 8 3098 #define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0xc458 3099 #define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 8 3100 #define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL 0xc458 3101 #define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL_BASE_IDX 8 3102 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0xc458 3103 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 8 3104 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0xc459 3105 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 8 3106 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0xc459 3107 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 8 3108 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0xc459 3109 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 8 3110 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0xc459 3111 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 8 3112 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0xc45a 3113 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 8 3114 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0xc45a 3115 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 8 3116 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0xc45a 3117 #define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 8 3118 #define regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL 0xc45c 3119 #define regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL_BASE_IDX 8 3120 #define regRCC_EP_DEV0_1_EP_PCIEP_RESERVED 0xc45d 3121 #define regRCC_EP_DEV0_1_EP_PCIEP_RESERVED_BASE_IDX 8 3122 #define regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL 0xc45f 3123 #define regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL_BASE_IDX 8 3124 #define regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID 0xc460 3125 #define regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 8 3126 #define regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL 0xc461 3127 #define regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL_BASE_IDX 8 3128 #define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL 0xc462 3129 #define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL_BASE_IDX 8 3130 #define regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL 0xc463 3131 #define regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 8 3132 3133 3134 // addressBlock: aid_nbio_nbif0_rcc_dwn_dev0_RCCPORTDEC 3135 // base address: 0x10131000 3136 #define regRCC_DWN_DEV0_1_DN_PCIE_RESERVED 0xc468 3137 #define regRCC_DWN_DEV0_1_DN_PCIE_RESERVED_BASE_IDX 8 3138 #define regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH 0xc469 3139 #define regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH_BASE_IDX 8 3140 #define regRCC_DWN_DEV0_1_DN_PCIE_CNTL 0xc46b 3141 #define regRCC_DWN_DEV0_1_DN_PCIE_CNTL_BASE_IDX 8 3142 #define regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL 0xc46c 3143 #define regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL_BASE_IDX 8 3144 #define regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2 0xc46d 3145 #define regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2_BASE_IDX 8 3146 #define regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL 0xc46e 3147 #define regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL_BASE_IDX 8 3148 #define regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL 0xc46f 3149 #define regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL_BASE_IDX 8 3150 #define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0 0xc470 3151 #define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0_BASE_IDX 8 3152 #define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC 0xc471 3153 #define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC_BASE_IDX 8 3154 #define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2 0xc472 3155 #define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2_BASE_IDX 8 3156 3157 3158 // addressBlock: aid_nbio_nbif0_rcc_dwnp_dev0_RCCPORTDEC 3159 // base address: 0x10131000 3160 #define regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL 0xc475 3161 #define regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL_BASE_IDX 8 3162 #define regRCC_DWNP_DEV0_1_PCIE_RX_CNTL 0xc476 3163 #define regRCC_DWNP_DEV0_1_PCIE_RX_CNTL_BASE_IDX 8 3164 #define regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL 0xc477 3165 #define regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL_BASE_IDX 8 3166 #define regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2 0xc478 3167 #define regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2_BASE_IDX 8 3168 #define regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC 0xc479 3169 #define regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC_BASE_IDX 8 3170 #define regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP 0xc47a 3171 #define regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP_BASE_IDX 8 3172 3173 3174 // addressBlock: aid_nbio_nbif0_rcc_pfc_amdgfx_RCCPFCDEC 3175 // base address: 0x10134000 3176 #define regRCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL 0xd040 3177 #define regRCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL_BASE_IDX 8 3178 #define regRCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE 0xd041 3179 #define regRCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE_BASE_IDX 8 3180 #define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0 0xd042 3181 #define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0_BASE_IDX 8 3182 #define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1 0xd043 3183 #define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1_BASE_IDX 8 3184 #define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2 0xd044 3185 #define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2_BASE_IDX 8 3186 #define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3 0xd045 3187 #define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3_BASE_IDX 8 3188 #define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4 0xd046 3189 #define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4_BASE_IDX 8 3190 #define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5 0xd047 3191 #define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5_BASE_IDX 8 3192 #define regRCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL 0xd048 3193 #define regRCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL_BASE_IDX 8 3194 3195 3196 // addressBlock: aid_nbio_nbif0_pciemsix_0_usb_MSIXTDEC 3197 // base address: 0x10168000 3198 #define regPCIEMSIX_VECT0_ADDR_LO 0x1a000 3199 #define regPCIEMSIX_VECT0_ADDR_LO_BASE_IDX 8 3200 #define regPCIEMSIX_VECT0_ADDR_HI 0x1a001 3201 #define regPCIEMSIX_VECT0_ADDR_HI_BASE_IDX 8 3202 #define regPCIEMSIX_VECT0_MSG_DATA 0x1a002 3203 #define regPCIEMSIX_VECT0_MSG_DATA_BASE_IDX 8 3204 #define regPCIEMSIX_VECT0_CONTROL 0x1a003 3205 #define regPCIEMSIX_VECT0_CONTROL_BASE_IDX 8 3206 #define regPCIEMSIX_VECT1_ADDR_LO 0x1a004 3207 #define regPCIEMSIX_VECT1_ADDR_LO_BASE_IDX 8 3208 #define regPCIEMSIX_VECT1_ADDR_HI 0x1a005 3209 #define regPCIEMSIX_VECT1_ADDR_HI_BASE_IDX 8 3210 #define regPCIEMSIX_VECT1_MSG_DATA 0x1a006 3211 #define regPCIEMSIX_VECT1_MSG_DATA_BASE_IDX 8 3212 #define regPCIEMSIX_VECT1_CONTROL 0x1a007 3213 #define regPCIEMSIX_VECT1_CONTROL_BASE_IDX 8 3214 #define regPCIEMSIX_VECT2_ADDR_LO 0x1a008 3215 #define regPCIEMSIX_VECT2_ADDR_LO_BASE_IDX 8 3216 #define regPCIEMSIX_VECT2_ADDR_HI 0x1a009 3217 #define regPCIEMSIX_VECT2_ADDR_HI_BASE_IDX 8 3218 #define regPCIEMSIX_VECT2_MSG_DATA 0x1a00a 3219 #define regPCIEMSIX_VECT2_MSG_DATA_BASE_IDX 8 3220 #define regPCIEMSIX_VECT2_CONTROL 0x1a00b 3221 #define regPCIEMSIX_VECT2_CONTROL_BASE_IDX 8 3222 #define regPCIEMSIX_VECT3_ADDR_LO 0x1a00c 3223 #define regPCIEMSIX_VECT3_ADDR_LO_BASE_IDX 8 3224 #define regPCIEMSIX_VECT3_ADDR_HI 0x1a00d 3225 #define regPCIEMSIX_VECT3_ADDR_HI_BASE_IDX 8 3226 #define regPCIEMSIX_VECT3_MSG_DATA 0x1a00e 3227 #define regPCIEMSIX_VECT3_MSG_DATA_BASE_IDX 8 3228 #define regPCIEMSIX_VECT3_CONTROL 0x1a00f 3229 #define regPCIEMSIX_VECT3_CONTROL_BASE_IDX 8 3230 #define regPCIEMSIX_VECT4_ADDR_LO 0x1a010 3231 #define regPCIEMSIX_VECT4_ADDR_LO_BASE_IDX 8 3232 #define regPCIEMSIX_VECT4_ADDR_HI 0x1a011 3233 #define regPCIEMSIX_VECT4_ADDR_HI_BASE_IDX 8 3234 #define regPCIEMSIX_VECT4_MSG_DATA 0x1a012 3235 #define regPCIEMSIX_VECT4_MSG_DATA_BASE_IDX 8 3236 #define regPCIEMSIX_VECT4_CONTROL 0x1a013 3237 #define regPCIEMSIX_VECT4_CONTROL_BASE_IDX 8 3238 #define regPCIEMSIX_VECT5_ADDR_LO 0x1a014 3239 #define regPCIEMSIX_VECT5_ADDR_LO_BASE_IDX 8 3240 #define regPCIEMSIX_VECT5_ADDR_HI 0x1a015 3241 #define regPCIEMSIX_VECT5_ADDR_HI_BASE_IDX 8 3242 #define regPCIEMSIX_VECT5_MSG_DATA 0x1a016 3243 #define regPCIEMSIX_VECT5_MSG_DATA_BASE_IDX 8 3244 #define regPCIEMSIX_VECT5_CONTROL 0x1a017 3245 #define regPCIEMSIX_VECT5_CONTROL_BASE_IDX 8 3246 #define regPCIEMSIX_VECT6_ADDR_LO 0x1a018 3247 #define regPCIEMSIX_VECT6_ADDR_LO_BASE_IDX 8 3248 #define regPCIEMSIX_VECT6_ADDR_HI 0x1a019 3249 #define regPCIEMSIX_VECT6_ADDR_HI_BASE_IDX 8 3250 #define regPCIEMSIX_VECT6_MSG_DATA 0x1a01a 3251 #define regPCIEMSIX_VECT6_MSG_DATA_BASE_IDX 8 3252 #define regPCIEMSIX_VECT6_CONTROL 0x1a01b 3253 #define regPCIEMSIX_VECT6_CONTROL_BASE_IDX 8 3254 #define regPCIEMSIX_VECT7_ADDR_LO 0x1a01c 3255 #define regPCIEMSIX_VECT7_ADDR_LO_BASE_IDX 8 3256 #define regPCIEMSIX_VECT7_ADDR_HI 0x1a01d 3257 #define regPCIEMSIX_VECT7_ADDR_HI_BASE_IDX 8 3258 #define regPCIEMSIX_VECT7_MSG_DATA 0x1a01e 3259 #define regPCIEMSIX_VECT7_MSG_DATA_BASE_IDX 8 3260 #define regPCIEMSIX_VECT7_CONTROL 0x1a01f 3261 #define regPCIEMSIX_VECT7_CONTROL_BASE_IDX 8 3262 #define regPCIEMSIX_VECT8_ADDR_LO 0x1a020 3263 #define regPCIEMSIX_VECT8_ADDR_LO_BASE_IDX 8 3264 #define regPCIEMSIX_VECT8_ADDR_HI 0x1a021 3265 #define regPCIEMSIX_VECT8_ADDR_HI_BASE_IDX 8 3266 #define regPCIEMSIX_VECT8_MSG_DATA 0x1a022 3267 #define regPCIEMSIX_VECT8_MSG_DATA_BASE_IDX 8 3268 #define regPCIEMSIX_VECT8_CONTROL 0x1a023 3269 #define regPCIEMSIX_VECT8_CONTROL_BASE_IDX 8 3270 #define regPCIEMSIX_VECT9_ADDR_LO 0x1a024 3271 #define regPCIEMSIX_VECT9_ADDR_LO_BASE_IDX 8 3272 #define regPCIEMSIX_VECT9_ADDR_HI 0x1a025 3273 #define regPCIEMSIX_VECT9_ADDR_HI_BASE_IDX 8 3274 #define regPCIEMSIX_VECT9_MSG_DATA 0x1a026 3275 #define regPCIEMSIX_VECT9_MSG_DATA_BASE_IDX 8 3276 #define regPCIEMSIX_VECT9_CONTROL 0x1a027 3277 #define regPCIEMSIX_VECT9_CONTROL_BASE_IDX 8 3278 #define regPCIEMSIX_VECT10_ADDR_LO 0x1a028 3279 #define regPCIEMSIX_VECT10_ADDR_LO_BASE_IDX 8 3280 #define regPCIEMSIX_VECT10_ADDR_HI 0x1a029 3281 #define regPCIEMSIX_VECT10_ADDR_HI_BASE_IDX 8 3282 #define regPCIEMSIX_VECT10_MSG_DATA 0x1a02a 3283 #define regPCIEMSIX_VECT10_MSG_DATA_BASE_IDX 8 3284 #define regPCIEMSIX_VECT10_CONTROL 0x1a02b 3285 #define regPCIEMSIX_VECT10_CONTROL_BASE_IDX 8 3286 #define regPCIEMSIX_VECT11_ADDR_LO 0x1a02c 3287 #define regPCIEMSIX_VECT11_ADDR_LO_BASE_IDX 8 3288 #define regPCIEMSIX_VECT11_ADDR_HI 0x1a02d 3289 #define regPCIEMSIX_VECT11_ADDR_HI_BASE_IDX 8 3290 #define regPCIEMSIX_VECT11_MSG_DATA 0x1a02e 3291 #define regPCIEMSIX_VECT11_MSG_DATA_BASE_IDX 8 3292 #define regPCIEMSIX_VECT11_CONTROL 0x1a02f 3293 #define regPCIEMSIX_VECT11_CONTROL_BASE_IDX 8 3294 #define regPCIEMSIX_VECT12_ADDR_LO 0x1a030 3295 #define regPCIEMSIX_VECT12_ADDR_LO_BASE_IDX 8 3296 #define regPCIEMSIX_VECT12_ADDR_HI 0x1a031 3297 #define regPCIEMSIX_VECT12_ADDR_HI_BASE_IDX 8 3298 #define regPCIEMSIX_VECT12_MSG_DATA 0x1a032 3299 #define regPCIEMSIX_VECT12_MSG_DATA_BASE_IDX 8 3300 #define regPCIEMSIX_VECT12_CONTROL 0x1a033 3301 #define regPCIEMSIX_VECT12_CONTROL_BASE_IDX 8 3302 #define regPCIEMSIX_VECT13_ADDR_LO 0x1a034 3303 #define regPCIEMSIX_VECT13_ADDR_LO_BASE_IDX 8 3304 #define regPCIEMSIX_VECT13_ADDR_HI 0x1a035 3305 #define regPCIEMSIX_VECT13_ADDR_HI_BASE_IDX 8 3306 #define regPCIEMSIX_VECT13_MSG_DATA 0x1a036 3307 #define regPCIEMSIX_VECT13_MSG_DATA_BASE_IDX 8 3308 #define regPCIEMSIX_VECT13_CONTROL 0x1a037 3309 #define regPCIEMSIX_VECT13_CONTROL_BASE_IDX 8 3310 #define regPCIEMSIX_VECT14_ADDR_LO 0x1a038 3311 #define regPCIEMSIX_VECT14_ADDR_LO_BASE_IDX 8 3312 #define regPCIEMSIX_VECT14_ADDR_HI 0x1a039 3313 #define regPCIEMSIX_VECT14_ADDR_HI_BASE_IDX 8 3314 #define regPCIEMSIX_VECT14_MSG_DATA 0x1a03a 3315 #define regPCIEMSIX_VECT14_MSG_DATA_BASE_IDX 8 3316 #define regPCIEMSIX_VECT14_CONTROL 0x1a03b 3317 #define regPCIEMSIX_VECT14_CONTROL_BASE_IDX 8 3318 #define regPCIEMSIX_VECT15_ADDR_LO 0x1a03c 3319 #define regPCIEMSIX_VECT15_ADDR_LO_BASE_IDX 8 3320 #define regPCIEMSIX_VECT15_ADDR_HI 0x1a03d 3321 #define regPCIEMSIX_VECT15_ADDR_HI_BASE_IDX 8 3322 #define regPCIEMSIX_VECT15_MSG_DATA 0x1a03e 3323 #define regPCIEMSIX_VECT15_MSG_DATA_BASE_IDX 8 3324 #define regPCIEMSIX_VECT15_CONTROL 0x1a03f 3325 #define regPCIEMSIX_VECT15_CONTROL_BASE_IDX 8 3326 #define regPCIEMSIX_VECT16_ADDR_LO 0x1a040 3327 #define regPCIEMSIX_VECT16_ADDR_LO_BASE_IDX 8 3328 #define regPCIEMSIX_VECT16_ADDR_HI 0x1a041 3329 #define regPCIEMSIX_VECT16_ADDR_HI_BASE_IDX 8 3330 #define regPCIEMSIX_VECT16_MSG_DATA 0x1a042 3331 #define regPCIEMSIX_VECT16_MSG_DATA_BASE_IDX 8 3332 #define regPCIEMSIX_VECT16_CONTROL 0x1a043 3333 #define regPCIEMSIX_VECT16_CONTROL_BASE_IDX 8 3334 #define regPCIEMSIX_VECT17_ADDR_LO 0x1a044 3335 #define regPCIEMSIX_VECT17_ADDR_LO_BASE_IDX 8 3336 #define regPCIEMSIX_VECT17_ADDR_HI 0x1a045 3337 #define regPCIEMSIX_VECT17_ADDR_HI_BASE_IDX 8 3338 #define regPCIEMSIX_VECT17_MSG_DATA 0x1a046 3339 #define regPCIEMSIX_VECT17_MSG_DATA_BASE_IDX 8 3340 #define regPCIEMSIX_VECT17_CONTROL 0x1a047 3341 #define regPCIEMSIX_VECT17_CONTROL_BASE_IDX 8 3342 #define regPCIEMSIX_VECT18_ADDR_LO 0x1a048 3343 #define regPCIEMSIX_VECT18_ADDR_LO_BASE_IDX 8 3344 #define regPCIEMSIX_VECT18_ADDR_HI 0x1a049 3345 #define regPCIEMSIX_VECT18_ADDR_HI_BASE_IDX 8 3346 #define regPCIEMSIX_VECT18_MSG_DATA 0x1a04a 3347 #define regPCIEMSIX_VECT18_MSG_DATA_BASE_IDX 8 3348 #define regPCIEMSIX_VECT18_CONTROL 0x1a04b 3349 #define regPCIEMSIX_VECT18_CONTROL_BASE_IDX 8 3350 #define regPCIEMSIX_VECT19_ADDR_LO 0x1a04c 3351 #define regPCIEMSIX_VECT19_ADDR_LO_BASE_IDX 8 3352 #define regPCIEMSIX_VECT19_ADDR_HI 0x1a04d 3353 #define regPCIEMSIX_VECT19_ADDR_HI_BASE_IDX 8 3354 #define regPCIEMSIX_VECT19_MSG_DATA 0x1a04e 3355 #define regPCIEMSIX_VECT19_MSG_DATA_BASE_IDX 8 3356 #define regPCIEMSIX_VECT19_CONTROL 0x1a04f 3357 #define regPCIEMSIX_VECT19_CONTROL_BASE_IDX 8 3358 #define regPCIEMSIX_VECT20_ADDR_LO 0x1a050 3359 #define regPCIEMSIX_VECT20_ADDR_LO_BASE_IDX 8 3360 #define regPCIEMSIX_VECT20_ADDR_HI 0x1a051 3361 #define regPCIEMSIX_VECT20_ADDR_HI_BASE_IDX 8 3362 #define regPCIEMSIX_VECT20_MSG_DATA 0x1a052 3363 #define regPCIEMSIX_VECT20_MSG_DATA_BASE_IDX 8 3364 #define regPCIEMSIX_VECT20_CONTROL 0x1a053 3365 #define regPCIEMSIX_VECT20_CONTROL_BASE_IDX 8 3366 #define regPCIEMSIX_VECT21_ADDR_LO 0x1a054 3367 #define regPCIEMSIX_VECT21_ADDR_LO_BASE_IDX 8 3368 #define regPCIEMSIX_VECT21_ADDR_HI 0x1a055 3369 #define regPCIEMSIX_VECT21_ADDR_HI_BASE_IDX 8 3370 #define regPCIEMSIX_VECT21_MSG_DATA 0x1a056 3371 #define regPCIEMSIX_VECT21_MSG_DATA_BASE_IDX 8 3372 #define regPCIEMSIX_VECT21_CONTROL 0x1a057 3373 #define regPCIEMSIX_VECT21_CONTROL_BASE_IDX 8 3374 #define regPCIEMSIX_VECT22_ADDR_LO 0x1a058 3375 #define regPCIEMSIX_VECT22_ADDR_LO_BASE_IDX 8 3376 #define regPCIEMSIX_VECT22_ADDR_HI 0x1a059 3377 #define regPCIEMSIX_VECT22_ADDR_HI_BASE_IDX 8 3378 #define regPCIEMSIX_VECT22_MSG_DATA 0x1a05a 3379 #define regPCIEMSIX_VECT22_MSG_DATA_BASE_IDX 8 3380 #define regPCIEMSIX_VECT22_CONTROL 0x1a05b 3381 #define regPCIEMSIX_VECT22_CONTROL_BASE_IDX 8 3382 #define regPCIEMSIX_VECT23_ADDR_LO 0x1a05c 3383 #define regPCIEMSIX_VECT23_ADDR_LO_BASE_IDX 8 3384 #define regPCIEMSIX_VECT23_ADDR_HI 0x1a05d 3385 #define regPCIEMSIX_VECT23_ADDR_HI_BASE_IDX 8 3386 #define regPCIEMSIX_VECT23_MSG_DATA 0x1a05e 3387 #define regPCIEMSIX_VECT23_MSG_DATA_BASE_IDX 8 3388 #define regPCIEMSIX_VECT23_CONTROL 0x1a05f 3389 #define regPCIEMSIX_VECT23_CONTROL_BASE_IDX 8 3390 #define regPCIEMSIX_VECT24_ADDR_LO 0x1a060 3391 #define regPCIEMSIX_VECT24_ADDR_LO_BASE_IDX 8 3392 #define regPCIEMSIX_VECT24_ADDR_HI 0x1a061 3393 #define regPCIEMSIX_VECT24_ADDR_HI_BASE_IDX 8 3394 #define regPCIEMSIX_VECT24_MSG_DATA 0x1a062 3395 #define regPCIEMSIX_VECT24_MSG_DATA_BASE_IDX 8 3396 #define regPCIEMSIX_VECT24_CONTROL 0x1a063 3397 #define regPCIEMSIX_VECT24_CONTROL_BASE_IDX 8 3398 #define regPCIEMSIX_VECT25_ADDR_LO 0x1a064 3399 #define regPCIEMSIX_VECT25_ADDR_LO_BASE_IDX 8 3400 #define regPCIEMSIX_VECT25_ADDR_HI 0x1a065 3401 #define regPCIEMSIX_VECT25_ADDR_HI_BASE_IDX 8 3402 #define regPCIEMSIX_VECT25_MSG_DATA 0x1a066 3403 #define regPCIEMSIX_VECT25_MSG_DATA_BASE_IDX 8 3404 #define regPCIEMSIX_VECT25_CONTROL 0x1a067 3405 #define regPCIEMSIX_VECT25_CONTROL_BASE_IDX 8 3406 #define regPCIEMSIX_VECT26_ADDR_LO 0x1a068 3407 #define regPCIEMSIX_VECT26_ADDR_LO_BASE_IDX 8 3408 #define regPCIEMSIX_VECT26_ADDR_HI 0x1a069 3409 #define regPCIEMSIX_VECT26_ADDR_HI_BASE_IDX 8 3410 #define regPCIEMSIX_VECT26_MSG_DATA 0x1a06a 3411 #define regPCIEMSIX_VECT26_MSG_DATA_BASE_IDX 8 3412 #define regPCIEMSIX_VECT26_CONTROL 0x1a06b 3413 #define regPCIEMSIX_VECT26_CONTROL_BASE_IDX 8 3414 #define regPCIEMSIX_VECT27_ADDR_LO 0x1a06c 3415 #define regPCIEMSIX_VECT27_ADDR_LO_BASE_IDX 8 3416 #define regPCIEMSIX_VECT27_ADDR_HI 0x1a06d 3417 #define regPCIEMSIX_VECT27_ADDR_HI_BASE_IDX 8 3418 #define regPCIEMSIX_VECT27_MSG_DATA 0x1a06e 3419 #define regPCIEMSIX_VECT27_MSG_DATA_BASE_IDX 8 3420 #define regPCIEMSIX_VECT27_CONTROL 0x1a06f 3421 #define regPCIEMSIX_VECT27_CONTROL_BASE_IDX 8 3422 #define regPCIEMSIX_VECT28_ADDR_LO 0x1a070 3423 #define regPCIEMSIX_VECT28_ADDR_LO_BASE_IDX 8 3424 #define regPCIEMSIX_VECT28_ADDR_HI 0x1a071 3425 #define regPCIEMSIX_VECT28_ADDR_HI_BASE_IDX 8 3426 #define regPCIEMSIX_VECT28_MSG_DATA 0x1a072 3427 #define regPCIEMSIX_VECT28_MSG_DATA_BASE_IDX 8 3428 #define regPCIEMSIX_VECT28_CONTROL 0x1a073 3429 #define regPCIEMSIX_VECT28_CONTROL_BASE_IDX 8 3430 #define regPCIEMSIX_VECT29_ADDR_LO 0x1a074 3431 #define regPCIEMSIX_VECT29_ADDR_LO_BASE_IDX 8 3432 #define regPCIEMSIX_VECT29_ADDR_HI 0x1a075 3433 #define regPCIEMSIX_VECT29_ADDR_HI_BASE_IDX 8 3434 #define regPCIEMSIX_VECT29_MSG_DATA 0x1a076 3435 #define regPCIEMSIX_VECT29_MSG_DATA_BASE_IDX 8 3436 #define regPCIEMSIX_VECT29_CONTROL 0x1a077 3437 #define regPCIEMSIX_VECT29_CONTROL_BASE_IDX 8 3438 #define regPCIEMSIX_VECT30_ADDR_LO 0x1a078 3439 #define regPCIEMSIX_VECT30_ADDR_LO_BASE_IDX 8 3440 #define regPCIEMSIX_VECT30_ADDR_HI 0x1a079 3441 #define regPCIEMSIX_VECT30_ADDR_HI_BASE_IDX 8 3442 #define regPCIEMSIX_VECT30_MSG_DATA 0x1a07a 3443 #define regPCIEMSIX_VECT30_MSG_DATA_BASE_IDX 8 3444 #define regPCIEMSIX_VECT30_CONTROL 0x1a07b 3445 #define regPCIEMSIX_VECT30_CONTROL_BASE_IDX 8 3446 #define regPCIEMSIX_VECT31_ADDR_LO 0x1a07c 3447 #define regPCIEMSIX_VECT31_ADDR_LO_BASE_IDX 8 3448 #define regPCIEMSIX_VECT31_ADDR_HI 0x1a07d 3449 #define regPCIEMSIX_VECT31_ADDR_HI_BASE_IDX 8 3450 #define regPCIEMSIX_VECT31_MSG_DATA 0x1a07e 3451 #define regPCIEMSIX_VECT31_MSG_DATA_BASE_IDX 8 3452 #define regPCIEMSIX_VECT31_CONTROL 0x1a07f 3453 #define regPCIEMSIX_VECT31_CONTROL_BASE_IDX 8 3454 #define regPCIEMSIX_VECT32_ADDR_LO 0x1a080 3455 #define regPCIEMSIX_VECT32_ADDR_LO_BASE_IDX 8 3456 #define regPCIEMSIX_VECT32_ADDR_HI 0x1a081 3457 #define regPCIEMSIX_VECT32_ADDR_HI_BASE_IDX 8 3458 #define regPCIEMSIX_VECT32_MSG_DATA 0x1a082 3459 #define regPCIEMSIX_VECT32_MSG_DATA_BASE_IDX 8 3460 #define regPCIEMSIX_VECT32_CONTROL 0x1a083 3461 #define regPCIEMSIX_VECT32_CONTROL_BASE_IDX 8 3462 #define regPCIEMSIX_VECT33_ADDR_LO 0x1a084 3463 #define regPCIEMSIX_VECT33_ADDR_LO_BASE_IDX 8 3464 #define regPCIEMSIX_VECT33_ADDR_HI 0x1a085 3465 #define regPCIEMSIX_VECT33_ADDR_HI_BASE_IDX 8 3466 #define regPCIEMSIX_VECT33_MSG_DATA 0x1a086 3467 #define regPCIEMSIX_VECT33_MSG_DATA_BASE_IDX 8 3468 #define regPCIEMSIX_VECT33_CONTROL 0x1a087 3469 #define regPCIEMSIX_VECT33_CONTROL_BASE_IDX 8 3470 #define regPCIEMSIX_VECT34_ADDR_LO 0x1a088 3471 #define regPCIEMSIX_VECT34_ADDR_LO_BASE_IDX 8 3472 #define regPCIEMSIX_VECT34_ADDR_HI 0x1a089 3473 #define regPCIEMSIX_VECT34_ADDR_HI_BASE_IDX 8 3474 #define regPCIEMSIX_VECT34_MSG_DATA 0x1a08a 3475 #define regPCIEMSIX_VECT34_MSG_DATA_BASE_IDX 8 3476 #define regPCIEMSIX_VECT34_CONTROL 0x1a08b 3477 #define regPCIEMSIX_VECT34_CONTROL_BASE_IDX 8 3478 #define regPCIEMSIX_VECT35_ADDR_LO 0x1a08c 3479 #define regPCIEMSIX_VECT35_ADDR_LO_BASE_IDX 8 3480 #define regPCIEMSIX_VECT35_ADDR_HI 0x1a08d 3481 #define regPCIEMSIX_VECT35_ADDR_HI_BASE_IDX 8 3482 #define regPCIEMSIX_VECT35_MSG_DATA 0x1a08e 3483 #define regPCIEMSIX_VECT35_MSG_DATA_BASE_IDX 8 3484 #define regPCIEMSIX_VECT35_CONTROL 0x1a08f 3485 #define regPCIEMSIX_VECT35_CONTROL_BASE_IDX 8 3486 #define regPCIEMSIX_VECT36_ADDR_LO 0x1a090 3487 #define regPCIEMSIX_VECT36_ADDR_LO_BASE_IDX 8 3488 #define regPCIEMSIX_VECT36_ADDR_HI 0x1a091 3489 #define regPCIEMSIX_VECT36_ADDR_HI_BASE_IDX 8 3490 #define regPCIEMSIX_VECT36_MSG_DATA 0x1a092 3491 #define regPCIEMSIX_VECT36_MSG_DATA_BASE_IDX 8 3492 #define regPCIEMSIX_VECT36_CONTROL 0x1a093 3493 #define regPCIEMSIX_VECT36_CONTROL_BASE_IDX 8 3494 #define regPCIEMSIX_VECT37_ADDR_LO 0x1a094 3495 #define regPCIEMSIX_VECT37_ADDR_LO_BASE_IDX 8 3496 #define regPCIEMSIX_VECT37_ADDR_HI 0x1a095 3497 #define regPCIEMSIX_VECT37_ADDR_HI_BASE_IDX 8 3498 #define regPCIEMSIX_VECT37_MSG_DATA 0x1a096 3499 #define regPCIEMSIX_VECT37_MSG_DATA_BASE_IDX 8 3500 #define regPCIEMSIX_VECT37_CONTROL 0x1a097 3501 #define regPCIEMSIX_VECT37_CONTROL_BASE_IDX 8 3502 #define regPCIEMSIX_VECT38_ADDR_LO 0x1a098 3503 #define regPCIEMSIX_VECT38_ADDR_LO_BASE_IDX 8 3504 #define regPCIEMSIX_VECT38_ADDR_HI 0x1a099 3505 #define regPCIEMSIX_VECT38_ADDR_HI_BASE_IDX 8 3506 #define regPCIEMSIX_VECT38_MSG_DATA 0x1a09a 3507 #define regPCIEMSIX_VECT38_MSG_DATA_BASE_IDX 8 3508 #define regPCIEMSIX_VECT38_CONTROL 0x1a09b 3509 #define regPCIEMSIX_VECT38_CONTROL_BASE_IDX 8 3510 #define regPCIEMSIX_VECT39_ADDR_LO 0x1a09c 3511 #define regPCIEMSIX_VECT39_ADDR_LO_BASE_IDX 8 3512 #define regPCIEMSIX_VECT39_ADDR_HI 0x1a09d 3513 #define regPCIEMSIX_VECT39_ADDR_HI_BASE_IDX 8 3514 #define regPCIEMSIX_VECT39_MSG_DATA 0x1a09e 3515 #define regPCIEMSIX_VECT39_MSG_DATA_BASE_IDX 8 3516 #define regPCIEMSIX_VECT39_CONTROL 0x1a09f 3517 #define regPCIEMSIX_VECT39_CONTROL_BASE_IDX 8 3518 #define regPCIEMSIX_VECT40_ADDR_LO 0x1a0a0 3519 #define regPCIEMSIX_VECT40_ADDR_LO_BASE_IDX 8 3520 #define regPCIEMSIX_VECT40_ADDR_HI 0x1a0a1 3521 #define regPCIEMSIX_VECT40_ADDR_HI_BASE_IDX 8 3522 #define regPCIEMSIX_VECT40_MSG_DATA 0x1a0a2 3523 #define regPCIEMSIX_VECT40_MSG_DATA_BASE_IDX 8 3524 #define regPCIEMSIX_VECT40_CONTROL 0x1a0a3 3525 #define regPCIEMSIX_VECT40_CONTROL_BASE_IDX 8 3526 #define regPCIEMSIX_VECT41_ADDR_LO 0x1a0a4 3527 #define regPCIEMSIX_VECT41_ADDR_LO_BASE_IDX 8 3528 #define regPCIEMSIX_VECT41_ADDR_HI 0x1a0a5 3529 #define regPCIEMSIX_VECT41_ADDR_HI_BASE_IDX 8 3530 #define regPCIEMSIX_VECT41_MSG_DATA 0x1a0a6 3531 #define regPCIEMSIX_VECT41_MSG_DATA_BASE_IDX 8 3532 #define regPCIEMSIX_VECT41_CONTROL 0x1a0a7 3533 #define regPCIEMSIX_VECT41_CONTROL_BASE_IDX 8 3534 #define regPCIEMSIX_VECT42_ADDR_LO 0x1a0a8 3535 #define regPCIEMSIX_VECT42_ADDR_LO_BASE_IDX 8 3536 #define regPCIEMSIX_VECT42_ADDR_HI 0x1a0a9 3537 #define regPCIEMSIX_VECT42_ADDR_HI_BASE_IDX 8 3538 #define regPCIEMSIX_VECT42_MSG_DATA 0x1a0aa 3539 #define regPCIEMSIX_VECT42_MSG_DATA_BASE_IDX 8 3540 #define regPCIEMSIX_VECT42_CONTROL 0x1a0ab 3541 #define regPCIEMSIX_VECT42_CONTROL_BASE_IDX 8 3542 #define regPCIEMSIX_VECT43_ADDR_LO 0x1a0ac 3543 #define regPCIEMSIX_VECT43_ADDR_LO_BASE_IDX 8 3544 #define regPCIEMSIX_VECT43_ADDR_HI 0x1a0ad 3545 #define regPCIEMSIX_VECT43_ADDR_HI_BASE_IDX 8 3546 #define regPCIEMSIX_VECT43_MSG_DATA 0x1a0ae 3547 #define regPCIEMSIX_VECT43_MSG_DATA_BASE_IDX 8 3548 #define regPCIEMSIX_VECT43_CONTROL 0x1a0af 3549 #define regPCIEMSIX_VECT43_CONTROL_BASE_IDX 8 3550 #define regPCIEMSIX_VECT44_ADDR_LO 0x1a0b0 3551 #define regPCIEMSIX_VECT44_ADDR_LO_BASE_IDX 8 3552 #define regPCIEMSIX_VECT44_ADDR_HI 0x1a0b1 3553 #define regPCIEMSIX_VECT44_ADDR_HI_BASE_IDX 8 3554 #define regPCIEMSIX_VECT44_MSG_DATA 0x1a0b2 3555 #define regPCIEMSIX_VECT44_MSG_DATA_BASE_IDX 8 3556 #define regPCIEMSIX_VECT44_CONTROL 0x1a0b3 3557 #define regPCIEMSIX_VECT44_CONTROL_BASE_IDX 8 3558 #define regPCIEMSIX_VECT45_ADDR_LO 0x1a0b4 3559 #define regPCIEMSIX_VECT45_ADDR_LO_BASE_IDX 8 3560 #define regPCIEMSIX_VECT45_ADDR_HI 0x1a0b5 3561 #define regPCIEMSIX_VECT45_ADDR_HI_BASE_IDX 8 3562 #define regPCIEMSIX_VECT45_MSG_DATA 0x1a0b6 3563 #define regPCIEMSIX_VECT45_MSG_DATA_BASE_IDX 8 3564 #define regPCIEMSIX_VECT45_CONTROL 0x1a0b7 3565 #define regPCIEMSIX_VECT45_CONTROL_BASE_IDX 8 3566 #define regPCIEMSIX_VECT46_ADDR_LO 0x1a0b8 3567 #define regPCIEMSIX_VECT46_ADDR_LO_BASE_IDX 8 3568 #define regPCIEMSIX_VECT46_ADDR_HI 0x1a0b9 3569 #define regPCIEMSIX_VECT46_ADDR_HI_BASE_IDX 8 3570 #define regPCIEMSIX_VECT46_MSG_DATA 0x1a0ba 3571 #define regPCIEMSIX_VECT46_MSG_DATA_BASE_IDX 8 3572 #define regPCIEMSIX_VECT46_CONTROL 0x1a0bb 3573 #define regPCIEMSIX_VECT46_CONTROL_BASE_IDX 8 3574 #define regPCIEMSIX_VECT47_ADDR_LO 0x1a0bc 3575 #define regPCIEMSIX_VECT47_ADDR_LO_BASE_IDX 8 3576 #define regPCIEMSIX_VECT47_ADDR_HI 0x1a0bd 3577 #define regPCIEMSIX_VECT47_ADDR_HI_BASE_IDX 8 3578 #define regPCIEMSIX_VECT47_MSG_DATA 0x1a0be 3579 #define regPCIEMSIX_VECT47_MSG_DATA_BASE_IDX 8 3580 #define regPCIEMSIX_VECT47_CONTROL 0x1a0bf 3581 #define regPCIEMSIX_VECT47_CONTROL_BASE_IDX 8 3582 #define regPCIEMSIX_VECT48_ADDR_LO 0x1a0c0 3583 #define regPCIEMSIX_VECT48_ADDR_LO_BASE_IDX 8 3584 #define regPCIEMSIX_VECT48_ADDR_HI 0x1a0c1 3585 #define regPCIEMSIX_VECT48_ADDR_HI_BASE_IDX 8 3586 #define regPCIEMSIX_VECT48_MSG_DATA 0x1a0c2 3587 #define regPCIEMSIX_VECT48_MSG_DATA_BASE_IDX 8 3588 #define regPCIEMSIX_VECT48_CONTROL 0x1a0c3 3589 #define regPCIEMSIX_VECT48_CONTROL_BASE_IDX 8 3590 #define regPCIEMSIX_VECT49_ADDR_LO 0x1a0c4 3591 #define regPCIEMSIX_VECT49_ADDR_LO_BASE_IDX 8 3592 #define regPCIEMSIX_VECT49_ADDR_HI 0x1a0c5 3593 #define regPCIEMSIX_VECT49_ADDR_HI_BASE_IDX 8 3594 #define regPCIEMSIX_VECT49_MSG_DATA 0x1a0c6 3595 #define regPCIEMSIX_VECT49_MSG_DATA_BASE_IDX 8 3596 #define regPCIEMSIX_VECT49_CONTROL 0x1a0c7 3597 #define regPCIEMSIX_VECT49_CONTROL_BASE_IDX 8 3598 #define regPCIEMSIX_VECT50_ADDR_LO 0x1a0c8 3599 #define regPCIEMSIX_VECT50_ADDR_LO_BASE_IDX 8 3600 #define regPCIEMSIX_VECT50_ADDR_HI 0x1a0c9 3601 #define regPCIEMSIX_VECT50_ADDR_HI_BASE_IDX 8 3602 #define regPCIEMSIX_VECT50_MSG_DATA 0x1a0ca 3603 #define regPCIEMSIX_VECT50_MSG_DATA_BASE_IDX 8 3604 #define regPCIEMSIX_VECT50_CONTROL 0x1a0cb 3605 #define regPCIEMSIX_VECT50_CONTROL_BASE_IDX 8 3606 #define regPCIEMSIX_VECT51_ADDR_LO 0x1a0cc 3607 #define regPCIEMSIX_VECT51_ADDR_LO_BASE_IDX 8 3608 #define regPCIEMSIX_VECT51_ADDR_HI 0x1a0cd 3609 #define regPCIEMSIX_VECT51_ADDR_HI_BASE_IDX 8 3610 #define regPCIEMSIX_VECT51_MSG_DATA 0x1a0ce 3611 #define regPCIEMSIX_VECT51_MSG_DATA_BASE_IDX 8 3612 #define regPCIEMSIX_VECT51_CONTROL 0x1a0cf 3613 #define regPCIEMSIX_VECT51_CONTROL_BASE_IDX 8 3614 #define regPCIEMSIX_VECT52_ADDR_LO 0x1a0d0 3615 #define regPCIEMSIX_VECT52_ADDR_LO_BASE_IDX 8 3616 #define regPCIEMSIX_VECT52_ADDR_HI 0x1a0d1 3617 #define regPCIEMSIX_VECT52_ADDR_HI_BASE_IDX 8 3618 #define regPCIEMSIX_VECT52_MSG_DATA 0x1a0d2 3619 #define regPCIEMSIX_VECT52_MSG_DATA_BASE_IDX 8 3620 #define regPCIEMSIX_VECT52_CONTROL 0x1a0d3 3621 #define regPCIEMSIX_VECT52_CONTROL_BASE_IDX 8 3622 #define regPCIEMSIX_VECT53_ADDR_LO 0x1a0d4 3623 #define regPCIEMSIX_VECT53_ADDR_LO_BASE_IDX 8 3624 #define regPCIEMSIX_VECT53_ADDR_HI 0x1a0d5 3625 #define regPCIEMSIX_VECT53_ADDR_HI_BASE_IDX 8 3626 #define regPCIEMSIX_VECT53_MSG_DATA 0x1a0d6 3627 #define regPCIEMSIX_VECT53_MSG_DATA_BASE_IDX 8 3628 #define regPCIEMSIX_VECT53_CONTROL 0x1a0d7 3629 #define regPCIEMSIX_VECT53_CONTROL_BASE_IDX 8 3630 #define regPCIEMSIX_VECT54_ADDR_LO 0x1a0d8 3631 #define regPCIEMSIX_VECT54_ADDR_LO_BASE_IDX 8 3632 #define regPCIEMSIX_VECT54_ADDR_HI 0x1a0d9 3633 #define regPCIEMSIX_VECT54_ADDR_HI_BASE_IDX 8 3634 #define regPCIEMSIX_VECT54_MSG_DATA 0x1a0da 3635 #define regPCIEMSIX_VECT54_MSG_DATA_BASE_IDX 8 3636 #define regPCIEMSIX_VECT54_CONTROL 0x1a0db 3637 #define regPCIEMSIX_VECT54_CONTROL_BASE_IDX 8 3638 #define regPCIEMSIX_VECT55_ADDR_LO 0x1a0dc 3639 #define regPCIEMSIX_VECT55_ADDR_LO_BASE_IDX 8 3640 #define regPCIEMSIX_VECT55_ADDR_HI 0x1a0dd 3641 #define regPCIEMSIX_VECT55_ADDR_HI_BASE_IDX 8 3642 #define regPCIEMSIX_VECT55_MSG_DATA 0x1a0de 3643 #define regPCIEMSIX_VECT55_MSG_DATA_BASE_IDX 8 3644 #define regPCIEMSIX_VECT55_CONTROL 0x1a0df 3645 #define regPCIEMSIX_VECT55_CONTROL_BASE_IDX 8 3646 #define regPCIEMSIX_VECT56_ADDR_LO 0x1a0e0 3647 #define regPCIEMSIX_VECT56_ADDR_LO_BASE_IDX 8 3648 #define regPCIEMSIX_VECT56_ADDR_HI 0x1a0e1 3649 #define regPCIEMSIX_VECT56_ADDR_HI_BASE_IDX 8 3650 #define regPCIEMSIX_VECT56_MSG_DATA 0x1a0e2 3651 #define regPCIEMSIX_VECT56_MSG_DATA_BASE_IDX 8 3652 #define regPCIEMSIX_VECT56_CONTROL 0x1a0e3 3653 #define regPCIEMSIX_VECT56_CONTROL_BASE_IDX 8 3654 #define regPCIEMSIX_VECT57_ADDR_LO 0x1a0e4 3655 #define regPCIEMSIX_VECT57_ADDR_LO_BASE_IDX 8 3656 #define regPCIEMSIX_VECT57_ADDR_HI 0x1a0e5 3657 #define regPCIEMSIX_VECT57_ADDR_HI_BASE_IDX 8 3658 #define regPCIEMSIX_VECT57_MSG_DATA 0x1a0e6 3659 #define regPCIEMSIX_VECT57_MSG_DATA_BASE_IDX 8 3660 #define regPCIEMSIX_VECT57_CONTROL 0x1a0e7 3661 #define regPCIEMSIX_VECT57_CONTROL_BASE_IDX 8 3662 #define regPCIEMSIX_VECT58_ADDR_LO 0x1a0e8 3663 #define regPCIEMSIX_VECT58_ADDR_LO_BASE_IDX 8 3664 #define regPCIEMSIX_VECT58_ADDR_HI 0x1a0e9 3665 #define regPCIEMSIX_VECT58_ADDR_HI_BASE_IDX 8 3666 #define regPCIEMSIX_VECT58_MSG_DATA 0x1a0ea 3667 #define regPCIEMSIX_VECT58_MSG_DATA_BASE_IDX 8 3668 #define regPCIEMSIX_VECT58_CONTROL 0x1a0eb 3669 #define regPCIEMSIX_VECT58_CONTROL_BASE_IDX 8 3670 #define regPCIEMSIX_VECT59_ADDR_LO 0x1a0ec 3671 #define regPCIEMSIX_VECT59_ADDR_LO_BASE_IDX 8 3672 #define regPCIEMSIX_VECT59_ADDR_HI 0x1a0ed 3673 #define regPCIEMSIX_VECT59_ADDR_HI_BASE_IDX 8 3674 #define regPCIEMSIX_VECT59_MSG_DATA 0x1a0ee 3675 #define regPCIEMSIX_VECT59_MSG_DATA_BASE_IDX 8 3676 #define regPCIEMSIX_VECT59_CONTROL 0x1a0ef 3677 #define regPCIEMSIX_VECT59_CONTROL_BASE_IDX 8 3678 #define regPCIEMSIX_VECT60_ADDR_LO 0x1a0f0 3679 #define regPCIEMSIX_VECT60_ADDR_LO_BASE_IDX 8 3680 #define regPCIEMSIX_VECT60_ADDR_HI 0x1a0f1 3681 #define regPCIEMSIX_VECT60_ADDR_HI_BASE_IDX 8 3682 #define regPCIEMSIX_VECT60_MSG_DATA 0x1a0f2 3683 #define regPCIEMSIX_VECT60_MSG_DATA_BASE_IDX 8 3684 #define regPCIEMSIX_VECT60_CONTROL 0x1a0f3 3685 #define regPCIEMSIX_VECT60_CONTROL_BASE_IDX 8 3686 #define regPCIEMSIX_VECT61_ADDR_LO 0x1a0f4 3687 #define regPCIEMSIX_VECT61_ADDR_LO_BASE_IDX 8 3688 #define regPCIEMSIX_VECT61_ADDR_HI 0x1a0f5 3689 #define regPCIEMSIX_VECT61_ADDR_HI_BASE_IDX 8 3690 #define regPCIEMSIX_VECT61_MSG_DATA 0x1a0f6 3691 #define regPCIEMSIX_VECT61_MSG_DATA_BASE_IDX 8 3692 #define regPCIEMSIX_VECT61_CONTROL 0x1a0f7 3693 #define regPCIEMSIX_VECT61_CONTROL_BASE_IDX 8 3694 #define regPCIEMSIX_VECT62_ADDR_LO 0x1a0f8 3695 #define regPCIEMSIX_VECT62_ADDR_LO_BASE_IDX 8 3696 #define regPCIEMSIX_VECT62_ADDR_HI 0x1a0f9 3697 #define regPCIEMSIX_VECT62_ADDR_HI_BASE_IDX 8 3698 #define regPCIEMSIX_VECT62_MSG_DATA 0x1a0fa 3699 #define regPCIEMSIX_VECT62_MSG_DATA_BASE_IDX 8 3700 #define regPCIEMSIX_VECT62_CONTROL 0x1a0fb 3701 #define regPCIEMSIX_VECT62_CONTROL_BASE_IDX 8 3702 #define regPCIEMSIX_VECT63_ADDR_LO 0x1a0fc 3703 #define regPCIEMSIX_VECT63_ADDR_LO_BASE_IDX 8 3704 #define regPCIEMSIX_VECT63_ADDR_HI 0x1a0fd 3705 #define regPCIEMSIX_VECT63_ADDR_HI_BASE_IDX 8 3706 #define regPCIEMSIX_VECT63_MSG_DATA 0x1a0fe 3707 #define regPCIEMSIX_VECT63_MSG_DATA_BASE_IDX 8 3708 #define regPCIEMSIX_VECT63_CONTROL 0x1a0ff 3709 #define regPCIEMSIX_VECT63_CONTROL_BASE_IDX 8 3710 #define regPCIEMSIX_VECT64_ADDR_LO 0x1a100 3711 #define regPCIEMSIX_VECT64_ADDR_LO_BASE_IDX 8 3712 #define regPCIEMSIX_VECT64_ADDR_HI 0x1a101 3713 #define regPCIEMSIX_VECT64_ADDR_HI_BASE_IDX 8 3714 #define regPCIEMSIX_VECT64_MSG_DATA 0x1a102 3715 #define regPCIEMSIX_VECT64_MSG_DATA_BASE_IDX 8 3716 #define regPCIEMSIX_VECT64_CONTROL 0x1a103 3717 #define regPCIEMSIX_VECT64_CONTROL_BASE_IDX 8 3718 #define regPCIEMSIX_VECT65_ADDR_LO 0x1a104 3719 #define regPCIEMSIX_VECT65_ADDR_LO_BASE_IDX 8 3720 #define regPCIEMSIX_VECT65_ADDR_HI 0x1a105 3721 #define regPCIEMSIX_VECT65_ADDR_HI_BASE_IDX 8 3722 #define regPCIEMSIX_VECT65_MSG_DATA 0x1a106 3723 #define regPCIEMSIX_VECT65_MSG_DATA_BASE_IDX 8 3724 #define regPCIEMSIX_VECT65_CONTROL 0x1a107 3725 #define regPCIEMSIX_VECT65_CONTROL_BASE_IDX 8 3726 #define regPCIEMSIX_VECT66_ADDR_LO 0x1a108 3727 #define regPCIEMSIX_VECT66_ADDR_LO_BASE_IDX 8 3728 #define regPCIEMSIX_VECT66_ADDR_HI 0x1a109 3729 #define regPCIEMSIX_VECT66_ADDR_HI_BASE_IDX 8 3730 #define regPCIEMSIX_VECT66_MSG_DATA 0x1a10a 3731 #define regPCIEMSIX_VECT66_MSG_DATA_BASE_IDX 8 3732 #define regPCIEMSIX_VECT66_CONTROL 0x1a10b 3733 #define regPCIEMSIX_VECT66_CONTROL_BASE_IDX 8 3734 #define regPCIEMSIX_VECT67_ADDR_LO 0x1a10c 3735 #define regPCIEMSIX_VECT67_ADDR_LO_BASE_IDX 8 3736 #define regPCIEMSIX_VECT67_ADDR_HI 0x1a10d 3737 #define regPCIEMSIX_VECT67_ADDR_HI_BASE_IDX 8 3738 #define regPCIEMSIX_VECT67_MSG_DATA 0x1a10e 3739 #define regPCIEMSIX_VECT67_MSG_DATA_BASE_IDX 8 3740 #define regPCIEMSIX_VECT67_CONTROL 0x1a10f 3741 #define regPCIEMSIX_VECT67_CONTROL_BASE_IDX 8 3742 #define regPCIEMSIX_VECT68_ADDR_LO 0x1a110 3743 #define regPCIEMSIX_VECT68_ADDR_LO_BASE_IDX 8 3744 #define regPCIEMSIX_VECT68_ADDR_HI 0x1a111 3745 #define regPCIEMSIX_VECT68_ADDR_HI_BASE_IDX 8 3746 #define regPCIEMSIX_VECT68_MSG_DATA 0x1a112 3747 #define regPCIEMSIX_VECT68_MSG_DATA_BASE_IDX 8 3748 #define regPCIEMSIX_VECT68_CONTROL 0x1a113 3749 #define regPCIEMSIX_VECT68_CONTROL_BASE_IDX 8 3750 #define regPCIEMSIX_VECT69_ADDR_LO 0x1a114 3751 #define regPCIEMSIX_VECT69_ADDR_LO_BASE_IDX 8 3752 #define regPCIEMSIX_VECT69_ADDR_HI 0x1a115 3753 #define regPCIEMSIX_VECT69_ADDR_HI_BASE_IDX 8 3754 #define regPCIEMSIX_VECT69_MSG_DATA 0x1a116 3755 #define regPCIEMSIX_VECT69_MSG_DATA_BASE_IDX 8 3756 #define regPCIEMSIX_VECT69_CONTROL 0x1a117 3757 #define regPCIEMSIX_VECT69_CONTROL_BASE_IDX 8 3758 #define regPCIEMSIX_VECT70_ADDR_LO 0x1a118 3759 #define regPCIEMSIX_VECT70_ADDR_LO_BASE_IDX 8 3760 #define regPCIEMSIX_VECT70_ADDR_HI 0x1a119 3761 #define regPCIEMSIX_VECT70_ADDR_HI_BASE_IDX 8 3762 #define regPCIEMSIX_VECT70_MSG_DATA 0x1a11a 3763 #define regPCIEMSIX_VECT70_MSG_DATA_BASE_IDX 8 3764 #define regPCIEMSIX_VECT70_CONTROL 0x1a11b 3765 #define regPCIEMSIX_VECT70_CONTROL_BASE_IDX 8 3766 #define regPCIEMSIX_VECT71_ADDR_LO 0x1a11c 3767 #define regPCIEMSIX_VECT71_ADDR_LO_BASE_IDX 8 3768 #define regPCIEMSIX_VECT71_ADDR_HI 0x1a11d 3769 #define regPCIEMSIX_VECT71_ADDR_HI_BASE_IDX 8 3770 #define regPCIEMSIX_VECT71_MSG_DATA 0x1a11e 3771 #define regPCIEMSIX_VECT71_MSG_DATA_BASE_IDX 8 3772 #define regPCIEMSIX_VECT71_CONTROL 0x1a11f 3773 #define regPCIEMSIX_VECT71_CONTROL_BASE_IDX 8 3774 #define regPCIEMSIX_VECT72_ADDR_LO 0x1a120 3775 #define regPCIEMSIX_VECT72_ADDR_LO_BASE_IDX 8 3776 #define regPCIEMSIX_VECT72_ADDR_HI 0x1a121 3777 #define regPCIEMSIX_VECT72_ADDR_HI_BASE_IDX 8 3778 #define regPCIEMSIX_VECT72_MSG_DATA 0x1a122 3779 #define regPCIEMSIX_VECT72_MSG_DATA_BASE_IDX 8 3780 #define regPCIEMSIX_VECT72_CONTROL 0x1a123 3781 #define regPCIEMSIX_VECT72_CONTROL_BASE_IDX 8 3782 #define regPCIEMSIX_VECT73_ADDR_LO 0x1a124 3783 #define regPCIEMSIX_VECT73_ADDR_LO_BASE_IDX 8 3784 #define regPCIEMSIX_VECT73_ADDR_HI 0x1a125 3785 #define regPCIEMSIX_VECT73_ADDR_HI_BASE_IDX 8 3786 #define regPCIEMSIX_VECT73_MSG_DATA 0x1a126 3787 #define regPCIEMSIX_VECT73_MSG_DATA_BASE_IDX 8 3788 #define regPCIEMSIX_VECT73_CONTROL 0x1a127 3789 #define regPCIEMSIX_VECT73_CONTROL_BASE_IDX 8 3790 #define regPCIEMSIX_VECT74_ADDR_LO 0x1a128 3791 #define regPCIEMSIX_VECT74_ADDR_LO_BASE_IDX 8 3792 #define regPCIEMSIX_VECT74_ADDR_HI 0x1a129 3793 #define regPCIEMSIX_VECT74_ADDR_HI_BASE_IDX 8 3794 #define regPCIEMSIX_VECT74_MSG_DATA 0x1a12a 3795 #define regPCIEMSIX_VECT74_MSG_DATA_BASE_IDX 8 3796 #define regPCIEMSIX_VECT74_CONTROL 0x1a12b 3797 #define regPCIEMSIX_VECT74_CONTROL_BASE_IDX 8 3798 #define regPCIEMSIX_VECT75_ADDR_LO 0x1a12c 3799 #define regPCIEMSIX_VECT75_ADDR_LO_BASE_IDX 8 3800 #define regPCIEMSIX_VECT75_ADDR_HI 0x1a12d 3801 #define regPCIEMSIX_VECT75_ADDR_HI_BASE_IDX 8 3802 #define regPCIEMSIX_VECT75_MSG_DATA 0x1a12e 3803 #define regPCIEMSIX_VECT75_MSG_DATA_BASE_IDX 8 3804 #define regPCIEMSIX_VECT75_CONTROL 0x1a12f 3805 #define regPCIEMSIX_VECT75_CONTROL_BASE_IDX 8 3806 #define regPCIEMSIX_VECT76_ADDR_LO 0x1a130 3807 #define regPCIEMSIX_VECT76_ADDR_LO_BASE_IDX 8 3808 #define regPCIEMSIX_VECT76_ADDR_HI 0x1a131 3809 #define regPCIEMSIX_VECT76_ADDR_HI_BASE_IDX 8 3810 #define regPCIEMSIX_VECT76_MSG_DATA 0x1a132 3811 #define regPCIEMSIX_VECT76_MSG_DATA_BASE_IDX 8 3812 #define regPCIEMSIX_VECT76_CONTROL 0x1a133 3813 #define regPCIEMSIX_VECT76_CONTROL_BASE_IDX 8 3814 #define regPCIEMSIX_VECT77_ADDR_LO 0x1a134 3815 #define regPCIEMSIX_VECT77_ADDR_LO_BASE_IDX 8 3816 #define regPCIEMSIX_VECT77_ADDR_HI 0x1a135 3817 #define regPCIEMSIX_VECT77_ADDR_HI_BASE_IDX 8 3818 #define regPCIEMSIX_VECT77_MSG_DATA 0x1a136 3819 #define regPCIEMSIX_VECT77_MSG_DATA_BASE_IDX 8 3820 #define regPCIEMSIX_VECT77_CONTROL 0x1a137 3821 #define regPCIEMSIX_VECT77_CONTROL_BASE_IDX 8 3822 #define regPCIEMSIX_VECT78_ADDR_LO 0x1a138 3823 #define regPCIEMSIX_VECT78_ADDR_LO_BASE_IDX 8 3824 #define regPCIEMSIX_VECT78_ADDR_HI 0x1a139 3825 #define regPCIEMSIX_VECT78_ADDR_HI_BASE_IDX 8 3826 #define regPCIEMSIX_VECT78_MSG_DATA 0x1a13a 3827 #define regPCIEMSIX_VECT78_MSG_DATA_BASE_IDX 8 3828 #define regPCIEMSIX_VECT78_CONTROL 0x1a13b 3829 #define regPCIEMSIX_VECT78_CONTROL_BASE_IDX 8 3830 #define regPCIEMSIX_VECT79_ADDR_LO 0x1a13c 3831 #define regPCIEMSIX_VECT79_ADDR_LO_BASE_IDX 8 3832 #define regPCIEMSIX_VECT79_ADDR_HI 0x1a13d 3833 #define regPCIEMSIX_VECT79_ADDR_HI_BASE_IDX 8 3834 #define regPCIEMSIX_VECT79_MSG_DATA 0x1a13e 3835 #define regPCIEMSIX_VECT79_MSG_DATA_BASE_IDX 8 3836 #define regPCIEMSIX_VECT79_CONTROL 0x1a13f 3837 #define regPCIEMSIX_VECT79_CONTROL_BASE_IDX 8 3838 #define regPCIEMSIX_VECT80_ADDR_LO 0x1a140 3839 #define regPCIEMSIX_VECT80_ADDR_LO_BASE_IDX 8 3840 #define regPCIEMSIX_VECT80_ADDR_HI 0x1a141 3841 #define regPCIEMSIX_VECT80_ADDR_HI_BASE_IDX 8 3842 #define regPCIEMSIX_VECT80_MSG_DATA 0x1a142 3843 #define regPCIEMSIX_VECT80_MSG_DATA_BASE_IDX 8 3844 #define regPCIEMSIX_VECT80_CONTROL 0x1a143 3845 #define regPCIEMSIX_VECT80_CONTROL_BASE_IDX 8 3846 #define regPCIEMSIX_VECT81_ADDR_LO 0x1a144 3847 #define regPCIEMSIX_VECT81_ADDR_LO_BASE_IDX 8 3848 #define regPCIEMSIX_VECT81_ADDR_HI 0x1a145 3849 #define regPCIEMSIX_VECT81_ADDR_HI_BASE_IDX 8 3850 #define regPCIEMSIX_VECT81_MSG_DATA 0x1a146 3851 #define regPCIEMSIX_VECT81_MSG_DATA_BASE_IDX 8 3852 #define regPCIEMSIX_VECT81_CONTROL 0x1a147 3853 #define regPCIEMSIX_VECT81_CONTROL_BASE_IDX 8 3854 #define regPCIEMSIX_VECT82_ADDR_LO 0x1a148 3855 #define regPCIEMSIX_VECT82_ADDR_LO_BASE_IDX 8 3856 #define regPCIEMSIX_VECT82_ADDR_HI 0x1a149 3857 #define regPCIEMSIX_VECT82_ADDR_HI_BASE_IDX 8 3858 #define regPCIEMSIX_VECT82_MSG_DATA 0x1a14a 3859 #define regPCIEMSIX_VECT82_MSG_DATA_BASE_IDX 8 3860 #define regPCIEMSIX_VECT82_CONTROL 0x1a14b 3861 #define regPCIEMSIX_VECT82_CONTROL_BASE_IDX 8 3862 #define regPCIEMSIX_VECT83_ADDR_LO 0x1a14c 3863 #define regPCIEMSIX_VECT83_ADDR_LO_BASE_IDX 8 3864 #define regPCIEMSIX_VECT83_ADDR_HI 0x1a14d 3865 #define regPCIEMSIX_VECT83_ADDR_HI_BASE_IDX 8 3866 #define regPCIEMSIX_VECT83_MSG_DATA 0x1a14e 3867 #define regPCIEMSIX_VECT83_MSG_DATA_BASE_IDX 8 3868 #define regPCIEMSIX_VECT83_CONTROL 0x1a14f 3869 #define regPCIEMSIX_VECT83_CONTROL_BASE_IDX 8 3870 #define regPCIEMSIX_VECT84_ADDR_LO 0x1a150 3871 #define regPCIEMSIX_VECT84_ADDR_LO_BASE_IDX 8 3872 #define regPCIEMSIX_VECT84_ADDR_HI 0x1a151 3873 #define regPCIEMSIX_VECT84_ADDR_HI_BASE_IDX 8 3874 #define regPCIEMSIX_VECT84_MSG_DATA 0x1a152 3875 #define regPCIEMSIX_VECT84_MSG_DATA_BASE_IDX 8 3876 #define regPCIEMSIX_VECT84_CONTROL 0x1a153 3877 #define regPCIEMSIX_VECT84_CONTROL_BASE_IDX 8 3878 #define regPCIEMSIX_VECT85_ADDR_LO 0x1a154 3879 #define regPCIEMSIX_VECT85_ADDR_LO_BASE_IDX 8 3880 #define regPCIEMSIX_VECT85_ADDR_HI 0x1a155 3881 #define regPCIEMSIX_VECT85_ADDR_HI_BASE_IDX 8 3882 #define regPCIEMSIX_VECT85_MSG_DATA 0x1a156 3883 #define regPCIEMSIX_VECT85_MSG_DATA_BASE_IDX 8 3884 #define regPCIEMSIX_VECT85_CONTROL 0x1a157 3885 #define regPCIEMSIX_VECT85_CONTROL_BASE_IDX 8 3886 #define regPCIEMSIX_VECT86_ADDR_LO 0x1a158 3887 #define regPCIEMSIX_VECT86_ADDR_LO_BASE_IDX 8 3888 #define regPCIEMSIX_VECT86_ADDR_HI 0x1a159 3889 #define regPCIEMSIX_VECT86_ADDR_HI_BASE_IDX 8 3890 #define regPCIEMSIX_VECT86_MSG_DATA 0x1a15a 3891 #define regPCIEMSIX_VECT86_MSG_DATA_BASE_IDX 8 3892 #define regPCIEMSIX_VECT86_CONTROL 0x1a15b 3893 #define regPCIEMSIX_VECT86_CONTROL_BASE_IDX 8 3894 #define regPCIEMSIX_VECT87_ADDR_LO 0x1a15c 3895 #define regPCIEMSIX_VECT87_ADDR_LO_BASE_IDX 8 3896 #define regPCIEMSIX_VECT87_ADDR_HI 0x1a15d 3897 #define regPCIEMSIX_VECT87_ADDR_HI_BASE_IDX 8 3898 #define regPCIEMSIX_VECT87_MSG_DATA 0x1a15e 3899 #define regPCIEMSIX_VECT87_MSG_DATA_BASE_IDX 8 3900 #define regPCIEMSIX_VECT87_CONTROL 0x1a15f 3901 #define regPCIEMSIX_VECT87_CONTROL_BASE_IDX 8 3902 #define regPCIEMSIX_VECT88_ADDR_LO 0x1a160 3903 #define regPCIEMSIX_VECT88_ADDR_LO_BASE_IDX 8 3904 #define regPCIEMSIX_VECT88_ADDR_HI 0x1a161 3905 #define regPCIEMSIX_VECT88_ADDR_HI_BASE_IDX 8 3906 #define regPCIEMSIX_VECT88_MSG_DATA 0x1a162 3907 #define regPCIEMSIX_VECT88_MSG_DATA_BASE_IDX 8 3908 #define regPCIEMSIX_VECT88_CONTROL 0x1a163 3909 #define regPCIEMSIX_VECT88_CONTROL_BASE_IDX 8 3910 #define regPCIEMSIX_VECT89_ADDR_LO 0x1a164 3911 #define regPCIEMSIX_VECT89_ADDR_LO_BASE_IDX 8 3912 #define regPCIEMSIX_VECT89_ADDR_HI 0x1a165 3913 #define regPCIEMSIX_VECT89_ADDR_HI_BASE_IDX 8 3914 #define regPCIEMSIX_VECT89_MSG_DATA 0x1a166 3915 #define regPCIEMSIX_VECT89_MSG_DATA_BASE_IDX 8 3916 #define regPCIEMSIX_VECT89_CONTROL 0x1a167 3917 #define regPCIEMSIX_VECT89_CONTROL_BASE_IDX 8 3918 #define regPCIEMSIX_VECT90_ADDR_LO 0x1a168 3919 #define regPCIEMSIX_VECT90_ADDR_LO_BASE_IDX 8 3920 #define regPCIEMSIX_VECT90_ADDR_HI 0x1a169 3921 #define regPCIEMSIX_VECT90_ADDR_HI_BASE_IDX 8 3922 #define regPCIEMSIX_VECT90_MSG_DATA 0x1a16a 3923 #define regPCIEMSIX_VECT90_MSG_DATA_BASE_IDX 8 3924 #define regPCIEMSIX_VECT90_CONTROL 0x1a16b 3925 #define regPCIEMSIX_VECT90_CONTROL_BASE_IDX 8 3926 #define regPCIEMSIX_VECT91_ADDR_LO 0x1a16c 3927 #define regPCIEMSIX_VECT91_ADDR_LO_BASE_IDX 8 3928 #define regPCIEMSIX_VECT91_ADDR_HI 0x1a16d 3929 #define regPCIEMSIX_VECT91_ADDR_HI_BASE_IDX 8 3930 #define regPCIEMSIX_VECT91_MSG_DATA 0x1a16e 3931 #define regPCIEMSIX_VECT91_MSG_DATA_BASE_IDX 8 3932 #define regPCIEMSIX_VECT91_CONTROL 0x1a16f 3933 #define regPCIEMSIX_VECT91_CONTROL_BASE_IDX 8 3934 #define regPCIEMSIX_VECT92_ADDR_LO 0x1a170 3935 #define regPCIEMSIX_VECT92_ADDR_LO_BASE_IDX 8 3936 #define regPCIEMSIX_VECT92_ADDR_HI 0x1a171 3937 #define regPCIEMSIX_VECT92_ADDR_HI_BASE_IDX 8 3938 #define regPCIEMSIX_VECT92_MSG_DATA 0x1a172 3939 #define regPCIEMSIX_VECT92_MSG_DATA_BASE_IDX 8 3940 #define regPCIEMSIX_VECT92_CONTROL 0x1a173 3941 #define regPCIEMSIX_VECT92_CONTROL_BASE_IDX 8 3942 #define regPCIEMSIX_VECT93_ADDR_LO 0x1a174 3943 #define regPCIEMSIX_VECT93_ADDR_LO_BASE_IDX 8 3944 #define regPCIEMSIX_VECT93_ADDR_HI 0x1a175 3945 #define regPCIEMSIX_VECT93_ADDR_HI_BASE_IDX 8 3946 #define regPCIEMSIX_VECT93_MSG_DATA 0x1a176 3947 #define regPCIEMSIX_VECT93_MSG_DATA_BASE_IDX 8 3948 #define regPCIEMSIX_VECT93_CONTROL 0x1a177 3949 #define regPCIEMSIX_VECT93_CONTROL_BASE_IDX 8 3950 #define regPCIEMSIX_VECT94_ADDR_LO 0x1a178 3951 #define regPCIEMSIX_VECT94_ADDR_LO_BASE_IDX 8 3952 #define regPCIEMSIX_VECT94_ADDR_HI 0x1a179 3953 #define regPCIEMSIX_VECT94_ADDR_HI_BASE_IDX 8 3954 #define regPCIEMSIX_VECT94_MSG_DATA 0x1a17a 3955 #define regPCIEMSIX_VECT94_MSG_DATA_BASE_IDX 8 3956 #define regPCIEMSIX_VECT94_CONTROL 0x1a17b 3957 #define regPCIEMSIX_VECT94_CONTROL_BASE_IDX 8 3958 #define regPCIEMSIX_VECT95_ADDR_LO 0x1a17c 3959 #define regPCIEMSIX_VECT95_ADDR_LO_BASE_IDX 8 3960 #define regPCIEMSIX_VECT95_ADDR_HI 0x1a17d 3961 #define regPCIEMSIX_VECT95_ADDR_HI_BASE_IDX 8 3962 #define regPCIEMSIX_VECT95_MSG_DATA 0x1a17e 3963 #define regPCIEMSIX_VECT95_MSG_DATA_BASE_IDX 8 3964 #define regPCIEMSIX_VECT95_CONTROL 0x1a17f 3965 #define regPCIEMSIX_VECT95_CONTROL_BASE_IDX 8 3966 #define regPCIEMSIX_VECT96_ADDR_LO 0x1a180 3967 #define regPCIEMSIX_VECT96_ADDR_LO_BASE_IDX 8 3968 #define regPCIEMSIX_VECT96_ADDR_HI 0x1a181 3969 #define regPCIEMSIX_VECT96_ADDR_HI_BASE_IDX 8 3970 #define regPCIEMSIX_VECT96_MSG_DATA 0x1a182 3971 #define regPCIEMSIX_VECT96_MSG_DATA_BASE_IDX 8 3972 #define regPCIEMSIX_VECT96_CONTROL 0x1a183 3973 #define regPCIEMSIX_VECT96_CONTROL_BASE_IDX 8 3974 #define regPCIEMSIX_VECT97_ADDR_LO 0x1a184 3975 #define regPCIEMSIX_VECT97_ADDR_LO_BASE_IDX 8 3976 #define regPCIEMSIX_VECT97_ADDR_HI 0x1a185 3977 #define regPCIEMSIX_VECT97_ADDR_HI_BASE_IDX 8 3978 #define regPCIEMSIX_VECT97_MSG_DATA 0x1a186 3979 #define regPCIEMSIX_VECT97_MSG_DATA_BASE_IDX 8 3980 #define regPCIEMSIX_VECT97_CONTROL 0x1a187 3981 #define regPCIEMSIX_VECT97_CONTROL_BASE_IDX 8 3982 #define regPCIEMSIX_VECT98_ADDR_LO 0x1a188 3983 #define regPCIEMSIX_VECT98_ADDR_LO_BASE_IDX 8 3984 #define regPCIEMSIX_VECT98_ADDR_HI 0x1a189 3985 #define regPCIEMSIX_VECT98_ADDR_HI_BASE_IDX 8 3986 #define regPCIEMSIX_VECT98_MSG_DATA 0x1a18a 3987 #define regPCIEMSIX_VECT98_MSG_DATA_BASE_IDX 8 3988 #define regPCIEMSIX_VECT98_CONTROL 0x1a18b 3989 #define regPCIEMSIX_VECT98_CONTROL_BASE_IDX 8 3990 #define regPCIEMSIX_VECT99_ADDR_LO 0x1a18c 3991 #define regPCIEMSIX_VECT99_ADDR_LO_BASE_IDX 8 3992 #define regPCIEMSIX_VECT99_ADDR_HI 0x1a18d 3993 #define regPCIEMSIX_VECT99_ADDR_HI_BASE_IDX 8 3994 #define regPCIEMSIX_VECT99_MSG_DATA 0x1a18e 3995 #define regPCIEMSIX_VECT99_MSG_DATA_BASE_IDX 8 3996 #define regPCIEMSIX_VECT99_CONTROL 0x1a18f 3997 #define regPCIEMSIX_VECT99_CONTROL_BASE_IDX 8 3998 #define regPCIEMSIX_VECT100_ADDR_LO 0x1a190 3999 #define regPCIEMSIX_VECT100_ADDR_LO_BASE_IDX 8 4000 #define regPCIEMSIX_VECT100_ADDR_HI 0x1a191 4001 #define regPCIEMSIX_VECT100_ADDR_HI_BASE_IDX 8 4002 #define regPCIEMSIX_VECT100_MSG_DATA 0x1a192 4003 #define regPCIEMSIX_VECT100_MSG_DATA_BASE_IDX 8 4004 #define regPCIEMSIX_VECT100_CONTROL 0x1a193 4005 #define regPCIEMSIX_VECT100_CONTROL_BASE_IDX 8 4006 #define regPCIEMSIX_VECT101_ADDR_LO 0x1a194 4007 #define regPCIEMSIX_VECT101_ADDR_LO_BASE_IDX 8 4008 #define regPCIEMSIX_VECT101_ADDR_HI 0x1a195 4009 #define regPCIEMSIX_VECT101_ADDR_HI_BASE_IDX 8 4010 #define regPCIEMSIX_VECT101_MSG_DATA 0x1a196 4011 #define regPCIEMSIX_VECT101_MSG_DATA_BASE_IDX 8 4012 #define regPCIEMSIX_VECT101_CONTROL 0x1a197 4013 #define regPCIEMSIX_VECT101_CONTROL_BASE_IDX 8 4014 #define regPCIEMSIX_VECT102_ADDR_LO 0x1a198 4015 #define regPCIEMSIX_VECT102_ADDR_LO_BASE_IDX 8 4016 #define regPCIEMSIX_VECT102_ADDR_HI 0x1a199 4017 #define regPCIEMSIX_VECT102_ADDR_HI_BASE_IDX 8 4018 #define regPCIEMSIX_VECT102_MSG_DATA 0x1a19a 4019 #define regPCIEMSIX_VECT102_MSG_DATA_BASE_IDX 8 4020 #define regPCIEMSIX_VECT102_CONTROL 0x1a19b 4021 #define regPCIEMSIX_VECT102_CONTROL_BASE_IDX 8 4022 #define regPCIEMSIX_VECT103_ADDR_LO 0x1a19c 4023 #define regPCIEMSIX_VECT103_ADDR_LO_BASE_IDX 8 4024 #define regPCIEMSIX_VECT103_ADDR_HI 0x1a19d 4025 #define regPCIEMSIX_VECT103_ADDR_HI_BASE_IDX 8 4026 #define regPCIEMSIX_VECT103_MSG_DATA 0x1a19e 4027 #define regPCIEMSIX_VECT103_MSG_DATA_BASE_IDX 8 4028 #define regPCIEMSIX_VECT103_CONTROL 0x1a19f 4029 #define regPCIEMSIX_VECT103_CONTROL_BASE_IDX 8 4030 #define regPCIEMSIX_VECT104_ADDR_LO 0x1a1a0 4031 #define regPCIEMSIX_VECT104_ADDR_LO_BASE_IDX 8 4032 #define regPCIEMSIX_VECT104_ADDR_HI 0x1a1a1 4033 #define regPCIEMSIX_VECT104_ADDR_HI_BASE_IDX 8 4034 #define regPCIEMSIX_VECT104_MSG_DATA 0x1a1a2 4035 #define regPCIEMSIX_VECT104_MSG_DATA_BASE_IDX 8 4036 #define regPCIEMSIX_VECT104_CONTROL 0x1a1a3 4037 #define regPCIEMSIX_VECT104_CONTROL_BASE_IDX 8 4038 #define regPCIEMSIX_VECT105_ADDR_LO 0x1a1a4 4039 #define regPCIEMSIX_VECT105_ADDR_LO_BASE_IDX 8 4040 #define regPCIEMSIX_VECT105_ADDR_HI 0x1a1a5 4041 #define regPCIEMSIX_VECT105_ADDR_HI_BASE_IDX 8 4042 #define regPCIEMSIX_VECT105_MSG_DATA 0x1a1a6 4043 #define regPCIEMSIX_VECT105_MSG_DATA_BASE_IDX 8 4044 #define regPCIEMSIX_VECT105_CONTROL 0x1a1a7 4045 #define regPCIEMSIX_VECT105_CONTROL_BASE_IDX 8 4046 #define regPCIEMSIX_VECT106_ADDR_LO 0x1a1a8 4047 #define regPCIEMSIX_VECT106_ADDR_LO_BASE_IDX 8 4048 #define regPCIEMSIX_VECT106_ADDR_HI 0x1a1a9 4049 #define regPCIEMSIX_VECT106_ADDR_HI_BASE_IDX 8 4050 #define regPCIEMSIX_VECT106_MSG_DATA 0x1a1aa 4051 #define regPCIEMSIX_VECT106_MSG_DATA_BASE_IDX 8 4052 #define regPCIEMSIX_VECT106_CONTROL 0x1a1ab 4053 #define regPCIEMSIX_VECT106_CONTROL_BASE_IDX 8 4054 #define regPCIEMSIX_VECT107_ADDR_LO 0x1a1ac 4055 #define regPCIEMSIX_VECT107_ADDR_LO_BASE_IDX 8 4056 #define regPCIEMSIX_VECT107_ADDR_HI 0x1a1ad 4057 #define regPCIEMSIX_VECT107_ADDR_HI_BASE_IDX 8 4058 #define regPCIEMSIX_VECT107_MSG_DATA 0x1a1ae 4059 #define regPCIEMSIX_VECT107_MSG_DATA_BASE_IDX 8 4060 #define regPCIEMSIX_VECT107_CONTROL 0x1a1af 4061 #define regPCIEMSIX_VECT107_CONTROL_BASE_IDX 8 4062 #define regPCIEMSIX_VECT108_ADDR_LO 0x1a1b0 4063 #define regPCIEMSIX_VECT108_ADDR_LO_BASE_IDX 8 4064 #define regPCIEMSIX_VECT108_ADDR_HI 0x1a1b1 4065 #define regPCIEMSIX_VECT108_ADDR_HI_BASE_IDX 8 4066 #define regPCIEMSIX_VECT108_MSG_DATA 0x1a1b2 4067 #define regPCIEMSIX_VECT108_MSG_DATA_BASE_IDX 8 4068 #define regPCIEMSIX_VECT108_CONTROL 0x1a1b3 4069 #define regPCIEMSIX_VECT108_CONTROL_BASE_IDX 8 4070 #define regPCIEMSIX_VECT109_ADDR_LO 0x1a1b4 4071 #define regPCIEMSIX_VECT109_ADDR_LO_BASE_IDX 8 4072 #define regPCIEMSIX_VECT109_ADDR_HI 0x1a1b5 4073 #define regPCIEMSIX_VECT109_ADDR_HI_BASE_IDX 8 4074 #define regPCIEMSIX_VECT109_MSG_DATA 0x1a1b6 4075 #define regPCIEMSIX_VECT109_MSG_DATA_BASE_IDX 8 4076 #define regPCIEMSIX_VECT109_CONTROL 0x1a1b7 4077 #define regPCIEMSIX_VECT109_CONTROL_BASE_IDX 8 4078 #define regPCIEMSIX_VECT110_ADDR_LO 0x1a1b8 4079 #define regPCIEMSIX_VECT110_ADDR_LO_BASE_IDX 8 4080 #define regPCIEMSIX_VECT110_ADDR_HI 0x1a1b9 4081 #define regPCIEMSIX_VECT110_ADDR_HI_BASE_IDX 8 4082 #define regPCIEMSIX_VECT110_MSG_DATA 0x1a1ba 4083 #define regPCIEMSIX_VECT110_MSG_DATA_BASE_IDX 8 4084 #define regPCIEMSIX_VECT110_CONTROL 0x1a1bb 4085 #define regPCIEMSIX_VECT110_CONTROL_BASE_IDX 8 4086 #define regPCIEMSIX_VECT111_ADDR_LO 0x1a1bc 4087 #define regPCIEMSIX_VECT111_ADDR_LO_BASE_IDX 8 4088 #define regPCIEMSIX_VECT111_ADDR_HI 0x1a1bd 4089 #define regPCIEMSIX_VECT111_ADDR_HI_BASE_IDX 8 4090 #define regPCIEMSIX_VECT111_MSG_DATA 0x1a1be 4091 #define regPCIEMSIX_VECT111_MSG_DATA_BASE_IDX 8 4092 #define regPCIEMSIX_VECT111_CONTROL 0x1a1bf 4093 #define regPCIEMSIX_VECT111_CONTROL_BASE_IDX 8 4094 #define regPCIEMSIX_VECT112_ADDR_LO 0x1a1c0 4095 #define regPCIEMSIX_VECT112_ADDR_LO_BASE_IDX 8 4096 #define regPCIEMSIX_VECT112_ADDR_HI 0x1a1c1 4097 #define regPCIEMSIX_VECT112_ADDR_HI_BASE_IDX 8 4098 #define regPCIEMSIX_VECT112_MSG_DATA 0x1a1c2 4099 #define regPCIEMSIX_VECT112_MSG_DATA_BASE_IDX 8 4100 #define regPCIEMSIX_VECT112_CONTROL 0x1a1c3 4101 #define regPCIEMSIX_VECT112_CONTROL_BASE_IDX 8 4102 #define regPCIEMSIX_VECT113_ADDR_LO 0x1a1c4 4103 #define regPCIEMSIX_VECT113_ADDR_LO_BASE_IDX 8 4104 #define regPCIEMSIX_VECT113_ADDR_HI 0x1a1c5 4105 #define regPCIEMSIX_VECT113_ADDR_HI_BASE_IDX 8 4106 #define regPCIEMSIX_VECT113_MSG_DATA 0x1a1c6 4107 #define regPCIEMSIX_VECT113_MSG_DATA_BASE_IDX 8 4108 #define regPCIEMSIX_VECT113_CONTROL 0x1a1c7 4109 #define regPCIEMSIX_VECT113_CONTROL_BASE_IDX 8 4110 #define regPCIEMSIX_VECT114_ADDR_LO 0x1a1c8 4111 #define regPCIEMSIX_VECT114_ADDR_LO_BASE_IDX 8 4112 #define regPCIEMSIX_VECT114_ADDR_HI 0x1a1c9 4113 #define regPCIEMSIX_VECT114_ADDR_HI_BASE_IDX 8 4114 #define regPCIEMSIX_VECT114_MSG_DATA 0x1a1ca 4115 #define regPCIEMSIX_VECT114_MSG_DATA_BASE_IDX 8 4116 #define regPCIEMSIX_VECT114_CONTROL 0x1a1cb 4117 #define regPCIEMSIX_VECT114_CONTROL_BASE_IDX 8 4118 #define regPCIEMSIX_VECT115_ADDR_LO 0x1a1cc 4119 #define regPCIEMSIX_VECT115_ADDR_LO_BASE_IDX 8 4120 #define regPCIEMSIX_VECT115_ADDR_HI 0x1a1cd 4121 #define regPCIEMSIX_VECT115_ADDR_HI_BASE_IDX 8 4122 #define regPCIEMSIX_VECT115_MSG_DATA 0x1a1ce 4123 #define regPCIEMSIX_VECT115_MSG_DATA_BASE_IDX 8 4124 #define regPCIEMSIX_VECT115_CONTROL 0x1a1cf 4125 #define regPCIEMSIX_VECT115_CONTROL_BASE_IDX 8 4126 #define regPCIEMSIX_VECT116_ADDR_LO 0x1a1d0 4127 #define regPCIEMSIX_VECT116_ADDR_LO_BASE_IDX 8 4128 #define regPCIEMSIX_VECT116_ADDR_HI 0x1a1d1 4129 #define regPCIEMSIX_VECT116_ADDR_HI_BASE_IDX 8 4130 #define regPCIEMSIX_VECT116_MSG_DATA 0x1a1d2 4131 #define regPCIEMSIX_VECT116_MSG_DATA_BASE_IDX 8 4132 #define regPCIEMSIX_VECT116_CONTROL 0x1a1d3 4133 #define regPCIEMSIX_VECT116_CONTROL_BASE_IDX 8 4134 #define regPCIEMSIX_VECT117_ADDR_LO 0x1a1d4 4135 #define regPCIEMSIX_VECT117_ADDR_LO_BASE_IDX 8 4136 #define regPCIEMSIX_VECT117_ADDR_HI 0x1a1d5 4137 #define regPCIEMSIX_VECT117_ADDR_HI_BASE_IDX 8 4138 #define regPCIEMSIX_VECT117_MSG_DATA 0x1a1d6 4139 #define regPCIEMSIX_VECT117_MSG_DATA_BASE_IDX 8 4140 #define regPCIEMSIX_VECT117_CONTROL 0x1a1d7 4141 #define regPCIEMSIX_VECT117_CONTROL_BASE_IDX 8 4142 #define regPCIEMSIX_VECT118_ADDR_LO 0x1a1d8 4143 #define regPCIEMSIX_VECT118_ADDR_LO_BASE_IDX 8 4144 #define regPCIEMSIX_VECT118_ADDR_HI 0x1a1d9 4145 #define regPCIEMSIX_VECT118_ADDR_HI_BASE_IDX 8 4146 #define regPCIEMSIX_VECT118_MSG_DATA 0x1a1da 4147 #define regPCIEMSIX_VECT118_MSG_DATA_BASE_IDX 8 4148 #define regPCIEMSIX_VECT118_CONTROL 0x1a1db 4149 #define regPCIEMSIX_VECT118_CONTROL_BASE_IDX 8 4150 #define regPCIEMSIX_VECT119_ADDR_LO 0x1a1dc 4151 #define regPCIEMSIX_VECT119_ADDR_LO_BASE_IDX 8 4152 #define regPCIEMSIX_VECT119_ADDR_HI 0x1a1dd 4153 #define regPCIEMSIX_VECT119_ADDR_HI_BASE_IDX 8 4154 #define regPCIEMSIX_VECT119_MSG_DATA 0x1a1de 4155 #define regPCIEMSIX_VECT119_MSG_DATA_BASE_IDX 8 4156 #define regPCIEMSIX_VECT119_CONTROL 0x1a1df 4157 #define regPCIEMSIX_VECT119_CONTROL_BASE_IDX 8 4158 #define regPCIEMSIX_VECT120_ADDR_LO 0x1a1e0 4159 #define regPCIEMSIX_VECT120_ADDR_LO_BASE_IDX 8 4160 #define regPCIEMSIX_VECT120_ADDR_HI 0x1a1e1 4161 #define regPCIEMSIX_VECT120_ADDR_HI_BASE_IDX 8 4162 #define regPCIEMSIX_VECT120_MSG_DATA 0x1a1e2 4163 #define regPCIEMSIX_VECT120_MSG_DATA_BASE_IDX 8 4164 #define regPCIEMSIX_VECT120_CONTROL 0x1a1e3 4165 #define regPCIEMSIX_VECT120_CONTROL_BASE_IDX 8 4166 #define regPCIEMSIX_VECT121_ADDR_LO 0x1a1e4 4167 #define regPCIEMSIX_VECT121_ADDR_LO_BASE_IDX 8 4168 #define regPCIEMSIX_VECT121_ADDR_HI 0x1a1e5 4169 #define regPCIEMSIX_VECT121_ADDR_HI_BASE_IDX 8 4170 #define regPCIEMSIX_VECT121_MSG_DATA 0x1a1e6 4171 #define regPCIEMSIX_VECT121_MSG_DATA_BASE_IDX 8 4172 #define regPCIEMSIX_VECT121_CONTROL 0x1a1e7 4173 #define regPCIEMSIX_VECT121_CONTROL_BASE_IDX 8 4174 #define regPCIEMSIX_VECT122_ADDR_LO 0x1a1e8 4175 #define regPCIEMSIX_VECT122_ADDR_LO_BASE_IDX 8 4176 #define regPCIEMSIX_VECT122_ADDR_HI 0x1a1e9 4177 #define regPCIEMSIX_VECT122_ADDR_HI_BASE_IDX 8 4178 #define regPCIEMSIX_VECT122_MSG_DATA 0x1a1ea 4179 #define regPCIEMSIX_VECT122_MSG_DATA_BASE_IDX 8 4180 #define regPCIEMSIX_VECT122_CONTROL 0x1a1eb 4181 #define regPCIEMSIX_VECT122_CONTROL_BASE_IDX 8 4182 #define regPCIEMSIX_VECT123_ADDR_LO 0x1a1ec 4183 #define regPCIEMSIX_VECT123_ADDR_LO_BASE_IDX 8 4184 #define regPCIEMSIX_VECT123_ADDR_HI 0x1a1ed 4185 #define regPCIEMSIX_VECT123_ADDR_HI_BASE_IDX 8 4186 #define regPCIEMSIX_VECT123_MSG_DATA 0x1a1ee 4187 #define regPCIEMSIX_VECT123_MSG_DATA_BASE_IDX 8 4188 #define regPCIEMSIX_VECT123_CONTROL 0x1a1ef 4189 #define regPCIEMSIX_VECT123_CONTROL_BASE_IDX 8 4190 #define regPCIEMSIX_VECT124_ADDR_LO 0x1a1f0 4191 #define regPCIEMSIX_VECT124_ADDR_LO_BASE_IDX 8 4192 #define regPCIEMSIX_VECT124_ADDR_HI 0x1a1f1 4193 #define regPCIEMSIX_VECT124_ADDR_HI_BASE_IDX 8 4194 #define regPCIEMSIX_VECT124_MSG_DATA 0x1a1f2 4195 #define regPCIEMSIX_VECT124_MSG_DATA_BASE_IDX 8 4196 #define regPCIEMSIX_VECT124_CONTROL 0x1a1f3 4197 #define regPCIEMSIX_VECT124_CONTROL_BASE_IDX 8 4198 #define regPCIEMSIX_VECT125_ADDR_LO 0x1a1f4 4199 #define regPCIEMSIX_VECT125_ADDR_LO_BASE_IDX 8 4200 #define regPCIEMSIX_VECT125_ADDR_HI 0x1a1f5 4201 #define regPCIEMSIX_VECT125_ADDR_HI_BASE_IDX 8 4202 #define regPCIEMSIX_VECT125_MSG_DATA 0x1a1f6 4203 #define regPCIEMSIX_VECT125_MSG_DATA_BASE_IDX 8 4204 #define regPCIEMSIX_VECT125_CONTROL 0x1a1f7 4205 #define regPCIEMSIX_VECT125_CONTROL_BASE_IDX 8 4206 #define regPCIEMSIX_VECT126_ADDR_LO 0x1a1f8 4207 #define regPCIEMSIX_VECT126_ADDR_LO_BASE_IDX 8 4208 #define regPCIEMSIX_VECT126_ADDR_HI 0x1a1f9 4209 #define regPCIEMSIX_VECT126_ADDR_HI_BASE_IDX 8 4210 #define regPCIEMSIX_VECT126_MSG_DATA 0x1a1fa 4211 #define regPCIEMSIX_VECT126_MSG_DATA_BASE_IDX 8 4212 #define regPCIEMSIX_VECT126_CONTROL 0x1a1fb 4213 #define regPCIEMSIX_VECT126_CONTROL_BASE_IDX 8 4214 #define regPCIEMSIX_VECT127_ADDR_LO 0x1a1fc 4215 #define regPCIEMSIX_VECT127_ADDR_LO_BASE_IDX 8 4216 #define regPCIEMSIX_VECT127_ADDR_HI 0x1a1fd 4217 #define regPCIEMSIX_VECT127_ADDR_HI_BASE_IDX 8 4218 #define regPCIEMSIX_VECT127_MSG_DATA 0x1a1fe 4219 #define regPCIEMSIX_VECT127_MSG_DATA_BASE_IDX 8 4220 #define regPCIEMSIX_VECT127_CONTROL 0x1a1ff 4221 #define regPCIEMSIX_VECT127_CONTROL_BASE_IDX 8 4222 #define regPCIEMSIX_VECT128_ADDR_LO 0x1a200 4223 #define regPCIEMSIX_VECT128_ADDR_LO_BASE_IDX 8 4224 #define regPCIEMSIX_VECT128_ADDR_HI 0x1a201 4225 #define regPCIEMSIX_VECT128_ADDR_HI_BASE_IDX 8 4226 #define regPCIEMSIX_VECT128_MSG_DATA 0x1a202 4227 #define regPCIEMSIX_VECT128_MSG_DATA_BASE_IDX 8 4228 #define regPCIEMSIX_VECT128_CONTROL 0x1a203 4229 #define regPCIEMSIX_VECT128_CONTROL_BASE_IDX 8 4230 #define regPCIEMSIX_VECT129_ADDR_LO 0x1a204 4231 #define regPCIEMSIX_VECT129_ADDR_LO_BASE_IDX 8 4232 #define regPCIEMSIX_VECT129_ADDR_HI 0x1a205 4233 #define regPCIEMSIX_VECT129_ADDR_HI_BASE_IDX 8 4234 #define regPCIEMSIX_VECT129_MSG_DATA 0x1a206 4235 #define regPCIEMSIX_VECT129_MSG_DATA_BASE_IDX 8 4236 #define regPCIEMSIX_VECT129_CONTROL 0x1a207 4237 #define regPCIEMSIX_VECT129_CONTROL_BASE_IDX 8 4238 #define regPCIEMSIX_VECT130_ADDR_LO 0x1a208 4239 #define regPCIEMSIX_VECT130_ADDR_LO_BASE_IDX 8 4240 #define regPCIEMSIX_VECT130_ADDR_HI 0x1a209 4241 #define regPCIEMSIX_VECT130_ADDR_HI_BASE_IDX 8 4242 #define regPCIEMSIX_VECT130_MSG_DATA 0x1a20a 4243 #define regPCIEMSIX_VECT130_MSG_DATA_BASE_IDX 8 4244 #define regPCIEMSIX_VECT130_CONTROL 0x1a20b 4245 #define regPCIEMSIX_VECT130_CONTROL_BASE_IDX 8 4246 #define regPCIEMSIX_VECT131_ADDR_LO 0x1a20c 4247 #define regPCIEMSIX_VECT131_ADDR_LO_BASE_IDX 8 4248 #define regPCIEMSIX_VECT131_ADDR_HI 0x1a20d 4249 #define regPCIEMSIX_VECT131_ADDR_HI_BASE_IDX 8 4250 #define regPCIEMSIX_VECT131_MSG_DATA 0x1a20e 4251 #define regPCIEMSIX_VECT131_MSG_DATA_BASE_IDX 8 4252 #define regPCIEMSIX_VECT131_CONTROL 0x1a20f 4253 #define regPCIEMSIX_VECT131_CONTROL_BASE_IDX 8 4254 #define regPCIEMSIX_VECT132_ADDR_LO 0x1a210 4255 #define regPCIEMSIX_VECT132_ADDR_LO_BASE_IDX 8 4256 #define regPCIEMSIX_VECT132_ADDR_HI 0x1a211 4257 #define regPCIEMSIX_VECT132_ADDR_HI_BASE_IDX 8 4258 #define regPCIEMSIX_VECT132_MSG_DATA 0x1a212 4259 #define regPCIEMSIX_VECT132_MSG_DATA_BASE_IDX 8 4260 #define regPCIEMSIX_VECT132_CONTROL 0x1a213 4261 #define regPCIEMSIX_VECT132_CONTROL_BASE_IDX 8 4262 #define regPCIEMSIX_VECT133_ADDR_LO 0x1a214 4263 #define regPCIEMSIX_VECT133_ADDR_LO_BASE_IDX 8 4264 #define regPCIEMSIX_VECT133_ADDR_HI 0x1a215 4265 #define regPCIEMSIX_VECT133_ADDR_HI_BASE_IDX 8 4266 #define regPCIEMSIX_VECT133_MSG_DATA 0x1a216 4267 #define regPCIEMSIX_VECT133_MSG_DATA_BASE_IDX 8 4268 #define regPCIEMSIX_VECT133_CONTROL 0x1a217 4269 #define regPCIEMSIX_VECT133_CONTROL_BASE_IDX 8 4270 #define regPCIEMSIX_VECT134_ADDR_LO 0x1a218 4271 #define regPCIEMSIX_VECT134_ADDR_LO_BASE_IDX 8 4272 #define regPCIEMSIX_VECT134_ADDR_HI 0x1a219 4273 #define regPCIEMSIX_VECT134_ADDR_HI_BASE_IDX 8 4274 #define regPCIEMSIX_VECT134_MSG_DATA 0x1a21a 4275 #define regPCIEMSIX_VECT134_MSG_DATA_BASE_IDX 8 4276 #define regPCIEMSIX_VECT134_CONTROL 0x1a21b 4277 #define regPCIEMSIX_VECT134_CONTROL_BASE_IDX 8 4278 #define regPCIEMSIX_VECT135_ADDR_LO 0x1a21c 4279 #define regPCIEMSIX_VECT135_ADDR_LO_BASE_IDX 8 4280 #define regPCIEMSIX_VECT135_ADDR_HI 0x1a21d 4281 #define regPCIEMSIX_VECT135_ADDR_HI_BASE_IDX 8 4282 #define regPCIEMSIX_VECT135_MSG_DATA 0x1a21e 4283 #define regPCIEMSIX_VECT135_MSG_DATA_BASE_IDX 8 4284 #define regPCIEMSIX_VECT135_CONTROL 0x1a21f 4285 #define regPCIEMSIX_VECT135_CONTROL_BASE_IDX 8 4286 #define regPCIEMSIX_VECT136_ADDR_LO 0x1a220 4287 #define regPCIEMSIX_VECT136_ADDR_LO_BASE_IDX 8 4288 #define regPCIEMSIX_VECT136_ADDR_HI 0x1a221 4289 #define regPCIEMSIX_VECT136_ADDR_HI_BASE_IDX 8 4290 #define regPCIEMSIX_VECT136_MSG_DATA 0x1a222 4291 #define regPCIEMSIX_VECT136_MSG_DATA_BASE_IDX 8 4292 #define regPCIEMSIX_VECT136_CONTROL 0x1a223 4293 #define regPCIEMSIX_VECT136_CONTROL_BASE_IDX 8 4294 #define regPCIEMSIX_VECT137_ADDR_LO 0x1a224 4295 #define regPCIEMSIX_VECT137_ADDR_LO_BASE_IDX 8 4296 #define regPCIEMSIX_VECT137_ADDR_HI 0x1a225 4297 #define regPCIEMSIX_VECT137_ADDR_HI_BASE_IDX 8 4298 #define regPCIEMSIX_VECT137_MSG_DATA 0x1a226 4299 #define regPCIEMSIX_VECT137_MSG_DATA_BASE_IDX 8 4300 #define regPCIEMSIX_VECT137_CONTROL 0x1a227 4301 #define regPCIEMSIX_VECT137_CONTROL_BASE_IDX 8 4302 #define regPCIEMSIX_VECT138_ADDR_LO 0x1a228 4303 #define regPCIEMSIX_VECT138_ADDR_LO_BASE_IDX 8 4304 #define regPCIEMSIX_VECT138_ADDR_HI 0x1a229 4305 #define regPCIEMSIX_VECT138_ADDR_HI_BASE_IDX 8 4306 #define regPCIEMSIX_VECT138_MSG_DATA 0x1a22a 4307 #define regPCIEMSIX_VECT138_MSG_DATA_BASE_IDX 8 4308 #define regPCIEMSIX_VECT138_CONTROL 0x1a22b 4309 #define regPCIEMSIX_VECT138_CONTROL_BASE_IDX 8 4310 #define regPCIEMSIX_VECT139_ADDR_LO 0x1a22c 4311 #define regPCIEMSIX_VECT139_ADDR_LO_BASE_IDX 8 4312 #define regPCIEMSIX_VECT139_ADDR_HI 0x1a22d 4313 #define regPCIEMSIX_VECT139_ADDR_HI_BASE_IDX 8 4314 #define regPCIEMSIX_VECT139_MSG_DATA 0x1a22e 4315 #define regPCIEMSIX_VECT139_MSG_DATA_BASE_IDX 8 4316 #define regPCIEMSIX_VECT139_CONTROL 0x1a22f 4317 #define regPCIEMSIX_VECT139_CONTROL_BASE_IDX 8 4318 #define regPCIEMSIX_VECT140_ADDR_LO 0x1a230 4319 #define regPCIEMSIX_VECT140_ADDR_LO_BASE_IDX 8 4320 #define regPCIEMSIX_VECT140_ADDR_HI 0x1a231 4321 #define regPCIEMSIX_VECT140_ADDR_HI_BASE_IDX 8 4322 #define regPCIEMSIX_VECT140_MSG_DATA 0x1a232 4323 #define regPCIEMSIX_VECT140_MSG_DATA_BASE_IDX 8 4324 #define regPCIEMSIX_VECT140_CONTROL 0x1a233 4325 #define regPCIEMSIX_VECT140_CONTROL_BASE_IDX 8 4326 #define regPCIEMSIX_VECT141_ADDR_LO 0x1a234 4327 #define regPCIEMSIX_VECT141_ADDR_LO_BASE_IDX 8 4328 #define regPCIEMSIX_VECT141_ADDR_HI 0x1a235 4329 #define regPCIEMSIX_VECT141_ADDR_HI_BASE_IDX 8 4330 #define regPCIEMSIX_VECT141_MSG_DATA 0x1a236 4331 #define regPCIEMSIX_VECT141_MSG_DATA_BASE_IDX 8 4332 #define regPCIEMSIX_VECT141_CONTROL 0x1a237 4333 #define regPCIEMSIX_VECT141_CONTROL_BASE_IDX 8 4334 #define regPCIEMSIX_VECT142_ADDR_LO 0x1a238 4335 #define regPCIEMSIX_VECT142_ADDR_LO_BASE_IDX 8 4336 #define regPCIEMSIX_VECT142_ADDR_HI 0x1a239 4337 #define regPCIEMSIX_VECT142_ADDR_HI_BASE_IDX 8 4338 #define regPCIEMSIX_VECT142_MSG_DATA 0x1a23a 4339 #define regPCIEMSIX_VECT142_MSG_DATA_BASE_IDX 8 4340 #define regPCIEMSIX_VECT142_CONTROL 0x1a23b 4341 #define regPCIEMSIX_VECT142_CONTROL_BASE_IDX 8 4342 #define regPCIEMSIX_VECT143_ADDR_LO 0x1a23c 4343 #define regPCIEMSIX_VECT143_ADDR_LO_BASE_IDX 8 4344 #define regPCIEMSIX_VECT143_ADDR_HI 0x1a23d 4345 #define regPCIEMSIX_VECT143_ADDR_HI_BASE_IDX 8 4346 #define regPCIEMSIX_VECT143_MSG_DATA 0x1a23e 4347 #define regPCIEMSIX_VECT143_MSG_DATA_BASE_IDX 8 4348 #define regPCIEMSIX_VECT143_CONTROL 0x1a23f 4349 #define regPCIEMSIX_VECT143_CONTROL_BASE_IDX 8 4350 #define regPCIEMSIX_VECT144_ADDR_LO 0x1a240 4351 #define regPCIEMSIX_VECT144_ADDR_LO_BASE_IDX 8 4352 #define regPCIEMSIX_VECT144_ADDR_HI 0x1a241 4353 #define regPCIEMSIX_VECT144_ADDR_HI_BASE_IDX 8 4354 #define regPCIEMSIX_VECT144_MSG_DATA 0x1a242 4355 #define regPCIEMSIX_VECT144_MSG_DATA_BASE_IDX 8 4356 #define regPCIEMSIX_VECT144_CONTROL 0x1a243 4357 #define regPCIEMSIX_VECT144_CONTROL_BASE_IDX 8 4358 #define regPCIEMSIX_VECT145_ADDR_LO 0x1a244 4359 #define regPCIEMSIX_VECT145_ADDR_LO_BASE_IDX 8 4360 #define regPCIEMSIX_VECT145_ADDR_HI 0x1a245 4361 #define regPCIEMSIX_VECT145_ADDR_HI_BASE_IDX 8 4362 #define regPCIEMSIX_VECT145_MSG_DATA 0x1a246 4363 #define regPCIEMSIX_VECT145_MSG_DATA_BASE_IDX 8 4364 #define regPCIEMSIX_VECT145_CONTROL 0x1a247 4365 #define regPCIEMSIX_VECT145_CONTROL_BASE_IDX 8 4366 #define regPCIEMSIX_VECT146_ADDR_LO 0x1a248 4367 #define regPCIEMSIX_VECT146_ADDR_LO_BASE_IDX 8 4368 #define regPCIEMSIX_VECT146_ADDR_HI 0x1a249 4369 #define regPCIEMSIX_VECT146_ADDR_HI_BASE_IDX 8 4370 #define regPCIEMSIX_VECT146_MSG_DATA 0x1a24a 4371 #define regPCIEMSIX_VECT146_MSG_DATA_BASE_IDX 8 4372 #define regPCIEMSIX_VECT146_CONTROL 0x1a24b 4373 #define regPCIEMSIX_VECT146_CONTROL_BASE_IDX 8 4374 #define regPCIEMSIX_VECT147_ADDR_LO 0x1a24c 4375 #define regPCIEMSIX_VECT147_ADDR_LO_BASE_IDX 8 4376 #define regPCIEMSIX_VECT147_ADDR_HI 0x1a24d 4377 #define regPCIEMSIX_VECT147_ADDR_HI_BASE_IDX 8 4378 #define regPCIEMSIX_VECT147_MSG_DATA 0x1a24e 4379 #define regPCIEMSIX_VECT147_MSG_DATA_BASE_IDX 8 4380 #define regPCIEMSIX_VECT147_CONTROL 0x1a24f 4381 #define regPCIEMSIX_VECT147_CONTROL_BASE_IDX 8 4382 #define regPCIEMSIX_VECT148_ADDR_LO 0x1a250 4383 #define regPCIEMSIX_VECT148_ADDR_LO_BASE_IDX 8 4384 #define regPCIEMSIX_VECT148_ADDR_HI 0x1a251 4385 #define regPCIEMSIX_VECT148_ADDR_HI_BASE_IDX 8 4386 #define regPCIEMSIX_VECT148_MSG_DATA 0x1a252 4387 #define regPCIEMSIX_VECT148_MSG_DATA_BASE_IDX 8 4388 #define regPCIEMSIX_VECT148_CONTROL 0x1a253 4389 #define regPCIEMSIX_VECT148_CONTROL_BASE_IDX 8 4390 #define regPCIEMSIX_VECT149_ADDR_LO 0x1a254 4391 #define regPCIEMSIX_VECT149_ADDR_LO_BASE_IDX 8 4392 #define regPCIEMSIX_VECT149_ADDR_HI 0x1a255 4393 #define regPCIEMSIX_VECT149_ADDR_HI_BASE_IDX 8 4394 #define regPCIEMSIX_VECT149_MSG_DATA 0x1a256 4395 #define regPCIEMSIX_VECT149_MSG_DATA_BASE_IDX 8 4396 #define regPCIEMSIX_VECT149_CONTROL 0x1a257 4397 #define regPCIEMSIX_VECT149_CONTROL_BASE_IDX 8 4398 #define regPCIEMSIX_VECT150_ADDR_LO 0x1a258 4399 #define regPCIEMSIX_VECT150_ADDR_LO_BASE_IDX 8 4400 #define regPCIEMSIX_VECT150_ADDR_HI 0x1a259 4401 #define regPCIEMSIX_VECT150_ADDR_HI_BASE_IDX 8 4402 #define regPCIEMSIX_VECT150_MSG_DATA 0x1a25a 4403 #define regPCIEMSIX_VECT150_MSG_DATA_BASE_IDX 8 4404 #define regPCIEMSIX_VECT150_CONTROL 0x1a25b 4405 #define regPCIEMSIX_VECT150_CONTROL_BASE_IDX 8 4406 #define regPCIEMSIX_VECT151_ADDR_LO 0x1a25c 4407 #define regPCIEMSIX_VECT151_ADDR_LO_BASE_IDX 8 4408 #define regPCIEMSIX_VECT151_ADDR_HI 0x1a25d 4409 #define regPCIEMSIX_VECT151_ADDR_HI_BASE_IDX 8 4410 #define regPCIEMSIX_VECT151_MSG_DATA 0x1a25e 4411 #define regPCIEMSIX_VECT151_MSG_DATA_BASE_IDX 8 4412 #define regPCIEMSIX_VECT151_CONTROL 0x1a25f 4413 #define regPCIEMSIX_VECT151_CONTROL_BASE_IDX 8 4414 #define regPCIEMSIX_VECT152_ADDR_LO 0x1a260 4415 #define regPCIEMSIX_VECT152_ADDR_LO_BASE_IDX 8 4416 #define regPCIEMSIX_VECT152_ADDR_HI 0x1a261 4417 #define regPCIEMSIX_VECT152_ADDR_HI_BASE_IDX 8 4418 #define regPCIEMSIX_VECT152_MSG_DATA 0x1a262 4419 #define regPCIEMSIX_VECT152_MSG_DATA_BASE_IDX 8 4420 #define regPCIEMSIX_VECT152_CONTROL 0x1a263 4421 #define regPCIEMSIX_VECT152_CONTROL_BASE_IDX 8 4422 #define regPCIEMSIX_VECT153_ADDR_LO 0x1a264 4423 #define regPCIEMSIX_VECT153_ADDR_LO_BASE_IDX 8 4424 #define regPCIEMSIX_VECT153_ADDR_HI 0x1a265 4425 #define regPCIEMSIX_VECT153_ADDR_HI_BASE_IDX 8 4426 #define regPCIEMSIX_VECT153_MSG_DATA 0x1a266 4427 #define regPCIEMSIX_VECT153_MSG_DATA_BASE_IDX 8 4428 #define regPCIEMSIX_VECT153_CONTROL 0x1a267 4429 #define regPCIEMSIX_VECT153_CONTROL_BASE_IDX 8 4430 #define regPCIEMSIX_VECT154_ADDR_LO 0x1a268 4431 #define regPCIEMSIX_VECT154_ADDR_LO_BASE_IDX 8 4432 #define regPCIEMSIX_VECT154_ADDR_HI 0x1a269 4433 #define regPCIEMSIX_VECT154_ADDR_HI_BASE_IDX 8 4434 #define regPCIEMSIX_VECT154_MSG_DATA 0x1a26a 4435 #define regPCIEMSIX_VECT154_MSG_DATA_BASE_IDX 8 4436 #define regPCIEMSIX_VECT154_CONTROL 0x1a26b 4437 #define regPCIEMSIX_VECT154_CONTROL_BASE_IDX 8 4438 #define regPCIEMSIX_VECT155_ADDR_LO 0x1a26c 4439 #define regPCIEMSIX_VECT155_ADDR_LO_BASE_IDX 8 4440 #define regPCIEMSIX_VECT155_ADDR_HI 0x1a26d 4441 #define regPCIEMSIX_VECT155_ADDR_HI_BASE_IDX 8 4442 #define regPCIEMSIX_VECT155_MSG_DATA 0x1a26e 4443 #define regPCIEMSIX_VECT155_MSG_DATA_BASE_IDX 8 4444 #define regPCIEMSIX_VECT155_CONTROL 0x1a26f 4445 #define regPCIEMSIX_VECT155_CONTROL_BASE_IDX 8 4446 #define regPCIEMSIX_VECT156_ADDR_LO 0x1a270 4447 #define regPCIEMSIX_VECT156_ADDR_LO_BASE_IDX 8 4448 #define regPCIEMSIX_VECT156_ADDR_HI 0x1a271 4449 #define regPCIEMSIX_VECT156_ADDR_HI_BASE_IDX 8 4450 #define regPCIEMSIX_VECT156_MSG_DATA 0x1a272 4451 #define regPCIEMSIX_VECT156_MSG_DATA_BASE_IDX 8 4452 #define regPCIEMSIX_VECT156_CONTROL 0x1a273 4453 #define regPCIEMSIX_VECT156_CONTROL_BASE_IDX 8 4454 #define regPCIEMSIX_VECT157_ADDR_LO 0x1a274 4455 #define regPCIEMSIX_VECT157_ADDR_LO_BASE_IDX 8 4456 #define regPCIEMSIX_VECT157_ADDR_HI 0x1a275 4457 #define regPCIEMSIX_VECT157_ADDR_HI_BASE_IDX 8 4458 #define regPCIEMSIX_VECT157_MSG_DATA 0x1a276 4459 #define regPCIEMSIX_VECT157_MSG_DATA_BASE_IDX 8 4460 #define regPCIEMSIX_VECT157_CONTROL 0x1a277 4461 #define regPCIEMSIX_VECT157_CONTROL_BASE_IDX 8 4462 #define regPCIEMSIX_VECT158_ADDR_LO 0x1a278 4463 #define regPCIEMSIX_VECT158_ADDR_LO_BASE_IDX 8 4464 #define regPCIEMSIX_VECT158_ADDR_HI 0x1a279 4465 #define regPCIEMSIX_VECT158_ADDR_HI_BASE_IDX 8 4466 #define regPCIEMSIX_VECT158_MSG_DATA 0x1a27a 4467 #define regPCIEMSIX_VECT158_MSG_DATA_BASE_IDX 8 4468 #define regPCIEMSIX_VECT158_CONTROL 0x1a27b 4469 #define regPCIEMSIX_VECT158_CONTROL_BASE_IDX 8 4470 #define regPCIEMSIX_VECT159_ADDR_LO 0x1a27c 4471 #define regPCIEMSIX_VECT159_ADDR_LO_BASE_IDX 8 4472 #define regPCIEMSIX_VECT159_ADDR_HI 0x1a27d 4473 #define regPCIEMSIX_VECT159_ADDR_HI_BASE_IDX 8 4474 #define regPCIEMSIX_VECT159_MSG_DATA 0x1a27e 4475 #define regPCIEMSIX_VECT159_MSG_DATA_BASE_IDX 8 4476 #define regPCIEMSIX_VECT159_CONTROL 0x1a27f 4477 #define regPCIEMSIX_VECT159_CONTROL_BASE_IDX 8 4478 #define regPCIEMSIX_VECT160_ADDR_LO 0x1a280 4479 #define regPCIEMSIX_VECT160_ADDR_LO_BASE_IDX 8 4480 #define regPCIEMSIX_VECT160_ADDR_HI 0x1a281 4481 #define regPCIEMSIX_VECT160_ADDR_HI_BASE_IDX 8 4482 #define regPCIEMSIX_VECT160_MSG_DATA 0x1a282 4483 #define regPCIEMSIX_VECT160_MSG_DATA_BASE_IDX 8 4484 #define regPCIEMSIX_VECT160_CONTROL 0x1a283 4485 #define regPCIEMSIX_VECT160_CONTROL_BASE_IDX 8 4486 #define regPCIEMSIX_VECT161_ADDR_LO 0x1a284 4487 #define regPCIEMSIX_VECT161_ADDR_LO_BASE_IDX 8 4488 #define regPCIEMSIX_VECT161_ADDR_HI 0x1a285 4489 #define regPCIEMSIX_VECT161_ADDR_HI_BASE_IDX 8 4490 #define regPCIEMSIX_VECT161_MSG_DATA 0x1a286 4491 #define regPCIEMSIX_VECT161_MSG_DATA_BASE_IDX 8 4492 #define regPCIEMSIX_VECT161_CONTROL 0x1a287 4493 #define regPCIEMSIX_VECT161_CONTROL_BASE_IDX 8 4494 #define regPCIEMSIX_VECT162_ADDR_LO 0x1a288 4495 #define regPCIEMSIX_VECT162_ADDR_LO_BASE_IDX 8 4496 #define regPCIEMSIX_VECT162_ADDR_HI 0x1a289 4497 #define regPCIEMSIX_VECT162_ADDR_HI_BASE_IDX 8 4498 #define regPCIEMSIX_VECT162_MSG_DATA 0x1a28a 4499 #define regPCIEMSIX_VECT162_MSG_DATA_BASE_IDX 8 4500 #define regPCIEMSIX_VECT162_CONTROL 0x1a28b 4501 #define regPCIEMSIX_VECT162_CONTROL_BASE_IDX 8 4502 #define regPCIEMSIX_VECT163_ADDR_LO 0x1a28c 4503 #define regPCIEMSIX_VECT163_ADDR_LO_BASE_IDX 8 4504 #define regPCIEMSIX_VECT163_ADDR_HI 0x1a28d 4505 #define regPCIEMSIX_VECT163_ADDR_HI_BASE_IDX 8 4506 #define regPCIEMSIX_VECT163_MSG_DATA 0x1a28e 4507 #define regPCIEMSIX_VECT163_MSG_DATA_BASE_IDX 8 4508 #define regPCIEMSIX_VECT163_CONTROL 0x1a28f 4509 #define regPCIEMSIX_VECT163_CONTROL_BASE_IDX 8 4510 #define regPCIEMSIX_VECT164_ADDR_LO 0x1a290 4511 #define regPCIEMSIX_VECT164_ADDR_LO_BASE_IDX 8 4512 #define regPCIEMSIX_VECT164_ADDR_HI 0x1a291 4513 #define regPCIEMSIX_VECT164_ADDR_HI_BASE_IDX 8 4514 #define regPCIEMSIX_VECT164_MSG_DATA 0x1a292 4515 #define regPCIEMSIX_VECT164_MSG_DATA_BASE_IDX 8 4516 #define regPCIEMSIX_VECT164_CONTROL 0x1a293 4517 #define regPCIEMSIX_VECT164_CONTROL_BASE_IDX 8 4518 #define regPCIEMSIX_VECT165_ADDR_LO 0x1a294 4519 #define regPCIEMSIX_VECT165_ADDR_LO_BASE_IDX 8 4520 #define regPCIEMSIX_VECT165_ADDR_HI 0x1a295 4521 #define regPCIEMSIX_VECT165_ADDR_HI_BASE_IDX 8 4522 #define regPCIEMSIX_VECT165_MSG_DATA 0x1a296 4523 #define regPCIEMSIX_VECT165_MSG_DATA_BASE_IDX 8 4524 #define regPCIEMSIX_VECT165_CONTROL 0x1a297 4525 #define regPCIEMSIX_VECT165_CONTROL_BASE_IDX 8 4526 #define regPCIEMSIX_VECT166_ADDR_LO 0x1a298 4527 #define regPCIEMSIX_VECT166_ADDR_LO_BASE_IDX 8 4528 #define regPCIEMSIX_VECT166_ADDR_HI 0x1a299 4529 #define regPCIEMSIX_VECT166_ADDR_HI_BASE_IDX 8 4530 #define regPCIEMSIX_VECT166_MSG_DATA 0x1a29a 4531 #define regPCIEMSIX_VECT166_MSG_DATA_BASE_IDX 8 4532 #define regPCIEMSIX_VECT166_CONTROL 0x1a29b 4533 #define regPCIEMSIX_VECT166_CONTROL_BASE_IDX 8 4534 #define regPCIEMSIX_VECT167_ADDR_LO 0x1a29c 4535 #define regPCIEMSIX_VECT167_ADDR_LO_BASE_IDX 8 4536 #define regPCIEMSIX_VECT167_ADDR_HI 0x1a29d 4537 #define regPCIEMSIX_VECT167_ADDR_HI_BASE_IDX 8 4538 #define regPCIEMSIX_VECT167_MSG_DATA 0x1a29e 4539 #define regPCIEMSIX_VECT167_MSG_DATA_BASE_IDX 8 4540 #define regPCIEMSIX_VECT167_CONTROL 0x1a29f 4541 #define regPCIEMSIX_VECT167_CONTROL_BASE_IDX 8 4542 #define regPCIEMSIX_VECT168_ADDR_LO 0x1a2a0 4543 #define regPCIEMSIX_VECT168_ADDR_LO_BASE_IDX 8 4544 #define regPCIEMSIX_VECT168_ADDR_HI 0x1a2a1 4545 #define regPCIEMSIX_VECT168_ADDR_HI_BASE_IDX 8 4546 #define regPCIEMSIX_VECT168_MSG_DATA 0x1a2a2 4547 #define regPCIEMSIX_VECT168_MSG_DATA_BASE_IDX 8 4548 #define regPCIEMSIX_VECT168_CONTROL 0x1a2a3 4549 #define regPCIEMSIX_VECT168_CONTROL_BASE_IDX 8 4550 #define regPCIEMSIX_VECT169_ADDR_LO 0x1a2a4 4551 #define regPCIEMSIX_VECT169_ADDR_LO_BASE_IDX 8 4552 #define regPCIEMSIX_VECT169_ADDR_HI 0x1a2a5 4553 #define regPCIEMSIX_VECT169_ADDR_HI_BASE_IDX 8 4554 #define regPCIEMSIX_VECT169_MSG_DATA 0x1a2a6 4555 #define regPCIEMSIX_VECT169_MSG_DATA_BASE_IDX 8 4556 #define regPCIEMSIX_VECT169_CONTROL 0x1a2a7 4557 #define regPCIEMSIX_VECT169_CONTROL_BASE_IDX 8 4558 #define regPCIEMSIX_VECT170_ADDR_LO 0x1a2a8 4559 #define regPCIEMSIX_VECT170_ADDR_LO_BASE_IDX 8 4560 #define regPCIEMSIX_VECT170_ADDR_HI 0x1a2a9 4561 #define regPCIEMSIX_VECT170_ADDR_HI_BASE_IDX 8 4562 #define regPCIEMSIX_VECT170_MSG_DATA 0x1a2aa 4563 #define regPCIEMSIX_VECT170_MSG_DATA_BASE_IDX 8 4564 #define regPCIEMSIX_VECT170_CONTROL 0x1a2ab 4565 #define regPCIEMSIX_VECT170_CONTROL_BASE_IDX 8 4566 #define regPCIEMSIX_VECT171_ADDR_LO 0x1a2ac 4567 #define regPCIEMSIX_VECT171_ADDR_LO_BASE_IDX 8 4568 #define regPCIEMSIX_VECT171_ADDR_HI 0x1a2ad 4569 #define regPCIEMSIX_VECT171_ADDR_HI_BASE_IDX 8 4570 #define regPCIEMSIX_VECT171_MSG_DATA 0x1a2ae 4571 #define regPCIEMSIX_VECT171_MSG_DATA_BASE_IDX 8 4572 #define regPCIEMSIX_VECT171_CONTROL 0x1a2af 4573 #define regPCIEMSIX_VECT171_CONTROL_BASE_IDX 8 4574 #define regPCIEMSIX_VECT172_ADDR_LO 0x1a2b0 4575 #define regPCIEMSIX_VECT172_ADDR_LO_BASE_IDX 8 4576 #define regPCIEMSIX_VECT172_ADDR_HI 0x1a2b1 4577 #define regPCIEMSIX_VECT172_ADDR_HI_BASE_IDX 8 4578 #define regPCIEMSIX_VECT172_MSG_DATA 0x1a2b2 4579 #define regPCIEMSIX_VECT172_MSG_DATA_BASE_IDX 8 4580 #define regPCIEMSIX_VECT172_CONTROL 0x1a2b3 4581 #define regPCIEMSIX_VECT172_CONTROL_BASE_IDX 8 4582 #define regPCIEMSIX_VECT173_ADDR_LO 0x1a2b4 4583 #define regPCIEMSIX_VECT173_ADDR_LO_BASE_IDX 8 4584 #define regPCIEMSIX_VECT173_ADDR_HI 0x1a2b5 4585 #define regPCIEMSIX_VECT173_ADDR_HI_BASE_IDX 8 4586 #define regPCIEMSIX_VECT173_MSG_DATA 0x1a2b6 4587 #define regPCIEMSIX_VECT173_MSG_DATA_BASE_IDX 8 4588 #define regPCIEMSIX_VECT173_CONTROL 0x1a2b7 4589 #define regPCIEMSIX_VECT173_CONTROL_BASE_IDX 8 4590 #define regPCIEMSIX_VECT174_ADDR_LO 0x1a2b8 4591 #define regPCIEMSIX_VECT174_ADDR_LO_BASE_IDX 8 4592 #define regPCIEMSIX_VECT174_ADDR_HI 0x1a2b9 4593 #define regPCIEMSIX_VECT174_ADDR_HI_BASE_IDX 8 4594 #define regPCIEMSIX_VECT174_MSG_DATA 0x1a2ba 4595 #define regPCIEMSIX_VECT174_MSG_DATA_BASE_IDX 8 4596 #define regPCIEMSIX_VECT174_CONTROL 0x1a2bb 4597 #define regPCIEMSIX_VECT174_CONTROL_BASE_IDX 8 4598 #define regPCIEMSIX_VECT175_ADDR_LO 0x1a2bc 4599 #define regPCIEMSIX_VECT175_ADDR_LO_BASE_IDX 8 4600 #define regPCIEMSIX_VECT175_ADDR_HI 0x1a2bd 4601 #define regPCIEMSIX_VECT175_ADDR_HI_BASE_IDX 8 4602 #define regPCIEMSIX_VECT175_MSG_DATA 0x1a2be 4603 #define regPCIEMSIX_VECT175_MSG_DATA_BASE_IDX 8 4604 #define regPCIEMSIX_VECT175_CONTROL 0x1a2bf 4605 #define regPCIEMSIX_VECT175_CONTROL_BASE_IDX 8 4606 #define regPCIEMSIX_VECT176_ADDR_LO 0x1a2c0 4607 #define regPCIEMSIX_VECT176_ADDR_LO_BASE_IDX 8 4608 #define regPCIEMSIX_VECT176_ADDR_HI 0x1a2c1 4609 #define regPCIEMSIX_VECT176_ADDR_HI_BASE_IDX 8 4610 #define regPCIEMSIX_VECT176_MSG_DATA 0x1a2c2 4611 #define regPCIEMSIX_VECT176_MSG_DATA_BASE_IDX 8 4612 #define regPCIEMSIX_VECT176_CONTROL 0x1a2c3 4613 #define regPCIEMSIX_VECT176_CONTROL_BASE_IDX 8 4614 #define regPCIEMSIX_VECT177_ADDR_LO 0x1a2c4 4615 #define regPCIEMSIX_VECT177_ADDR_LO_BASE_IDX 8 4616 #define regPCIEMSIX_VECT177_ADDR_HI 0x1a2c5 4617 #define regPCIEMSIX_VECT177_ADDR_HI_BASE_IDX 8 4618 #define regPCIEMSIX_VECT177_MSG_DATA 0x1a2c6 4619 #define regPCIEMSIX_VECT177_MSG_DATA_BASE_IDX 8 4620 #define regPCIEMSIX_VECT177_CONTROL 0x1a2c7 4621 #define regPCIEMSIX_VECT177_CONTROL_BASE_IDX 8 4622 #define regPCIEMSIX_VECT178_ADDR_LO 0x1a2c8 4623 #define regPCIEMSIX_VECT178_ADDR_LO_BASE_IDX 8 4624 #define regPCIEMSIX_VECT178_ADDR_HI 0x1a2c9 4625 #define regPCIEMSIX_VECT178_ADDR_HI_BASE_IDX 8 4626 #define regPCIEMSIX_VECT178_MSG_DATA 0x1a2ca 4627 #define regPCIEMSIX_VECT178_MSG_DATA_BASE_IDX 8 4628 #define regPCIEMSIX_VECT178_CONTROL 0x1a2cb 4629 #define regPCIEMSIX_VECT178_CONTROL_BASE_IDX 8 4630 #define regPCIEMSIX_VECT179_ADDR_LO 0x1a2cc 4631 #define regPCIEMSIX_VECT179_ADDR_LO_BASE_IDX 8 4632 #define regPCIEMSIX_VECT179_ADDR_HI 0x1a2cd 4633 #define regPCIEMSIX_VECT179_ADDR_HI_BASE_IDX 8 4634 #define regPCIEMSIX_VECT179_MSG_DATA 0x1a2ce 4635 #define regPCIEMSIX_VECT179_MSG_DATA_BASE_IDX 8 4636 #define regPCIEMSIX_VECT179_CONTROL 0x1a2cf 4637 #define regPCIEMSIX_VECT179_CONTROL_BASE_IDX 8 4638 #define regPCIEMSIX_VECT180_ADDR_LO 0x1a2d0 4639 #define regPCIEMSIX_VECT180_ADDR_LO_BASE_IDX 8 4640 #define regPCIEMSIX_VECT180_ADDR_HI 0x1a2d1 4641 #define regPCIEMSIX_VECT180_ADDR_HI_BASE_IDX 8 4642 #define regPCIEMSIX_VECT180_MSG_DATA 0x1a2d2 4643 #define regPCIEMSIX_VECT180_MSG_DATA_BASE_IDX 8 4644 #define regPCIEMSIX_VECT180_CONTROL 0x1a2d3 4645 #define regPCIEMSIX_VECT180_CONTROL_BASE_IDX 8 4646 #define regPCIEMSIX_VECT181_ADDR_LO 0x1a2d4 4647 #define regPCIEMSIX_VECT181_ADDR_LO_BASE_IDX 8 4648 #define regPCIEMSIX_VECT181_ADDR_HI 0x1a2d5 4649 #define regPCIEMSIX_VECT181_ADDR_HI_BASE_IDX 8 4650 #define regPCIEMSIX_VECT181_MSG_DATA 0x1a2d6 4651 #define regPCIEMSIX_VECT181_MSG_DATA_BASE_IDX 8 4652 #define regPCIEMSIX_VECT181_CONTROL 0x1a2d7 4653 #define regPCIEMSIX_VECT181_CONTROL_BASE_IDX 8 4654 #define regPCIEMSIX_VECT182_ADDR_LO 0x1a2d8 4655 #define regPCIEMSIX_VECT182_ADDR_LO_BASE_IDX 8 4656 #define regPCIEMSIX_VECT182_ADDR_HI 0x1a2d9 4657 #define regPCIEMSIX_VECT182_ADDR_HI_BASE_IDX 8 4658 #define regPCIEMSIX_VECT182_MSG_DATA 0x1a2da 4659 #define regPCIEMSIX_VECT182_MSG_DATA_BASE_IDX 8 4660 #define regPCIEMSIX_VECT182_CONTROL 0x1a2db 4661 #define regPCIEMSIX_VECT182_CONTROL_BASE_IDX 8 4662 #define regPCIEMSIX_VECT183_ADDR_LO 0x1a2dc 4663 #define regPCIEMSIX_VECT183_ADDR_LO_BASE_IDX 8 4664 #define regPCIEMSIX_VECT183_ADDR_HI 0x1a2dd 4665 #define regPCIEMSIX_VECT183_ADDR_HI_BASE_IDX 8 4666 #define regPCIEMSIX_VECT183_MSG_DATA 0x1a2de 4667 #define regPCIEMSIX_VECT183_MSG_DATA_BASE_IDX 8 4668 #define regPCIEMSIX_VECT183_CONTROL 0x1a2df 4669 #define regPCIEMSIX_VECT183_CONTROL_BASE_IDX 8 4670 #define regPCIEMSIX_VECT184_ADDR_LO 0x1a2e0 4671 #define regPCIEMSIX_VECT184_ADDR_LO_BASE_IDX 8 4672 #define regPCIEMSIX_VECT184_ADDR_HI 0x1a2e1 4673 #define regPCIEMSIX_VECT184_ADDR_HI_BASE_IDX 8 4674 #define regPCIEMSIX_VECT184_MSG_DATA 0x1a2e2 4675 #define regPCIEMSIX_VECT184_MSG_DATA_BASE_IDX 8 4676 #define regPCIEMSIX_VECT184_CONTROL 0x1a2e3 4677 #define regPCIEMSIX_VECT184_CONTROL_BASE_IDX 8 4678 #define regPCIEMSIX_VECT185_ADDR_LO 0x1a2e4 4679 #define regPCIEMSIX_VECT185_ADDR_LO_BASE_IDX 8 4680 #define regPCIEMSIX_VECT185_ADDR_HI 0x1a2e5 4681 #define regPCIEMSIX_VECT185_ADDR_HI_BASE_IDX 8 4682 #define regPCIEMSIX_VECT185_MSG_DATA 0x1a2e6 4683 #define regPCIEMSIX_VECT185_MSG_DATA_BASE_IDX 8 4684 #define regPCIEMSIX_VECT185_CONTROL 0x1a2e7 4685 #define regPCIEMSIX_VECT185_CONTROL_BASE_IDX 8 4686 #define regPCIEMSIX_VECT186_ADDR_LO 0x1a2e8 4687 #define regPCIEMSIX_VECT186_ADDR_LO_BASE_IDX 8 4688 #define regPCIEMSIX_VECT186_ADDR_HI 0x1a2e9 4689 #define regPCIEMSIX_VECT186_ADDR_HI_BASE_IDX 8 4690 #define regPCIEMSIX_VECT186_MSG_DATA 0x1a2ea 4691 #define regPCIEMSIX_VECT186_MSG_DATA_BASE_IDX 8 4692 #define regPCIEMSIX_VECT186_CONTROL 0x1a2eb 4693 #define regPCIEMSIX_VECT186_CONTROL_BASE_IDX 8 4694 #define regPCIEMSIX_VECT187_ADDR_LO 0x1a2ec 4695 #define regPCIEMSIX_VECT187_ADDR_LO_BASE_IDX 8 4696 #define regPCIEMSIX_VECT187_ADDR_HI 0x1a2ed 4697 #define regPCIEMSIX_VECT187_ADDR_HI_BASE_IDX 8 4698 #define regPCIEMSIX_VECT187_MSG_DATA 0x1a2ee 4699 #define regPCIEMSIX_VECT187_MSG_DATA_BASE_IDX 8 4700 #define regPCIEMSIX_VECT187_CONTROL 0x1a2ef 4701 #define regPCIEMSIX_VECT187_CONTROL_BASE_IDX 8 4702 #define regPCIEMSIX_VECT188_ADDR_LO 0x1a2f0 4703 #define regPCIEMSIX_VECT188_ADDR_LO_BASE_IDX 8 4704 #define regPCIEMSIX_VECT188_ADDR_HI 0x1a2f1 4705 #define regPCIEMSIX_VECT188_ADDR_HI_BASE_IDX 8 4706 #define regPCIEMSIX_VECT188_MSG_DATA 0x1a2f2 4707 #define regPCIEMSIX_VECT188_MSG_DATA_BASE_IDX 8 4708 #define regPCIEMSIX_VECT188_CONTROL 0x1a2f3 4709 #define regPCIEMSIX_VECT188_CONTROL_BASE_IDX 8 4710 #define regPCIEMSIX_VECT189_ADDR_LO 0x1a2f4 4711 #define regPCIEMSIX_VECT189_ADDR_LO_BASE_IDX 8 4712 #define regPCIEMSIX_VECT189_ADDR_HI 0x1a2f5 4713 #define regPCIEMSIX_VECT189_ADDR_HI_BASE_IDX 8 4714 #define regPCIEMSIX_VECT189_MSG_DATA 0x1a2f6 4715 #define regPCIEMSIX_VECT189_MSG_DATA_BASE_IDX 8 4716 #define regPCIEMSIX_VECT189_CONTROL 0x1a2f7 4717 #define regPCIEMSIX_VECT189_CONTROL_BASE_IDX 8 4718 #define regPCIEMSIX_VECT190_ADDR_LO 0x1a2f8 4719 #define regPCIEMSIX_VECT190_ADDR_LO_BASE_IDX 8 4720 #define regPCIEMSIX_VECT190_ADDR_HI 0x1a2f9 4721 #define regPCIEMSIX_VECT190_ADDR_HI_BASE_IDX 8 4722 #define regPCIEMSIX_VECT190_MSG_DATA 0x1a2fa 4723 #define regPCIEMSIX_VECT190_MSG_DATA_BASE_IDX 8 4724 #define regPCIEMSIX_VECT190_CONTROL 0x1a2fb 4725 #define regPCIEMSIX_VECT190_CONTROL_BASE_IDX 8 4726 #define regPCIEMSIX_VECT191_ADDR_LO 0x1a2fc 4727 #define regPCIEMSIX_VECT191_ADDR_LO_BASE_IDX 8 4728 #define regPCIEMSIX_VECT191_ADDR_HI 0x1a2fd 4729 #define regPCIEMSIX_VECT191_ADDR_HI_BASE_IDX 8 4730 #define regPCIEMSIX_VECT191_MSG_DATA 0x1a2fe 4731 #define regPCIEMSIX_VECT191_MSG_DATA_BASE_IDX 8 4732 #define regPCIEMSIX_VECT191_CONTROL 0x1a2ff 4733 #define regPCIEMSIX_VECT191_CONTROL_BASE_IDX 8 4734 #define regPCIEMSIX_VECT192_ADDR_LO 0x1a300 4735 #define regPCIEMSIX_VECT192_ADDR_LO_BASE_IDX 8 4736 #define regPCIEMSIX_VECT192_ADDR_HI 0x1a301 4737 #define regPCIEMSIX_VECT192_ADDR_HI_BASE_IDX 8 4738 #define regPCIEMSIX_VECT192_MSG_DATA 0x1a302 4739 #define regPCIEMSIX_VECT192_MSG_DATA_BASE_IDX 8 4740 #define regPCIEMSIX_VECT192_CONTROL 0x1a303 4741 #define regPCIEMSIX_VECT192_CONTROL_BASE_IDX 8 4742 #define regPCIEMSIX_VECT193_ADDR_LO 0x1a304 4743 #define regPCIEMSIX_VECT193_ADDR_LO_BASE_IDX 8 4744 #define regPCIEMSIX_VECT193_ADDR_HI 0x1a305 4745 #define regPCIEMSIX_VECT193_ADDR_HI_BASE_IDX 8 4746 #define regPCIEMSIX_VECT193_MSG_DATA 0x1a306 4747 #define regPCIEMSIX_VECT193_MSG_DATA_BASE_IDX 8 4748 #define regPCIEMSIX_VECT193_CONTROL 0x1a307 4749 #define regPCIEMSIX_VECT193_CONTROL_BASE_IDX 8 4750 #define regPCIEMSIX_VECT194_ADDR_LO 0x1a308 4751 #define regPCIEMSIX_VECT194_ADDR_LO_BASE_IDX 8 4752 #define regPCIEMSIX_VECT194_ADDR_HI 0x1a309 4753 #define regPCIEMSIX_VECT194_ADDR_HI_BASE_IDX 8 4754 #define regPCIEMSIX_VECT194_MSG_DATA 0x1a30a 4755 #define regPCIEMSIX_VECT194_MSG_DATA_BASE_IDX 8 4756 #define regPCIEMSIX_VECT194_CONTROL 0x1a30b 4757 #define regPCIEMSIX_VECT194_CONTROL_BASE_IDX 8 4758 #define regPCIEMSIX_VECT195_ADDR_LO 0x1a30c 4759 #define regPCIEMSIX_VECT195_ADDR_LO_BASE_IDX 8 4760 #define regPCIEMSIX_VECT195_ADDR_HI 0x1a30d 4761 #define regPCIEMSIX_VECT195_ADDR_HI_BASE_IDX 8 4762 #define regPCIEMSIX_VECT195_MSG_DATA 0x1a30e 4763 #define regPCIEMSIX_VECT195_MSG_DATA_BASE_IDX 8 4764 #define regPCIEMSIX_VECT195_CONTROL 0x1a30f 4765 #define regPCIEMSIX_VECT195_CONTROL_BASE_IDX 8 4766 #define regPCIEMSIX_VECT196_ADDR_LO 0x1a310 4767 #define regPCIEMSIX_VECT196_ADDR_LO_BASE_IDX 8 4768 #define regPCIEMSIX_VECT196_ADDR_HI 0x1a311 4769 #define regPCIEMSIX_VECT196_ADDR_HI_BASE_IDX 8 4770 #define regPCIEMSIX_VECT196_MSG_DATA 0x1a312 4771 #define regPCIEMSIX_VECT196_MSG_DATA_BASE_IDX 8 4772 #define regPCIEMSIX_VECT196_CONTROL 0x1a313 4773 #define regPCIEMSIX_VECT196_CONTROL_BASE_IDX 8 4774 #define regPCIEMSIX_VECT197_ADDR_LO 0x1a314 4775 #define regPCIEMSIX_VECT197_ADDR_LO_BASE_IDX 8 4776 #define regPCIEMSIX_VECT197_ADDR_HI 0x1a315 4777 #define regPCIEMSIX_VECT197_ADDR_HI_BASE_IDX 8 4778 #define regPCIEMSIX_VECT197_MSG_DATA 0x1a316 4779 #define regPCIEMSIX_VECT197_MSG_DATA_BASE_IDX 8 4780 #define regPCIEMSIX_VECT197_CONTROL 0x1a317 4781 #define regPCIEMSIX_VECT197_CONTROL_BASE_IDX 8 4782 #define regPCIEMSIX_VECT198_ADDR_LO 0x1a318 4783 #define regPCIEMSIX_VECT198_ADDR_LO_BASE_IDX 8 4784 #define regPCIEMSIX_VECT198_ADDR_HI 0x1a319 4785 #define regPCIEMSIX_VECT198_ADDR_HI_BASE_IDX 8 4786 #define regPCIEMSIX_VECT198_MSG_DATA 0x1a31a 4787 #define regPCIEMSIX_VECT198_MSG_DATA_BASE_IDX 8 4788 #define regPCIEMSIX_VECT198_CONTROL 0x1a31b 4789 #define regPCIEMSIX_VECT198_CONTROL_BASE_IDX 8 4790 #define regPCIEMSIX_VECT199_ADDR_LO 0x1a31c 4791 #define regPCIEMSIX_VECT199_ADDR_LO_BASE_IDX 8 4792 #define regPCIEMSIX_VECT199_ADDR_HI 0x1a31d 4793 #define regPCIEMSIX_VECT199_ADDR_HI_BASE_IDX 8 4794 #define regPCIEMSIX_VECT199_MSG_DATA 0x1a31e 4795 #define regPCIEMSIX_VECT199_MSG_DATA_BASE_IDX 8 4796 #define regPCIEMSIX_VECT199_CONTROL 0x1a31f 4797 #define regPCIEMSIX_VECT199_CONTROL_BASE_IDX 8 4798 #define regPCIEMSIX_VECT200_ADDR_LO 0x1a320 4799 #define regPCIEMSIX_VECT200_ADDR_LO_BASE_IDX 8 4800 #define regPCIEMSIX_VECT200_ADDR_HI 0x1a321 4801 #define regPCIEMSIX_VECT200_ADDR_HI_BASE_IDX 8 4802 #define regPCIEMSIX_VECT200_MSG_DATA 0x1a322 4803 #define regPCIEMSIX_VECT200_MSG_DATA_BASE_IDX 8 4804 #define regPCIEMSIX_VECT200_CONTROL 0x1a323 4805 #define regPCIEMSIX_VECT200_CONTROL_BASE_IDX 8 4806 #define regPCIEMSIX_VECT201_ADDR_LO 0x1a324 4807 #define regPCIEMSIX_VECT201_ADDR_LO_BASE_IDX 8 4808 #define regPCIEMSIX_VECT201_ADDR_HI 0x1a325 4809 #define regPCIEMSIX_VECT201_ADDR_HI_BASE_IDX 8 4810 #define regPCIEMSIX_VECT201_MSG_DATA 0x1a326 4811 #define regPCIEMSIX_VECT201_MSG_DATA_BASE_IDX 8 4812 #define regPCIEMSIX_VECT201_CONTROL 0x1a327 4813 #define regPCIEMSIX_VECT201_CONTROL_BASE_IDX 8 4814 #define regPCIEMSIX_VECT202_ADDR_LO 0x1a328 4815 #define regPCIEMSIX_VECT202_ADDR_LO_BASE_IDX 8 4816 #define regPCIEMSIX_VECT202_ADDR_HI 0x1a329 4817 #define regPCIEMSIX_VECT202_ADDR_HI_BASE_IDX 8 4818 #define regPCIEMSIX_VECT202_MSG_DATA 0x1a32a 4819 #define regPCIEMSIX_VECT202_MSG_DATA_BASE_IDX 8 4820 #define regPCIEMSIX_VECT202_CONTROL 0x1a32b 4821 #define regPCIEMSIX_VECT202_CONTROL_BASE_IDX 8 4822 #define regPCIEMSIX_VECT203_ADDR_LO 0x1a32c 4823 #define regPCIEMSIX_VECT203_ADDR_LO_BASE_IDX 8 4824 #define regPCIEMSIX_VECT203_ADDR_HI 0x1a32d 4825 #define regPCIEMSIX_VECT203_ADDR_HI_BASE_IDX 8 4826 #define regPCIEMSIX_VECT203_MSG_DATA 0x1a32e 4827 #define regPCIEMSIX_VECT203_MSG_DATA_BASE_IDX 8 4828 #define regPCIEMSIX_VECT203_CONTROL 0x1a32f 4829 #define regPCIEMSIX_VECT203_CONTROL_BASE_IDX 8 4830 #define regPCIEMSIX_VECT204_ADDR_LO 0x1a330 4831 #define regPCIEMSIX_VECT204_ADDR_LO_BASE_IDX 8 4832 #define regPCIEMSIX_VECT204_ADDR_HI 0x1a331 4833 #define regPCIEMSIX_VECT204_ADDR_HI_BASE_IDX 8 4834 #define regPCIEMSIX_VECT204_MSG_DATA 0x1a332 4835 #define regPCIEMSIX_VECT204_MSG_DATA_BASE_IDX 8 4836 #define regPCIEMSIX_VECT204_CONTROL 0x1a333 4837 #define regPCIEMSIX_VECT204_CONTROL_BASE_IDX 8 4838 #define regPCIEMSIX_VECT205_ADDR_LO 0x1a334 4839 #define regPCIEMSIX_VECT205_ADDR_LO_BASE_IDX 8 4840 #define regPCIEMSIX_VECT205_ADDR_HI 0x1a335 4841 #define regPCIEMSIX_VECT205_ADDR_HI_BASE_IDX 8 4842 #define regPCIEMSIX_VECT205_MSG_DATA 0x1a336 4843 #define regPCIEMSIX_VECT205_MSG_DATA_BASE_IDX 8 4844 #define regPCIEMSIX_VECT205_CONTROL 0x1a337 4845 #define regPCIEMSIX_VECT205_CONTROL_BASE_IDX 8 4846 #define regPCIEMSIX_VECT206_ADDR_LO 0x1a338 4847 #define regPCIEMSIX_VECT206_ADDR_LO_BASE_IDX 8 4848 #define regPCIEMSIX_VECT206_ADDR_HI 0x1a339 4849 #define regPCIEMSIX_VECT206_ADDR_HI_BASE_IDX 8 4850 #define regPCIEMSIX_VECT206_MSG_DATA 0x1a33a 4851 #define regPCIEMSIX_VECT206_MSG_DATA_BASE_IDX 8 4852 #define regPCIEMSIX_VECT206_CONTROL 0x1a33b 4853 #define regPCIEMSIX_VECT206_CONTROL_BASE_IDX 8 4854 #define regPCIEMSIX_VECT207_ADDR_LO 0x1a33c 4855 #define regPCIEMSIX_VECT207_ADDR_LO_BASE_IDX 8 4856 #define regPCIEMSIX_VECT207_ADDR_HI 0x1a33d 4857 #define regPCIEMSIX_VECT207_ADDR_HI_BASE_IDX 8 4858 #define regPCIEMSIX_VECT207_MSG_DATA 0x1a33e 4859 #define regPCIEMSIX_VECT207_MSG_DATA_BASE_IDX 8 4860 #define regPCIEMSIX_VECT207_CONTROL 0x1a33f 4861 #define regPCIEMSIX_VECT207_CONTROL_BASE_IDX 8 4862 #define regPCIEMSIX_VECT208_ADDR_LO 0x1a340 4863 #define regPCIEMSIX_VECT208_ADDR_LO_BASE_IDX 8 4864 #define regPCIEMSIX_VECT208_ADDR_HI 0x1a341 4865 #define regPCIEMSIX_VECT208_ADDR_HI_BASE_IDX 8 4866 #define regPCIEMSIX_VECT208_MSG_DATA 0x1a342 4867 #define regPCIEMSIX_VECT208_MSG_DATA_BASE_IDX 8 4868 #define regPCIEMSIX_VECT208_CONTROL 0x1a343 4869 #define regPCIEMSIX_VECT208_CONTROL_BASE_IDX 8 4870 #define regPCIEMSIX_VECT209_ADDR_LO 0x1a344 4871 #define regPCIEMSIX_VECT209_ADDR_LO_BASE_IDX 8 4872 #define regPCIEMSIX_VECT209_ADDR_HI 0x1a345 4873 #define regPCIEMSIX_VECT209_ADDR_HI_BASE_IDX 8 4874 #define regPCIEMSIX_VECT209_MSG_DATA 0x1a346 4875 #define regPCIEMSIX_VECT209_MSG_DATA_BASE_IDX 8 4876 #define regPCIEMSIX_VECT209_CONTROL 0x1a347 4877 #define regPCIEMSIX_VECT209_CONTROL_BASE_IDX 8 4878 #define regPCIEMSIX_VECT210_ADDR_LO 0x1a348 4879 #define regPCIEMSIX_VECT210_ADDR_LO_BASE_IDX 8 4880 #define regPCIEMSIX_VECT210_ADDR_HI 0x1a349 4881 #define regPCIEMSIX_VECT210_ADDR_HI_BASE_IDX 8 4882 #define regPCIEMSIX_VECT210_MSG_DATA 0x1a34a 4883 #define regPCIEMSIX_VECT210_MSG_DATA_BASE_IDX 8 4884 #define regPCIEMSIX_VECT210_CONTROL 0x1a34b 4885 #define regPCIEMSIX_VECT210_CONTROL_BASE_IDX 8 4886 #define regPCIEMSIX_VECT211_ADDR_LO 0x1a34c 4887 #define regPCIEMSIX_VECT211_ADDR_LO_BASE_IDX 8 4888 #define regPCIEMSIX_VECT211_ADDR_HI 0x1a34d 4889 #define regPCIEMSIX_VECT211_ADDR_HI_BASE_IDX 8 4890 #define regPCIEMSIX_VECT211_MSG_DATA 0x1a34e 4891 #define regPCIEMSIX_VECT211_MSG_DATA_BASE_IDX 8 4892 #define regPCIEMSIX_VECT211_CONTROL 0x1a34f 4893 #define regPCIEMSIX_VECT211_CONTROL_BASE_IDX 8 4894 #define regPCIEMSIX_VECT212_ADDR_LO 0x1a350 4895 #define regPCIEMSIX_VECT212_ADDR_LO_BASE_IDX 8 4896 #define regPCIEMSIX_VECT212_ADDR_HI 0x1a351 4897 #define regPCIEMSIX_VECT212_ADDR_HI_BASE_IDX 8 4898 #define regPCIEMSIX_VECT212_MSG_DATA 0x1a352 4899 #define regPCIEMSIX_VECT212_MSG_DATA_BASE_IDX 8 4900 #define regPCIEMSIX_VECT212_CONTROL 0x1a353 4901 #define regPCIEMSIX_VECT212_CONTROL_BASE_IDX 8 4902 #define regPCIEMSIX_VECT213_ADDR_LO 0x1a354 4903 #define regPCIEMSIX_VECT213_ADDR_LO_BASE_IDX 8 4904 #define regPCIEMSIX_VECT213_ADDR_HI 0x1a355 4905 #define regPCIEMSIX_VECT213_ADDR_HI_BASE_IDX 8 4906 #define regPCIEMSIX_VECT213_MSG_DATA 0x1a356 4907 #define regPCIEMSIX_VECT213_MSG_DATA_BASE_IDX 8 4908 #define regPCIEMSIX_VECT213_CONTROL 0x1a357 4909 #define regPCIEMSIX_VECT213_CONTROL_BASE_IDX 8 4910 #define regPCIEMSIX_VECT214_ADDR_LO 0x1a358 4911 #define regPCIEMSIX_VECT214_ADDR_LO_BASE_IDX 8 4912 #define regPCIEMSIX_VECT214_ADDR_HI 0x1a359 4913 #define regPCIEMSIX_VECT214_ADDR_HI_BASE_IDX 8 4914 #define regPCIEMSIX_VECT214_MSG_DATA 0x1a35a 4915 #define regPCIEMSIX_VECT214_MSG_DATA_BASE_IDX 8 4916 #define regPCIEMSIX_VECT214_CONTROL 0x1a35b 4917 #define regPCIEMSIX_VECT214_CONTROL_BASE_IDX 8 4918 #define regPCIEMSIX_VECT215_ADDR_LO 0x1a35c 4919 #define regPCIEMSIX_VECT215_ADDR_LO_BASE_IDX 8 4920 #define regPCIEMSIX_VECT215_ADDR_HI 0x1a35d 4921 #define regPCIEMSIX_VECT215_ADDR_HI_BASE_IDX 8 4922 #define regPCIEMSIX_VECT215_MSG_DATA 0x1a35e 4923 #define regPCIEMSIX_VECT215_MSG_DATA_BASE_IDX 8 4924 #define regPCIEMSIX_VECT215_CONTROL 0x1a35f 4925 #define regPCIEMSIX_VECT215_CONTROL_BASE_IDX 8 4926 #define regPCIEMSIX_VECT216_ADDR_LO 0x1a360 4927 #define regPCIEMSIX_VECT216_ADDR_LO_BASE_IDX 8 4928 #define regPCIEMSIX_VECT216_ADDR_HI 0x1a361 4929 #define regPCIEMSIX_VECT216_ADDR_HI_BASE_IDX 8 4930 #define regPCIEMSIX_VECT216_MSG_DATA 0x1a362 4931 #define regPCIEMSIX_VECT216_MSG_DATA_BASE_IDX 8 4932 #define regPCIEMSIX_VECT216_CONTROL 0x1a363 4933 #define regPCIEMSIX_VECT216_CONTROL_BASE_IDX 8 4934 #define regPCIEMSIX_VECT217_ADDR_LO 0x1a364 4935 #define regPCIEMSIX_VECT217_ADDR_LO_BASE_IDX 8 4936 #define regPCIEMSIX_VECT217_ADDR_HI 0x1a365 4937 #define regPCIEMSIX_VECT217_ADDR_HI_BASE_IDX 8 4938 #define regPCIEMSIX_VECT217_MSG_DATA 0x1a366 4939 #define regPCIEMSIX_VECT217_MSG_DATA_BASE_IDX 8 4940 #define regPCIEMSIX_VECT217_CONTROL 0x1a367 4941 #define regPCIEMSIX_VECT217_CONTROL_BASE_IDX 8 4942 #define regPCIEMSIX_VECT218_ADDR_LO 0x1a368 4943 #define regPCIEMSIX_VECT218_ADDR_LO_BASE_IDX 8 4944 #define regPCIEMSIX_VECT218_ADDR_HI 0x1a369 4945 #define regPCIEMSIX_VECT218_ADDR_HI_BASE_IDX 8 4946 #define regPCIEMSIX_VECT218_MSG_DATA 0x1a36a 4947 #define regPCIEMSIX_VECT218_MSG_DATA_BASE_IDX 8 4948 #define regPCIEMSIX_VECT218_CONTROL 0x1a36b 4949 #define regPCIEMSIX_VECT218_CONTROL_BASE_IDX 8 4950 #define regPCIEMSIX_VECT219_ADDR_LO 0x1a36c 4951 #define regPCIEMSIX_VECT219_ADDR_LO_BASE_IDX 8 4952 #define regPCIEMSIX_VECT219_ADDR_HI 0x1a36d 4953 #define regPCIEMSIX_VECT219_ADDR_HI_BASE_IDX 8 4954 #define regPCIEMSIX_VECT219_MSG_DATA 0x1a36e 4955 #define regPCIEMSIX_VECT219_MSG_DATA_BASE_IDX 8 4956 #define regPCIEMSIX_VECT219_CONTROL 0x1a36f 4957 #define regPCIEMSIX_VECT219_CONTROL_BASE_IDX 8 4958 #define regPCIEMSIX_VECT220_ADDR_LO 0x1a370 4959 #define regPCIEMSIX_VECT220_ADDR_LO_BASE_IDX 8 4960 #define regPCIEMSIX_VECT220_ADDR_HI 0x1a371 4961 #define regPCIEMSIX_VECT220_ADDR_HI_BASE_IDX 8 4962 #define regPCIEMSIX_VECT220_MSG_DATA 0x1a372 4963 #define regPCIEMSIX_VECT220_MSG_DATA_BASE_IDX 8 4964 #define regPCIEMSIX_VECT220_CONTROL 0x1a373 4965 #define regPCIEMSIX_VECT220_CONTROL_BASE_IDX 8 4966 #define regPCIEMSIX_VECT221_ADDR_LO 0x1a374 4967 #define regPCIEMSIX_VECT221_ADDR_LO_BASE_IDX 8 4968 #define regPCIEMSIX_VECT221_ADDR_HI 0x1a375 4969 #define regPCIEMSIX_VECT221_ADDR_HI_BASE_IDX 8 4970 #define regPCIEMSIX_VECT221_MSG_DATA 0x1a376 4971 #define regPCIEMSIX_VECT221_MSG_DATA_BASE_IDX 8 4972 #define regPCIEMSIX_VECT221_CONTROL 0x1a377 4973 #define regPCIEMSIX_VECT221_CONTROL_BASE_IDX 8 4974 #define regPCIEMSIX_VECT222_ADDR_LO 0x1a378 4975 #define regPCIEMSIX_VECT222_ADDR_LO_BASE_IDX 8 4976 #define regPCIEMSIX_VECT222_ADDR_HI 0x1a379 4977 #define regPCIEMSIX_VECT222_ADDR_HI_BASE_IDX 8 4978 #define regPCIEMSIX_VECT222_MSG_DATA 0x1a37a 4979 #define regPCIEMSIX_VECT222_MSG_DATA_BASE_IDX 8 4980 #define regPCIEMSIX_VECT222_CONTROL 0x1a37b 4981 #define regPCIEMSIX_VECT222_CONTROL_BASE_IDX 8 4982 #define regPCIEMSIX_VECT223_ADDR_LO 0x1a37c 4983 #define regPCIEMSIX_VECT223_ADDR_LO_BASE_IDX 8 4984 #define regPCIEMSIX_VECT223_ADDR_HI 0x1a37d 4985 #define regPCIEMSIX_VECT223_ADDR_HI_BASE_IDX 8 4986 #define regPCIEMSIX_VECT223_MSG_DATA 0x1a37e 4987 #define regPCIEMSIX_VECT223_MSG_DATA_BASE_IDX 8 4988 #define regPCIEMSIX_VECT223_CONTROL 0x1a37f 4989 #define regPCIEMSIX_VECT223_CONTROL_BASE_IDX 8 4990 #define regPCIEMSIX_VECT224_ADDR_LO 0x1a380 4991 #define regPCIEMSIX_VECT224_ADDR_LO_BASE_IDX 8 4992 #define regPCIEMSIX_VECT224_ADDR_HI 0x1a381 4993 #define regPCIEMSIX_VECT224_ADDR_HI_BASE_IDX 8 4994 #define regPCIEMSIX_VECT224_MSG_DATA 0x1a382 4995 #define regPCIEMSIX_VECT224_MSG_DATA_BASE_IDX 8 4996 #define regPCIEMSIX_VECT224_CONTROL 0x1a383 4997 #define regPCIEMSIX_VECT224_CONTROL_BASE_IDX 8 4998 #define regPCIEMSIX_VECT225_ADDR_LO 0x1a384 4999 #define regPCIEMSIX_VECT225_ADDR_LO_BASE_IDX 8 5000 #define regPCIEMSIX_VECT225_ADDR_HI 0x1a385 5001 #define regPCIEMSIX_VECT225_ADDR_HI_BASE_IDX 8 5002 #define regPCIEMSIX_VECT225_MSG_DATA 0x1a386 5003 #define regPCIEMSIX_VECT225_MSG_DATA_BASE_IDX 8 5004 #define regPCIEMSIX_VECT225_CONTROL 0x1a387 5005 #define regPCIEMSIX_VECT225_CONTROL_BASE_IDX 8 5006 #define regPCIEMSIX_VECT226_ADDR_LO 0x1a388 5007 #define regPCIEMSIX_VECT226_ADDR_LO_BASE_IDX 8 5008 #define regPCIEMSIX_VECT226_ADDR_HI 0x1a389 5009 #define regPCIEMSIX_VECT226_ADDR_HI_BASE_IDX 8 5010 #define regPCIEMSIX_VECT226_MSG_DATA 0x1a38a 5011 #define regPCIEMSIX_VECT226_MSG_DATA_BASE_IDX 8 5012 #define regPCIEMSIX_VECT226_CONTROL 0x1a38b 5013 #define regPCIEMSIX_VECT226_CONTROL_BASE_IDX 8 5014 #define regPCIEMSIX_VECT227_ADDR_LO 0x1a38c 5015 #define regPCIEMSIX_VECT227_ADDR_LO_BASE_IDX 8 5016 #define regPCIEMSIX_VECT227_ADDR_HI 0x1a38d 5017 #define regPCIEMSIX_VECT227_ADDR_HI_BASE_IDX 8 5018 #define regPCIEMSIX_VECT227_MSG_DATA 0x1a38e 5019 #define regPCIEMSIX_VECT227_MSG_DATA_BASE_IDX 8 5020 #define regPCIEMSIX_VECT227_CONTROL 0x1a38f 5021 #define regPCIEMSIX_VECT227_CONTROL_BASE_IDX 8 5022 #define regPCIEMSIX_VECT228_ADDR_LO 0x1a390 5023 #define regPCIEMSIX_VECT228_ADDR_LO_BASE_IDX 8 5024 #define regPCIEMSIX_VECT228_ADDR_HI 0x1a391 5025 #define regPCIEMSIX_VECT228_ADDR_HI_BASE_IDX 8 5026 #define regPCIEMSIX_VECT228_MSG_DATA 0x1a392 5027 #define regPCIEMSIX_VECT228_MSG_DATA_BASE_IDX 8 5028 #define regPCIEMSIX_VECT228_CONTROL 0x1a393 5029 #define regPCIEMSIX_VECT228_CONTROL_BASE_IDX 8 5030 #define regPCIEMSIX_VECT229_ADDR_LO 0x1a394 5031 #define regPCIEMSIX_VECT229_ADDR_LO_BASE_IDX 8 5032 #define regPCIEMSIX_VECT229_ADDR_HI 0x1a395 5033 #define regPCIEMSIX_VECT229_ADDR_HI_BASE_IDX 8 5034 #define regPCIEMSIX_VECT229_MSG_DATA 0x1a396 5035 #define regPCIEMSIX_VECT229_MSG_DATA_BASE_IDX 8 5036 #define regPCIEMSIX_VECT229_CONTROL 0x1a397 5037 #define regPCIEMSIX_VECT229_CONTROL_BASE_IDX 8 5038 #define regPCIEMSIX_VECT230_ADDR_LO 0x1a398 5039 #define regPCIEMSIX_VECT230_ADDR_LO_BASE_IDX 8 5040 #define regPCIEMSIX_VECT230_ADDR_HI 0x1a399 5041 #define regPCIEMSIX_VECT230_ADDR_HI_BASE_IDX 8 5042 #define regPCIEMSIX_VECT230_MSG_DATA 0x1a39a 5043 #define regPCIEMSIX_VECT230_MSG_DATA_BASE_IDX 8 5044 #define regPCIEMSIX_VECT230_CONTROL 0x1a39b 5045 #define regPCIEMSIX_VECT230_CONTROL_BASE_IDX 8 5046 #define regPCIEMSIX_VECT231_ADDR_LO 0x1a39c 5047 #define regPCIEMSIX_VECT231_ADDR_LO_BASE_IDX 8 5048 #define regPCIEMSIX_VECT231_ADDR_HI 0x1a39d 5049 #define regPCIEMSIX_VECT231_ADDR_HI_BASE_IDX 8 5050 #define regPCIEMSIX_VECT231_MSG_DATA 0x1a39e 5051 #define regPCIEMSIX_VECT231_MSG_DATA_BASE_IDX 8 5052 #define regPCIEMSIX_VECT231_CONTROL 0x1a39f 5053 #define regPCIEMSIX_VECT231_CONTROL_BASE_IDX 8 5054 #define regPCIEMSIX_VECT232_ADDR_LO 0x1a3a0 5055 #define regPCIEMSIX_VECT232_ADDR_LO_BASE_IDX 8 5056 #define regPCIEMSIX_VECT232_ADDR_HI 0x1a3a1 5057 #define regPCIEMSIX_VECT232_ADDR_HI_BASE_IDX 8 5058 #define regPCIEMSIX_VECT232_MSG_DATA 0x1a3a2 5059 #define regPCIEMSIX_VECT232_MSG_DATA_BASE_IDX 8 5060 #define regPCIEMSIX_VECT232_CONTROL 0x1a3a3 5061 #define regPCIEMSIX_VECT232_CONTROL_BASE_IDX 8 5062 #define regPCIEMSIX_VECT233_ADDR_LO 0x1a3a4 5063 #define regPCIEMSIX_VECT233_ADDR_LO_BASE_IDX 8 5064 #define regPCIEMSIX_VECT233_ADDR_HI 0x1a3a5 5065 #define regPCIEMSIX_VECT233_ADDR_HI_BASE_IDX 8 5066 #define regPCIEMSIX_VECT233_MSG_DATA 0x1a3a6 5067 #define regPCIEMSIX_VECT233_MSG_DATA_BASE_IDX 8 5068 #define regPCIEMSIX_VECT233_CONTROL 0x1a3a7 5069 #define regPCIEMSIX_VECT233_CONTROL_BASE_IDX 8 5070 #define regPCIEMSIX_VECT234_ADDR_LO 0x1a3a8 5071 #define regPCIEMSIX_VECT234_ADDR_LO_BASE_IDX 8 5072 #define regPCIEMSIX_VECT234_ADDR_HI 0x1a3a9 5073 #define regPCIEMSIX_VECT234_ADDR_HI_BASE_IDX 8 5074 #define regPCIEMSIX_VECT234_MSG_DATA 0x1a3aa 5075 #define regPCIEMSIX_VECT234_MSG_DATA_BASE_IDX 8 5076 #define regPCIEMSIX_VECT234_CONTROL 0x1a3ab 5077 #define regPCIEMSIX_VECT234_CONTROL_BASE_IDX 8 5078 #define regPCIEMSIX_VECT235_ADDR_LO 0x1a3ac 5079 #define regPCIEMSIX_VECT235_ADDR_LO_BASE_IDX 8 5080 #define regPCIEMSIX_VECT235_ADDR_HI 0x1a3ad 5081 #define regPCIEMSIX_VECT235_ADDR_HI_BASE_IDX 8 5082 #define regPCIEMSIX_VECT235_MSG_DATA 0x1a3ae 5083 #define regPCIEMSIX_VECT235_MSG_DATA_BASE_IDX 8 5084 #define regPCIEMSIX_VECT235_CONTROL 0x1a3af 5085 #define regPCIEMSIX_VECT235_CONTROL_BASE_IDX 8 5086 #define regPCIEMSIX_VECT236_ADDR_LO 0x1a3b0 5087 #define regPCIEMSIX_VECT236_ADDR_LO_BASE_IDX 8 5088 #define regPCIEMSIX_VECT236_ADDR_HI 0x1a3b1 5089 #define regPCIEMSIX_VECT236_ADDR_HI_BASE_IDX 8 5090 #define regPCIEMSIX_VECT236_MSG_DATA 0x1a3b2 5091 #define regPCIEMSIX_VECT236_MSG_DATA_BASE_IDX 8 5092 #define regPCIEMSIX_VECT236_CONTROL 0x1a3b3 5093 #define regPCIEMSIX_VECT236_CONTROL_BASE_IDX 8 5094 #define regPCIEMSIX_VECT237_ADDR_LO 0x1a3b4 5095 #define regPCIEMSIX_VECT237_ADDR_LO_BASE_IDX 8 5096 #define regPCIEMSIX_VECT237_ADDR_HI 0x1a3b5 5097 #define regPCIEMSIX_VECT237_ADDR_HI_BASE_IDX 8 5098 #define regPCIEMSIX_VECT237_MSG_DATA 0x1a3b6 5099 #define regPCIEMSIX_VECT237_MSG_DATA_BASE_IDX 8 5100 #define regPCIEMSIX_VECT237_CONTROL 0x1a3b7 5101 #define regPCIEMSIX_VECT237_CONTROL_BASE_IDX 8 5102 #define regPCIEMSIX_VECT238_ADDR_LO 0x1a3b8 5103 #define regPCIEMSIX_VECT238_ADDR_LO_BASE_IDX 8 5104 #define regPCIEMSIX_VECT238_ADDR_HI 0x1a3b9 5105 #define regPCIEMSIX_VECT238_ADDR_HI_BASE_IDX 8 5106 #define regPCIEMSIX_VECT238_MSG_DATA 0x1a3ba 5107 #define regPCIEMSIX_VECT238_MSG_DATA_BASE_IDX 8 5108 #define regPCIEMSIX_VECT238_CONTROL 0x1a3bb 5109 #define regPCIEMSIX_VECT238_CONTROL_BASE_IDX 8 5110 #define regPCIEMSIX_VECT239_ADDR_LO 0x1a3bc 5111 #define regPCIEMSIX_VECT239_ADDR_LO_BASE_IDX 8 5112 #define regPCIEMSIX_VECT239_ADDR_HI 0x1a3bd 5113 #define regPCIEMSIX_VECT239_ADDR_HI_BASE_IDX 8 5114 #define regPCIEMSIX_VECT239_MSG_DATA 0x1a3be 5115 #define regPCIEMSIX_VECT239_MSG_DATA_BASE_IDX 8 5116 #define regPCIEMSIX_VECT239_CONTROL 0x1a3bf 5117 #define regPCIEMSIX_VECT239_CONTROL_BASE_IDX 8 5118 #define regPCIEMSIX_VECT240_ADDR_LO 0x1a3c0 5119 #define regPCIEMSIX_VECT240_ADDR_LO_BASE_IDX 8 5120 #define regPCIEMSIX_VECT240_ADDR_HI 0x1a3c1 5121 #define regPCIEMSIX_VECT240_ADDR_HI_BASE_IDX 8 5122 #define regPCIEMSIX_VECT240_MSG_DATA 0x1a3c2 5123 #define regPCIEMSIX_VECT240_MSG_DATA_BASE_IDX 8 5124 #define regPCIEMSIX_VECT240_CONTROL 0x1a3c3 5125 #define regPCIEMSIX_VECT240_CONTROL_BASE_IDX 8 5126 #define regPCIEMSIX_VECT241_ADDR_LO 0x1a3c4 5127 #define regPCIEMSIX_VECT241_ADDR_LO_BASE_IDX 8 5128 #define regPCIEMSIX_VECT241_ADDR_HI 0x1a3c5 5129 #define regPCIEMSIX_VECT241_ADDR_HI_BASE_IDX 8 5130 #define regPCIEMSIX_VECT241_MSG_DATA 0x1a3c6 5131 #define regPCIEMSIX_VECT241_MSG_DATA_BASE_IDX 8 5132 #define regPCIEMSIX_VECT241_CONTROL 0x1a3c7 5133 #define regPCIEMSIX_VECT241_CONTROL_BASE_IDX 8 5134 #define regPCIEMSIX_VECT242_ADDR_LO 0x1a3c8 5135 #define regPCIEMSIX_VECT242_ADDR_LO_BASE_IDX 8 5136 #define regPCIEMSIX_VECT242_ADDR_HI 0x1a3c9 5137 #define regPCIEMSIX_VECT242_ADDR_HI_BASE_IDX 8 5138 #define regPCIEMSIX_VECT242_MSG_DATA 0x1a3ca 5139 #define regPCIEMSIX_VECT242_MSG_DATA_BASE_IDX 8 5140 #define regPCIEMSIX_VECT242_CONTROL 0x1a3cb 5141 #define regPCIEMSIX_VECT242_CONTROL_BASE_IDX 8 5142 #define regPCIEMSIX_VECT243_ADDR_LO 0x1a3cc 5143 #define regPCIEMSIX_VECT243_ADDR_LO_BASE_IDX 8 5144 #define regPCIEMSIX_VECT243_ADDR_HI 0x1a3cd 5145 #define regPCIEMSIX_VECT243_ADDR_HI_BASE_IDX 8 5146 #define regPCIEMSIX_VECT243_MSG_DATA 0x1a3ce 5147 #define regPCIEMSIX_VECT243_MSG_DATA_BASE_IDX 8 5148 #define regPCIEMSIX_VECT243_CONTROL 0x1a3cf 5149 #define regPCIEMSIX_VECT243_CONTROL_BASE_IDX 8 5150 #define regPCIEMSIX_VECT244_ADDR_LO 0x1a3d0 5151 #define regPCIEMSIX_VECT244_ADDR_LO_BASE_IDX 8 5152 #define regPCIEMSIX_VECT244_ADDR_HI 0x1a3d1 5153 #define regPCIEMSIX_VECT244_ADDR_HI_BASE_IDX 8 5154 #define regPCIEMSIX_VECT244_MSG_DATA 0x1a3d2 5155 #define regPCIEMSIX_VECT244_MSG_DATA_BASE_IDX 8 5156 #define regPCIEMSIX_VECT244_CONTROL 0x1a3d3 5157 #define regPCIEMSIX_VECT244_CONTROL_BASE_IDX 8 5158 #define regPCIEMSIX_VECT245_ADDR_LO 0x1a3d4 5159 #define regPCIEMSIX_VECT245_ADDR_LO_BASE_IDX 8 5160 #define regPCIEMSIX_VECT245_ADDR_HI 0x1a3d5 5161 #define regPCIEMSIX_VECT245_ADDR_HI_BASE_IDX 8 5162 #define regPCIEMSIX_VECT245_MSG_DATA 0x1a3d6 5163 #define regPCIEMSIX_VECT245_MSG_DATA_BASE_IDX 8 5164 #define regPCIEMSIX_VECT245_CONTROL 0x1a3d7 5165 #define regPCIEMSIX_VECT245_CONTROL_BASE_IDX 8 5166 #define regPCIEMSIX_VECT246_ADDR_LO 0x1a3d8 5167 #define regPCIEMSIX_VECT246_ADDR_LO_BASE_IDX 8 5168 #define regPCIEMSIX_VECT246_ADDR_HI 0x1a3d9 5169 #define regPCIEMSIX_VECT246_ADDR_HI_BASE_IDX 8 5170 #define regPCIEMSIX_VECT246_MSG_DATA 0x1a3da 5171 #define regPCIEMSIX_VECT246_MSG_DATA_BASE_IDX 8 5172 #define regPCIEMSIX_VECT246_CONTROL 0x1a3db 5173 #define regPCIEMSIX_VECT246_CONTROL_BASE_IDX 8 5174 #define regPCIEMSIX_VECT247_ADDR_LO 0x1a3dc 5175 #define regPCIEMSIX_VECT247_ADDR_LO_BASE_IDX 8 5176 #define regPCIEMSIX_VECT247_ADDR_HI 0x1a3dd 5177 #define regPCIEMSIX_VECT247_ADDR_HI_BASE_IDX 8 5178 #define regPCIEMSIX_VECT247_MSG_DATA 0x1a3de 5179 #define regPCIEMSIX_VECT247_MSG_DATA_BASE_IDX 8 5180 #define regPCIEMSIX_VECT247_CONTROL 0x1a3df 5181 #define regPCIEMSIX_VECT247_CONTROL_BASE_IDX 8 5182 #define regPCIEMSIX_VECT248_ADDR_LO 0x1a3e0 5183 #define regPCIEMSIX_VECT248_ADDR_LO_BASE_IDX 8 5184 #define regPCIEMSIX_VECT248_ADDR_HI 0x1a3e1 5185 #define regPCIEMSIX_VECT248_ADDR_HI_BASE_IDX 8 5186 #define regPCIEMSIX_VECT248_MSG_DATA 0x1a3e2 5187 #define regPCIEMSIX_VECT248_MSG_DATA_BASE_IDX 8 5188 #define regPCIEMSIX_VECT248_CONTROL 0x1a3e3 5189 #define regPCIEMSIX_VECT248_CONTROL_BASE_IDX 8 5190 #define regPCIEMSIX_VECT249_ADDR_LO 0x1a3e4 5191 #define regPCIEMSIX_VECT249_ADDR_LO_BASE_IDX 8 5192 #define regPCIEMSIX_VECT249_ADDR_HI 0x1a3e5 5193 #define regPCIEMSIX_VECT249_ADDR_HI_BASE_IDX 8 5194 #define regPCIEMSIX_VECT249_MSG_DATA 0x1a3e6 5195 #define regPCIEMSIX_VECT249_MSG_DATA_BASE_IDX 8 5196 #define regPCIEMSIX_VECT249_CONTROL 0x1a3e7 5197 #define regPCIEMSIX_VECT249_CONTROL_BASE_IDX 8 5198 #define regPCIEMSIX_VECT250_ADDR_LO 0x1a3e8 5199 #define regPCIEMSIX_VECT250_ADDR_LO_BASE_IDX 8 5200 #define regPCIEMSIX_VECT250_ADDR_HI 0x1a3e9 5201 #define regPCIEMSIX_VECT250_ADDR_HI_BASE_IDX 8 5202 #define regPCIEMSIX_VECT250_MSG_DATA 0x1a3ea 5203 #define regPCIEMSIX_VECT250_MSG_DATA_BASE_IDX 8 5204 #define regPCIEMSIX_VECT250_CONTROL 0x1a3eb 5205 #define regPCIEMSIX_VECT250_CONTROL_BASE_IDX 8 5206 #define regPCIEMSIX_VECT251_ADDR_LO 0x1a3ec 5207 #define regPCIEMSIX_VECT251_ADDR_LO_BASE_IDX 8 5208 #define regPCIEMSIX_VECT251_ADDR_HI 0x1a3ed 5209 #define regPCIEMSIX_VECT251_ADDR_HI_BASE_IDX 8 5210 #define regPCIEMSIX_VECT251_MSG_DATA 0x1a3ee 5211 #define regPCIEMSIX_VECT251_MSG_DATA_BASE_IDX 8 5212 #define regPCIEMSIX_VECT251_CONTROL 0x1a3ef 5213 #define regPCIEMSIX_VECT251_CONTROL_BASE_IDX 8 5214 #define regPCIEMSIX_VECT252_ADDR_LO 0x1a3f0 5215 #define regPCIEMSIX_VECT252_ADDR_LO_BASE_IDX 8 5216 #define regPCIEMSIX_VECT252_ADDR_HI 0x1a3f1 5217 #define regPCIEMSIX_VECT252_ADDR_HI_BASE_IDX 8 5218 #define regPCIEMSIX_VECT252_MSG_DATA 0x1a3f2 5219 #define regPCIEMSIX_VECT252_MSG_DATA_BASE_IDX 8 5220 #define regPCIEMSIX_VECT252_CONTROL 0x1a3f3 5221 #define regPCIEMSIX_VECT252_CONTROL_BASE_IDX 8 5222 #define regPCIEMSIX_VECT253_ADDR_LO 0x1a3f4 5223 #define regPCIEMSIX_VECT253_ADDR_LO_BASE_IDX 8 5224 #define regPCIEMSIX_VECT253_ADDR_HI 0x1a3f5 5225 #define regPCIEMSIX_VECT253_ADDR_HI_BASE_IDX 8 5226 #define regPCIEMSIX_VECT253_MSG_DATA 0x1a3f6 5227 #define regPCIEMSIX_VECT253_MSG_DATA_BASE_IDX 8 5228 #define regPCIEMSIX_VECT253_CONTROL 0x1a3f7 5229 #define regPCIEMSIX_VECT253_CONTROL_BASE_IDX 8 5230 #define regPCIEMSIX_VECT254_ADDR_LO 0x1a3f8 5231 #define regPCIEMSIX_VECT254_ADDR_LO_BASE_IDX 8 5232 #define regPCIEMSIX_VECT254_ADDR_HI 0x1a3f9 5233 #define regPCIEMSIX_VECT254_ADDR_HI_BASE_IDX 8 5234 #define regPCIEMSIX_VECT254_MSG_DATA 0x1a3fa 5235 #define regPCIEMSIX_VECT254_MSG_DATA_BASE_IDX 8 5236 #define regPCIEMSIX_VECT254_CONTROL 0x1a3fb 5237 #define regPCIEMSIX_VECT254_CONTROL_BASE_IDX 8 5238 #define regPCIEMSIX_VECT255_ADDR_LO 0x1a3fc 5239 #define regPCIEMSIX_VECT255_ADDR_LO_BASE_IDX 8 5240 #define regPCIEMSIX_VECT255_ADDR_HI 0x1a3fd 5241 #define regPCIEMSIX_VECT255_ADDR_HI_BASE_IDX 8 5242 #define regPCIEMSIX_VECT255_MSG_DATA 0x1a3fe 5243 #define regPCIEMSIX_VECT255_MSG_DATA_BASE_IDX 8 5244 #define regPCIEMSIX_VECT255_CONTROL 0x1a3ff 5245 #define regPCIEMSIX_VECT255_CONTROL_BASE_IDX 8 5246 5247 5248 // addressBlock: aid_nbio_nbif0_pciemsix_0_usb_MSIXPDEC 5249 // base address: 0x10169000 5250 #define regPCIEMSIX_PBA_0 0x1a400 5251 #define regPCIEMSIX_PBA_0_BASE_IDX 8 5252 #define regPCIEMSIX_PBA_1 0x1a401 5253 #define regPCIEMSIX_PBA_1_BASE_IDX 8 5254 #define regPCIEMSIX_PBA_2 0x1a402 5255 #define regPCIEMSIX_PBA_2_BASE_IDX 8 5256 #define regPCIEMSIX_PBA_3 0x1a403 5257 #define regPCIEMSIX_PBA_3_BASE_IDX 8 5258 #define regPCIEMSIX_PBA_4 0x1a404 5259 #define regPCIEMSIX_PBA_4_BASE_IDX 8 5260 #define regPCIEMSIX_PBA_5 0x1a405 5261 #define regPCIEMSIX_PBA_5_BASE_IDX 8 5262 #define regPCIEMSIX_PBA_6 0x1a406 5263 #define regPCIEMSIX_PBA_6_BASE_IDX 8 5264 #define regPCIEMSIX_PBA_7 0x1a407 5265 #define regPCIEMSIX_PBA_7_BASE_IDX 8 5266 5267 5268 // addressBlock: aid_nbio_nbif0_bif_swus_SUMDEC 5269 // base address: 0x1013b000 5270 #define regSUM_INDEX 0xec38 5271 #define regSUM_INDEX_BASE_IDX 8 5272 #define regSUM_DATA 0xec39 5273 #define regSUM_DATA_BASE_IDX 8 5274 #define regSUM_INDEX_HI 0xec3b 5275 #define regSUM_INDEX_HI_BASE_IDX 8 5276 5277 5278 // addressBlock: aid_nbio_nbif0_rcc_strap_rcc_strap_internal 5279 // base address: 0x10100000 5280 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP0 0xc400 5281 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP0_BASE_IDX 8 5282 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP1 0xc401 5283 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP1_BASE_IDX 8 5284 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP2 0xc402 5285 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP2_BASE_IDX 8 5286 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP3 0xc403 5287 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP3_BASE_IDX 8 5288 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP4 0xc404 5289 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP4_BASE_IDX 8 5290 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP5 0xc405 5291 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP5_BASE_IDX 8 5292 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP6 0xc406 5293 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP6_BASE_IDX 8 5294 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP7 0xc407 5295 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP7_BASE_IDX 8 5296 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP8 0xc408 5297 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP8_BASE_IDX 8 5298 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP9 0xc409 5299 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP9_BASE_IDX 8 5300 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP10 0xc40a 5301 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP10_BASE_IDX 8 5302 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP11 0xc40b 5303 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP11_BASE_IDX 8 5304 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP12 0xc40c 5305 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP12_BASE_IDX 8 5306 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP13 0xc40d 5307 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP13_BASE_IDX 8 5308 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP14 0xc40e 5309 #define regRCC_STRAP1_RCC_DEV0_PORT_STRAP14_BASE_IDX 8 5310 #define regRCC_DEV1_PORT_STRAP0 0xc480 5311 #define regRCC_DEV1_PORT_STRAP0_BASE_IDX 8 5312 #define regRCC_DEV1_PORT_STRAP1 0xc481 5313 #define regRCC_DEV1_PORT_STRAP1_BASE_IDX 8 5314 #define regRCC_DEV1_PORT_STRAP2 0xc482 5315 #define regRCC_DEV1_PORT_STRAP2_BASE_IDX 8 5316 #define regRCC_DEV1_PORT_STRAP3 0xc483 5317 #define regRCC_DEV1_PORT_STRAP3_BASE_IDX 8 5318 #define regRCC_DEV1_PORT_STRAP4 0xc484 5319 #define regRCC_DEV1_PORT_STRAP4_BASE_IDX 8 5320 #define regRCC_DEV1_PORT_STRAP5 0xc485 5321 #define regRCC_DEV1_PORT_STRAP5_BASE_IDX 8 5322 #define regRCC_DEV1_PORT_STRAP6 0xc486 5323 #define regRCC_DEV1_PORT_STRAP6_BASE_IDX 8 5324 #define regRCC_DEV1_PORT_STRAP7 0xc487 5325 #define regRCC_DEV1_PORT_STRAP7_BASE_IDX 8 5326 #define regRCC_DEV1_PORT_STRAP8 0xc488 5327 #define regRCC_DEV1_PORT_STRAP8_BASE_IDX 8 5328 #define regRCC_DEV1_PORT_STRAP9 0xc489 5329 #define regRCC_DEV1_PORT_STRAP9_BASE_IDX 8 5330 #define regRCC_DEV1_PORT_STRAP10 0xc48a 5331 #define regRCC_DEV1_PORT_STRAP10_BASE_IDX 8 5332 #define regRCC_DEV1_PORT_STRAP11 0xc48b 5333 #define regRCC_DEV1_PORT_STRAP11_BASE_IDX 8 5334 #define regRCC_DEV1_PORT_STRAP12 0xc48c 5335 #define regRCC_DEV1_PORT_STRAP12_BASE_IDX 8 5336 #define regRCC_DEV1_PORT_STRAP13 0xc48d 5337 #define regRCC_DEV1_PORT_STRAP13_BASE_IDX 8 5338 #define regRCC_DEV1_PORT_STRAP14 0xc48e 5339 #define regRCC_DEV1_PORT_STRAP14_BASE_IDX 8 5340 #define regRCC_DEV2_PORT_STRAP0 0xc500 5341 #define regRCC_DEV2_PORT_STRAP0_BASE_IDX 8 5342 #define regRCC_DEV2_PORT_STRAP1 0xc501 5343 #define regRCC_DEV2_PORT_STRAP1_BASE_IDX 8 5344 #define regRCC_DEV2_PORT_STRAP2 0xc502 5345 #define regRCC_DEV2_PORT_STRAP2_BASE_IDX 8 5346 #define regRCC_DEV2_PORT_STRAP3 0xc503 5347 #define regRCC_DEV2_PORT_STRAP3_BASE_IDX 8 5348 #define regRCC_DEV2_PORT_STRAP4 0xc504 5349 #define regRCC_DEV2_PORT_STRAP4_BASE_IDX 8 5350 #define regRCC_DEV2_PORT_STRAP5 0xc505 5351 #define regRCC_DEV2_PORT_STRAP5_BASE_IDX 8 5352 #define regRCC_DEV2_PORT_STRAP6 0xc506 5353 #define regRCC_DEV2_PORT_STRAP6_BASE_IDX 8 5354 #define regRCC_DEV2_PORT_STRAP7 0xc507 5355 #define regRCC_DEV2_PORT_STRAP7_BASE_IDX 8 5356 #define regRCC_DEV2_PORT_STRAP8 0xc508 5357 #define regRCC_DEV2_PORT_STRAP8_BASE_IDX 8 5358 #define regRCC_DEV2_PORT_STRAP9 0xc509 5359 #define regRCC_DEV2_PORT_STRAP9_BASE_IDX 8 5360 #define regRCC_DEV2_PORT_STRAP10 0xc50a 5361 #define regRCC_DEV2_PORT_STRAP10_BASE_IDX 8 5362 #define regRCC_DEV2_PORT_STRAP11 0xc50b 5363 #define regRCC_DEV2_PORT_STRAP11_BASE_IDX 8 5364 #define regRCC_DEV2_PORT_STRAP12 0xc50c 5365 #define regRCC_DEV2_PORT_STRAP12_BASE_IDX 8 5366 #define regRCC_DEV2_PORT_STRAP13 0xc50d 5367 #define regRCC_DEV2_PORT_STRAP13_BASE_IDX 8 5368 #define regRCC_DEV2_PORT_STRAP14 0xc50e 5369 #define regRCC_DEV2_PORT_STRAP14_BASE_IDX 8 5370 #define regRCC_STRAP1_RCC_BIF_STRAP0 0xc600 5371 #define regRCC_STRAP1_RCC_BIF_STRAP0_BASE_IDX 8 5372 #define regRCC_STRAP1_RCC_BIF_STRAP1 0xc601 5373 #define regRCC_STRAP1_RCC_BIF_STRAP1_BASE_IDX 8 5374 #define regRCC_STRAP1_RCC_BIF_STRAP2 0xc602 5375 #define regRCC_STRAP1_RCC_BIF_STRAP2_BASE_IDX 8 5376 #define regRCC_STRAP1_RCC_BIF_STRAP3 0xc603 5377 #define regRCC_STRAP1_RCC_BIF_STRAP3_BASE_IDX 8 5378 #define regRCC_STRAP1_RCC_BIF_STRAP4 0xc604 5379 #define regRCC_STRAP1_RCC_BIF_STRAP4_BASE_IDX 8 5380 #define regRCC_STRAP1_RCC_BIF_STRAP5 0xc605 5381 #define regRCC_STRAP1_RCC_BIF_STRAP5_BASE_IDX 8 5382 #define regRCC_STRAP1_RCC_BIF_STRAP6 0xc606 5383 #define regRCC_STRAP1_RCC_BIF_STRAP6_BASE_IDX 8 5384 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0 0xd000 5385 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0_BASE_IDX 8 5386 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1 0xd001 5387 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1_BASE_IDX 8 5388 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2 0xd002 5389 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2_BASE_IDX 8 5390 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3 0xd003 5391 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3_BASE_IDX 8 5392 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4 0xd004 5393 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4_BASE_IDX 8 5394 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5 0xd005 5395 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5_BASE_IDX 8 5396 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8 0xd008 5397 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8_BASE_IDX 8 5398 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9 0xd009 5399 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9_BASE_IDX 8 5400 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13 0xd00d 5401 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13_BASE_IDX 8 5402 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14 0xd00e 5403 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14_BASE_IDX 8 5404 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15 0xd00f 5405 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15_BASE_IDX 8 5406 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16 0xd010 5407 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16_BASE_IDX 8 5408 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17 0xd011 5409 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17_BASE_IDX 8 5410 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18 0xd012 5411 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18_BASE_IDX 8 5412 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP26 0xd01a 5413 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP26_BASE_IDX 8 5414 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0 0xd080 5415 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0_BASE_IDX 8 5416 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2 0xd082 5417 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2_BASE_IDX 8 5418 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3 0xd083 5419 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3_BASE_IDX 8 5420 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4 0xd084 5421 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4_BASE_IDX 8 5422 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5 0xd085 5423 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5_BASE_IDX 8 5424 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6 0xd086 5425 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6_BASE_IDX 8 5426 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7 0xd087 5427 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7_BASE_IDX 8 5428 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP20 0xd094 5429 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP20_BASE_IDX 8 5430 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP21 0xd095 5431 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP21_BASE_IDX 8 5432 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP22 0xd096 5433 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP22_BASE_IDX 8 5434 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP23 0xd097 5435 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP23_BASE_IDX 8 5436 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP24 0xd098 5437 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP24_BASE_IDX 8 5438 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP25 0xd099 5439 #define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP25_BASE_IDX 8 5440 #define regRCC_DEV0_EPF2_STRAP0 0xd100 5441 #define regRCC_DEV0_EPF2_STRAP0_BASE_IDX 8 5442 #define regRCC_DEV0_EPF2_STRAP2 0xd102 5443 #define regRCC_DEV0_EPF2_STRAP2_BASE_IDX 8 5444 #define regRCC_DEV0_EPF2_STRAP3 0xd103 5445 #define regRCC_DEV0_EPF2_STRAP3_BASE_IDX 8 5446 #define regRCC_DEV0_EPF2_STRAP4 0xd104 5447 #define regRCC_DEV0_EPF2_STRAP4_BASE_IDX 8 5448 #define regRCC_DEV0_EPF2_STRAP5 0xd105 5449 #define regRCC_DEV0_EPF2_STRAP5_BASE_IDX 8 5450 #define regRCC_DEV0_EPF2_STRAP6 0xd106 5451 #define regRCC_DEV0_EPF2_STRAP6_BASE_IDX 8 5452 #define regRCC_DEV0_EPF2_STRAP7 0xd107 5453 #define regRCC_DEV0_EPF2_STRAP7_BASE_IDX 8 5454 #define regRCC_DEV0_EPF2_STRAP10 0xd10a 5455 #define regRCC_DEV0_EPF2_STRAP10_BASE_IDX 8 5456 #define regRCC_DEV0_EPF2_STRAP11 0xd10b 5457 #define regRCC_DEV0_EPF2_STRAP11_BASE_IDX 8 5458 #define regRCC_DEV0_EPF2_STRAP12 0xd10c 5459 #define regRCC_DEV0_EPF2_STRAP12_BASE_IDX 8 5460 #define regRCC_DEV0_EPF2_STRAP13 0xd10d 5461 #define regRCC_DEV0_EPF2_STRAP13_BASE_IDX 8 5462 #define regRCC_DEV0_EPF2_STRAP14 0xd10e 5463 #define regRCC_DEV0_EPF2_STRAP14_BASE_IDX 8 5464 #define regRCC_DEV0_EPF2_STRAP20 0xd114 5465 #define regRCC_DEV0_EPF2_STRAP20_BASE_IDX 8 5466 #define regRCC_DEV0_EPF3_STRAP0 0xd180 5467 #define regRCC_DEV0_EPF3_STRAP0_BASE_IDX 8 5468 #define regRCC_DEV0_EPF3_STRAP2 0xd182 5469 #define regRCC_DEV0_EPF3_STRAP2_BASE_IDX 8 5470 #define regRCC_DEV0_EPF3_STRAP3 0xd183 5471 #define regRCC_DEV0_EPF3_STRAP3_BASE_IDX 8 5472 #define regRCC_DEV0_EPF3_STRAP4 0xd184 5473 #define regRCC_DEV0_EPF3_STRAP4_BASE_IDX 8 5474 #define regRCC_DEV0_EPF3_STRAP5 0xd185 5475 #define regRCC_DEV0_EPF3_STRAP5_BASE_IDX 8 5476 #define regRCC_DEV0_EPF3_STRAP6 0xd186 5477 #define regRCC_DEV0_EPF3_STRAP6_BASE_IDX 8 5478 #define regRCC_DEV0_EPF3_STRAP7 0xd187 5479 #define regRCC_DEV0_EPF3_STRAP7_BASE_IDX 8 5480 #define regRCC_DEV0_EPF3_STRAP10 0xd18a 5481 #define regRCC_DEV0_EPF3_STRAP10_BASE_IDX 8 5482 #define regRCC_DEV0_EPF3_STRAP11 0xd18b 5483 #define regRCC_DEV0_EPF3_STRAP11_BASE_IDX 8 5484 #define regRCC_DEV0_EPF3_STRAP12 0xd18c 5485 #define regRCC_DEV0_EPF3_STRAP12_BASE_IDX 8 5486 #define regRCC_DEV0_EPF3_STRAP13 0xd18d 5487 #define regRCC_DEV0_EPF3_STRAP13_BASE_IDX 8 5488 #define regRCC_DEV0_EPF3_STRAP14 0xd18e 5489 #define regRCC_DEV0_EPF3_STRAP14_BASE_IDX 8 5490 #define regRCC_DEV0_EPF3_STRAP20 0xd194 5491 #define regRCC_DEV0_EPF3_STRAP20_BASE_IDX 8 5492 #define regRCC_DEV0_EPF4_STRAP0 0xd200 5493 #define regRCC_DEV0_EPF4_STRAP0_BASE_IDX 8 5494 #define regRCC_DEV0_EPF4_STRAP2 0xd202 5495 #define regRCC_DEV0_EPF4_STRAP2_BASE_IDX 8 5496 #define regRCC_DEV0_EPF4_STRAP3 0xd203 5497 #define regRCC_DEV0_EPF4_STRAP3_BASE_IDX 8 5498 #define regRCC_DEV0_EPF4_STRAP4 0xd204 5499 #define regRCC_DEV0_EPF4_STRAP4_BASE_IDX 8 5500 #define regRCC_DEV0_EPF4_STRAP5 0xd205 5501 #define regRCC_DEV0_EPF4_STRAP5_BASE_IDX 8 5502 #define regRCC_DEV0_EPF4_STRAP6 0xd206 5503 #define regRCC_DEV0_EPF4_STRAP6_BASE_IDX 8 5504 #define regRCC_DEV0_EPF4_STRAP7 0xd207 5505 #define regRCC_DEV0_EPF4_STRAP7_BASE_IDX 8 5506 #define regRCC_DEV0_EPF4_STRAP13 0xd20d 5507 #define regRCC_DEV0_EPF4_STRAP13_BASE_IDX 8 5508 #define regRCC_DEV0_EPF4_STRAP14 0xd20e 5509 #define regRCC_DEV0_EPF4_STRAP14_BASE_IDX 8 5510 #define regRCC_DEV0_EPF5_STRAP0 0xd280 5511 #define regRCC_DEV0_EPF5_STRAP0_BASE_IDX 8 5512 #define regRCC_DEV0_EPF5_STRAP2 0xd282 5513 #define regRCC_DEV0_EPF5_STRAP2_BASE_IDX 8 5514 #define regRCC_DEV0_EPF5_STRAP3 0xd283 5515 #define regRCC_DEV0_EPF5_STRAP3_BASE_IDX 8 5516 #define regRCC_DEV0_EPF5_STRAP4 0xd284 5517 #define regRCC_DEV0_EPF5_STRAP4_BASE_IDX 8 5518 #define regRCC_DEV0_EPF5_STRAP5 0xd285 5519 #define regRCC_DEV0_EPF5_STRAP5_BASE_IDX 8 5520 #define regRCC_DEV0_EPF5_STRAP6 0xd286 5521 #define regRCC_DEV0_EPF5_STRAP6_BASE_IDX 8 5522 #define regRCC_DEV0_EPF5_STRAP7 0xd287 5523 #define regRCC_DEV0_EPF5_STRAP7_BASE_IDX 8 5524 #define regRCC_DEV0_EPF5_STRAP13 0xd28d 5525 #define regRCC_DEV0_EPF5_STRAP13_BASE_IDX 8 5526 #define regRCC_DEV0_EPF5_STRAP14 0xd28e 5527 #define regRCC_DEV0_EPF5_STRAP14_BASE_IDX 8 5528 #define regRCC_DEV0_EPF6_STRAP0 0xd300 5529 #define regRCC_DEV0_EPF6_STRAP0_BASE_IDX 8 5530 #define regRCC_DEV0_EPF6_STRAP2 0xd302 5531 #define regRCC_DEV0_EPF6_STRAP2_BASE_IDX 8 5532 #define regRCC_DEV0_EPF6_STRAP3 0xd303 5533 #define regRCC_DEV0_EPF6_STRAP3_BASE_IDX 8 5534 #define regRCC_DEV0_EPF6_STRAP4 0xd304 5535 #define regRCC_DEV0_EPF6_STRAP4_BASE_IDX 8 5536 #define regRCC_DEV0_EPF6_STRAP5 0xd305 5537 #define regRCC_DEV0_EPF6_STRAP5_BASE_IDX 8 5538 #define regRCC_DEV0_EPF6_STRAP6 0xd306 5539 #define regRCC_DEV0_EPF6_STRAP6_BASE_IDX 8 5540 #define regRCC_DEV0_EPF6_STRAP13 0xd30d 5541 #define regRCC_DEV0_EPF6_STRAP13_BASE_IDX 8 5542 #define regRCC_DEV0_EPF6_STRAP14 0xd30e 5543 #define regRCC_DEV0_EPF6_STRAP14_BASE_IDX 8 5544 #define regRCC_DEV0_EPF7_STRAP0 0xd380 5545 #define regRCC_DEV0_EPF7_STRAP0_BASE_IDX 8 5546 #define regRCC_DEV0_EPF7_STRAP2 0xd382 5547 #define regRCC_DEV0_EPF7_STRAP2_BASE_IDX 8 5548 #define regRCC_DEV0_EPF7_STRAP3 0xd383 5549 #define regRCC_DEV0_EPF7_STRAP3_BASE_IDX 8 5550 #define regRCC_DEV0_EPF7_STRAP4 0xd384 5551 #define regRCC_DEV0_EPF7_STRAP4_BASE_IDX 8 5552 #define regRCC_DEV0_EPF7_STRAP5 0xd385 5553 #define regRCC_DEV0_EPF7_STRAP5_BASE_IDX 8 5554 #define regRCC_DEV0_EPF7_STRAP6 0xd386 5555 #define regRCC_DEV0_EPF7_STRAP6_BASE_IDX 8 5556 #define regRCC_DEV0_EPF7_STRAP7 0xd387 5557 #define regRCC_DEV0_EPF7_STRAP7_BASE_IDX 8 5558 #define regRCC_DEV0_EPF7_STRAP13 0xd38d 5559 #define regRCC_DEV0_EPF7_STRAP13_BASE_IDX 8 5560 #define regRCC_DEV0_EPF7_STRAP14 0xd38e 5561 #define regRCC_DEV0_EPF7_STRAP14_BASE_IDX 8 5562 #define regRCC_DEV1_EPF0_STRAP0 0xd400 5563 #define regRCC_DEV1_EPF0_STRAP0_BASE_IDX 8 5564 #define regRCC_DEV1_EPF0_STRAP2 0xd402 5565 #define regRCC_DEV1_EPF0_STRAP2_BASE_IDX 8 5566 #define regRCC_DEV1_EPF0_STRAP3 0xd403 5567 #define regRCC_DEV1_EPF0_STRAP3_BASE_IDX 8 5568 #define regRCC_DEV1_EPF0_STRAP4 0xd404 5569 #define regRCC_DEV1_EPF0_STRAP4_BASE_IDX 8 5570 #define regRCC_DEV1_EPF0_STRAP5 0xd405 5571 #define regRCC_DEV1_EPF0_STRAP5_BASE_IDX 8 5572 #define regRCC_DEV1_EPF0_STRAP6 0xd406 5573 #define regRCC_DEV1_EPF0_STRAP6_BASE_IDX 8 5574 #define regRCC_DEV1_EPF0_STRAP7 0xd407 5575 #define regRCC_DEV1_EPF0_STRAP7_BASE_IDX 8 5576 #define regRCC_DEV1_EPF0_STRAP13 0xd40d 5577 #define regRCC_DEV1_EPF0_STRAP13_BASE_IDX 8 5578 #define regRCC_DEV1_EPF0_STRAP14 0xd40e 5579 #define regRCC_DEV1_EPF0_STRAP14_BASE_IDX 8 5580 #define regRCC_DEV1_EPF1_STRAP0 0xd480 5581 #define regRCC_DEV1_EPF1_STRAP0_BASE_IDX 8 5582 #define regRCC_DEV1_EPF1_STRAP2 0xd482 5583 #define regRCC_DEV1_EPF1_STRAP2_BASE_IDX 8 5584 #define regRCC_DEV1_EPF1_STRAP3 0xd483 5585 #define regRCC_DEV1_EPF1_STRAP3_BASE_IDX 8 5586 #define regRCC_DEV1_EPF1_STRAP4 0xd484 5587 #define regRCC_DEV1_EPF1_STRAP4_BASE_IDX 8 5588 #define regRCC_DEV1_EPF1_STRAP5 0xd485 5589 #define regRCC_DEV1_EPF1_STRAP5_BASE_IDX 8 5590 #define regRCC_DEV1_EPF1_STRAP6 0xd486 5591 #define regRCC_DEV1_EPF1_STRAP6_BASE_IDX 8 5592 #define regRCC_DEV1_EPF1_STRAP7 0xd487 5593 #define regRCC_DEV1_EPF1_STRAP7_BASE_IDX 8 5594 #define regRCC_DEV1_EPF1_STRAP13 0xd48d 5595 #define regRCC_DEV1_EPF1_STRAP13_BASE_IDX 8 5596 #define regRCC_DEV1_EPF1_STRAP14 0xd48e 5597 #define regRCC_DEV1_EPF1_STRAP14_BASE_IDX 8 5598 #define regRCC_DEV2_EPF0_STRAP0 0xd800 5599 #define regRCC_DEV2_EPF0_STRAP0_BASE_IDX 8 5600 #define regRCC_DEV2_EPF0_STRAP2 0xd802 5601 #define regRCC_DEV2_EPF0_STRAP2_BASE_IDX 8 5602 #define regRCC_DEV2_EPF0_STRAP3 0xd803 5603 #define regRCC_DEV2_EPF0_STRAP3_BASE_IDX 8 5604 #define regRCC_DEV2_EPF0_STRAP4 0xd804 5605 #define regRCC_DEV2_EPF0_STRAP4_BASE_IDX 8 5606 #define regRCC_DEV2_EPF0_STRAP5 0xd805 5607 #define regRCC_DEV2_EPF0_STRAP5_BASE_IDX 8 5608 #define regRCC_DEV2_EPF0_STRAP6 0xd806 5609 #define regRCC_DEV2_EPF0_STRAP6_BASE_IDX 8 5610 #define regRCC_DEV2_EPF0_STRAP7 0xd807 5611 #define regRCC_DEV2_EPF0_STRAP7_BASE_IDX 8 5612 #define regRCC_DEV2_EPF0_STRAP13 0xd80d 5613 #define regRCC_DEV2_EPF0_STRAP13_BASE_IDX 8 5614 #define regRCC_DEV2_EPF0_STRAP14 0xd80e 5615 #define regRCC_DEV2_EPF0_STRAP14_BASE_IDX 8 5616 #define regRCC_DEV2_EPF1_STRAP0 0xd880 5617 #define regRCC_DEV2_EPF1_STRAP0_BASE_IDX 8 5618 #define regRCC_DEV2_EPF1_STRAP2 0xd882 5619 #define regRCC_DEV2_EPF1_STRAP2_BASE_IDX 8 5620 #define regRCC_DEV2_EPF1_STRAP3 0xd883 5621 #define regRCC_DEV2_EPF1_STRAP3_BASE_IDX 8 5622 #define regRCC_DEV2_EPF1_STRAP4 0xd884 5623 #define regRCC_DEV2_EPF1_STRAP4_BASE_IDX 8 5624 #define regRCC_DEV2_EPF1_STRAP5 0xd885 5625 #define regRCC_DEV2_EPF1_STRAP5_BASE_IDX 8 5626 #define regRCC_DEV2_EPF1_STRAP6 0xd886 5627 #define regRCC_DEV2_EPF1_STRAP6_BASE_IDX 8 5628 #define regRCC_DEV2_EPF1_STRAP13 0xd88d 5629 #define regRCC_DEV2_EPF1_STRAP13_BASE_IDX 8 5630 #define regRCC_DEV2_EPF1_STRAP14 0xd88e 5631 #define regRCC_DEV2_EPF1_STRAP14_BASE_IDX 8 5632 #define regRCC_DEV2_EPF2_STRAP0 0xd900 5633 #define regRCC_DEV2_EPF2_STRAP0_BASE_IDX 8 5634 #define regRCC_DEV2_EPF2_STRAP2 0xd902 5635 #define regRCC_DEV2_EPF2_STRAP2_BASE_IDX 8 5636 #define regRCC_DEV2_EPF2_STRAP3 0xd903 5637 #define regRCC_DEV2_EPF2_STRAP3_BASE_IDX 8 5638 #define regRCC_DEV2_EPF2_STRAP4 0xd904 5639 #define regRCC_DEV2_EPF2_STRAP4_BASE_IDX 8 5640 #define regRCC_DEV2_EPF2_STRAP5 0xd905 5641 #define regRCC_DEV2_EPF2_STRAP5_BASE_IDX 8 5642 #define regRCC_DEV2_EPF2_STRAP6 0xd906 5643 #define regRCC_DEV2_EPF2_STRAP6_BASE_IDX 8 5644 #define regRCC_DEV2_EPF2_STRAP13 0xd90d 5645 #define regRCC_DEV2_EPF2_STRAP13_BASE_IDX 8 5646 #define regRCC_DEV2_EPF2_STRAP14 0xd90e 5647 #define regRCC_DEV2_EPF2_STRAP14_BASE_IDX 8 5648 5649 5650 // addressBlock: aid_nbio_nbif0_bif_rst_bif_rst_regblk 5651 // base address: 0x10100000 5652 #define regHARD_RST_CTRL 0xe000 5653 #define regHARD_RST_CTRL_BASE_IDX 8 5654 #define regSELF_SOFT_RST 0xe002 5655 #define regSELF_SOFT_RST_BASE_IDX 8 5656 #define regBIF_GFX_DRV_VPU_RST 0xe003 5657 #define regBIF_GFX_DRV_VPU_RST_BASE_IDX 8 5658 #define regBIF_RST_MISC_CTRL 0xe004 5659 #define regBIF_RST_MISC_CTRL_BASE_IDX 8 5660 #define regBIF_RST_MISC_CTRL2 0xe005 5661 #define regBIF_RST_MISC_CTRL2_BASE_IDX 8 5662 #define regBIF_RST_MISC_CTRL3 0xe006 5663 #define regBIF_RST_MISC_CTRL3_BASE_IDX 8 5664 #define regDEV0_PF0_FLR_RST_CTRL 0xe008 5665 #define regDEV0_PF0_FLR_RST_CTRL_BASE_IDX 8 5666 #define regDEV0_PF1_FLR_RST_CTRL 0xe009 5667 #define regDEV0_PF1_FLR_RST_CTRL_BASE_IDX 8 5668 #define regBIF_INST_RESET_INTR_STS 0xe010 5669 #define regBIF_INST_RESET_INTR_STS_BASE_IDX 8 5670 #define regBIF_PF_FLR_INTR_STS 0xe011 5671 #define regBIF_PF_FLR_INTR_STS_BASE_IDX 8 5672 #define regBIF_D3HOTD0_INTR_STS 0xe012 5673 #define regBIF_D3HOTD0_INTR_STS_BASE_IDX 8 5674 #define regBIF_POWER_INTR_STS 0xe014 5675 #define regBIF_POWER_INTR_STS_BASE_IDX 8 5676 #define regBIF_PF_DSTATE_INTR_STS 0xe015 5677 #define regBIF_PF_DSTATE_INTR_STS_BASE_IDX 8 5678 #define regSELF_SOFT_RST_2 0xe016 5679 #define regSELF_SOFT_RST_2_BASE_IDX 8 5680 #define regBIF_INST_RESET_INTR_MASK 0xe020 5681 #define regBIF_INST_RESET_INTR_MASK_BASE_IDX 8 5682 #define regBIF_PF_FLR_INTR_MASK 0xe021 5683 #define regBIF_PF_FLR_INTR_MASK_BASE_IDX 8 5684 #define regBIF_D3HOTD0_INTR_MASK 0xe022 5685 #define regBIF_D3HOTD0_INTR_MASK_BASE_IDX 8 5686 #define regBIF_POWER_INTR_MASK 0xe024 5687 #define regBIF_POWER_INTR_MASK_BASE_IDX 8 5688 #define regBIF_PF_DSTATE_INTR_MASK 0xe025 5689 #define regBIF_PF_DSTATE_INTR_MASK_BASE_IDX 8 5690 #define regBIF_PF_FLR_RST 0xe040 5691 #define regBIF_PF_FLR_RST_BASE_IDX 8 5692 #define regBIF_DEV0_PF0_DSTATE_VALUE 0xe050 5693 #define regBIF_DEV0_PF0_DSTATE_VALUE_BASE_IDX 8 5694 #define regBIF_DEV0_PF1_DSTATE_VALUE 0xe051 5695 #define regBIF_DEV0_PF1_DSTATE_VALUE_BASE_IDX 8 5696 #define regDEV0_PF0_D3HOTD0_RST_CTRL 0xe078 5697 #define regDEV0_PF0_D3HOTD0_RST_CTRL_BASE_IDX 8 5698 #define regDEV0_PF1_D3HOTD0_RST_CTRL 0xe079 5699 #define regDEV0_PF1_D3HOTD0_RST_CTRL_BASE_IDX 8 5700 #define regBIF_PORT0_DSTATE_VALUE 0xe230 5701 #define regBIF_PORT0_DSTATE_VALUE_BASE_IDX 8 5702 5703 5704 // addressBlock: aid_nbio_nbif0_bif_misc_bif_misc_regblk 5705 // base address: 0x10100000 5706 #define regREGS_ROM_OFFSET_CTRL 0xcc23 5707 #define regREGS_ROM_OFFSET_CTRL_BASE_IDX 8 5708 #define regNBIF_STRAP_BIOS_CNTL 0xcc81 5709 #define regNBIF_STRAP_BIOS_CNTL_BASE_IDX 8 5710 #define regDOORBELL0_CTRL_ENTRY_0 0xcd00 5711 #define regDOORBELL0_CTRL_ENTRY_0_BASE_IDX 8 5712 #define regDOORBELL0_CTRL_ENTRY_1 0xcd01 5713 #define regDOORBELL0_CTRL_ENTRY_1_BASE_IDX 8 5714 #define regDOORBELL0_CTRL_ENTRY_2 0xcd02 5715 #define regDOORBELL0_CTRL_ENTRY_2_BASE_IDX 8 5716 #define regDOORBELL0_CTRL_ENTRY_3 0xcd03 5717 #define regDOORBELL0_CTRL_ENTRY_3_BASE_IDX 8 5718 #define regDOORBELL0_CTRL_ENTRY_4 0xcd04 5719 #define regDOORBELL0_CTRL_ENTRY_4_BASE_IDX 8 5720 #define regDOORBELL0_CTRL_ENTRY_5 0xcd05 5721 #define regDOORBELL0_CTRL_ENTRY_5_BASE_IDX 8 5722 #define regDOORBELL0_CTRL_ENTRY_6 0xcd06 5723 #define regDOORBELL0_CTRL_ENTRY_6_BASE_IDX 8 5724 #define regDOORBELL0_CTRL_ENTRY_7 0xcd07 5725 #define regDOORBELL0_CTRL_ENTRY_7_BASE_IDX 8 5726 #define regDOORBELL0_CTRL_ENTRY_8 0xcd08 5727 #define regDOORBELL0_CTRL_ENTRY_8_BASE_IDX 8 5728 #define regDOORBELL0_CTRL_ENTRY_9 0xcd09 5729 #define regDOORBELL0_CTRL_ENTRY_9_BASE_IDX 8 5730 #define regDOORBELL0_CTRL_ENTRY_10 0xcd0a 5731 #define regDOORBELL0_CTRL_ENTRY_10_BASE_IDX 8 5732 #define regDOORBELL0_CTRL_ENTRY_11 0xcd0b 5733 #define regDOORBELL0_CTRL_ENTRY_11_BASE_IDX 8 5734 #define regDOORBELL0_CTRL_ENTRY_12 0xcd0c 5735 #define regDOORBELL0_CTRL_ENTRY_12_BASE_IDX 8 5736 #define regDOORBELL0_CTRL_ENTRY_13 0xcd0d 5737 #define regDOORBELL0_CTRL_ENTRY_13_BASE_IDX 8 5738 #define regDOORBELL0_CTRL_ENTRY_14 0xcd0e 5739 #define regDOORBELL0_CTRL_ENTRY_14_BASE_IDX 8 5740 #define regDOORBELL0_CTRL_ENTRY_15 0xcd0f 5741 #define regDOORBELL0_CTRL_ENTRY_15_BASE_IDX 8 5742 #define regDOORBELL0_CTRL_ENTRY_16 0xcd10 5743 #define regDOORBELL0_CTRL_ENTRY_16_BASE_IDX 8 5744 #define regDOORBELL0_CTRL_ENTRY_17 0xcd11 5745 #define regDOORBELL0_CTRL_ENTRY_17_BASE_IDX 8 5746 #define regDOORBELL0_CTRL_ENTRY_18 0xcd12 5747 #define regDOORBELL0_CTRL_ENTRY_18_BASE_IDX 8 5748 #define regDOORBELL0_CTRL_ENTRY_19 0xcd13 5749 #define regDOORBELL0_CTRL_ENTRY_19_BASE_IDX 8 5750 #define regDOORBELL0_CTRL_ENTRY_20 0xcd14 5751 #define regDOORBELL0_CTRL_ENTRY_20_BASE_IDX 8 5752 #define regAID0_VF0_BASE_ADDR 0xcd40 5753 #define regAID0_VF0_BASE_ADDR_BASE_IDX 8 5754 #define regAID1_VF0_BASE_ADDR 0xcd41 5755 #define regAID1_VF0_BASE_ADDR_BASE_IDX 8 5756 #define regAID2_VF0_BASE_ADDR 0xcd42 5757 #define regAID2_VF0_BASE_ADDR_BASE_IDX 8 5758 #define regAID3_VF0_BASE_ADDR 0xcd43 5759 #define regAID3_VF0_BASE_ADDR_BASE_IDX 8 5760 #define regAID0_XCC0_VF0_BASE_ADDR 0xcd44 5761 #define regAID0_XCC0_VF0_BASE_ADDR_BASE_IDX 8 5762 #define regAID0_XCC1_VF0_BASE_ADDR 0xcd45 5763 #define regAID0_XCC1_VF0_BASE_ADDR_BASE_IDX 8 5764 #define regAID1_XCC0_VF0_BASE_ADDR 0xcd46 5765 #define regAID1_XCC0_VF0_BASE_ADDR_BASE_IDX 8 5766 #define regAID1_XCC1_VF0_BASE_ADDR 0xcd47 5767 #define regAID1_XCC1_VF0_BASE_ADDR_BASE_IDX 8 5768 #define regAID2_XCC0_VF0_BASE_ADDR 0xcd48 5769 #define regAID2_XCC0_VF0_BASE_ADDR_BASE_IDX 8 5770 #define regAID2_XCC1_VF0_BASE_ADDR 0xcd49 5771 #define regAID2_XCC1_VF0_BASE_ADDR_BASE_IDX 8 5772 #define regAID3_XCC0_VF0_BASE_ADDR 0xcd4a 5773 #define regAID3_XCC0_VF0_BASE_ADDR_BASE_IDX 8 5774 #define regAID3_XCC1_VF0_BASE_ADDR 0xcd4b 5775 #define regAID3_XCC1_VF0_BASE_ADDR_BASE_IDX 8 5776 #define regAID0_NBIF_VF0_BASE_ADDR 0xcd4c 5777 #define regAID0_NBIF_VF0_BASE_ADDR_BASE_IDX 8 5778 #define regAID0_ATHUB_VF0_BASE_ADDR 0xcd4d 5779 #define regAID0_ATHUB_VF0_BASE_ADDR_BASE_IDX 8 5780 #define regAID0_IH_VF0_BASE_ADDR 0xcd4e 5781 #define regAID0_IH_VF0_BASE_ADDR_BASE_IDX 8 5782 #define regAID0_HDP_VF0_BASE_ADDR 0xcd4f 5783 #define regAID0_HDP_VF0_BASE_ADDR_BASE_IDX 8 5784 #define regAID0_VF1_BASE_ADDR 0xcd50 5785 #define regAID0_VF1_BASE_ADDR_BASE_IDX 8 5786 #define regAID1_VF1_BASE_ADDR 0xcd51 5787 #define regAID1_VF1_BASE_ADDR_BASE_IDX 8 5788 #define regAID2_VF1_BASE_ADDR 0xcd52 5789 #define regAID2_VF1_BASE_ADDR_BASE_IDX 8 5790 #define regAID3_VF1_BASE_ADDR 0xcd53 5791 #define regAID3_VF1_BASE_ADDR_BASE_IDX 8 5792 #define regAID0_XCC0_VF1_BASE_ADDR 0xcd54 5793 #define regAID0_XCC0_VF1_BASE_ADDR_BASE_IDX 8 5794 #define regAID0_XCC1_VF1_BASE_ADDR 0xcd55 5795 #define regAID0_XCC1_VF1_BASE_ADDR_BASE_IDX 8 5796 #define regAID1_XCC0_VF1_BASE_ADDR 0xcd56 5797 #define regAID1_XCC0_VF1_BASE_ADDR_BASE_IDX 8 5798 #define regAID1_XCC1_VF1_BASE_ADDR 0xcd57 5799 #define regAID1_XCC1_VF1_BASE_ADDR_BASE_IDX 8 5800 #define regAID2_XCC0_VF1_BASE_ADDR 0xcd58 5801 #define regAID2_XCC0_VF1_BASE_ADDR_BASE_IDX 8 5802 #define regAID2_XCC1_VF1_BASE_ADDR 0xcd59 5803 #define regAID2_XCC1_VF1_BASE_ADDR_BASE_IDX 8 5804 #define regAID3_XCC0_VF1_BASE_ADDR 0xcd5a 5805 #define regAID3_XCC0_VF1_BASE_ADDR_BASE_IDX 8 5806 #define regAID3_XCC1_VF1_BASE_ADDR 0xcd5b 5807 #define regAID3_XCC1_VF1_BASE_ADDR_BASE_IDX 8 5808 #define regAID0_NBIF_VF1_BASE_ADDR 0xcd5c 5809 #define regAID0_NBIF_VF1_BASE_ADDR_BASE_IDX 8 5810 #define regAID0_ATHUB_VF1_BASE_ADDR 0xcd5d 5811 #define regAID0_ATHUB_VF1_BASE_ADDR_BASE_IDX 8 5812 #define regAID0_IH_VF1_BASE_ADDR 0xcd5e 5813 #define regAID0_IH_VF1_BASE_ADDR_BASE_IDX 8 5814 #define regAID0_HDP_VF1_BASE_ADDR 0xcd5f 5815 #define regAID0_HDP_VF1_BASE_ADDR_BASE_IDX 8 5816 #define regAID0_VF2_BASE_ADDR 0xcd60 5817 #define regAID0_VF2_BASE_ADDR_BASE_IDX 8 5818 #define regAID1_VF2_BASE_ADDR 0xcd61 5819 #define regAID1_VF2_BASE_ADDR_BASE_IDX 8 5820 #define regAID2_VF2_BASE_ADDR 0xcd62 5821 #define regAID2_VF2_BASE_ADDR_BASE_IDX 8 5822 #define regAID3_VF2_BASE_ADDR 0xcd63 5823 #define regAID3_VF2_BASE_ADDR_BASE_IDX 8 5824 #define regAID0_XCC0_VF2_BASE_ADDR 0xcd64 5825 #define regAID0_XCC0_VF2_BASE_ADDR_BASE_IDX 8 5826 #define regAID0_XCC1_VF2_BASE_ADDR 0xcd65 5827 #define regAID0_XCC1_VF2_BASE_ADDR_BASE_IDX 8 5828 #define regAID1_XCC0_VF2_BASE_ADDR 0xcd66 5829 #define regAID1_XCC0_VF2_BASE_ADDR_BASE_IDX 8 5830 #define regAID1_XCC1_VF2_BASE_ADDR 0xcd67 5831 #define regAID1_XCC1_VF2_BASE_ADDR_BASE_IDX 8 5832 #define regAID2_XCC0_VF2_BASE_ADDR 0xcd68 5833 #define regAID2_XCC0_VF2_BASE_ADDR_BASE_IDX 8 5834 #define regAID2_XCC1_VF2_BASE_ADDR 0xcd69 5835 #define regAID2_XCC1_VF2_BASE_ADDR_BASE_IDX 8 5836 #define regAID3_XCC0_VF2_BASE_ADDR 0xcd6a 5837 #define regAID3_XCC0_VF2_BASE_ADDR_BASE_IDX 8 5838 #define regAID3_XCC1_VF2_BASE_ADDR 0xcd6b 5839 #define regAID3_XCC1_VF2_BASE_ADDR_BASE_IDX 8 5840 #define regAID0_NBIF_VF2_BASE_ADDR 0xcd6c 5841 #define regAID0_NBIF_VF2_BASE_ADDR_BASE_IDX 8 5842 #define regAID0_ATHUB_VF2_BASE_ADDR 0xcd6d 5843 #define regAID0_ATHUB_VF2_BASE_ADDR_BASE_IDX 8 5844 #define regAID0_IH_VF2_BASE_ADDR 0xcd6e 5845 #define regAID0_IH_VF2_BASE_ADDR_BASE_IDX 8 5846 #define regAID0_HDP_VF2_BASE_ADDR 0xcd6f 5847 #define regAID0_HDP_VF2_BASE_ADDR_BASE_IDX 8 5848 #define regAID0_VF3_BASE_ADDR 0xcd70 5849 #define regAID0_VF3_BASE_ADDR_BASE_IDX 8 5850 #define regAID1_VF3_BASE_ADDR 0xcd71 5851 #define regAID1_VF3_BASE_ADDR_BASE_IDX 8 5852 #define regAID2_VF3_BASE_ADDR 0xcd72 5853 #define regAID2_VF3_BASE_ADDR_BASE_IDX 8 5854 #define regAID3_VF3_BASE_ADDR 0xcd73 5855 #define regAID3_VF3_BASE_ADDR_BASE_IDX 8 5856 #define regAID0_XCC0_VF3_BASE_ADDR 0xcd74 5857 #define regAID0_XCC0_VF3_BASE_ADDR_BASE_IDX 8 5858 #define regAID0_XCC1_VF3_BASE_ADDR 0xcd75 5859 #define regAID0_XCC1_VF3_BASE_ADDR_BASE_IDX 8 5860 #define regAID1_XCC0_VF3_BASE_ADDR 0xcd76 5861 #define regAID1_XCC0_VF3_BASE_ADDR_BASE_IDX 8 5862 #define regAID1_XCC1_VF3_BASE_ADDR 0xcd77 5863 #define regAID1_XCC1_VF3_BASE_ADDR_BASE_IDX 8 5864 #define regAID2_XCC0_VF3_BASE_ADDR 0xcd78 5865 #define regAID2_XCC0_VF3_BASE_ADDR_BASE_IDX 8 5866 #define regAID2_XCC1_VF3_BASE_ADDR 0xcd79 5867 #define regAID2_XCC1_VF3_BASE_ADDR_BASE_IDX 8 5868 #define regAID3_XCC0_VF3_BASE_ADDR 0xcd7a 5869 #define regAID3_XCC0_VF3_BASE_ADDR_BASE_IDX 8 5870 #define regAID3_XCC1_VF3_BASE_ADDR 0xcd7b 5871 #define regAID3_XCC1_VF3_BASE_ADDR_BASE_IDX 8 5872 #define regAID0_NBIF_VF3_BASE_ADDR 0xcd7c 5873 #define regAID0_NBIF_VF3_BASE_ADDR_BASE_IDX 8 5874 #define regAID0_ATHUB_VF3_BASE_ADDR 0xcd7d 5875 #define regAID0_ATHUB_VF3_BASE_ADDR_BASE_IDX 8 5876 #define regAID0_IH_VF3_BASE_ADDR 0xcd7e 5877 #define regAID0_IH_VF3_BASE_ADDR_BASE_IDX 8 5878 #define regAID0_HDP_VF3_BASE_ADDR 0xcd7f 5879 #define regAID0_HDP_VF3_BASE_ADDR_BASE_IDX 8 5880 #define regAID0_VF4_BASE_ADDR 0xcd80 5881 #define regAID0_VF4_BASE_ADDR_BASE_IDX 8 5882 #define regAID1_VF4_BASE_ADDR 0xcd81 5883 #define regAID1_VF4_BASE_ADDR_BASE_IDX 8 5884 #define regAID2_VF4_BASE_ADDR 0xcd82 5885 #define regAID2_VF4_BASE_ADDR_BASE_IDX 8 5886 #define regAID3_VF4_BASE_ADDR 0xcd83 5887 #define regAID3_VF4_BASE_ADDR_BASE_IDX 8 5888 #define regAID0_XCC0_VF4_BASE_ADDR 0xcd84 5889 #define regAID0_XCC0_VF4_BASE_ADDR_BASE_IDX 8 5890 #define regAID0_XCC1_VF4_BASE_ADDR 0xcd85 5891 #define regAID0_XCC1_VF4_BASE_ADDR_BASE_IDX 8 5892 #define regAID1_XCC0_VF4_BASE_ADDR 0xcd86 5893 #define regAID1_XCC0_VF4_BASE_ADDR_BASE_IDX 8 5894 #define regAID1_XCC1_VF4_BASE_ADDR 0xcd87 5895 #define regAID1_XCC1_VF4_BASE_ADDR_BASE_IDX 8 5896 #define regAID2_XCC0_VF4_BASE_ADDR 0xcd88 5897 #define regAID2_XCC0_VF4_BASE_ADDR_BASE_IDX 8 5898 #define regAID2_XCC1_VF4_BASE_ADDR 0xcd89 5899 #define regAID2_XCC1_VF4_BASE_ADDR_BASE_IDX 8 5900 #define regAID3_XCC0_VF4_BASE_ADDR 0xcd8a 5901 #define regAID3_XCC0_VF4_BASE_ADDR_BASE_IDX 8 5902 #define regAID3_XCC1_VF4_BASE_ADDR 0xcd8b 5903 #define regAID3_XCC1_VF4_BASE_ADDR_BASE_IDX 8 5904 #define regAID0_NBIF_VF4_BASE_ADDR 0xcd8c 5905 #define regAID0_NBIF_VF4_BASE_ADDR_BASE_IDX 8 5906 #define regAID0_ATHUB_VF4_BASE_ADDR 0xcd8d 5907 #define regAID0_ATHUB_VF4_BASE_ADDR_BASE_IDX 8 5908 #define regAID0_IH_VF4_BASE_ADDR 0xcd8e 5909 #define regAID0_IH_VF4_BASE_ADDR_BASE_IDX 8 5910 #define regAID0_HDP_VF4_BASE_ADDR 0xcd8f 5911 #define regAID0_HDP_VF4_BASE_ADDR_BASE_IDX 8 5912 #define regAID0_VF5_BASE_ADDR 0xcd90 5913 #define regAID0_VF5_BASE_ADDR_BASE_IDX 8 5914 #define regAID1_VF5_BASE_ADDR 0xcd91 5915 #define regAID1_VF5_BASE_ADDR_BASE_IDX 8 5916 #define regAID2_VF5_BASE_ADDR 0xcd92 5917 #define regAID2_VF5_BASE_ADDR_BASE_IDX 8 5918 #define regAID3_VF5_BASE_ADDR 0xcd93 5919 #define regAID3_VF5_BASE_ADDR_BASE_IDX 8 5920 #define regAID0_XCC0_VF5_BASE_ADDR 0xcd94 5921 #define regAID0_XCC0_VF5_BASE_ADDR_BASE_IDX 8 5922 #define regAID0_XCC1_VF5_BASE_ADDR 0xcd95 5923 #define regAID0_XCC1_VF5_BASE_ADDR_BASE_IDX 8 5924 #define regAID1_XCC0_VF5_BASE_ADDR 0xcd96 5925 #define regAID1_XCC0_VF5_BASE_ADDR_BASE_IDX 8 5926 #define regAID1_XCC1_VF5_BASE_ADDR 0xcd97 5927 #define regAID1_XCC1_VF5_BASE_ADDR_BASE_IDX 8 5928 #define regAID2_XCC0_VF5_BASE_ADDR 0xcd98 5929 #define regAID2_XCC0_VF5_BASE_ADDR_BASE_IDX 8 5930 #define regAID2_XCC1_VF5_BASE_ADDR 0xcd99 5931 #define regAID2_XCC1_VF5_BASE_ADDR_BASE_IDX 8 5932 #define regAID3_XCC0_VF5_BASE_ADDR 0xcd9a 5933 #define regAID3_XCC0_VF5_BASE_ADDR_BASE_IDX 8 5934 #define regAID3_XCC1_VF5_BASE_ADDR 0xcd9b 5935 #define regAID3_XCC1_VF5_BASE_ADDR_BASE_IDX 8 5936 #define regAID0_NBIF_VF5_BASE_ADDR 0xcd9c 5937 #define regAID0_NBIF_VF5_BASE_ADDR_BASE_IDX 8 5938 #define regAID0_ATHUB_VF5_BASE_ADDR 0xcd9d 5939 #define regAID0_ATHUB_VF5_BASE_ADDR_BASE_IDX 8 5940 #define regAID0_IH_VF5_BASE_ADDR 0xcd9e 5941 #define regAID0_IH_VF5_BASE_ADDR_BASE_IDX 8 5942 #define regAID0_HDP_VF5_BASE_ADDR 0xcd9f 5943 #define regAID0_HDP_VF5_BASE_ADDR_BASE_IDX 8 5944 #define regAID0_VF6_BASE_ADDR 0xcda0 5945 #define regAID0_VF6_BASE_ADDR_BASE_IDX 8 5946 #define regAID1_VF6_BASE_ADDR 0xcda1 5947 #define regAID1_VF6_BASE_ADDR_BASE_IDX 8 5948 #define regAID2_VF6_BASE_ADDR 0xcda2 5949 #define regAID2_VF6_BASE_ADDR_BASE_IDX 8 5950 #define regAID3_VF6_BASE_ADDR 0xcda3 5951 #define regAID3_VF6_BASE_ADDR_BASE_IDX 8 5952 #define regAID0_XCC0_VF6_BASE_ADDR 0xcda4 5953 #define regAID0_XCC0_VF6_BASE_ADDR_BASE_IDX 8 5954 #define regAID0_XCC1_VF6_BASE_ADDR 0xcda5 5955 #define regAID0_XCC1_VF6_BASE_ADDR_BASE_IDX 8 5956 #define regAID1_XCC0_VF6_BASE_ADDR 0xcda6 5957 #define regAID1_XCC0_VF6_BASE_ADDR_BASE_IDX 8 5958 #define regAID1_XCC1_VF6_BASE_ADDR 0xcda7 5959 #define regAID1_XCC1_VF6_BASE_ADDR_BASE_IDX 8 5960 #define regAID2_XCC0_VF6_BASE_ADDR 0xcda8 5961 #define regAID2_XCC0_VF6_BASE_ADDR_BASE_IDX 8 5962 #define regAID2_XCC1_VF6_BASE_ADDR 0xcda9 5963 #define regAID2_XCC1_VF6_BASE_ADDR_BASE_IDX 8 5964 #define regAID3_XCC0_VF6_BASE_ADDR 0xcdaa 5965 #define regAID3_XCC0_VF6_BASE_ADDR_BASE_IDX 8 5966 #define regAID3_XCC1_VF6_BASE_ADDR 0xcdab 5967 #define regAID3_XCC1_VF6_BASE_ADDR_BASE_IDX 8 5968 #define regAID0_NBIF_VF6_BASE_ADDR 0xcdac 5969 #define regAID0_NBIF_VF6_BASE_ADDR_BASE_IDX 8 5970 #define regAID0_ATHUB_VF6_BASE_ADDR 0xcdad 5971 #define regAID0_ATHUB_VF6_BASE_ADDR_BASE_IDX 8 5972 #define regAID0_IH_VF6_BASE_ADDR 0xcdae 5973 #define regAID0_IH_VF6_BASE_ADDR_BASE_IDX 8 5974 #define regAID0_HDP_VF6_BASE_ADDR 0xcdaf 5975 #define regAID0_HDP_VF6_BASE_ADDR_BASE_IDX 8 5976 #define regAID0_VF7_BASE_ADDR 0xcdb0 5977 #define regAID0_VF7_BASE_ADDR_BASE_IDX 8 5978 #define regAID1_VF7_BASE_ADDR 0xcdb1 5979 #define regAID1_VF7_BASE_ADDR_BASE_IDX 8 5980 #define regAID2_VF7_BASE_ADDR 0xcdb2 5981 #define regAID2_VF7_BASE_ADDR_BASE_IDX 8 5982 #define regAID3_VF7_BASE_ADDR 0xcdb3 5983 #define regAID3_VF7_BASE_ADDR_BASE_IDX 8 5984 #define regAID0_XCC0_VF7_BASE_ADDR 0xcdb4 5985 #define regAID0_XCC0_VF7_BASE_ADDR_BASE_IDX 8 5986 #define regAID0_XCC1_VF7_BASE_ADDR 0xcdb5 5987 #define regAID0_XCC1_VF7_BASE_ADDR_BASE_IDX 8 5988 #define regAID1_XCC0_VF7_BASE_ADDR 0xcdb6 5989 #define regAID1_XCC0_VF7_BASE_ADDR_BASE_IDX 8 5990 #define regAID1_XCC1_VF7_BASE_ADDR 0xcdb7 5991 #define regAID1_XCC1_VF7_BASE_ADDR_BASE_IDX 8 5992 #define regAID2_XCC0_VF7_BASE_ADDR 0xcdb8 5993 #define regAID2_XCC0_VF7_BASE_ADDR_BASE_IDX 8 5994 #define regAID2_XCC1_VF7_BASE_ADDR 0xcdb9 5995 #define regAID2_XCC1_VF7_BASE_ADDR_BASE_IDX 8 5996 #define regAID3_XCC0_VF7_BASE_ADDR 0xcdba 5997 #define regAID3_XCC0_VF7_BASE_ADDR_BASE_IDX 8 5998 #define regAID3_XCC1_VF7_BASE_ADDR 0xcdbb 5999 #define regAID3_XCC1_VF7_BASE_ADDR_BASE_IDX 8 6000 #define regAID0_NBIF_VF7_BASE_ADDR 0xcdbc 6001 #define regAID0_NBIF_VF7_BASE_ADDR_BASE_IDX 8 6002 #define regAID0_ATHUB_VF7_BASE_ADDR 0xcdbd 6003 #define regAID0_ATHUB_VF7_BASE_ADDR_BASE_IDX 8 6004 #define regAID0_IH_VF7_BASE_ADDR 0xcdbe 6005 #define regAID0_IH_VF7_BASE_ADDR_BASE_IDX 8 6006 #define regAID0_HDP_VF7_BASE_ADDR 0xcdbf 6007 #define regAID0_HDP_VF7_BASE_ADDR_BASE_IDX 8 6008 #define regAID0_PF_BASE_ADDR 0xcdc0 6009 #define regAID0_PF_BASE_ADDR_BASE_IDX 8 6010 #define regAID0_XCC0_PF_BASE_ADDR 0xcdc1 6011 #define regAID0_XCC0_PF_BASE_ADDR_BASE_IDX 8 6012 #define regAID0_XCC1_PF_BASE_ADDR 0xcdc2 6013 #define regAID0_XCC1_PF_BASE_ADDR_BASE_IDX 8 6014 #define regAID1_PF_BASE_ADDR 0xcdc3 6015 #define regAID1_PF_BASE_ADDR_BASE_IDX 8 6016 #define regAID1_XCC0_PF_BASE_ADDR 0xcdc4 6017 #define regAID1_XCC0_PF_BASE_ADDR_BASE_IDX 8 6018 #define regAID1_XCC1_PF_BASE_ADDR 0xcdc5 6019 #define regAID1_XCC1_PF_BASE_ADDR_BASE_IDX 8 6020 #define regAID2_PF_BASE_ADDR 0xcdc6 6021 #define regAID2_PF_BASE_ADDR_BASE_IDX 8 6022 #define regAID2_XCC0_PF_BASE_ADDR 0xcdc7 6023 #define regAID2_XCC0_PF_BASE_ADDR_BASE_IDX 8 6024 #define regAID2_XCC1_PF_BASE_ADDR 0xcdc8 6025 #define regAID2_XCC1_PF_BASE_ADDR_BASE_IDX 8 6026 #define regAID3_PF_BASE_ADDR 0xcdc9 6027 #define regAID3_PF_BASE_ADDR_BASE_IDX 8 6028 #define regAID3_XCC0_PF_BASE_ADDR 0xcdca 6029 #define regAID3_XCC0_PF_BASE_ADDR_BASE_IDX 8 6030 #define regAID3_XCC1_PF_BASE_ADDR 0xcdcb 6031 #define regAID3_XCC1_PF_BASE_ADDR_BASE_IDX 8 6032 #define regNBIF_RRMT_CNTL 0xcddc 6033 #define regNBIF_RRMT_CNTL_BASE_IDX 8 6034 #define regBIFC_DOORBELL_ACCESS_EN_PF 0xcf6e 6035 #define regBIFC_DOORBELL_ACCESS_EN_PF_BASE_IDX 8 6036 #define regBIFC_DOORBELL_ACCESS_EN_VF0 0xcf6f 6037 #define regBIFC_DOORBELL_ACCESS_EN_VF0_BASE_IDX 8 6038 #define regBIFC_DOORBELL_ACCESS_EN_VF1 0xcf70 6039 #define regBIFC_DOORBELL_ACCESS_EN_VF1_BASE_IDX 8 6040 #define regBIFC_DOORBELL_ACCESS_EN_VF2 0xcf71 6041 #define regBIFC_DOORBELL_ACCESS_EN_VF2_BASE_IDX 8 6042 #define regBIFC_DOORBELL_ACCESS_EN_VF3 0xcf72 6043 #define regBIFC_DOORBELL_ACCESS_EN_VF3_BASE_IDX 8 6044 #define regBIFC_DOORBELL_ACCESS_EN_VF4 0xcf73 6045 #define regBIFC_DOORBELL_ACCESS_EN_VF4_BASE_IDX 8 6046 #define regBIFC_DOORBELL_ACCESS_EN_VF5 0xcf74 6047 #define regBIFC_DOORBELL_ACCESS_EN_VF5_BASE_IDX 8 6048 #define regBIFC_DOORBELL_ACCESS_EN_VF6 0xcf75 6049 #define regBIFC_DOORBELL_ACCESS_EN_VF6_BASE_IDX 8 6050 #define regBIFC_DOORBELL_ACCESS_EN_VF7 0xcf76 6051 #define regBIFC_DOORBELL_ACCESS_EN_VF7_BASE_IDX 8 6052 #define regMISC_SCRATCH 0xe800 6053 #define regMISC_SCRATCH_BASE_IDX 8 6054 #define regINTR_LINE_POLARITY 0xe801 6055 #define regINTR_LINE_POLARITY_BASE_IDX 8 6056 #define regINTR_LINE_ENABLE 0xe802 6057 #define regINTR_LINE_ENABLE_BASE_IDX 8 6058 #define regOUTSTANDING_VC_ALLOC 0xe803 6059 #define regOUTSTANDING_VC_ALLOC_BASE_IDX 8 6060 #define regBIFC_MISC_CTRL0 0xe804 6061 #define regBIFC_MISC_CTRL0_BASE_IDX 8 6062 #define regBIFC_MISC_CTRL1 0xe805 6063 #define regBIFC_MISC_CTRL1_BASE_IDX 8 6064 #define regBIFC_BME_ERR_LOG_LB 0xe806 6065 #define regBIFC_BME_ERR_LOG_LB_BASE_IDX 8 6066 #define regBIFC_LC_TIMER_CTRL 0xe807 6067 #define regBIFC_LC_TIMER_CTRL_BASE_IDX 8 6068 #define regBIFC_RCCBIH_BME_ERR_LOG0 0xe808 6069 #define regBIFC_RCCBIH_BME_ERR_LOG0_BASE_IDX 8 6070 #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 0xe80a 6071 #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1_BASE_IDX 8 6072 #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 0xe80b 6073 #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3_BASE_IDX 8 6074 #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 0xe80c 6075 #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5_BASE_IDX 8 6076 #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 0xe80d 6077 #define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7_BASE_IDX 8 6078 #define regBIFC_DMA_ATTR_CNTL2_DEV0 0xe81a 6079 #define regBIFC_DMA_ATTR_CNTL2_DEV0_BASE_IDX 8 6080 #define regBME_DUMMY_CNTL_0 0xe825 6081 #define regBME_DUMMY_CNTL_0_BASE_IDX 8 6082 #define regBIFC_THT_CNTL 0xe827 6083 #define regBIFC_THT_CNTL_BASE_IDX 8 6084 #define regBIFC_HSTARB_CNTL 0xe828 6085 #define regBIFC_HSTARB_CNTL_BASE_IDX 8 6086 #define regBIFC_GSI_CNTL 0xe829 6087 #define regBIFC_GSI_CNTL_BASE_IDX 8 6088 #define regBIFC_PCIEFUNC_CNTL 0xe82a 6089 #define regBIFC_PCIEFUNC_CNTL_BASE_IDX 8 6090 #define regBIFC_PASID_CHECK_DIS 0xe82b 6091 #define regBIFC_PASID_CHECK_DIS_BASE_IDX 8 6092 #define regBIFC_SDP_CNTL_0 0xe82c 6093 #define regBIFC_SDP_CNTL_0_BASE_IDX 8 6094 #define regBIFC_SDP_CNTL_1 0xe82d 6095 #define regBIFC_SDP_CNTL_1_BASE_IDX 8 6096 #define regBIFC_PASID_STS 0xe82e 6097 #define regBIFC_PASID_STS_BASE_IDX 8 6098 #define regBIFC_ATHUB_ACT_CNTL 0xe82f 6099 #define regBIFC_ATHUB_ACT_CNTL_BASE_IDX 8 6100 #define regBIFC_PERF_CNTL_0 0xe830 6101 #define regBIFC_PERF_CNTL_0_BASE_IDX 8 6102 #define regBIFC_PERF_CNTL_1 0xe831 6103 #define regBIFC_PERF_CNTL_1_BASE_IDX 8 6104 #define regBIFC_PERF_CNT_MMIO_RD_L32BIT 0xe832 6105 #define regBIFC_PERF_CNT_MMIO_RD_L32BIT_BASE_IDX 8 6106 #define regBIFC_PERF_CNT_MMIO_WR_L32BIT 0xe833 6107 #define regBIFC_PERF_CNT_MMIO_WR_L32BIT_BASE_IDX 8 6108 #define regBIFC_PERF_CNT_DMA_RD_L32BIT 0xe834 6109 #define regBIFC_PERF_CNT_DMA_RD_L32BIT_BASE_IDX 8 6110 #define regBIFC_PERF_CNT_DMA_WR_L32BIT 0xe835 6111 #define regBIFC_PERF_CNT_DMA_WR_L32BIT_BASE_IDX 8 6112 #define regNBIF_REGIF_ERRSET_CTRL 0xe836 6113 #define regNBIF_REGIF_ERRSET_CTRL_BASE_IDX 8 6114 #define regBIFC_SDP_CNTL_2 0xe837 6115 #define regBIFC_SDP_CNTL_2_BASE_IDX 8 6116 #define regNBIF_PGMST_CTRL 0xe838 6117 #define regNBIF_PGMST_CTRL_BASE_IDX 8 6118 #define regNBIF_PGSLV_CTRL 0xe839 6119 #define regNBIF_PGSLV_CTRL_BASE_IDX 8 6120 #define regNBIF_PG_MISC_CTRL 0xe83a 6121 #define regNBIF_PG_MISC_CTRL_BASE_IDX 8 6122 #define regSMN_MST_EP_CNTL3 0xe83c 6123 #define regSMN_MST_EP_CNTL3_BASE_IDX 8 6124 #define regSMN_MST_EP_CNTL4 0xe83d 6125 #define regSMN_MST_EP_CNTL4_BASE_IDX 8 6126 #define regSMN_MST_CNTL1 0xe83e 6127 #define regSMN_MST_CNTL1_BASE_IDX 8 6128 #define regSMN_MST_EP_CNTL5 0xe83f 6129 #define regSMN_MST_EP_CNTL5_BASE_IDX 8 6130 #define regBIF_SELFRING_BUFFER_VID 0xe840 6131 #define regBIF_SELFRING_BUFFER_VID_BASE_IDX 8 6132 #define regBIF_SELFRING_VECTOR_CNTL 0xe841 6133 #define regBIF_SELFRING_VECTOR_CNTL_BASE_IDX 8 6134 #define regNBIF_STRAP_WRITE_CTRL 0xe845 6135 #define regNBIF_STRAP_WRITE_CTRL_BASE_IDX 8 6136 #define regNBIF_INTX_DSTATE_MISC_CNTL 0xe846 6137 #define regNBIF_INTX_DSTATE_MISC_CNTL_BASE_IDX 8 6138 #define regNBIF_PENDING_MISC_CNTL 0xe847 6139 #define regNBIF_PENDING_MISC_CNTL_BASE_IDX 8 6140 #define regBIF_GMI_WRR_WEIGHT 0xe848 6141 #define regBIF_GMI_WRR_WEIGHT_BASE_IDX 8 6142 #define regBIF_GMI_WRR_WEIGHT2 0xe849 6143 #define regBIF_GMI_WRR_WEIGHT2_BASE_IDX 8 6144 #define regBIF_GMI_WRR_WEIGHT3 0xe84a 6145 #define regBIF_GMI_WRR_WEIGHT3_BASE_IDX 8 6146 #define regNBIF_PWRBRK_REQUEST 0xe84c 6147 #define regNBIF_PWRBRK_REQUEST_BASE_IDX 8 6148 #define regBIF_ATOMIC_ERR_LOG_DEV0_F0 0xe850 6149 #define regBIF_ATOMIC_ERR_LOG_DEV0_F0_BASE_IDX 8 6150 #define regBIF_ATOMIC_ERR_LOG_DEV0_F1 0xe851 6151 #define regBIF_ATOMIC_ERR_LOG_DEV0_F1_BASE_IDX 8 6152 #define regBIF_DMA_MP4_ERR_LOG 0xe870 6153 #define regBIF_DMA_MP4_ERR_LOG_BASE_IDX 8 6154 #define regBIF_PASID_ERR_LOG 0xe871 6155 #define regBIF_PASID_ERR_LOG_BASE_IDX 8 6156 #define regBIF_PASID_ERR_CLR 0xe872 6157 #define regBIF_PASID_ERR_CLR_BASE_IDX 8 6158 #define regNBIF_VWIRE_CTRL 0xe880 6159 #define regNBIF_VWIRE_CTRL_BASE_IDX 8 6160 #define regNBIF_SMN_VWR_VCHG_DIS_CTRL 0xe881 6161 #define regNBIF_SMN_VWR_VCHG_DIS_CTRL_BASE_IDX 8 6162 #define regNBIF_SMN_VWR_VCHG_RST_CTRL0 0xe882 6163 #define regNBIF_SMN_VWR_VCHG_RST_CTRL0_BASE_IDX 8 6164 #define regNBIF_SMN_VWR_VCHG_TRIG 0xe884 6165 #define regNBIF_SMN_VWR_VCHG_TRIG_BASE_IDX 8 6166 #define regNBIF_SMN_VWR_WTRIG_CNTL 0xe885 6167 #define regNBIF_SMN_VWR_WTRIG_CNTL_BASE_IDX 8 6168 #define regNBIF_SMN_VWR_VCHG_DIS_CTRL_1 0xe886 6169 #define regNBIF_SMN_VWR_VCHG_DIS_CTRL_1_BASE_IDX 8 6170 #define regNBIF_MGCG_CTRL_LCLK 0xe887 6171 #define regNBIF_MGCG_CTRL_LCLK_BASE_IDX 8 6172 #define regNBIF_DS_CTRL_LCLK 0xe888 6173 #define regNBIF_DS_CTRL_LCLK_BASE_IDX 8 6174 #define regSMN_MST_CNTL0 0xe889 6175 #define regSMN_MST_CNTL0_BASE_IDX 8 6176 #define regSMN_MST_EP_CNTL1 0xe88a 6177 #define regSMN_MST_EP_CNTL1_BASE_IDX 8 6178 #define regSMN_MST_EP_CNTL2 0xe88b 6179 #define regSMN_MST_EP_CNTL2_BASE_IDX 8 6180 #define regNBIF_SDP_VWR_VCHG_DIS_CTRL 0xe88c 6181 #define regNBIF_SDP_VWR_VCHG_DIS_CTRL_BASE_IDX 8 6182 #define regNBIF_SDP_VWR_VCHG_RST_CTRL0 0xe88d 6183 #define regNBIF_SDP_VWR_VCHG_RST_CTRL0_BASE_IDX 8 6184 #define regNBIF_SDP_VWR_VCHG_RST_CTRL1 0xe88e 6185 #define regNBIF_SDP_VWR_VCHG_RST_CTRL1_BASE_IDX 8 6186 #define regNBIF_SDP_VWR_VCHG_TRIG 0xe88f 6187 #define regNBIF_SDP_VWR_VCHG_TRIG_BASE_IDX 8 6188 #define regNBIF_SHUB_TODET_CTRL 0xe898 6189 #define regNBIF_SHUB_TODET_CTRL_BASE_IDX 8 6190 #define regNBIF_SHUB_TODET_CLIENT_CTRL 0xe899 6191 #define regNBIF_SHUB_TODET_CLIENT_CTRL_BASE_IDX 8 6192 #define regNBIF_SHUB_TODET_CLIENT_STATUS 0xe89a 6193 #define regNBIF_SHUB_TODET_CLIENT_STATUS_BASE_IDX 8 6194 #define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL 0xe89b 6195 #define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL_BASE_IDX 8 6196 #define regNBIF_SHUB_TODET_CLIENT_CTRL2 0xe89c 6197 #define regNBIF_SHUB_TODET_CLIENT_CTRL2_BASE_IDX 8 6198 #define regNBIF_SHUB_TODET_CLIENT_STATUS2 0xe89d 6199 #define regNBIF_SHUB_TODET_CLIENT_STATUS2_BASE_IDX 8 6200 #define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2 0xe89e 6201 #define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2_BASE_IDX 8 6202 #define regBIFC_BME_ERR_LOG_HB 0xe8ab 6203 #define regBIFC_BME_ERR_LOG_HB_BASE_IDX 8 6204 #define regBIFC_GFX_INT_MONITOR_MASK 0xe8ad 6205 #define regBIFC_GFX_INT_MONITOR_MASK_BASE_IDX 8 6206 #define regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC 0xe8c0 6207 #define regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC_BASE_IDX 8 6208 #define regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC 0xe8c1 6209 #define regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC_BASE_IDX 8 6210 #define regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC 0xe8c2 6211 #define regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC_BASE_IDX 8 6212 #define regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC 0xe8c3 6213 #define regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC_BASE_IDX 8 6214 #define regDISCON_HYSTERESIS_HEAD_CTRL 0xe8c6 6215 #define regDISCON_HYSTERESIS_HEAD_CTRL_BASE_IDX 8 6216 #define regBIFC_EARLY_WAKEUP_CNTL 0xe8d2 6217 #define regBIFC_EARLY_WAKEUP_CNTL_BASE_IDX 8 6218 #define regBIFC_PERF_CNT_MMIO_RD_H16BIT 0xe8f0 6219 #define regBIFC_PERF_CNT_MMIO_RD_H16BIT_BASE_IDX 8 6220 #define regBIFC_PERF_CNT_MMIO_WR_H16BIT 0xe8f1 6221 #define regBIFC_PERF_CNT_MMIO_WR_H16BIT_BASE_IDX 8 6222 #define regBIFC_PERF_CNT_DMA_RD_H16BIT 0xe8f2 6223 #define regBIFC_PERF_CNT_DMA_RD_H16BIT_BASE_IDX 8 6224 #define regBIFC_PERF_CNT_DMA_WR_H16BIT 0xe8f3 6225 #define regBIFC_PERF_CNT_DMA_WR_H16BIT_BASE_IDX 8 6226 #define regBIFC_A2S_SDP_PORT_CTRL 0xeb00 6227 #define regBIFC_A2S_SDP_PORT_CTRL_BASE_IDX 8 6228 #define regBIFC_A2S_CNTL_SW0 0xeb01 6229 #define regBIFC_A2S_CNTL_SW0_BASE_IDX 8 6230 #define regBIFC_A2S_MISC_CNTL 0xeb02 6231 #define regBIFC_A2S_MISC_CNTL_BASE_IDX 8 6232 #define regBIFC_A2S_TAG_ALLOC_0 0xeb03 6233 #define regBIFC_A2S_TAG_ALLOC_0_BASE_IDX 8 6234 #define regBIFC_A2S_TAG_ALLOC_1 0xeb04 6235 #define regBIFC_A2S_TAG_ALLOC_1_BASE_IDX 8 6236 #define regBIFC_A2S_CNTL_CL0 0xeb05 6237 #define regBIFC_A2S_CNTL_CL0_BASE_IDX 8 6238 6239 6240 // addressBlock: aid_nbio_nbif0_rcc_dwn_dev0_BIFDEC1 6241 // base address: 0x10120000 6242 #define regRCC_DWN_DEV0_2_DN_PCIE_RESERVED 0x8d80 6243 #define regRCC_DWN_DEV0_2_DN_PCIE_RESERVED_BASE_IDX 8 6244 #define regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH 0x8d81 6245 #define regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH_BASE_IDX 8 6246 #define regRCC_DWN_DEV0_2_DN_PCIE_CNTL 0x8d83 6247 #define regRCC_DWN_DEV0_2_DN_PCIE_CNTL_BASE_IDX 8 6248 #define regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL 0x8d84 6249 #define regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL_BASE_IDX 8 6250 #define regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2 0x8d85 6251 #define regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2_BASE_IDX 8 6252 #define regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL 0x8d86 6253 #define regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL_BASE_IDX 8 6254 #define regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL 0x8d87 6255 #define regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL_BASE_IDX 8 6256 #define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0 0x8d88 6257 #define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0_BASE_IDX 8 6258 #define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC 0x8d89 6259 #define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC_BASE_IDX 8 6260 #define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2 0x8d8a 6261 #define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2_BASE_IDX 8 6262 6263 6264 // addressBlock: aid_nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 6265 // base address: 0x10120000 6266 #define regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL 0x8d8c 6267 #define regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL_BASE_IDX 8 6268 #define regRCC_DWNP_DEV0_2_PCIE_RX_CNTL 0x8d8d 6269 #define regRCC_DWNP_DEV0_2_PCIE_RX_CNTL_BASE_IDX 8 6270 #define regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL 0x8d8e 6271 #define regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL_BASE_IDX 8 6272 #define regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2 0x8d8f 6273 #define regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2_BASE_IDX 8 6274 #define regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC 0x8d90 6275 #define regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC_BASE_IDX 8 6276 #define regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP 0x8d91 6277 #define regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP_BASE_IDX 8 6278 6279 6280 // addressBlock: aid_nbio_nbif0_rcc_ep_dev0_BIFDEC1 6281 // base address: 0x10120000 6282 #define regRCC_EP_DEV0_2_EP_PCIE_SCRATCH 0x8d60 6283 #define regRCC_EP_DEV0_2_EP_PCIE_SCRATCH_BASE_IDX 8 6284 #define regRCC_EP_DEV0_2_EP_PCIE_CNTL 0x8d62 6285 #define regRCC_EP_DEV0_2_EP_PCIE_CNTL_BASE_IDX 8 6286 #define regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL 0x8d63 6287 #define regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL_BASE_IDX 8 6288 #define regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS 0x8d64 6289 #define regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS_BASE_IDX 8 6290 #define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2 0x8d65 6291 #define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2_BASE_IDX 8 6292 #define regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL 0x8d66 6293 #define regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL_BASE_IDX 8 6294 #define regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL 0x8d67 6295 #define regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL_BASE_IDX 8 6296 #define regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL 0x8d69 6297 #define regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL_BASE_IDX 8 6298 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x8d6a 6299 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 8 6300 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x8d6a 6301 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 8 6302 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x8d6a 6303 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 8 6304 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x8d6a 6305 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 8 6306 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x8d6b 6307 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 8 6308 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x8d6b 6309 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 8 6310 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x8d6b 6311 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 8 6312 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x8d6b 6313 #define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 8 6314 #define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC 0x8d6c 6315 #define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC_BASE_IDX 8 6316 #define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2 0x8d6d 6317 #define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2_BASE_IDX 8 6318 #define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP 0x8d6f 6319 #define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP_BASE_IDX 8 6320 #define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0x8d70 6321 #define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 8 6322 #define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL 0x8d70 6323 #define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL_BASE_IDX 8 6324 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x8d70 6325 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 8 6326 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x8d71 6327 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 8 6328 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x8d71 6329 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 8 6330 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x8d71 6331 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 8 6332 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x8d71 6333 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 8 6334 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x8d72 6335 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 8 6336 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x8d72 6337 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 8 6338 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x8d72 6339 #define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 8 6340 #define regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL 0x8d72 6341 #define regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL_BASE_IDX 8 6342 #define regRCC_EP_DEV0_2_EP_PCIEP_RESERVED 0x8d73 6343 #define regRCC_EP_DEV0_2_EP_PCIEP_RESERVED_BASE_IDX 8 6344 #define regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL 0x8d75 6345 #define regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL_BASE_IDX 8 6346 #define regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID 0x8d76 6347 #define regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 8 6348 #define regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL 0x8d77 6349 #define regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL_BASE_IDX 8 6350 #define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL 0x8d78 6351 #define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL_BASE_IDX 8 6352 #define regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL 0x8d79 6353 #define regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 8 6354 6355 6356 // addressBlock: aid_nbio_nbif0_rcc_dev0_BIFDEC1 6357 // base address: 0x10120000 6358 #define regRCC_DEV0_1_RCC_ERR_INT_CNTL 0x8da6 6359 #define regRCC_DEV0_1_RCC_ERR_INT_CNTL_BASE_IDX 8 6360 #define regRCC_DEV0_1_RCC_BACO_CNTL_MISC 0x8da7 6361 #define regRCC_DEV0_1_RCC_BACO_CNTL_MISC_BASE_IDX 8 6362 #define regRCC_DEV0_1_RCC_RESET_EN 0x8da8 6363 #define regRCC_DEV0_1_RCC_RESET_EN_BASE_IDX 8 6364 #define regRCC_DEV0_2_RCC_VDM_SUPPORT 0x8da9 6365 #define regRCC_DEV0_2_RCC_VDM_SUPPORT_BASE_IDX 8 6366 #define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0 0x8daa 6367 #define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 8 6368 #define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1 0x8dab 6369 #define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 8 6370 #define regRCC_DEV0_1_RCC_GPUIOV_REGION 0x8dac 6371 #define regRCC_DEV0_1_RCC_GPUIOV_REGION_BASE_IDX 8 6372 #define regRCC_DEV0_1_RCC_GPU_HOSTVM_EN 0x8dad 6373 #define regRCC_DEV0_1_RCC_GPU_HOSTVM_EN_BASE_IDX 8 6374 #define regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL 0x8dae 6375 #define regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX 8 6376 #define regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET 0x8daf 6377 #define regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX 8 6378 #define regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE 0x8daf 6379 #define regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX 8 6380 #define regRCC_DEV0_1_RCC_PEER_REG_RANGE0 0x8dde 6381 #define regRCC_DEV0_1_RCC_PEER_REG_RANGE0_BASE_IDX 8 6382 #define regRCC_DEV0_1_RCC_PEER_REG_RANGE1 0x8ddf 6383 #define regRCC_DEV0_1_RCC_PEER_REG_RANGE1_BASE_IDX 8 6384 #define regRCC_DEV0_2_RCC_BUS_CNTL 0x8de1 6385 #define regRCC_DEV0_2_RCC_BUS_CNTL_BASE_IDX 8 6386 #define regRCC_DEV0_1_RCC_CONFIG_CNTL 0x8de2 6387 #define regRCC_DEV0_1_RCC_CONFIG_CNTL_BASE_IDX 8 6388 #define regRCC_DEV0_1_RCC_CONFIG_F0_BASE 0x8de6 6389 #define regRCC_DEV0_1_RCC_CONFIG_F0_BASE_BASE_IDX 8 6390 #define regRCC_DEV0_1_RCC_CONFIG_APER_SIZE 0x8de7 6391 #define regRCC_DEV0_1_RCC_CONFIG_APER_SIZE_BASE_IDX 8 6392 #define regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE 0x8de8 6393 #define regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE_BASE_IDX 8 6394 #define regRCC_DEV0_1_RCC_XDMA_LO 0x8de9 6395 #define regRCC_DEV0_1_RCC_XDMA_LO_BASE_IDX 8 6396 #define regRCC_DEV0_1_RCC_XDMA_HI 0x8dea 6397 #define regRCC_DEV0_1_RCC_XDMA_HI_BASE_IDX 8 6398 #define regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC 0x8deb 6399 #define regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC_BASE_IDX 8 6400 #define regRCC_DEV0_1_RCC_BUSNUM_CNTL1 0x8dec 6401 #define regRCC_DEV0_1_RCC_BUSNUM_CNTL1_BASE_IDX 8 6402 #define regRCC_DEV0_1_RCC_BUSNUM_LIST0 0x8ded 6403 #define regRCC_DEV0_1_RCC_BUSNUM_LIST0_BASE_IDX 8 6404 #define regRCC_DEV0_1_RCC_BUSNUM_LIST1 0x8dee 6405 #define regRCC_DEV0_1_RCC_BUSNUM_LIST1_BASE_IDX 8 6406 #define regRCC_DEV0_1_RCC_BUSNUM_CNTL2 0x8def 6407 #define regRCC_DEV0_1_RCC_BUSNUM_CNTL2_BASE_IDX 8 6408 #define regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM 0x8df0 6409 #define regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX 8 6410 #define regRCC_DEV0_1_RCC_HOST_BUSNUM 0x8df1 6411 #define regRCC_DEV0_1_RCC_HOST_BUSNUM_BASE_IDX 8 6412 #define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI 0x8df2 6413 #define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI_BASE_IDX 8 6414 #define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO 0x8df3 6415 #define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO_BASE_IDX 8 6416 #define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI 0x8df4 6417 #define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI_BASE_IDX 8 6418 #define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO 0x8df5 6419 #define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO_BASE_IDX 8 6420 #define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI 0x8df6 6421 #define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI_BASE_IDX 8 6422 #define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO 0x8df7 6423 #define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO_BASE_IDX 8 6424 #define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI 0x8df8 6425 #define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI_BASE_IDX 8 6426 #define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO 0x8df9 6427 #define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO_BASE_IDX 8 6428 #define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0 0x8dfa 6429 #define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0_BASE_IDX 8 6430 #define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1 0x8dfb 6431 #define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1_BASE_IDX 8 6432 #define regRCC_DEV0_2_RCC_DEV0_LINK_CNTL 0x8dfd 6433 #define regRCC_DEV0_2_RCC_DEV0_LINK_CNTL_BASE_IDX 8 6434 #define regRCC_DEV0_2_RCC_CMN_LINK_CNTL 0x8dfe 6435 #define regRCC_DEV0_2_RCC_CMN_LINK_CNTL_BASE_IDX 8 6436 #define regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE 0x8dff 6437 #define regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 8 6438 #define regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL 0x8e00 6439 #define regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL_BASE_IDX 8 6440 #define regRCC_DEV0_2_RCC_MH_ARB_CNTL 0x8e01 6441 #define regRCC_DEV0_2_RCC_MH_ARB_CNTL_BASE_IDX 8 6442 6443 6444 // addressBlock: aid_nbio_nbif0_bif_bx_SYSDEC 6445 // base address: 0x10120000 6446 #define regBIF_BX1_PCIE_INDEX 0x800c 6447 #define regBIF_BX1_PCIE_INDEX_BASE_IDX 8 6448 #define regBIF_BX1_PCIE_DATA 0x800d 6449 #define regBIF_BX1_PCIE_DATA_BASE_IDX 8 6450 #define regBIF_BX1_PCIE_INDEX2 0x800e 6451 #define regBIF_BX1_PCIE_INDEX2_BASE_IDX 8 6452 #define regBIF_BX1_PCIE_DATA2 0x800f 6453 #define regBIF_BX1_PCIE_DATA2_BASE_IDX 8 6454 #define regBIF_BX1_PCIE_INDEX_HI 0x8010 6455 #define regBIF_BX1_PCIE_INDEX_HI_BASE_IDX 8 6456 #define regBIF_BX1_PCIE_INDEX2_HI 0x8011 6457 #define regBIF_BX1_PCIE_INDEX2_HI_BASE_IDX 8 6458 #define regBIF_BX1_SBIOS_SCRATCH_0 0x8048 6459 #define regBIF_BX1_SBIOS_SCRATCH_0_BASE_IDX 8 6460 #define regBIF_BX1_SBIOS_SCRATCH_1 0x8049 6461 #define regBIF_BX1_SBIOS_SCRATCH_1_BASE_IDX 8 6462 #define regBIF_BX1_SBIOS_SCRATCH_2 0x804a 6463 #define regBIF_BX1_SBIOS_SCRATCH_2_BASE_IDX 8 6464 #define regBIF_BX1_SBIOS_SCRATCH_3 0x804b 6465 #define regBIF_BX1_SBIOS_SCRATCH_3_BASE_IDX 8 6466 #define regBIF_BX1_BIOS_SCRATCH_0 0x804c 6467 #define regBIF_BX1_BIOS_SCRATCH_0_BASE_IDX 8 6468 #define regBIF_BX1_BIOS_SCRATCH_1 0x804d 6469 #define regBIF_BX1_BIOS_SCRATCH_1_BASE_IDX 8 6470 #define regBIF_BX1_BIOS_SCRATCH_2 0x804e 6471 #define regBIF_BX1_BIOS_SCRATCH_2_BASE_IDX 8 6472 #define regBIF_BX1_BIOS_SCRATCH_3 0x804f 6473 #define regBIF_BX1_BIOS_SCRATCH_3_BASE_IDX 8 6474 #define regBIF_BX1_BIOS_SCRATCH_4 0x8050 6475 #define regBIF_BX1_BIOS_SCRATCH_4_BASE_IDX 8 6476 #define regBIF_BX1_BIOS_SCRATCH_5 0x8051 6477 #define regBIF_BX1_BIOS_SCRATCH_5_BASE_IDX 8 6478 #define regBIF_BX1_BIOS_SCRATCH_6 0x8052 6479 #define regBIF_BX1_BIOS_SCRATCH_6_BASE_IDX 8 6480 #define regBIF_BX1_BIOS_SCRATCH_7 0x8053 6481 #define regBIF_BX1_BIOS_SCRATCH_7_BASE_IDX 8 6482 #define regBIF_BX1_BIOS_SCRATCH_8 0x8054 6483 #define regBIF_BX1_BIOS_SCRATCH_8_BASE_IDX 8 6484 #define regBIF_BX1_BIOS_SCRATCH_9 0x8055 6485 #define regBIF_BX1_BIOS_SCRATCH_9_BASE_IDX 8 6486 #define regBIF_BX1_BIOS_SCRATCH_10 0x8056 6487 #define regBIF_BX1_BIOS_SCRATCH_10_BASE_IDX 8 6488 #define regBIF_BX1_BIOS_SCRATCH_11 0x8057 6489 #define regBIF_BX1_BIOS_SCRATCH_11_BASE_IDX 8 6490 #define regBIF_BX1_BIOS_SCRATCH_12 0x8058 6491 #define regBIF_BX1_BIOS_SCRATCH_12_BASE_IDX 8 6492 #define regBIF_BX1_BIOS_SCRATCH_13 0x8059 6493 #define regBIF_BX1_BIOS_SCRATCH_13_BASE_IDX 8 6494 #define regBIF_BX1_BIOS_SCRATCH_14 0x805a 6495 #define regBIF_BX1_BIOS_SCRATCH_14_BASE_IDX 8 6496 #define regBIF_BX1_BIOS_SCRATCH_15 0x805b 6497 #define regBIF_BX1_BIOS_SCRATCH_15_BASE_IDX 8 6498 #define regBIF_BX1_BIF_RLC_INTR_CNTL 0x8060 6499 #define regBIF_BX1_BIF_RLC_INTR_CNTL_BASE_IDX 8 6500 #define regBIF_BX1_BIF_VCE_INTR_CNTL 0x8061 6501 #define regBIF_BX1_BIF_VCE_INTR_CNTL_BASE_IDX 8 6502 #define regBIF_BX1_BIF_UVD_INTR_CNTL 0x8062 6503 #define regBIF_BX1_BIF_UVD_INTR_CNTL_BASE_IDX 8 6504 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR0 0x8080 6505 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR0_BASE_IDX 8 6506 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0 0x8081 6507 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 8 6508 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR1 0x8082 6509 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR1_BASE_IDX 8 6510 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1 0x8083 6511 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 8 6512 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR2 0x8084 6513 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR2_BASE_IDX 8 6514 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2 0x8085 6515 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 8 6516 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR3 0x8086 6517 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR3_BASE_IDX 8 6518 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3 0x8087 6519 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 8 6520 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR4 0x8088 6521 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR4_BASE_IDX 8 6522 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4 0x8089 6523 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 8 6524 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR5 0x808a 6525 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR5_BASE_IDX 8 6526 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5 0x808b 6527 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 8 6528 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR6 0x808c 6529 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR6_BASE_IDX 8 6530 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6 0x808d 6531 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 8 6532 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR7 0x808e 6533 #define regBIF_BX1_GFX_MMIOREG_CAM_ADDR7_BASE_IDX 8 6534 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7 0x808f 6535 #define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 8 6536 #define regBIF_BX1_GFX_MMIOREG_CAM_CNTL 0x8090 6537 #define regBIF_BX1_GFX_MMIOREG_CAM_CNTL_BASE_IDX 8 6538 #define regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL 0x8091 6539 #define regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 8 6540 #define regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL 0x8092 6541 #define regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 8 6542 #define regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x8093 6543 #define regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 8 6544 #define regBIF_BX1_DRIVER_SCRATCH_0 0x8094 6545 #define regBIF_BX1_DRIVER_SCRATCH_0_BASE_IDX 8 6546 #define regBIF_BX1_DRIVER_SCRATCH_1 0x8095 6547 #define regBIF_BX1_DRIVER_SCRATCH_1_BASE_IDX 8 6548 #define regBIF_BX1_DRIVER_SCRATCH_2 0x8096 6549 #define regBIF_BX1_DRIVER_SCRATCH_2_BASE_IDX 8 6550 #define regBIF_BX1_DRIVER_SCRATCH_3 0x8097 6551 #define regBIF_BX1_DRIVER_SCRATCH_3_BASE_IDX 8 6552 #define regBIF_BX1_DRIVER_SCRATCH_4 0x8098 6553 #define regBIF_BX1_DRIVER_SCRATCH_4_BASE_IDX 8 6554 #define regBIF_BX1_DRIVER_SCRATCH_5 0x8099 6555 #define regBIF_BX1_DRIVER_SCRATCH_5_BASE_IDX 8 6556 #define regBIF_BX1_DRIVER_SCRATCH_6 0x809a 6557 #define regBIF_BX1_DRIVER_SCRATCH_6_BASE_IDX 8 6558 #define regBIF_BX1_DRIVER_SCRATCH_7 0x809b 6559 #define regBIF_BX1_DRIVER_SCRATCH_7_BASE_IDX 8 6560 #define regBIF_BX1_DRIVER_SCRATCH_8 0x809c 6561 #define regBIF_BX1_DRIVER_SCRATCH_8_BASE_IDX 8 6562 #define regBIF_BX1_DRIVER_SCRATCH_9 0x809d 6563 #define regBIF_BX1_DRIVER_SCRATCH_9_BASE_IDX 8 6564 #define regBIF_BX1_DRIVER_SCRATCH_10 0x809e 6565 #define regBIF_BX1_DRIVER_SCRATCH_10_BASE_IDX 8 6566 #define regBIF_BX1_DRIVER_SCRATCH_11 0x809f 6567 #define regBIF_BX1_DRIVER_SCRATCH_11_BASE_IDX 8 6568 #define regBIF_BX1_DRIVER_SCRATCH_12 0x80a0 6569 #define regBIF_BX1_DRIVER_SCRATCH_12_BASE_IDX 8 6570 #define regBIF_BX1_DRIVER_SCRATCH_13 0x80a1 6571 #define regBIF_BX1_DRIVER_SCRATCH_13_BASE_IDX 8 6572 #define regBIF_BX1_DRIVER_SCRATCH_14 0x80a2 6573 #define regBIF_BX1_DRIVER_SCRATCH_14_BASE_IDX 8 6574 #define regBIF_BX1_DRIVER_SCRATCH_15 0x80a3 6575 #define regBIF_BX1_DRIVER_SCRATCH_15_BASE_IDX 8 6576 #define regBIF_BX1_FW_SCRATCH_0 0x80a4 6577 #define regBIF_BX1_FW_SCRATCH_0_BASE_IDX 8 6578 #define regBIF_BX1_FW_SCRATCH_1 0x80a5 6579 #define regBIF_BX1_FW_SCRATCH_1_BASE_IDX 8 6580 #define regBIF_BX1_FW_SCRATCH_2 0x80a6 6581 #define regBIF_BX1_FW_SCRATCH_2_BASE_IDX 8 6582 #define regBIF_BX1_FW_SCRATCH_3 0x80a7 6583 #define regBIF_BX1_FW_SCRATCH_3_BASE_IDX 8 6584 #define regBIF_BX1_FW_SCRATCH_4 0x80a8 6585 #define regBIF_BX1_FW_SCRATCH_4_BASE_IDX 8 6586 #define regBIF_BX1_FW_SCRATCH_5 0x80a9 6587 #define regBIF_BX1_FW_SCRATCH_5_BASE_IDX 8 6588 #define regBIF_BX1_FW_SCRATCH_6 0x80aa 6589 #define regBIF_BX1_FW_SCRATCH_6_BASE_IDX 8 6590 #define regBIF_BX1_FW_SCRATCH_7 0x80ab 6591 #define regBIF_BX1_FW_SCRATCH_7_BASE_IDX 8 6592 #define regBIF_BX1_FW_SCRATCH_8 0x80ac 6593 #define regBIF_BX1_FW_SCRATCH_8_BASE_IDX 8 6594 #define regBIF_BX1_FW_SCRATCH_9 0x80ad 6595 #define regBIF_BX1_FW_SCRATCH_9_BASE_IDX 8 6596 #define regBIF_BX1_FW_SCRATCH_10 0x80ae 6597 #define regBIF_BX1_FW_SCRATCH_10_BASE_IDX 8 6598 #define regBIF_BX1_FW_SCRATCH_11 0x80af 6599 #define regBIF_BX1_FW_SCRATCH_11_BASE_IDX 8 6600 #define regBIF_BX1_FW_SCRATCH_12 0x80b0 6601 #define regBIF_BX1_FW_SCRATCH_12_BASE_IDX 8 6602 #define regBIF_BX1_FW_SCRATCH_13 0x80b1 6603 #define regBIF_BX1_FW_SCRATCH_13_BASE_IDX 8 6604 #define regBIF_BX1_FW_SCRATCH_14 0x80b2 6605 #define regBIF_BX1_FW_SCRATCH_14_BASE_IDX 8 6606 #define regBIF_BX1_FW_SCRATCH_15 0x80b3 6607 #define regBIF_BX1_FW_SCRATCH_15_BASE_IDX 8 6608 #define regBIF_BX1_SBIOS_SCRATCH_4 0x80b4 6609 #define regBIF_BX1_SBIOS_SCRATCH_4_BASE_IDX 8 6610 #define regBIF_BX1_SBIOS_SCRATCH_5 0x80b5 6611 #define regBIF_BX1_SBIOS_SCRATCH_5_BASE_IDX 8 6612 #define regBIF_BX1_SBIOS_SCRATCH_6 0x80b6 6613 #define regBIF_BX1_SBIOS_SCRATCH_6_BASE_IDX 8 6614 #define regBIF_BX1_SBIOS_SCRATCH_7 0x80b7 6615 #define regBIF_BX1_SBIOS_SCRATCH_7_BASE_IDX 8 6616 #define regBIF_BX1_SBIOS_SCRATCH_8 0x80b8 6617 #define regBIF_BX1_SBIOS_SCRATCH_8_BASE_IDX 8 6618 #define regBIF_BX1_SBIOS_SCRATCH_9 0x80b9 6619 #define regBIF_BX1_SBIOS_SCRATCH_9_BASE_IDX 8 6620 #define regBIF_BX1_SBIOS_SCRATCH_10 0x80ba 6621 #define regBIF_BX1_SBIOS_SCRATCH_10_BASE_IDX 8 6622 #define regBIF_BX1_SBIOS_SCRATCH_11 0x80bb 6623 #define regBIF_BX1_SBIOS_SCRATCH_11_BASE_IDX 8 6624 #define regBIF_BX1_SBIOS_SCRATCH_12 0x80bc 6625 #define regBIF_BX1_SBIOS_SCRATCH_12_BASE_IDX 8 6626 #define regBIF_BX1_SBIOS_SCRATCH_13 0x80bd 6627 #define regBIF_BX1_SBIOS_SCRATCH_13_BASE_IDX 8 6628 #define regBIF_BX1_SBIOS_SCRATCH_14 0x80be 6629 #define regBIF_BX1_SBIOS_SCRATCH_14_BASE_IDX 8 6630 #define regBIF_BX1_SBIOS_SCRATCH_15 0x80bf 6631 #define regBIF_BX1_SBIOS_SCRATCH_15_BASE_IDX 8 6632 6633 6634 // addressBlock: aid_nbio_nbif0_bif_bx_pf_SYSPFVFDEC 6635 // base address: 0x10120000 6636 #define regBIF_BX_PF1_MM_INDEX 0x8000 6637 #define regBIF_BX_PF1_MM_INDEX_BASE_IDX 8 6638 #define regBIF_BX_PF1_MM_DATA 0x8001 6639 #define regBIF_BX_PF1_MM_DATA_BASE_IDX 8 6640 #define regBIF_BX_PF1_MM_INDEX_HI 0x8006 6641 #define regBIF_BX_PF1_MM_INDEX_HI_BASE_IDX 8 6642 6643 6644 // addressBlock: aid_nbio_nbif0_bif_bx_BIFDEC1 6645 // base address: 0x10120000 6646 #define regBIF_BX1_CC_BIF_BX_STRAP0 0x8e02 6647 #define regBIF_BX1_CC_BIF_BX_STRAP0_BASE_IDX 8 6648 #define regBIF_BX1_CC_BIF_BX_PINSTRAP0 0x8e04 6649 #define regBIF_BX1_CC_BIF_BX_PINSTRAP0_BASE_IDX 8 6650 #define regBIF_BX1_BIF_MM_INDACCESS_CNTL 0x8e06 6651 #define regBIF_BX1_BIF_MM_INDACCESS_CNTL_BASE_IDX 8 6652 #define regBIF_BX1_BUS_CNTL 0x8e07 6653 #define regBIF_BX1_BUS_CNTL_BASE_IDX 8 6654 #define regBIF_BX1_BIF_SCRATCH0 0x8e08 6655 #define regBIF_BX1_BIF_SCRATCH0_BASE_IDX 8 6656 #define regBIF_BX1_BIF_SCRATCH1 0x8e09 6657 #define regBIF_BX1_BIF_SCRATCH1_BASE_IDX 8 6658 #define regBIF_BX1_BX_RESET_EN 0x8e0d 6659 #define regBIF_BX1_BX_RESET_EN_BASE_IDX 8 6660 #define regBIF_BX1_MM_CFGREGS_CNTL 0x8e0e 6661 #define regBIF_BX1_MM_CFGREGS_CNTL_BASE_IDX 8 6662 #define regBIF_BX1_BX_RESET_CNTL 0x8e10 6663 #define regBIF_BX1_BX_RESET_CNTL_BASE_IDX 8 6664 #define regBIF_BX1_INTERRUPT_CNTL 0x8e11 6665 #define regBIF_BX1_INTERRUPT_CNTL_BASE_IDX 8 6666 #define regBIF_BX1_INTERRUPT_CNTL2 0x8e12 6667 #define regBIF_BX1_INTERRUPT_CNTL2_BASE_IDX 8 6668 #define regBIF_BX1_CLKREQB_PAD_CNTL 0x8e18 6669 #define regBIF_BX1_CLKREQB_PAD_CNTL_BASE_IDX 8 6670 #define regBIF_BX1_BIF_FEATURES_CONTROL_MISC 0x8e1b 6671 #define regBIF_BX1_BIF_FEATURES_CONTROL_MISC_BASE_IDX 8 6672 #define regBIF_BX1_HDP_ATOMIC_CONTROL_MISC 0x8e1c 6673 #define regBIF_BX1_HDP_ATOMIC_CONTROL_MISC_BASE_IDX 8 6674 #define regBIF_BX1_BIF_DOORBELL_CNTL 0x8e1d 6675 #define regBIF_BX1_BIF_DOORBELL_CNTL_BASE_IDX 8 6676 #define regBIF_BX1_BIF_DOORBELL_INT_CNTL 0x8e1e 6677 #define regBIF_BX1_BIF_DOORBELL_INT_CNTL_BASE_IDX 8 6678 #define regBIF_BX1_BIF_FB_EN 0x8e20 6679 #define regBIF_BX1_BIF_FB_EN_BASE_IDX 8 6680 #define regBIF_BX1_BIF_INTR_CNTL 0x8e21 6681 #define regBIF_BX1_BIF_INTR_CNTL_BASE_IDX 8 6682 #define regBIF_BX1_BIF_MST_TRANS_PENDING_VF 0x8e29 6683 #define regBIF_BX1_BIF_MST_TRANS_PENDING_VF_BASE_IDX 8 6684 #define regBIF_BX1_BIF_SLV_TRANS_PENDING_VF 0x8e2a 6685 #define regBIF_BX1_BIF_SLV_TRANS_PENDING_VF_BASE_IDX 8 6686 #define regBIF_BX1_BACO_CNTL 0x8e2b 6687 #define regBIF_BX1_BACO_CNTL_BASE_IDX 8 6688 #define regBIF_BX1_BIF_BACO_EXIT_TIME0 0x8e2c 6689 #define regBIF_BX1_BIF_BACO_EXIT_TIME0_BASE_IDX 8 6690 #define regBIF_BX1_BIF_BACO_EXIT_TIMER1 0x8e2d 6691 #define regBIF_BX1_BIF_BACO_EXIT_TIMER1_BASE_IDX 8 6692 #define regBIF_BX1_BIF_BACO_EXIT_TIMER2 0x8e2e 6693 #define regBIF_BX1_BIF_BACO_EXIT_TIMER2_BASE_IDX 8 6694 #define regBIF_BX1_BIF_BACO_EXIT_TIMER3 0x8e2f 6695 #define regBIF_BX1_BIF_BACO_EXIT_TIMER3_BASE_IDX 8 6696 #define regBIF_BX1_BIF_BACO_EXIT_TIMER4 0x8e30 6697 #define regBIF_BX1_BIF_BACO_EXIT_TIMER4_BASE_IDX 8 6698 #define regBIF_BX1_MEM_TYPE_CNTL 0x8e31 6699 #define regBIF_BX1_MEM_TYPE_CNTL_BASE_IDX 8 6700 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_CNTL 0x8e33 6701 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX 8 6702 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_0 0x8e34 6703 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_0_BASE_IDX 8 6704 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_1 0x8e35 6705 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_1_BASE_IDX 8 6706 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_2 0x8e36 6707 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_2_BASE_IDX 8 6708 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_3 0x8e37 6709 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_3_BASE_IDX 8 6710 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_4 0x8e38 6711 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_4_BASE_IDX 8 6712 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_5 0x8e39 6713 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_5_BASE_IDX 8 6714 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_6 0x8e3a 6715 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_6_BASE_IDX 8 6716 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_7 0x8e3b 6717 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_7_BASE_IDX 8 6718 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_8 0x8e3c 6719 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_8_BASE_IDX 8 6720 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_9 0x8e3d 6721 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_9_BASE_IDX 8 6722 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_10 0x8e3e 6723 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_10_BASE_IDX 8 6724 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_11 0x8e3f 6725 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_11_BASE_IDX 8 6726 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_12 0x8e40 6727 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_12_BASE_IDX 8 6728 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_13 0x8e41 6729 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_13_BASE_IDX 8 6730 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_14 0x8e42 6731 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_14_BASE_IDX 8 6732 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_15 0x8e43 6733 #define regBIF_BX1_NBIF_GFX_ADDR_LUT_15_BASE_IDX 8 6734 #define regBIF_BX1_VF_REGWR_EN 0x8e44 6735 #define regBIF_BX1_VF_REGWR_EN_BASE_IDX 8 6736 #define regBIF_BX1_VF_DOORBELL_EN 0x8e45 6737 #define regBIF_BX1_VF_DOORBELL_EN_BASE_IDX 8 6738 #define regBIF_BX1_VF_FB_EN 0x8e46 6739 #define regBIF_BX1_VF_FB_EN_BASE_IDX 8 6740 #define regBIF_BX1_VF_REGWR_STATUS 0x8e47 6741 #define regBIF_BX1_VF_REGWR_STATUS_BASE_IDX 8 6742 #define regBIF_BX1_VF_DOORBELL_STATUS 0x8e48 6743 #define regBIF_BX1_VF_DOORBELL_STATUS_BASE_IDX 8 6744 #define regBIF_BX1_VF_FB_STATUS 0x8e49 6745 #define regBIF_BX1_VF_FB_STATUS_BASE_IDX 8 6746 #define regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL 0x8e4d 6747 #define regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 8 6748 #define regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL 0x8e4e 6749 #define regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 8 6750 #define regBIF_BX1_BIF_RB_CNTL 0x8e4f 6751 #define regBIF_BX1_BIF_RB_CNTL_BASE_IDX 8 6752 #define regBIF_BX1_BIF_RB_BASE 0x8e50 6753 #define regBIF_BX1_BIF_RB_BASE_BASE_IDX 8 6754 #define regBIF_BX1_BIF_RB_RPTR 0x8e51 6755 #define regBIF_BX1_BIF_RB_RPTR_BASE_IDX 8 6756 #define regBIF_BX1_BIF_RB_WPTR 0x8e52 6757 #define regBIF_BX1_BIF_RB_WPTR_BASE_IDX 8 6758 #define regBIF_BX1_BIF_RB_WPTR_ADDR_HI 0x8e53 6759 #define regBIF_BX1_BIF_RB_WPTR_ADDR_HI_BASE_IDX 8 6760 #define regBIF_BX1_BIF_RB_WPTR_ADDR_LO 0x8e54 6761 #define regBIF_BX1_BIF_RB_WPTR_ADDR_LO_BASE_IDX 8 6762 #define regBIF_BX1_MAILBOX_INDEX 0x8e55 6763 #define regBIF_BX1_MAILBOX_INDEX_BASE_IDX 8 6764 #define regBIF_BX1_BIF_MP1_INTR_CTRL 0x8e62 6765 #define regBIF_BX1_BIF_MP1_INTR_CTRL_BASE_IDX 8 6766 #define regBIF_BX1_BIF_PERSTB_PAD_CNTL 0x8e66 6767 #define regBIF_BX1_BIF_PERSTB_PAD_CNTL_BASE_IDX 8 6768 #define regBIF_BX1_BIF_PX_EN_PAD_CNTL 0x8e67 6769 #define regBIF_BX1_BIF_PX_EN_PAD_CNTL_BASE_IDX 8 6770 #define regBIF_BX1_BIF_REFPADKIN_PAD_CNTL 0x8e68 6771 #define regBIF_BX1_BIF_REFPADKIN_PAD_CNTL_BASE_IDX 8 6772 #define regBIF_BX1_BIF_CLKREQB_PAD_CNTL 0x8e69 6773 #define regBIF_BX1_BIF_CLKREQB_PAD_CNTL_BASE_IDX 8 6774 #define regBIF_BX1_BIF_PWRBRK_PAD_CNTL 0x8e6a 6775 #define regBIF_BX1_BIF_PWRBRK_PAD_CNTL_BASE_IDX 8 6776 #define regBIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE 0x8e6b 6777 #define regBIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE_BASE_IDX 8 6778 #define regBIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE 0x8e6c 6779 #define regBIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE_BASE_IDX 8 6780 6781 6782 // addressBlock: aid_nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 6783 // base address: 0x10120000 6784 #define regBIF_BX_PF1_BIF_BME_STATUS 0x8e0b 6785 #define regBIF_BX_PF1_BIF_BME_STATUS_BASE_IDX 8 6786 #define regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG 0x8e0c 6787 #define regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG_BASE_IDX 8 6788 #define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13 6789 #define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 8 6790 #define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14 6791 #define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 8 6792 #define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15 6793 #define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 8 6794 #define regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16 6795 #define regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 8 6796 #define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17 6797 #define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 8 6798 #define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19 6799 #define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 8 6800 #define regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a 6801 #define regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 8 6802 #define regBIF_BX_PF1_GPU_HDP_FLUSH_REQ 0x8e26 6803 #define regBIF_BX_PF1_GPU_HDP_FLUSH_REQ_BASE_IDX 8 6804 #define regBIF_BX_PF1_GPU_HDP_FLUSH_DONE 0x8e27 6805 #define regBIF_BX_PF1_GPU_HDP_FLUSH_DONE_BASE_IDX 8 6806 #define regBIF_BX_PF1_BIF_TRANS_PENDING 0x8e28 6807 #define regBIF_BX_PF1_BIF_TRANS_PENDING_BASE_IDX 8 6808 #define regBIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS 0x8e32 6809 #define regBIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 8 6810 #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0 0x8e56 6811 #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 8 6812 #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1 0x8e57 6813 #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 8 6814 #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2 0x8e58 6815 #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 8 6816 #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3 0x8e59 6817 #define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 8 6818 #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0 0x8e5a 6819 #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 8 6820 #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1 0x8e5b 6821 #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 8 6822 #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2 0x8e5c 6823 #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 8 6824 #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3 0x8e5d 6825 #define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 8 6826 #define regBIF_BX_PF1_MAILBOX_CONTROL 0x8e5e 6827 #define regBIF_BX_PF1_MAILBOX_CONTROL_BASE_IDX 8 6828 #define regBIF_BX_PF1_MAILBOX_INT_CNTL 0x8e5f 6829 #define regBIF_BX_PF1_MAILBOX_INT_CNTL_BASE_IDX 8 6830 #define regBIF_BX_PF1_BIF_VMHV_MAILBOX 0x8e60 6831 #define regBIF_BX_PF1_BIF_VMHV_MAILBOX_BASE_IDX 8 6832 #define regBIF_BX_PF1_PARTITION_COMPUTE_CAP 0x8e81 6833 #define regBIF_BX_PF1_PARTITION_COMPUTE_CAP_BASE_IDX 8 6834 #define regBIF_BX_PF1_PARTITION_MEM_CAP 0x8e82 6835 #define regBIF_BX_PF1_PARTITION_MEM_CAP_BASE_IDX 8 6836 #define regBIF_BX_PF1_PARTITION_COMPUTE_STATUS 0x8e83 6837 #define regBIF_BX_PF1_PARTITION_COMPUTE_STATUS_BASE_IDX 8 6838 #define regBIF_BX_PF1_PARTITION_MEM_STATUS 0x8e84 6839 #define regBIF_BX_PF1_PARTITION_MEM_STATUS_BASE_IDX 8 6840 6841 6842 // addressBlock: aid_nbio_nbif0_rcc_strap_BIFDEC1:1 6843 // base address: 0x10120000 6844 #define regRCC_STRAP2_RCC_BIF_STRAP0 0x8d20 6845 #define regRCC_STRAP2_RCC_BIF_STRAP0_BASE_IDX 8 6846 #define regRCC_STRAP2_RCC_BIF_STRAP1 0x8d21 6847 #define regRCC_STRAP2_RCC_BIF_STRAP1_BASE_IDX 8 6848 #define regRCC_STRAP2_RCC_BIF_STRAP2 0x8d22 6849 #define regRCC_STRAP2_RCC_BIF_STRAP2_BASE_IDX 8 6850 #define regRCC_STRAP2_RCC_BIF_STRAP3 0x8d23 6851 #define regRCC_STRAP2_RCC_BIF_STRAP3_BASE_IDX 8 6852 #define regRCC_STRAP2_RCC_BIF_STRAP4 0x8d24 6853 #define regRCC_STRAP2_RCC_BIF_STRAP4_BASE_IDX 8 6854 #define regRCC_STRAP2_RCC_BIF_STRAP5 0x8d25 6855 #define regRCC_STRAP2_RCC_BIF_STRAP5_BASE_IDX 8 6856 #define regRCC_STRAP2_RCC_BIF_STRAP6 0x8d26 6857 #define regRCC_STRAP2_RCC_BIF_STRAP6_BASE_IDX 8 6858 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP0 0x8d27 6859 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP0_BASE_IDX 8 6860 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP1 0x8d28 6861 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP1_BASE_IDX 8 6862 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP10 0x8d29 6863 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP10_BASE_IDX 8 6864 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP11 0x8d2a 6865 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP11_BASE_IDX 8 6866 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP12 0x8d2b 6867 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP12_BASE_IDX 8 6868 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP13 0x8d2c 6869 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP13_BASE_IDX 8 6870 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP14 0x8d2d 6871 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP14_BASE_IDX 8 6872 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP2 0x8d2e 6873 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP2_BASE_IDX 8 6874 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP3 0x8d2f 6875 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP3_BASE_IDX 8 6876 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP4 0x8d30 6877 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP4_BASE_IDX 8 6878 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP5 0x8d31 6879 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP5_BASE_IDX 8 6880 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP6 0x8d32 6881 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP6_BASE_IDX 8 6882 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP7 0x8d33 6883 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP7_BASE_IDX 8 6884 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP8 0x8d34 6885 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP8_BASE_IDX 8 6886 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP9 0x8d35 6887 #define regRCC_STRAP2_RCC_DEV0_PORT_STRAP9_BASE_IDX 8 6888 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0 0x8d36 6889 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0_BASE_IDX 8 6890 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1 0x8d37 6891 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1_BASE_IDX 8 6892 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13 0x8d38 6893 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13_BASE_IDX 8 6894 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14 0x8d39 6895 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14_BASE_IDX 8 6896 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15 0x8d3a 6897 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15_BASE_IDX 8 6898 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16 0x8d3b 6899 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16_BASE_IDX 8 6900 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17 0x8d3c 6901 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17_BASE_IDX 8 6902 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18 0x8d3d 6903 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18_BASE_IDX 8 6904 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2 0x8d3e 6905 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2_BASE_IDX 8 6906 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP26 0x8d3f 6907 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP26_BASE_IDX 8 6908 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3 0x8d40 6909 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3_BASE_IDX 8 6910 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4 0x8d41 6911 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4_BASE_IDX 8 6912 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5 0x8d42 6913 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5_BASE_IDX 8 6914 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8 0x8d44 6915 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8_BASE_IDX 8 6916 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9 0x8d45 6917 #define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9_BASE_IDX 8 6918 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0 0x8d46 6919 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0_BASE_IDX 8 6920 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2 0x8d52 6921 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2_BASE_IDX 8 6922 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP20 0x8d53 6923 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP20_BASE_IDX 8 6924 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP21 0x8d54 6925 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP21_BASE_IDX 8 6926 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP22 0x8d55 6927 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP22_BASE_IDX 8 6928 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP23 0x8d56 6929 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP23_BASE_IDX 8 6930 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP24 0x8d57 6931 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP24_BASE_IDX 8 6932 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP25 0x8d58 6933 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP25_BASE_IDX 8 6934 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3 0x8d59 6935 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3_BASE_IDX 8 6936 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4 0x8d5a 6937 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4_BASE_IDX 8 6938 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5 0x8d5b 6939 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5_BASE_IDX 8 6940 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6 0x8d5c 6941 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6_BASE_IDX 8 6942 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7 0x8d5d 6943 #define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7_BASE_IDX 8 6944 6945 6946 // addressBlock: aid_nbio_nbif0_gdc_hst_sion_SIONDEC 6947 // base address: 0x1400000 6948 #define regS2A_DOORBELL_ENTRY_0_CTRL 0x7a80 6949 #define regS2A_DOORBELL_ENTRY_0_CTRL_BASE_IDX 5 6950 #define regS2A_DOORBELL_ENTRY_1_CTRL 0x7a81 6951 #define regS2A_DOORBELL_ENTRY_1_CTRL_BASE_IDX 5 6952 #define regS2A_DOORBELL_ENTRY_2_CTRL 0x7a82 6953 #define regS2A_DOORBELL_ENTRY_2_CTRL_BASE_IDX 5 6954 #define regS2A_DOORBELL_ENTRY_3_CTRL 0x7a83 6955 #define regS2A_DOORBELL_ENTRY_3_CTRL_BASE_IDX 5 6956 #define regS2A_DOORBELL_ENTRY_4_CTRL 0x7a84 6957 #define regS2A_DOORBELL_ENTRY_4_CTRL_BASE_IDX 5 6958 #define regS2A_DOORBELL_ENTRY_5_CTRL 0x7a85 6959 #define regS2A_DOORBELL_ENTRY_5_CTRL_BASE_IDX 5 6960 #define regS2A_DOORBELL_ENTRY_6_CTRL 0x7a86 6961 #define regS2A_DOORBELL_ENTRY_6_CTRL_BASE_IDX 5 6962 #define regS2A_DOORBELL_ENTRY_7_CTRL 0x7a87 6963 #define regS2A_DOORBELL_ENTRY_7_CTRL_BASE_IDX 5 6964 #define regS2A_DOORBELL_ENTRY_8_CTRL 0x7a88 6965 #define regS2A_DOORBELL_ENTRY_8_CTRL_BASE_IDX 5 6966 #define regS2A_DOORBELL_ENTRY_9_CTRL 0x7a89 6967 #define regS2A_DOORBELL_ENTRY_9_CTRL_BASE_IDX 5 6968 #define regS2A_DOORBELL_ENTRY_10_CTRL 0x7a8a 6969 #define regS2A_DOORBELL_ENTRY_10_CTRL_BASE_IDX 5 6970 #define regS2A_DOORBELL_ENTRY_11_CTRL 0x7a8b 6971 #define regS2A_DOORBELL_ENTRY_11_CTRL_BASE_IDX 5 6972 #define regS2A_DOORBELL_ENTRY_12_CTRL 0x7a8c 6973 #define regS2A_DOORBELL_ENTRY_12_CTRL_BASE_IDX 5 6974 #define regS2A_DOORBELL_ENTRY_13_CTRL 0x7a8d 6975 #define regS2A_DOORBELL_ENTRY_13_CTRL_BASE_IDX 5 6976 #define regS2A_DOORBELL_ENTRY_14_CTRL 0x7a8e 6977 #define regS2A_DOORBELL_ENTRY_14_CTRL_BASE_IDX 5 6978 #define regS2A_DOORBELL_ENTRY_15_CTRL 0x7a8f 6979 #define regS2A_DOORBELL_ENTRY_15_CTRL_BASE_IDX 5 6980 #define regS2A_DOORBELL_COMMON_CTRL_REG 0x7a90 6981 #define regS2A_DOORBELL_COMMON_CTRL_REG_BASE_IDX 5 6982 6983 6984 // addressBlock: aid_nbio_nbif0_gdc_GDCDEC 6985 // base address: 0x1400000 6986 #define regGDC1_A2S_CNTL_CL0 0x0ea0 6987 #define regGDC1_A2S_CNTL_CL0_BASE_IDX 5 6988 #define regGDC1_A2S_CNTL_CL1 0x0ea1 6989 #define regGDC1_A2S_CNTL_CL1_BASE_IDX 5 6990 #define regGDC1_A2S_CNTL3_CL0 0x0eb8 6991 #define regGDC1_A2S_CNTL3_CL0_BASE_IDX 5 6992 #define regGDC1_A2S_CNTL3_CL1 0x0eb9 6993 #define regGDC1_A2S_CNTL3_CL1_BASE_IDX 5 6994 #define regGDC1_A2S_CNTL_SW0 0x0ed0 6995 #define regGDC1_A2S_CNTL_SW0_BASE_IDX 5 6996 #define regGDC1_A2S_CNTL_SW1 0x0ed1 6997 #define regGDC1_A2S_CNTL_SW1_BASE_IDX 5 6998 #define regGDC1_A2S_CNTL_SW2 0x0ed2 6999 #define regGDC1_A2S_CNTL_SW2_BASE_IDX 5 7000 #define regGDC1_A2S_TAG_ALLOC_0 0x0edd 7001 #define regGDC1_A2S_TAG_ALLOC_0_BASE_IDX 5 7002 #define regGDC1_A2S_TAG_ALLOC_1 0x0ede 7003 #define regGDC1_A2S_TAG_ALLOC_1_BASE_IDX 5 7004 #define regGDC1_A2S_MISC_CNTL 0x0ee1 7005 #define regGDC1_A2S_MISC_CNTL_BASE_IDX 5 7006 #define regGDC1_SHUB_REGS_IF_CTL 0x0ee3 7007 #define regGDC1_SHUB_REGS_IF_CTL_BASE_IDX 5 7008 #define regGDC1_NGDC_MGCG_CTRL 0x0eea 7009 #define regGDC1_NGDC_MGCG_CTRL_BASE_IDX 5 7010 #define regGDC1_NGDC_RESERVED_0 0x0eeb 7011 #define regGDC1_NGDC_RESERVED_0_BASE_IDX 5 7012 #define regGDC1_NGDC_RESERVED_1 0x0eec 7013 #define regGDC1_NGDC_RESERVED_1_BASE_IDX 5 7014 #define regGDC1_NBIF_GFX_DOORBELL_STATUS 0x0eef 7015 #define regGDC1_NBIF_GFX_DOORBELL_STATUS_BASE_IDX 5 7016 #define regGDC1_ATDMA_MISC_CNTL 0x0efd 7017 #define regGDC1_ATDMA_MISC_CNTL_BASE_IDX 5 7018 #define regGDC1_S2A_MISC_CNTL 0x0eff 7019 #define regGDC1_S2A_MISC_CNTL_BASE_IDX 5 7020 #define regGDC1_NGDC_EARLY_WAKEUP_CTRL 0x0f01 7021 #define regGDC1_NGDC_EARLY_WAKEUP_CTRL_BASE_IDX 5 7022 #define regGDC1_NGDC_PG_MISC_CTRL 0x0f18 7023 #define regGDC1_NGDC_PG_MISC_CTRL_BASE_IDX 5 7024 #define regGDC1_NGDC_PGMST_CTRL 0x0f19 7025 #define regGDC1_NGDC_PGMST_CTRL_BASE_IDX 5 7026 #define regGDC1_NGDC_PGSLV_CTRL 0x0f1a 7027 #define regGDC1_NGDC_PGSLV_CTRL_BASE_IDX 5 7028 7029 7030 // addressBlock: aid_nbio_nbif0_gdc_sec_GDCSEC_DEC 7031 // base address: 0x1400000 7032 #define regXCC_DOORBELL_FENCE 0x740c 7033 #define regXCC_DOORBELL_FENCE_BASE_IDX 5 7034 7035 7036 // addressBlock: aid_nbio_nbif0_gdc_rst_GDCRST_DEC 7037 // base address: 0x1400000 7038 #define regSHUB_PF_FLR_RST 0x7c00 7039 #define regSHUB_PF_FLR_RST_BASE_IDX 5 7040 #define regSHUB_GFX_DRV_VPU_RST 0x7c01 7041 #define regSHUB_GFX_DRV_VPU_RST_BASE_IDX 5 7042 #define regSHUB_LINK_RESET 0x7c02 7043 #define regSHUB_LINK_RESET_BASE_IDX 5 7044 #define regSHUB_HARD_RST_CTRL 0x7c10 7045 #define regSHUB_HARD_RST_CTRL_BASE_IDX 5 7046 #define regSHUB_SOFT_RST_CTRL 0x7c11 7047 #define regSHUB_SOFT_RST_CTRL_BASE_IDX 5 7048 #define regSHUB_SDP_PORT_RST 0x7c12 7049 #define regSHUB_SDP_PORT_RST_BASE_IDX 5 7050 #define regSHUB_RST_MISC_TRL 0x7c13 7051 #define regSHUB_RST_MISC_TRL_BASE_IDX 5 7052 7053 7054 // addressBlock: aid_nbio_nbif0_syshub_mmreg_syshubdirect 7055 // base address: 0x1400000 7056 #define regHST_CLK0_SW0_CL0_CNTL 0x4140 7057 #define regHST_CLK0_SW0_CL0_CNTL_BASE_IDX 5 7058 #define regHST_CLK0_SW1_CL0_CNTL 0x4160 7059 #define regHST_CLK0_SW1_CL0_CNTL_BASE_IDX 5 7060 #define regHST_CLK0_SW1_CL1_CNTL 0x4161 7061 #define regHST_CLK0_SW1_CL1_CNTL_BASE_IDX 5 7062 #define regHST_CLK0_SW1_CL2_CNTL 0x4162 7063 #define regHST_CLK0_SW1_CL2_CNTL_BASE_IDX 5 7064 #define regDMA_CLK0_SW0_CL0_CNTL 0x4240 7065 #define regDMA_CLK0_SW0_CL0_CNTL_BASE_IDX 5 7066 #define regDMA_CLK0_SW0_CL1_CNTL 0x4241 7067 #define regDMA_CLK0_SW0_CL1_CNTL_BASE_IDX 5 7068 #define regNIC400_1_ASIB_0_FN_MOD 0xc042 7069 #define regNIC400_1_ASIB_0_FN_MOD_BASE_IDX 5 7070 #define regNIC400_1_IB_0_FN_MOD 0xfc42 7071 #define regNIC400_1_IB_0_FN_MOD_BASE_IDX 5 7072 #define regNIC400_2_ASIB_0_FN_MOD 0x10c42 7073 #define regNIC400_2_ASIB_0_FN_MOD_BASE_IDX 5 7074 #define regNIC400_2_ASIB_0_QOS_CNTL 0x10c43 7075 #define regNIC400_2_ASIB_0_QOS_CNTL_BASE_IDX 5 7076 #define regNIC400_2_ASIB_0_MAX_OT 0x10c44 7077 #define regNIC400_2_ASIB_0_MAX_OT_BASE_IDX 5 7078 #define regNIC400_2_ASIB_0_MAX_COMB_OT 0x10c45 7079 #define regNIC400_2_ASIB_0_MAX_COMB_OT_BASE_IDX 5 7080 #define regNIC400_2_ASIB_0_AW_P 0x10c46 7081 #define regNIC400_2_ASIB_0_AW_P_BASE_IDX 5 7082 #define regNIC400_2_ASIB_0_AW_B 0x10c47 7083 #define regNIC400_2_ASIB_0_AW_B_BASE_IDX 5 7084 #define regNIC400_2_ASIB_0_AW_R 0x10c48 7085 #define regNIC400_2_ASIB_0_AW_R_BASE_IDX 5 7086 #define regNIC400_2_ASIB_0_AR_P 0x10c49 7087 #define regNIC400_2_ASIB_0_AR_P_BASE_IDX 5 7088 #define regNIC400_2_ASIB_0_AR_B 0x10c4a 7089 #define regNIC400_2_ASIB_0_AR_B_BASE_IDX 5 7090 #define regNIC400_2_ASIB_0_AR_R 0x10c4b 7091 #define regNIC400_2_ASIB_0_AR_R_BASE_IDX 5 7092 #define regNIC400_2_ASIB_0_TARGET_FC 0x10c4c 7093 #define regNIC400_2_ASIB_0_TARGET_FC_BASE_IDX 5 7094 #define regNIC400_2_ASIB_0_KI_FC 0x10c4d 7095 #define regNIC400_2_ASIB_0_KI_FC_BASE_IDX 5 7096 #define regNIC400_2_ASIB_0_QOS_RANGE 0x10c4e 7097 #define regNIC400_2_ASIB_0_QOS_RANGE_BASE_IDX 5 7098 #define regNIC400_2_ASIB_1_FN_MOD 0x11042 7099 #define regNIC400_2_ASIB_1_FN_MOD_BASE_IDX 5 7100 #define regNIC400_2_ASIB_1_QOS_CNTL 0x11043 7101 #define regNIC400_2_ASIB_1_QOS_CNTL_BASE_IDX 5 7102 #define regNIC400_2_ASIB_1_MAX_OT 0x11044 7103 #define regNIC400_2_ASIB_1_MAX_OT_BASE_IDX 5 7104 #define regNIC400_2_ASIB_1_MAX_COMB_OT 0x11045 7105 #define regNIC400_2_ASIB_1_MAX_COMB_OT_BASE_IDX 5 7106 #define regNIC400_2_ASIB_1_AW_P 0x11046 7107 #define regNIC400_2_ASIB_1_AW_P_BASE_IDX 5 7108 #define regNIC400_2_ASIB_1_AW_B 0x11047 7109 #define regNIC400_2_ASIB_1_AW_B_BASE_IDX 5 7110 #define regNIC400_2_ASIB_1_AW_R 0x11048 7111 #define regNIC400_2_ASIB_1_AW_R_BASE_IDX 5 7112 #define regNIC400_2_ASIB_1_AR_P 0x11049 7113 #define regNIC400_2_ASIB_1_AR_P_BASE_IDX 5 7114 #define regNIC400_2_ASIB_1_AR_B 0x1104a 7115 #define regNIC400_2_ASIB_1_AR_B_BASE_IDX 5 7116 #define regNIC400_2_ASIB_1_AR_R 0x1104b 7117 #define regNIC400_2_ASIB_1_AR_R_BASE_IDX 5 7118 #define regNIC400_2_ASIB_1_TARGET_FC 0x1104c 7119 #define regNIC400_2_ASIB_1_TARGET_FC_BASE_IDX 5 7120 #define regNIC400_2_ASIB_1_KI_FC 0x1104d 7121 #define regNIC400_2_ASIB_1_KI_FC_BASE_IDX 5 7122 #define regNIC400_2_ASIB_1_QOS_RANGE 0x1104e 7123 #define regNIC400_2_ASIB_1_QOS_RANGE_BASE_IDX 5 7124 #define regNIC400_2_IB_0_FN_MOD 0x13c42 7125 #define regNIC400_2_IB_0_FN_MOD_BASE_IDX 5 7126 7127 7128 // addressBlock: aid_nbio_iohub_nb_nbcfg_nb_cfgdec 7129 // base address: 0x13b00000 7130 #define regNB_NBCFG0_NBCFG_SCRATCH_4 0xe8001e 7131 #define regNB_NBCFG0_NBCFG_SCRATCH_4_BASE_IDX 8 7132 7133 7134 // addressBlock: aid_nbio_iohub_nb_misc_misc_cfgdec 7135 // base address: 0x13b10000 7136 #define regNB_CNTL 0xe84000 7137 #define regNB_CNTL_BASE_IDX 8 7138 #define regNB_SPARE1 0xe84003 7139 #define regNB_SPARE1_BASE_IDX 8 7140 #define regNB_SPARE2 0xe84004 7141 #define regNB_SPARE2_BASE_IDX 8 7142 #define regNB_REVID 0xe84005 7143 #define regNB_REVID_BASE_IDX 8 7144 #define regNBIO_LCLK_DS_MASK 0xe84009 7145 #define regNBIO_LCLK_DS_MASK_BASE_IDX 8 7146 #define regNB_BUS_NUM_CNTL 0xe84011 7147 #define regNB_BUS_NUM_CNTL_BASE_IDX 8 7148 #define regNB_MMIOBASE 0xe84017 7149 #define regNB_MMIOBASE_BASE_IDX 8 7150 #define regNB_MMIOLIMIT 0xe84018 7151 #define regNB_MMIOLIMIT_BASE_IDX 8 7152 #define regNB_LOWER_TOP_OF_DRAM2 0xe84019 7153 #define regNB_LOWER_TOP_OF_DRAM2_BASE_IDX 8 7154 #define regNB_UPPER_TOP_OF_DRAM2 0xe8401a 7155 #define regNB_UPPER_TOP_OF_DRAM2_BASE_IDX 8 7156 #define regNB_LOWER_DRAM2_BASE 0xe8401b 7157 #define regNB_LOWER_DRAM2_BASE_BASE_IDX 8 7158 #define regNB_UPPER_DRAM2_BASE 0xe8401c 7159 #define regNB_UPPER_DRAM2_BASE_BASE_IDX 8 7160 #define regSB_LOCATION 0xe8401f 7161 #define regSB_LOCATION_BASE_IDX 8 7162 #define regSW_US_LOCATION 0xe84020 7163 #define regSW_US_LOCATION_BASE_IDX 8 7164 #define regNB_PROG_DEVICE_REMAP_PBr0 0xe8402e 7165 #define regNB_PROG_DEVICE_REMAP_PBr0_BASE_IDX 8 7166 #define regNB_PROG_DEVICE_REMAP_PBr1 0xe8402f 7167 #define regNB_PROG_DEVICE_REMAP_PBr1_BASE_IDX 8 7168 #define regNB_PROG_DEVICE_REMAP_PBr2 0xe84030 7169 #define regNB_PROG_DEVICE_REMAP_PBr2_BASE_IDX 8 7170 #define regNB_PROG_DEVICE_REMAP_PBr3 0xe84031 7171 #define regNB_PROG_DEVICE_REMAP_PBr3_BASE_IDX 8 7172 #define regNB_PROG_DEVICE_REMAP_PBr4 0xe84032 7173 #define regNB_PROG_DEVICE_REMAP_PBr4_BASE_IDX 8 7174 #define regNB_PROG_DEVICE_REMAP_PBr5 0xe84033 7175 #define regNB_PROG_DEVICE_REMAP_PBr5_BASE_IDX 8 7176 #define regNB_PROG_DEVICE_REMAP_PBr6 0xe84034 7177 #define regNB_PROG_DEVICE_REMAP_PBr6_BASE_IDX 8 7178 #define regNB_PROG_DEVICE_REMAP_PBr7 0xe84035 7179 #define regNB_PROG_DEVICE_REMAP_PBr7_BASE_IDX 8 7180 #define regNB_PROG_DEVICE_REMAP_PBr8 0xe84036 7181 #define regNB_PROG_DEVICE_REMAP_PBr8_BASE_IDX 8 7182 #define regNB_PROG_DEVICE_REMAP_PBr10 0xe84038 7183 #define regNB_PROG_DEVICE_REMAP_PBr10_BASE_IDX 8 7184 #define regNB_PROG_DEVICE_REMAP_PBr11 0xe84039 7185 #define regNB_PROG_DEVICE_REMAP_PBr11_BASE_IDX 8 7186 #define regNB_PROG_DEVICE_REMAP_PBr12 0xe8403a 7187 #define regNB_PROG_DEVICE_REMAP_PBr12_BASE_IDX 8 7188 #define regNB_PROG_DEVICE_REMAP_PBr13 0xe8403b 7189 #define regNB_PROG_DEVICE_REMAP_PBr13_BASE_IDX 8 7190 #define regSW_NMI_CNTL 0xe84042 7191 #define regSW_NMI_CNTL_BASE_IDX 8 7192 #define regSW_SMI_CNTL 0xe84043 7193 #define regSW_SMI_CNTL_BASE_IDX 8 7194 #define regSW_SCI_CNTL 0xe84044 7195 #define regSW_SCI_CNTL_BASE_IDX 8 7196 #define regAPML_SW_STATUS 0xe84045 7197 #define regAPML_SW_STATUS_BASE_IDX 8 7198 #define regSW_GIC_SPI_CNTL 0xe84047 7199 #define regSW_GIC_SPI_CNTL_BASE_IDX 8 7200 #define regSW_SYNCFLOOD_CNTL 0xe84049 7201 #define regSW_SYNCFLOOD_CNTL_BASE_IDX 8 7202 #define regNB_TOP_OF_DRAM3 0xe8404e 7203 #define regNB_TOP_OF_DRAM3_BASE_IDX 8 7204 #define regCAM_CONTROL 0xe84052 7205 #define regCAM_CONTROL_BASE_IDX 8 7206 #define regCAM_TARGET_INDEX_ADDR_BOTTOM 0xe84053 7207 #define regCAM_TARGET_INDEX_ADDR_BOTTOM_BASE_IDX 8 7208 #define regCAM_TARGET_INDEX_ADDR_TOP 0xe84054 7209 #define regCAM_TARGET_INDEX_ADDR_TOP_BASE_IDX 8 7210 #define regCAM_TARGET_INDEX_DATA 0xe84055 7211 #define regCAM_TARGET_INDEX_DATA_BASE_IDX 8 7212 #define regCAM_TARGET_INDEX_DATA_MASK 0xe84056 7213 #define regCAM_TARGET_INDEX_DATA_MASK_BASE_IDX 8 7214 #define regCAM_TARGET_DATA_ADDR_BOTTOM 0xe84057 7215 #define regCAM_TARGET_DATA_ADDR_BOTTOM_BASE_IDX 8 7216 #define regCAM_TARGET_DATA_ADDR_TOP 0xe84059 7217 #define regCAM_TARGET_DATA_ADDR_TOP_BASE_IDX 8 7218 #define regCAM_TARGET_DATA 0xe8405a 7219 #define regCAM_TARGET_DATA_BASE_IDX 8 7220 #define regCAM_TARGET_DATA_MASK 0xe8405b 7221 #define regCAM_TARGET_DATA_MASK_BASE_IDX 8 7222 #define regP_DMA_DROPPED_LOG_LOWER 0xe84060 7223 #define regP_DMA_DROPPED_LOG_LOWER_BASE_IDX 8 7224 #define regP_DMA_DROPPED_LOG_UPPER 0xe84061 7225 #define regP_DMA_DROPPED_LOG_UPPER_BASE_IDX 8 7226 #define regNP_DMA_DROPPED_LOG_LOWER 0xe84062 7227 #define regNP_DMA_DROPPED_LOG_LOWER_BASE_IDX 8 7228 #define regNP_DMA_DROPPED_LOG_UPPER 0xe84063 7229 #define regNP_DMA_DROPPED_LOG_UPPER_BASE_IDX 8 7230 #define regPCIE_VDM_NODE0_CTRL4 0xe84064 7231 #define regPCIE_VDM_NODE0_CTRL4_BASE_IDX 8 7232 #define regPCIE_VDM_CNTL2 0xe8408c 7233 #define regPCIE_VDM_CNTL2_BASE_IDX 8 7234 #define regPCIE_VDM_CNTL3 0xe8408d 7235 #define regPCIE_VDM_CNTL3_BASE_IDX 8 7236 #define regSTALL_CONTROL_XBARPORT0_0 0xe84090 7237 #define regSTALL_CONTROL_XBARPORT0_0_BASE_IDX 8 7238 #define regSTALL_CONTROL_XBARPORT0_1 0xe84091 7239 #define regSTALL_CONTROL_XBARPORT0_1_BASE_IDX 8 7240 #define regSTALL_CONTROL_XBARPORT1_0 0xe84093 7241 #define regSTALL_CONTROL_XBARPORT1_0_BASE_IDX 8 7242 #define regSTALL_CONTROL_XBARPORT1_1 0xe84094 7243 #define regSTALL_CONTROL_XBARPORT1_1_BASE_IDX 8 7244 #define regSTALL_CONTROL_XBARPORT2_0 0xe84096 7245 #define regSTALL_CONTROL_XBARPORT2_0_BASE_IDX 8 7246 #define regSTALL_CONTROL_XBARPORT2_1 0xe84097 7247 #define regSTALL_CONTROL_XBARPORT2_1_BASE_IDX 8 7248 #define regSTALL_CONTROL_XBARPORT3_0 0xe84099 7249 #define regSTALL_CONTROL_XBARPORT3_0_BASE_IDX 8 7250 #define regSTALL_CONTROL_XBARPORT3_1 0xe8409a 7251 #define regSTALL_CONTROL_XBARPORT3_1_BASE_IDX 8 7252 #define regSTALL_CONTROL_XBARPORT4_0 0xe8409c 7253 #define regSTALL_CONTROL_XBARPORT4_0_BASE_IDX 8 7254 #define regSTALL_CONTROL_XBARPORT4_1 0xe8409d 7255 #define regSTALL_CONTROL_XBARPORT4_1_BASE_IDX 8 7256 #define regSTALL_CONTROL_XBARPORT5_0 0xe8409f 7257 #define regSTALL_CONTROL_XBARPORT5_0_BASE_IDX 8 7258 #define regSTALL_CONTROL_XBARPORT5_1 0xe840a0 7259 #define regSTALL_CONTROL_XBARPORT5_1_BASE_IDX 8 7260 #define regNB_DRAM3_BASE 0xe840b1 7261 #define regNB_DRAM3_BASE_BASE_IDX 8 7262 #define regPSP_BASE_ADDR_LO 0xe840b8 7263 #define regPSP_BASE_ADDR_LO_BASE_IDX 8 7264 #define regPSP_BASE_ADDR_HI 0xe840b9 7265 #define regPSP_BASE_ADDR_HI_BASE_IDX 8 7266 #define regSMU_BASE_ADDR_LO 0xe840ba 7267 #define regSMU_BASE_ADDR_LO_BASE_IDX 8 7268 #define regSMU_BASE_ADDR_HI 0xe840bb 7269 #define regSMU_BASE_ADDR_HI_BASE_IDX 8 7270 #define regSCRATCH_4 0xe840fc 7271 #define regSCRATCH_4_BASE_IDX 8 7272 #define regSCRATCH_5 0xe840fd 7273 #define regSCRATCH_5_BASE_IDX 8 7274 #define regSMU_BLOCK_CPU 0xe840fe 7275 #define regSMU_BLOCK_CPU_BASE_IDX 8 7276 #define regSMU_BLOCK_CPU_STATUS 0xe840ff 7277 #define regSMU_BLOCK_CPU_STATUS_BASE_IDX 8 7278 #define regTRAP_STATUS 0xe84100 7279 #define regTRAP_STATUS_BASE_IDX 8 7280 #define regTRAP_REQUEST0 0xe84101 7281 #define regTRAP_REQUEST0_BASE_IDX 8 7282 #define regTRAP_REQUEST1 0xe84102 7283 #define regTRAP_REQUEST1_BASE_IDX 8 7284 #define regTRAP_REQUEST2 0xe84103 7285 #define regTRAP_REQUEST2_BASE_IDX 8 7286 #define regTRAP_REQUEST3 0xe84104 7287 #define regTRAP_REQUEST3_BASE_IDX 8 7288 #define regTRAP_REQUEST4 0xe84105 7289 #define regTRAP_REQUEST4_BASE_IDX 8 7290 #define regTRAP_REQUEST5 0xe84106 7291 #define regTRAP_REQUEST5_BASE_IDX 8 7292 #define regTRAP_REQUEST_DATASTRB0 0xe84108 7293 #define regTRAP_REQUEST_DATASTRB0_BASE_IDX 8 7294 #define regTRAP_REQUEST_DATASTRB1 0xe84109 7295 #define regTRAP_REQUEST_DATASTRB1_BASE_IDX 8 7296 #define regTRAP_REQUEST_DATA0 0xe84110 7297 #define regTRAP_REQUEST_DATA0_BASE_IDX 8 7298 #define regTRAP_REQUEST_DATA1 0xe84111 7299 #define regTRAP_REQUEST_DATA1_BASE_IDX 8 7300 #define regTRAP_REQUEST_DATA2 0xe84112 7301 #define regTRAP_REQUEST_DATA2_BASE_IDX 8 7302 #define regTRAP_REQUEST_DATA3 0xe84113 7303 #define regTRAP_REQUEST_DATA3_BASE_IDX 8 7304 #define regTRAP_REQUEST_DATA4 0xe84114 7305 #define regTRAP_REQUEST_DATA4_BASE_IDX 8 7306 #define regTRAP_REQUEST_DATA5 0xe84115 7307 #define regTRAP_REQUEST_DATA5_BASE_IDX 8 7308 #define regTRAP_REQUEST_DATA6 0xe84116 7309 #define regTRAP_REQUEST_DATA6_BASE_IDX 8 7310 #define regTRAP_REQUEST_DATA7 0xe84117 7311 #define regTRAP_REQUEST_DATA7_BASE_IDX 8 7312 #define regTRAP_REQUEST_DATA8 0xe84118 7313 #define regTRAP_REQUEST_DATA8_BASE_IDX 8 7314 #define regTRAP_REQUEST_DATA9 0xe84119 7315 #define regTRAP_REQUEST_DATA9_BASE_IDX 8 7316 #define regTRAP_REQUEST_DATA10 0xe8411a 7317 #define regTRAP_REQUEST_DATA10_BASE_IDX 8 7318 #define regTRAP_REQUEST_DATA11 0xe8411b 7319 #define regTRAP_REQUEST_DATA11_BASE_IDX 8 7320 #define regTRAP_REQUEST_DATA12 0xe8411c 7321 #define regTRAP_REQUEST_DATA12_BASE_IDX 8 7322 #define regTRAP_REQUEST_DATA13 0xe8411d 7323 #define regTRAP_REQUEST_DATA13_BASE_IDX 8 7324 #define regTRAP_REQUEST_DATA14 0xe8411e 7325 #define regTRAP_REQUEST_DATA14_BASE_IDX 8 7326 #define regTRAP_REQUEST_DATA15 0xe8411f 7327 #define regTRAP_REQUEST_DATA15_BASE_IDX 8 7328 #define regTRAP_RESPONSE_CONTROL 0xe84130 7329 #define regTRAP_RESPONSE_CONTROL_BASE_IDX 8 7330 #define regTRAP_RESPONSE0 0xe84131 7331 #define regTRAP_RESPONSE0_BASE_IDX 8 7332 #define regTRAP_RESPONSE_DATA0 0xe84140 7333 #define regTRAP_RESPONSE_DATA0_BASE_IDX 8 7334 #define regTRAP_RESPONSE_DATA1 0xe84141 7335 #define regTRAP_RESPONSE_DATA1_BASE_IDX 8 7336 #define regTRAP_RESPONSE_DATA2 0xe84142 7337 #define regTRAP_RESPONSE_DATA2_BASE_IDX 8 7338 #define regTRAP_RESPONSE_DATA3 0xe84143 7339 #define regTRAP_RESPONSE_DATA3_BASE_IDX 8 7340 #define regTRAP_RESPONSE_DATA4 0xe84144 7341 #define regTRAP_RESPONSE_DATA4_BASE_IDX 8 7342 #define regTRAP_RESPONSE_DATA5 0xe84145 7343 #define regTRAP_RESPONSE_DATA5_BASE_IDX 8 7344 #define regTRAP_RESPONSE_DATA6 0xe84146 7345 #define regTRAP_RESPONSE_DATA6_BASE_IDX 8 7346 #define regTRAP_RESPONSE_DATA7 0xe84147 7347 #define regTRAP_RESPONSE_DATA7_BASE_IDX 8 7348 #define regTRAP_RESPONSE_DATA8 0xe84148 7349 #define regTRAP_RESPONSE_DATA8_BASE_IDX 8 7350 #define regTRAP_RESPONSE_DATA9 0xe84149 7351 #define regTRAP_RESPONSE_DATA9_BASE_IDX 8 7352 #define regTRAP_RESPONSE_DATA10 0xe8414a 7353 #define regTRAP_RESPONSE_DATA10_BASE_IDX 8 7354 #define regTRAP_RESPONSE_DATA11 0xe8414b 7355 #define regTRAP_RESPONSE_DATA11_BASE_IDX 8 7356 #define regTRAP_RESPONSE_DATA12 0xe8414c 7357 #define regTRAP_RESPONSE_DATA12_BASE_IDX 8 7358 #define regTRAP_RESPONSE_DATA13 0xe8414d 7359 #define regTRAP_RESPONSE_DATA13_BASE_IDX 8 7360 #define regTRAP_RESPONSE_DATA14 0xe8414e 7361 #define regTRAP_RESPONSE_DATA14_BASE_IDX 8 7362 #define regTRAP_RESPONSE_DATA15 0xe8414f 7363 #define regTRAP_RESPONSE_DATA15_BASE_IDX 8 7364 #define regTRAP0_CONTROL0 0xe84200 7365 #define regTRAP0_CONTROL0_BASE_IDX 8 7366 #define regTRAP0_ADDRESS_LO 0xe84202 7367 #define regTRAP0_ADDRESS_LO_BASE_IDX 8 7368 #define regTRAP0_ADDRESS_HI 0xe84203 7369 #define regTRAP0_ADDRESS_HI_BASE_IDX 8 7370 #define regTRAP0_COMMAND 0xe84204 7371 #define regTRAP0_COMMAND_BASE_IDX 8 7372 #define regTRAP0_ADDRESS_LO_MASK 0xe84206 7373 #define regTRAP0_ADDRESS_LO_MASK_BASE_IDX 8 7374 #define regTRAP0_ADDRESS_HI_MASK 0xe84207 7375 #define regTRAP0_ADDRESS_HI_MASK_BASE_IDX 8 7376 #define regTRAP0_COMMAND_MASK 0xe84208 7377 #define regTRAP0_COMMAND_MASK_BASE_IDX 8 7378 #define regTRAP1_CONTROL0 0xe84210 7379 #define regTRAP1_CONTROL0_BASE_IDX 8 7380 #define regTRAP1_ADDRESS_LO 0xe84212 7381 #define regTRAP1_ADDRESS_LO_BASE_IDX 8 7382 #define regTRAP1_ADDRESS_HI 0xe84213 7383 #define regTRAP1_ADDRESS_HI_BASE_IDX 8 7384 #define regTRAP1_COMMAND 0xe84214 7385 #define regTRAP1_COMMAND_BASE_IDX 8 7386 #define regTRAP1_ADDRESS_LO_MASK 0xe84216 7387 #define regTRAP1_ADDRESS_LO_MASK_BASE_IDX 8 7388 #define regTRAP1_ADDRESS_HI_MASK 0xe84217 7389 #define regTRAP1_ADDRESS_HI_MASK_BASE_IDX 8 7390 #define regTRAP1_COMMAND_MASK 0xe84218 7391 #define regTRAP1_COMMAND_MASK_BASE_IDX 8 7392 #define regTRAP2_CONTROL0 0xe84220 7393 #define regTRAP2_CONTROL0_BASE_IDX 8 7394 #define regTRAP2_ADDRESS_LO 0xe84222 7395 #define regTRAP2_ADDRESS_LO_BASE_IDX 8 7396 #define regTRAP2_ADDRESS_HI 0xe84223 7397 #define regTRAP2_ADDRESS_HI_BASE_IDX 8 7398 #define regTRAP2_COMMAND 0xe84224 7399 #define regTRAP2_COMMAND_BASE_IDX 8 7400 #define regTRAP2_ADDRESS_LO_MASK 0xe84226 7401 #define regTRAP2_ADDRESS_LO_MASK_BASE_IDX 8 7402 #define regTRAP2_ADDRESS_HI_MASK 0xe84227 7403 #define regTRAP2_ADDRESS_HI_MASK_BASE_IDX 8 7404 #define regTRAP2_COMMAND_MASK 0xe84228 7405 #define regTRAP2_COMMAND_MASK_BASE_IDX 8 7406 #define regTRAP3_CONTROL0 0xe84230 7407 #define regTRAP3_CONTROL0_BASE_IDX 8 7408 #define regTRAP3_ADDRESS_LO 0xe84232 7409 #define regTRAP3_ADDRESS_LO_BASE_IDX 8 7410 #define regTRAP3_ADDRESS_HI 0xe84233 7411 #define regTRAP3_ADDRESS_HI_BASE_IDX 8 7412 #define regTRAP3_COMMAND 0xe84234 7413 #define regTRAP3_COMMAND_BASE_IDX 8 7414 #define regTRAP3_ADDRESS_LO_MASK 0xe84236 7415 #define regTRAP3_ADDRESS_LO_MASK_BASE_IDX 8 7416 #define regTRAP3_ADDRESS_HI_MASK 0xe84237 7417 #define regTRAP3_ADDRESS_HI_MASK_BASE_IDX 8 7418 #define regTRAP3_COMMAND_MASK 0xe84238 7419 #define regTRAP3_COMMAND_MASK_BASE_IDX 8 7420 #define regTRAP4_CONTROL0 0xe84240 7421 #define regTRAP4_CONTROL0_BASE_IDX 8 7422 #define regTRAP4_ADDRESS_LO 0xe84242 7423 #define regTRAP4_ADDRESS_LO_BASE_IDX 8 7424 #define regTRAP4_ADDRESS_HI 0xe84243 7425 #define regTRAP4_ADDRESS_HI_BASE_IDX 8 7426 #define regTRAP4_COMMAND 0xe84244 7427 #define regTRAP4_COMMAND_BASE_IDX 8 7428 #define regTRAP4_ADDRESS_LO_MASK 0xe84246 7429 #define regTRAP4_ADDRESS_LO_MASK_BASE_IDX 8 7430 #define regTRAP4_ADDRESS_HI_MASK 0xe84247 7431 #define regTRAP4_ADDRESS_HI_MASK_BASE_IDX 8 7432 #define regTRAP4_COMMAND_MASK 0xe84248 7433 #define regTRAP4_COMMAND_MASK_BASE_IDX 8 7434 #define regTRAP5_CONTROL0 0xe84250 7435 #define regTRAP5_CONTROL0_BASE_IDX 8 7436 #define regTRAP5_ADDRESS_LO 0xe84252 7437 #define regTRAP5_ADDRESS_LO_BASE_IDX 8 7438 #define regTRAP5_ADDRESS_HI 0xe84253 7439 #define regTRAP5_ADDRESS_HI_BASE_IDX 8 7440 #define regTRAP5_COMMAND 0xe84254 7441 #define regTRAP5_COMMAND_BASE_IDX 8 7442 #define regTRAP5_ADDRESS_LO_MASK 0xe84256 7443 #define regTRAP5_ADDRESS_LO_MASK_BASE_IDX 8 7444 #define regTRAP5_ADDRESS_HI_MASK 0xe84257 7445 #define regTRAP5_ADDRESS_HI_MASK_BASE_IDX 8 7446 #define regTRAP5_COMMAND_MASK 0xe84258 7447 #define regTRAP5_COMMAND_MASK_BASE_IDX 8 7448 #define regTRAP6_CONTROL0 0xe84260 7449 #define regTRAP6_CONTROL0_BASE_IDX 8 7450 #define regTRAP6_ADDRESS_LO 0xe84262 7451 #define regTRAP6_ADDRESS_LO_BASE_IDX 8 7452 #define regTRAP6_ADDRESS_HI 0xe84263 7453 #define regTRAP6_ADDRESS_HI_BASE_IDX 8 7454 #define regTRAP6_COMMAND 0xe84264 7455 #define regTRAP6_COMMAND_BASE_IDX 8 7456 #define regTRAP6_ADDRESS_LO_MASK 0xe84266 7457 #define regTRAP6_ADDRESS_LO_MASK_BASE_IDX 8 7458 #define regTRAP6_ADDRESS_HI_MASK 0xe84267 7459 #define regTRAP6_ADDRESS_HI_MASK_BASE_IDX 8 7460 #define regTRAP6_COMMAND_MASK 0xe84268 7461 #define regTRAP6_COMMAND_MASK_BASE_IDX 8 7462 #define regTRAP7_CONTROL0 0xe84270 7463 #define regTRAP7_CONTROL0_BASE_IDX 8 7464 #define regTRAP7_ADDRESS_LO 0xe84272 7465 #define regTRAP7_ADDRESS_LO_BASE_IDX 8 7466 #define regTRAP7_ADDRESS_HI 0xe84273 7467 #define regTRAP7_ADDRESS_HI_BASE_IDX 8 7468 #define regTRAP7_COMMAND 0xe84274 7469 #define regTRAP7_COMMAND_BASE_IDX 8 7470 #define regTRAP7_ADDRESS_LO_MASK 0xe84276 7471 #define regTRAP7_ADDRESS_LO_MASK_BASE_IDX 8 7472 #define regTRAP7_ADDRESS_HI_MASK 0xe84277 7473 #define regTRAP7_ADDRESS_HI_MASK_BASE_IDX 8 7474 #define regTRAP7_COMMAND_MASK 0xe84278 7475 #define regTRAP7_COMMAND_MASK_BASE_IDX 8 7476 #define regTRAP8_CONTROL0 0xe84280 7477 #define regTRAP8_CONTROL0_BASE_IDX 8 7478 #define regTRAP8_ADDRESS_LO 0xe84282 7479 #define regTRAP8_ADDRESS_LO_BASE_IDX 8 7480 #define regTRAP8_ADDRESS_HI 0xe84283 7481 #define regTRAP8_ADDRESS_HI_BASE_IDX 8 7482 #define regTRAP8_COMMAND 0xe84284 7483 #define regTRAP8_COMMAND_BASE_IDX 8 7484 #define regTRAP8_ADDRESS_LO_MASK 0xe84286 7485 #define regTRAP8_ADDRESS_LO_MASK_BASE_IDX 8 7486 #define regTRAP8_ADDRESS_HI_MASK 0xe84287 7487 #define regTRAP8_ADDRESS_HI_MASK_BASE_IDX 8 7488 #define regTRAP8_COMMAND_MASK 0xe84288 7489 #define regTRAP8_COMMAND_MASK_BASE_IDX 8 7490 #define regTRAP9_CONTROL0 0xe84290 7491 #define regTRAP9_CONTROL0_BASE_IDX 8 7492 #define regTRAP9_ADDRESS_LO 0xe84292 7493 #define regTRAP9_ADDRESS_LO_BASE_IDX 8 7494 #define regTRAP9_ADDRESS_HI 0xe84293 7495 #define regTRAP9_ADDRESS_HI_BASE_IDX 8 7496 #define regTRAP9_COMMAND 0xe84294 7497 #define regTRAP9_COMMAND_BASE_IDX 8 7498 #define regTRAP9_ADDRESS_LO_MASK 0xe84296 7499 #define regTRAP9_ADDRESS_LO_MASK_BASE_IDX 8 7500 #define regTRAP9_ADDRESS_HI_MASK 0xe84297 7501 #define regTRAP9_ADDRESS_HI_MASK_BASE_IDX 8 7502 #define regTRAP9_COMMAND_MASK 0xe84298 7503 #define regTRAP9_COMMAND_MASK_BASE_IDX 8 7504 #define regTRAP10_CONTROL0 0xe842a0 7505 #define regTRAP10_CONTROL0_BASE_IDX 8 7506 #define regTRAP10_ADDRESS_LO 0xe842a2 7507 #define regTRAP10_ADDRESS_LO_BASE_IDX 8 7508 #define regTRAP10_ADDRESS_HI 0xe842a3 7509 #define regTRAP10_ADDRESS_HI_BASE_IDX 8 7510 #define regTRAP10_COMMAND 0xe842a4 7511 #define regTRAP10_COMMAND_BASE_IDX 8 7512 #define regTRAP10_ADDRESS_LO_MASK 0xe842a6 7513 #define regTRAP10_ADDRESS_LO_MASK_BASE_IDX 8 7514 #define regTRAP10_ADDRESS_HI_MASK 0xe842a7 7515 #define regTRAP10_ADDRESS_HI_MASK_BASE_IDX 8 7516 #define regTRAP10_COMMAND_MASK 0xe842a8 7517 #define regTRAP10_COMMAND_MASK_BASE_IDX 8 7518 #define regTRAP11_CONTROL0 0xe842b0 7519 #define regTRAP11_CONTROL0_BASE_IDX 8 7520 #define regTRAP11_ADDRESS_LO 0xe842b2 7521 #define regTRAP11_ADDRESS_LO_BASE_IDX 8 7522 #define regTRAP11_ADDRESS_HI 0xe842b3 7523 #define regTRAP11_ADDRESS_HI_BASE_IDX 8 7524 #define regTRAP11_COMMAND 0xe842b4 7525 #define regTRAP11_COMMAND_BASE_IDX 8 7526 #define regTRAP11_ADDRESS_LO_MASK 0xe842b6 7527 #define regTRAP11_ADDRESS_LO_MASK_BASE_IDX 8 7528 #define regTRAP11_ADDRESS_HI_MASK 0xe842b7 7529 #define regTRAP11_ADDRESS_HI_MASK_BASE_IDX 8 7530 #define regTRAP11_COMMAND_MASK 0xe842b8 7531 #define regTRAP11_COMMAND_MASK_BASE_IDX 8 7532 #define regTRAP12_CONTROL0 0xe842c0 7533 #define regTRAP12_CONTROL0_BASE_IDX 8 7534 #define regTRAP12_ADDRESS_LO 0xe842c2 7535 #define regTRAP12_ADDRESS_LO_BASE_IDX 8 7536 #define regTRAP12_ADDRESS_HI 0xe842c3 7537 #define regTRAP12_ADDRESS_HI_BASE_IDX 8 7538 #define regTRAP12_COMMAND 0xe842c4 7539 #define regTRAP12_COMMAND_BASE_IDX 8 7540 #define regTRAP12_ADDRESS_LO_MASK 0xe842c6 7541 #define regTRAP12_ADDRESS_LO_MASK_BASE_IDX 8 7542 #define regTRAP12_ADDRESS_HI_MASK 0xe842c7 7543 #define regTRAP12_ADDRESS_HI_MASK_BASE_IDX 8 7544 #define regTRAP12_COMMAND_MASK 0xe842c8 7545 #define regTRAP12_COMMAND_MASK_BASE_IDX 8 7546 #define regTRAP13_CONTROL0 0xe842d0 7547 #define regTRAP13_CONTROL0_BASE_IDX 8 7548 #define regTRAP13_ADDRESS_LO 0xe842d2 7549 #define regTRAP13_ADDRESS_LO_BASE_IDX 8 7550 #define regTRAP13_ADDRESS_HI 0xe842d3 7551 #define regTRAP13_ADDRESS_HI_BASE_IDX 8 7552 #define regTRAP13_COMMAND 0xe842d4 7553 #define regTRAP13_COMMAND_BASE_IDX 8 7554 #define regTRAP13_ADDRESS_LO_MASK 0xe842d6 7555 #define regTRAP13_ADDRESS_LO_MASK_BASE_IDX 8 7556 #define regTRAP13_ADDRESS_HI_MASK 0xe842d7 7557 #define regTRAP13_ADDRESS_HI_MASK_BASE_IDX 8 7558 #define regTRAP13_COMMAND_MASK 0xe842d8 7559 #define regTRAP13_COMMAND_MASK_BASE_IDX 8 7560 #define regTRAP14_CONTROL0 0xe842e0 7561 #define regTRAP14_CONTROL0_BASE_IDX 8 7562 #define regTRAP14_ADDRESS_LO 0xe842e2 7563 #define regTRAP14_ADDRESS_LO_BASE_IDX 8 7564 #define regTRAP14_ADDRESS_HI 0xe842e3 7565 #define regTRAP14_ADDRESS_HI_BASE_IDX 8 7566 #define regTRAP14_COMMAND 0xe842e4 7567 #define regTRAP14_COMMAND_BASE_IDX 8 7568 #define regTRAP14_ADDRESS_LO_MASK 0xe842e6 7569 #define regTRAP14_ADDRESS_LO_MASK_BASE_IDX 8 7570 #define regTRAP14_ADDRESS_HI_MASK 0xe842e7 7571 #define regTRAP14_ADDRESS_HI_MASK_BASE_IDX 8 7572 #define regTRAP14_COMMAND_MASK 0xe842e8 7573 #define regTRAP14_COMMAND_MASK_BASE_IDX 8 7574 #define regTRAP15_CONTROL0 0xe842f0 7575 #define regTRAP15_CONTROL0_BASE_IDX 8 7576 #define regTRAP15_ADDRESS_LO 0xe842f2 7577 #define regTRAP15_ADDRESS_LO_BASE_IDX 8 7578 #define regTRAP15_ADDRESS_HI 0xe842f3 7579 #define regTRAP15_ADDRESS_HI_BASE_IDX 8 7580 #define regTRAP15_COMMAND 0xe842f4 7581 #define regTRAP15_COMMAND_BASE_IDX 8 7582 #define regTRAP15_ADDRESS_LO_MASK 0xe842f6 7583 #define regTRAP15_ADDRESS_LO_MASK_BASE_IDX 8 7584 #define regTRAP15_ADDRESS_HI_MASK 0xe842f7 7585 #define regTRAP15_ADDRESS_HI_MASK_BASE_IDX 8 7586 #define regTRAP15_COMMAND_MASK 0xe842f8 7587 #define regTRAP15_COMMAND_MASK_BASE_IDX 8 7588 #define regSB_COMMAND 0xe85000 7589 #define regSB_COMMAND_BASE_IDX 8 7590 #define regSB_SUB_BUS_NUMBER_LATENCY 0xe85001 7591 #define regSB_SUB_BUS_NUMBER_LATENCY_BASE_IDX 8 7592 #define regSB_IO_BASE_LIMIT 0xe85002 7593 #define regSB_IO_BASE_LIMIT_BASE_IDX 8 7594 #define regSB_MEM_BASE_LIMIT 0xe85003 7595 #define regSB_MEM_BASE_LIMIT_BASE_IDX 8 7596 #define regSB_PREF_BASE_LIMIT 0xe85004 7597 #define regSB_PREF_BASE_LIMIT_BASE_IDX 8 7598 #define regSB_PREF_BASE_UPPER 0xe85005 7599 #define regSB_PREF_BASE_UPPER_BASE_IDX 8 7600 #define regSB_PREF_LIMIT_UPPER 0xe85006 7601 #define regSB_PREF_LIMIT_UPPER_BASE_IDX 8 7602 #define regSB_IO_BASE_LIMIT_HI 0xe85007 7603 #define regSB_IO_BASE_LIMIT_HI_BASE_IDX 8 7604 #define regSB_IRQ_BRIDGE_CNTL 0xe85008 7605 #define regSB_IRQ_BRIDGE_CNTL_BASE_IDX 8 7606 #define regSB_EXT_BRIDGE_CNTL 0xe85009 7607 #define regSB_EXT_BRIDGE_CNTL_BASE_IDX 8 7608 #define regSB_PMI_STATUS_CNTL 0xe8500a 7609 #define regSB_PMI_STATUS_CNTL_BASE_IDX 8 7610 #define regSB_SLOT_CAP 0xe8500b 7611 #define regSB_SLOT_CAP_BASE_IDX 8 7612 #define regSB_ROOT_CNTL 0xe8500c 7613 #define regSB_ROOT_CNTL_BASE_IDX 8 7614 #define regSB_DEVICE_CNTL2 0xe8500d 7615 #define regSB_DEVICE_CNTL2_BASE_IDX 8 7616 #define regMCA_SMN_INT_REQ_ADDR 0xe85020 7617 #define regMCA_SMN_INT_REQ_ADDR_BASE_IDX 8 7618 #define regMCA_SMN_INT_MCM_ADDR 0xe85021 7619 #define regMCA_SMN_INT_MCM_ADDR_BASE_IDX 8 7620 #define regMCA_SMN_INT_APERTUREID 0xe85022 7621 #define regMCA_SMN_INT_APERTUREID_BASE_IDX 8 7622 #define regMCA_SMN_INT_CONTROL 0xe85023 7623 #define regMCA_SMN_INT_CONTROL_BASE_IDX 8 7624 7625 7626 // addressBlock: aid_nbio_iohub_nb_rascfg_ras_cfgdec 7627 // base address: 0x13b20000 7628 #define regPARITY_CONTROL_0 0xe88000 7629 #define regPARITY_CONTROL_0_BASE_IDX 8 7630 #define regPARITY_CONTROL_1 0xe88001 7631 #define regPARITY_CONTROL_1_BASE_IDX 8 7632 #define regPARITY_SEVERITY_CONTROL_UNCORR_0 0xe88002 7633 #define regPARITY_SEVERITY_CONTROL_UNCORR_0_BASE_IDX 8 7634 #define regPARITY_SEVERITY_CONTROL_CORR_0 0xe88004 7635 #define regPARITY_SEVERITY_CONTROL_CORR_0_BASE_IDX 8 7636 #define regPARITY_SEVERITY_CONTROL_UCP_0 0xe88006 7637 #define regPARITY_SEVERITY_CONTROL_UCP_0_BASE_IDX 8 7638 #define regRAS_GLOBAL_STATUS_LO 0xe88008 7639 #define regRAS_GLOBAL_STATUS_LO_BASE_IDX 8 7640 #define regRAS_GLOBAL_STATUS_HI 0xe88009 7641 #define regRAS_GLOBAL_STATUS_HI_BASE_IDX 8 7642 #define regPARITY_ERROR_STATUS_UNCORR_GRP0 0xe8800a 7643 #define regPARITY_ERROR_STATUS_UNCORR_GRP0_BASE_IDX 8 7644 #define regPARITY_ERROR_STATUS_UNCORR_GRP1 0xe8800b 7645 #define regPARITY_ERROR_STATUS_UNCORR_GRP1_BASE_IDX 8 7646 #define regPARITY_ERROR_STATUS_UNCORR_GRP2 0xe8800c 7647 #define regPARITY_ERROR_STATUS_UNCORR_GRP2_BASE_IDX 8 7648 #define regPARITY_ERROR_STATUS_UNCORR_GRP3 0xe8800d 7649 #define regPARITY_ERROR_STATUS_UNCORR_GRP3_BASE_IDX 8 7650 #define regPARITY_ERROR_STATUS_UNCORR_GRP4 0xe8800e 7651 #define regPARITY_ERROR_STATUS_UNCORR_GRP4_BASE_IDX 8 7652 #define regPARITY_ERROR_STATUS_UNCORR_GRP5 0xe8800f 7653 #define regPARITY_ERROR_STATUS_UNCORR_GRP5_BASE_IDX 8 7654 #define regPARITY_ERROR_STATUS_UNCORR_GRP6 0xe88010 7655 #define regPARITY_ERROR_STATUS_UNCORR_GRP6_BASE_IDX 8 7656 #define regPARITY_ERROR_STATUS_UNCORR_GRP7 0xe88011 7657 #define regPARITY_ERROR_STATUS_UNCORR_GRP7_BASE_IDX 8 7658 #define regPARITY_ERROR_STATUS_UNCORR_GRP10 0xe88014 7659 #define regPARITY_ERROR_STATUS_UNCORR_GRP10_BASE_IDX 8 7660 #define regPARITY_ERROR_STATUS_UNCORR_GRP11 0xe88015 7661 #define regPARITY_ERROR_STATUS_UNCORR_GRP11_BASE_IDX 8 7662 #define regPARITY_ERROR_STATUS_UNCORR_GRP12 0xe88016 7663 #define regPARITY_ERROR_STATUS_UNCORR_GRP12_BASE_IDX 8 7664 #define regPARITY_ERROR_STATUS_UNCORR_GRP13 0xe88017 7665 #define regPARITY_ERROR_STATUS_UNCORR_GRP13_BASE_IDX 8 7666 #define regPARITY_ERROR_STATUS_UNCORR_GRP14 0xe88018 7667 #define regPARITY_ERROR_STATUS_UNCORR_GRP14_BASE_IDX 8 7668 #define regPARITY_ERROR_STATUS_UNCORR_GRP15 0xe88019 7669 #define regPARITY_ERROR_STATUS_UNCORR_GRP15_BASE_IDX 8 7670 #define regPARITY_ERROR_STATUS_UNCORR_GRP16 0xe8801a 7671 #define regPARITY_ERROR_STATUS_UNCORR_GRP16_BASE_IDX 8 7672 #define regPARITY_ERROR_STATUS_CORR_GRP0 0xe8801b 7673 #define regPARITY_ERROR_STATUS_CORR_GRP0_BASE_IDX 8 7674 #define regPARITY_ERROR_STATUS_CORR_GRP1 0xe8801c 7675 #define regPARITY_ERROR_STATUS_CORR_GRP1_BASE_IDX 8 7676 #define regPARITY_ERROR_STATUS_CORR_GRP2 0xe8801d 7677 #define regPARITY_ERROR_STATUS_CORR_GRP2_BASE_IDX 8 7678 #define regPARITY_ERROR_STATUS_CORR_GRP3 0xe8801e 7679 #define regPARITY_ERROR_STATUS_CORR_GRP3_BASE_IDX 8 7680 #define regPARITY_ERROR_STATUS_CORR_GRP4 0xe8801f 7681 #define regPARITY_ERROR_STATUS_CORR_GRP4_BASE_IDX 8 7682 #define regPARITY_ERROR_STATUS_CORR_GRP5 0xe88020 7683 #define regPARITY_ERROR_STATUS_CORR_GRP5_BASE_IDX 8 7684 #define regPARITY_ERROR_STATUS_CORR_GRP6 0xe88021 7685 #define regPARITY_ERROR_STATUS_CORR_GRP6_BASE_IDX 8 7686 #define regPARITY_ERROR_STATUS_CORR_GRP7 0xe88022 7687 #define regPARITY_ERROR_STATUS_CORR_GRP7_BASE_IDX 8 7688 #define regPARITY_ERROR_STATUS_CORR_GRP10 0xe88025 7689 #define regPARITY_ERROR_STATUS_CORR_GRP10_BASE_IDX 8 7690 #define regPARITY_ERROR_STATUS_CORR_GRP11 0xe88026 7691 #define regPARITY_ERROR_STATUS_CORR_GRP11_BASE_IDX 8 7692 #define regPARITY_ERROR_STATUS_CORR_GRP12 0xe88027 7693 #define regPARITY_ERROR_STATUS_CORR_GRP12_BASE_IDX 8 7694 #define regPARITY_ERROR_STATUS_CORR_GRP13 0xe88028 7695 #define regPARITY_ERROR_STATUS_CORR_GRP13_BASE_IDX 8 7696 #define regPARITY_ERROR_STATUS_CORR_GRP14 0xe88029 7697 #define regPARITY_ERROR_STATUS_CORR_GRP14_BASE_IDX 8 7698 #define regPARITY_ERROR_STATUS_CORR_GRP15 0xe8802a 7699 #define regPARITY_ERROR_STATUS_CORR_GRP15_BASE_IDX 8 7700 #define regPARITY_ERROR_STATUS_CORR_GRP16 0xe8802b 7701 #define regPARITY_ERROR_STATUS_CORR_GRP16_BASE_IDX 8 7702 #define regPARITY_ERROR_STATUS_CORR_GRP17 0xe8802c 7703 #define regPARITY_ERROR_STATUS_CORR_GRP17_BASE_IDX 8 7704 #define regPARITY_COUNTER_CORR_GRP0 0xe8802d 7705 #define regPARITY_COUNTER_CORR_GRP0_BASE_IDX 8 7706 #define regPARITY_COUNTER_CORR_GRP1 0xe8802e 7707 #define regPARITY_COUNTER_CORR_GRP1_BASE_IDX 8 7708 #define regPARITY_COUNTER_CORR_GRP2 0xe8802f 7709 #define regPARITY_COUNTER_CORR_GRP2_BASE_IDX 8 7710 #define regPARITY_COUNTER_CORR_GRP3 0xe88030 7711 #define regPARITY_COUNTER_CORR_GRP3_BASE_IDX 8 7712 #define regPARITY_COUNTER_CORR_GRP4 0xe88031 7713 #define regPARITY_COUNTER_CORR_GRP4_BASE_IDX 8 7714 #define regPARITY_COUNTER_CORR_GRP5 0xe88032 7715 #define regPARITY_COUNTER_CORR_GRP5_BASE_IDX 8 7716 #define regPARITY_COUNTER_CORR_GRP6 0xe88033 7717 #define regPARITY_COUNTER_CORR_GRP6_BASE_IDX 8 7718 #define regPARITY_COUNTER_CORR_GRP7 0xe88034 7719 #define regPARITY_COUNTER_CORR_GRP7_BASE_IDX 8 7720 #define regPARITY_COUNTER_CORR_GRP10 0xe88037 7721 #define regPARITY_COUNTER_CORR_GRP10_BASE_IDX 8 7722 #define regPARITY_COUNTER_CORR_GRP11 0xe88038 7723 #define regPARITY_COUNTER_CORR_GRP11_BASE_IDX 8 7724 #define regPARITY_COUNTER_CORR_GRP12 0xe88039 7725 #define regPARITY_COUNTER_CORR_GRP12_BASE_IDX 8 7726 #define regPARITY_COUNTER_CORR_GRP13 0xe8803a 7727 #define regPARITY_COUNTER_CORR_GRP13_BASE_IDX 8 7728 #define regPARITY_COUNTER_CORR_GRP14 0xe8803b 7729 #define regPARITY_COUNTER_CORR_GRP14_BASE_IDX 8 7730 #define regPARITY_COUNTER_CORR_GRP15 0xe8803c 7731 #define regPARITY_COUNTER_CORR_GRP15_BASE_IDX 8 7732 #define regPARITY_COUNTER_CORR_GRP16 0xe8803d 7733 #define regPARITY_COUNTER_CORR_GRP16_BASE_IDX 8 7734 #define regPARITY_COUNTER_CORR_GRP17 0xe8803e 7735 #define regPARITY_COUNTER_CORR_GRP17_BASE_IDX 8 7736 #define regPARITY_ERROR_STATUS_UCP_GRP0 0xe8803f 7737 #define regPARITY_ERROR_STATUS_UCP_GRP0_BASE_IDX 8 7738 #define regPARITY_ERROR_STATUS_UCP_GRP1 0xe88040 7739 #define regPARITY_ERROR_STATUS_UCP_GRP1_BASE_IDX 8 7740 #define regPARITY_ERROR_STATUS_UCP_GRP2 0xe88041 7741 #define regPARITY_ERROR_STATUS_UCP_GRP2_BASE_IDX 8 7742 #define regPARITY_ERROR_STATUS_UCP_GRP3 0xe88042 7743 #define regPARITY_ERROR_STATUS_UCP_GRP3_BASE_IDX 8 7744 #define regPARITY_ERROR_STATUS_UCP_GRP4 0xe88043 7745 #define regPARITY_ERROR_STATUS_UCP_GRP4_BASE_IDX 8 7746 #define regPARITY_ERROR_STATUS_UCP_GRP5 0xe88044 7747 #define regPARITY_ERROR_STATUS_UCP_GRP5_BASE_IDX 8 7748 #define regPARITY_ERROR_STATUS_UCP_GRP6 0xe88045 7749 #define regPARITY_ERROR_STATUS_UCP_GRP6_BASE_IDX 8 7750 #define regPARITY_ERROR_STATUS_UCP_GRP7 0xe88046 7751 #define regPARITY_ERROR_STATUS_UCP_GRP7_BASE_IDX 8 7752 #define regPARITY_ERROR_STATUS_UCP_GRP10 0xe88049 7753 #define regPARITY_ERROR_STATUS_UCP_GRP10_BASE_IDX 8 7754 #define regPARITY_ERROR_STATUS_UCP_GRP11 0xe8804a 7755 #define regPARITY_ERROR_STATUS_UCP_GRP11_BASE_IDX 8 7756 #define regPARITY_ERROR_STATUS_UCP_GRP12 0xe8804b 7757 #define regPARITY_ERROR_STATUS_UCP_GRP12_BASE_IDX 8 7758 #define regPARITY_COUNTER_UCP_GRP0 0xe8804c 7759 #define regPARITY_COUNTER_UCP_GRP0_BASE_IDX 8 7760 #define regPARITY_COUNTER_UCP_GRP1 0xe8804d 7761 #define regPARITY_COUNTER_UCP_GRP1_BASE_IDX 8 7762 #define regPARITY_COUNTER_UCP_GRP2 0xe8804e 7763 #define regPARITY_COUNTER_UCP_GRP2_BASE_IDX 8 7764 #define regPARITY_COUNTER_UCP_GRP3 0xe8804f 7765 #define regPARITY_COUNTER_UCP_GRP3_BASE_IDX 8 7766 #define regPARITY_COUNTER_UCP_GRP4 0xe88050 7767 #define regPARITY_COUNTER_UCP_GRP4_BASE_IDX 8 7768 #define regPARITY_COUNTER_UCP_GRP5 0xe88051 7769 #define regPARITY_COUNTER_UCP_GRP5_BASE_IDX 8 7770 #define regPARITY_COUNTER_UCP_GRP6 0xe88052 7771 #define regPARITY_COUNTER_UCP_GRP6_BASE_IDX 8 7772 #define regPARITY_COUNTER_UCP_GRP7 0xe88053 7773 #define regPARITY_COUNTER_UCP_GRP7_BASE_IDX 8 7774 #define regPARITY_COUNTER_UCP_GRP10 0xe88056 7775 #define regPARITY_COUNTER_UCP_GRP10_BASE_IDX 8 7776 #define regPARITY_COUNTER_UCP_GRP11 0xe88057 7777 #define regPARITY_COUNTER_UCP_GRP11_BASE_IDX 8 7778 #define regPARITY_COUNTER_UCP_GRP12 0xe88058 7779 #define regPARITY_COUNTER_UCP_GRP12_BASE_IDX 8 7780 #define regMISC_SEVERITY_CONTROL 0xe88059 7781 #define regMISC_SEVERITY_CONTROL_BASE_IDX 8 7782 #define regMISC_RAS_CONTROL 0xe8805a 7783 #define regMISC_RAS_CONTROL_BASE_IDX 8 7784 #define regRAS_SCRATCH_0 0xe8805b 7785 #define regRAS_SCRATCH_0_BASE_IDX 8 7786 #define regRAS_SCRATCH_1 0xe8805c 7787 #define regRAS_SCRATCH_1_BASE_IDX 8 7788 #define regErrEvent_ACTION_CONTROL 0xe8805d 7789 #define regErrEvent_ACTION_CONTROL_BASE_IDX 8 7790 #define regParitySerr_ACTION_CONTROL 0xe8805e 7791 #define regParitySerr_ACTION_CONTROL_BASE_IDX 8 7792 #define regParityFatal_ACTION_CONTROL 0xe8805f 7793 #define regParityFatal_ACTION_CONTROL_BASE_IDX 8 7794 #define regParityNonFatal_ACTION_CONTROL 0xe88060 7795 #define regParityNonFatal_ACTION_CONTROL_BASE_IDX 8 7796 #define regParityCorr_ACTION_CONTROL 0xe88061 7797 #define regParityCorr_ACTION_CONTROL_BASE_IDX 8 7798 #define regPCIE0PortASerr_ACTION_CONTROL 0xe88062 7799 #define regPCIE0PortASerr_ACTION_CONTROL_BASE_IDX 8 7800 #define regPCIE0PortAIntFatal_ACTION_CONTROL 0xe88063 7801 #define regPCIE0PortAIntFatal_ACTION_CONTROL_BASE_IDX 8 7802 #define regPCIE0PortAIntNonFatal_ACTION_CONTROL 0xe88064 7803 #define regPCIE0PortAIntNonFatal_ACTION_CONTROL_BASE_IDX 8 7804 #define regPCIE0PortAIntCorr_ACTION_CONTROL 0xe88065 7805 #define regPCIE0PortAIntCorr_ACTION_CONTROL_BASE_IDX 8 7806 #define regPCIE0PortAExtFatal_ACTION_CONTROL 0xe88066 7807 #define regPCIE0PortAExtFatal_ACTION_CONTROL_BASE_IDX 8 7808 #define regPCIE0PortAExtNonFatal_ACTION_CONTROL 0xe88067 7809 #define regPCIE0PortAExtNonFatal_ACTION_CONTROL_BASE_IDX 8 7810 #define regPCIE0PortAExtCorr_ACTION_CONTROL 0xe88068 7811 #define regPCIE0PortAExtCorr_ACTION_CONTROL_BASE_IDX 8 7812 #define regPCIE0PortAParityErr_ACTION_CONTROL 0xe88069 7813 #define regPCIE0PortAParityErr_ACTION_CONTROL_BASE_IDX 8 7814 #define regPCIE0PortBSerr_ACTION_CONTROL 0xe8806a 7815 #define regPCIE0PortBSerr_ACTION_CONTROL_BASE_IDX 8 7816 #define regPCIE0PortBIntFatal_ACTION_CONTROL 0xe8806b 7817 #define regPCIE0PortBIntFatal_ACTION_CONTROL_BASE_IDX 8 7818 #define regPCIE0PortBIntNonFatal_ACTION_CONTROL 0xe8806c 7819 #define regPCIE0PortBIntNonFatal_ACTION_CONTROL_BASE_IDX 8 7820 #define regPCIE0PortBIntCorr_ACTION_CONTROL 0xe8806d 7821 #define regPCIE0PortBIntCorr_ACTION_CONTROL_BASE_IDX 8 7822 #define regPCIE0PortBExtFatal_ACTION_CONTROL 0xe8806e 7823 #define regPCIE0PortBExtFatal_ACTION_CONTROL_BASE_IDX 8 7824 #define regPCIE0PortBExtNonFatal_ACTION_CONTROL 0xe8806f 7825 #define regPCIE0PortBExtNonFatal_ACTION_CONTROL_BASE_IDX 8 7826 #define regPCIE0PortBExtCorr_ACTION_CONTROL 0xe88070 7827 #define regPCIE0PortBExtCorr_ACTION_CONTROL_BASE_IDX 8 7828 #define regPCIE0PortBParityErr_ACTION_CONTROL 0xe88071 7829 #define regPCIE0PortBParityErr_ACTION_CONTROL_BASE_IDX 8 7830 #define regPCIE0PortCSerr_ACTION_CONTROL 0xe88072 7831 #define regPCIE0PortCSerr_ACTION_CONTROL_BASE_IDX 8 7832 #define regPCIE0PortCIntFatal_ACTION_CONTROL 0xe88073 7833 #define regPCIE0PortCIntFatal_ACTION_CONTROL_BASE_IDX 8 7834 #define regPCIE0PortCIntNonFatal_ACTION_CONTROL 0xe88074 7835 #define regPCIE0PortCIntNonFatal_ACTION_CONTROL_BASE_IDX 8 7836 #define regPCIE0PortCIntCorr_ACTION_CONTROL 0xe88075 7837 #define regPCIE0PortCIntCorr_ACTION_CONTROL_BASE_IDX 8 7838 #define regPCIE0PortCExtFatal_ACTION_CONTROL 0xe88076 7839 #define regPCIE0PortCExtFatal_ACTION_CONTROL_BASE_IDX 8 7840 #define regPCIE0PortCExtNonFatal_ACTION_CONTROL 0xe88077 7841 #define regPCIE0PortCExtNonFatal_ACTION_CONTROL_BASE_IDX 8 7842 #define regPCIE0PortCExtCorr_ACTION_CONTROL 0xe88078 7843 #define regPCIE0PortCExtCorr_ACTION_CONTROL_BASE_IDX 8 7844 #define regPCIE0PortCParityErr_ACTION_CONTROL 0xe88079 7845 #define regPCIE0PortCParityErr_ACTION_CONTROL_BASE_IDX 8 7846 #define regPCIE0PortDSerr_ACTION_CONTROL 0xe8807a 7847 #define regPCIE0PortDSerr_ACTION_CONTROL_BASE_IDX 8 7848 #define regPCIE0PortDIntFatal_ACTION_CONTROL 0xe8807b 7849 #define regPCIE0PortDIntFatal_ACTION_CONTROL_BASE_IDX 8 7850 #define regPCIE0PortDIntNonFatal_ACTION_CONTROL 0xe8807c 7851 #define regPCIE0PortDIntNonFatal_ACTION_CONTROL_BASE_IDX 8 7852 #define regPCIE0PortDIntCorr_ACTION_CONTROL 0xe8807d 7853 #define regPCIE0PortDIntCorr_ACTION_CONTROL_BASE_IDX 8 7854 #define regPCIE0PortDExtFatal_ACTION_CONTROL 0xe8807e 7855 #define regPCIE0PortDExtFatal_ACTION_CONTROL_BASE_IDX 8 7856 #define regPCIE0PortDExtNonFatal_ACTION_CONTROL 0xe8807f 7857 #define regPCIE0PortDExtNonFatal_ACTION_CONTROL_BASE_IDX 8 7858 #define regPCIE0PortDExtCorr_ACTION_CONTROL 0xe88080 7859 #define regPCIE0PortDExtCorr_ACTION_CONTROL_BASE_IDX 8 7860 #define regPCIE0PortDParityErr_ACTION_CONTROL 0xe88081 7861 #define regPCIE0PortDParityErr_ACTION_CONTROL_BASE_IDX 8 7862 #define regPCIE0PortESerr_ACTION_CONTROL 0xe88082 7863 #define regPCIE0PortESerr_ACTION_CONTROL_BASE_IDX 8 7864 #define regPCIE0PortEIntFatal_ACTION_CONTROL 0xe88083 7865 #define regPCIE0PortEIntFatal_ACTION_CONTROL_BASE_IDX 8 7866 #define regPCIE0PortEIntNonFatal_ACTION_CONTROL 0xe88084 7867 #define regPCIE0PortEIntNonFatal_ACTION_CONTROL_BASE_IDX 8 7868 #define regPCIE0PortEIntCorr_ACTION_CONTROL 0xe88085 7869 #define regPCIE0PortEIntCorr_ACTION_CONTROL_BASE_IDX 8 7870 #define regPCIE0PortEExtFatal_ACTION_CONTROL 0xe88086 7871 #define regPCIE0PortEExtFatal_ACTION_CONTROL_BASE_IDX 8 7872 #define regPCIE0PortEExtNonFatal_ACTION_CONTROL 0xe88087 7873 #define regPCIE0PortEExtNonFatal_ACTION_CONTROL_BASE_IDX 8 7874 #define regPCIE0PortEExtCorr_ACTION_CONTROL 0xe88088 7875 #define regPCIE0PortEExtCorr_ACTION_CONTROL_BASE_IDX 8 7876 #define regPCIE0PortEParityErr_ACTION_CONTROL 0xe88089 7877 #define regPCIE0PortEParityErr_ACTION_CONTROL_BASE_IDX 8 7878 #define regPCIE0PortFSerr_ACTION_CONTROL 0xe8808a 7879 #define regPCIE0PortFSerr_ACTION_CONTROL_BASE_IDX 8 7880 #define regPCIE0PortFIntFatal_ACTION_CONTROL 0xe8808b 7881 #define regPCIE0PortFIntFatal_ACTION_CONTROL_BASE_IDX 8 7882 #define regPCIE0PortFIntNonFatal_ACTION_CONTROL 0xe8808c 7883 #define regPCIE0PortFIntNonFatal_ACTION_CONTROL_BASE_IDX 8 7884 #define regPCIE0PortFIntCorr_ACTION_CONTROL 0xe8808d 7885 #define regPCIE0PortFIntCorr_ACTION_CONTROL_BASE_IDX 8 7886 #define regPCIE0PortFExtFatal_ACTION_CONTROL 0xe8808e 7887 #define regPCIE0PortFExtFatal_ACTION_CONTROL_BASE_IDX 8 7888 #define regPCIE0PortFExtNonFatal_ACTION_CONTROL 0xe8808f 7889 #define regPCIE0PortFExtNonFatal_ACTION_CONTROL_BASE_IDX 8 7890 #define regPCIE0PortFExtCorr_ACTION_CONTROL 0xe88090 7891 #define regPCIE0PortFExtCorr_ACTION_CONTROL_BASE_IDX 8 7892 #define regPCIE0PortFParityErr_ACTION_CONTROL 0xe88091 7893 #define regPCIE0PortFParityErr_ACTION_CONTROL_BASE_IDX 8 7894 #define regPCIE0PortGSerr_ACTION_CONTROL 0xe88092 7895 #define regPCIE0PortGSerr_ACTION_CONTROL_BASE_IDX 8 7896 #define regPCIE0PortGIntFatal_ACTION_CONTROL 0xe88093 7897 #define regPCIE0PortGIntFatal_ACTION_CONTROL_BASE_IDX 8 7898 #define regPCIE0PortGIntNonFatal_ACTION_CONTROL 0xe88094 7899 #define regPCIE0PortGIntNonFatal_ACTION_CONTROL_BASE_IDX 8 7900 #define regPCIE0PortGIntCorr_ACTION_CONTROL 0xe88095 7901 #define regPCIE0PortGIntCorr_ACTION_CONTROL_BASE_IDX 8 7902 #define regPCIE0PortGExtFatal_ACTION_CONTROL 0xe88096 7903 #define regPCIE0PortGExtFatal_ACTION_CONTROL_BASE_IDX 8 7904 #define regPCIE0PortGExtNonFatal_ACTION_CONTROL 0xe88097 7905 #define regPCIE0PortGExtNonFatal_ACTION_CONTROL_BASE_IDX 8 7906 #define regPCIE0PortGExtCorr_ACTION_CONTROL 0xe88098 7907 #define regPCIE0PortGExtCorr_ACTION_CONTROL_BASE_IDX 8 7908 #define regPCIE0PortGParityErr_ACTION_CONTROL 0xe88099 7909 #define regPCIE0PortGParityErr_ACTION_CONTROL_BASE_IDX 8 7910 #define regNBIF1PortASerr_ACTION_CONTROL 0xe880ca 7911 #define regNBIF1PortASerr_ACTION_CONTROL_BASE_IDX 8 7912 #define regNBIF1PortAIntFatal_ACTION_CONTROL 0xe880cb 7913 #define regNBIF1PortAIntFatal_ACTION_CONTROL_BASE_IDX 8 7914 #define regNBIF1PortAIntNonFatal_ACTION_CONTROL 0xe880cc 7915 #define regNBIF1PortAIntNonFatal_ACTION_CONTROL_BASE_IDX 8 7916 #define regNBIF1PortAIntCorr_ACTION_CONTROL 0xe880cd 7917 #define regNBIF1PortAIntCorr_ACTION_CONTROL_BASE_IDX 8 7918 #define regNBIF1PortAExtFatal_ACTION_CONTROL 0xe880ce 7919 #define regNBIF1PortAExtFatal_ACTION_CONTROL_BASE_IDX 8 7920 #define regNBIF1PortAExtNonFatal_ACTION_CONTROL 0xe880cf 7921 #define regNBIF1PortAExtNonFatal_ACTION_CONTROL_BASE_IDX 8 7922 #define regNBIF1PortAExtCorr_ACTION_CONTROL 0xe880d0 7923 #define regNBIF1PortAExtCorr_ACTION_CONTROL_BASE_IDX 8 7924 #define regNBIF1PortAParityErr_ACTION_CONTROL 0xe880d1 7925 #define regNBIF1PortAParityErr_ACTION_CONTROL_BASE_IDX 8 7926 #define regSYNCFLOOD_STATUS 0xe88200 7927 #define regSYNCFLOOD_STATUS_BASE_IDX 8 7928 #define regNMI_STATUS 0xe88201 7929 #define regNMI_STATUS_BASE_IDX 8 7930 #define regPOISON_ACTION_CONTROL 0xe88205 7931 #define regPOISON_ACTION_CONTROL_BASE_IDX 8 7932 #define regINTERNAL_POISON_STATUS 0xe88206 7933 #define regINTERNAL_POISON_STATUS_BASE_IDX 8 7934 #define regINTERNAL_POISON_MASK 0xe88207 7935 #define regINTERNAL_POISON_MASK_BASE_IDX 8 7936 #define regEGRESS_POISON_STATUS_LO 0xe88208 7937 #define regEGRESS_POISON_STATUS_LO_BASE_IDX 8 7938 #define regEGRESS_POISON_STATUS_HI 0xe88209 7939 #define regEGRESS_POISON_STATUS_HI_BASE_IDX 8 7940 #define regEGRESS_POISON_MASK_LO 0xe8820a 7941 #define regEGRESS_POISON_MASK_LO_BASE_IDX 8 7942 #define regEGRESS_POISON_MASK_HI 0xe8820b 7943 #define regEGRESS_POISON_MASK_HI_BASE_IDX 8 7944 #define regEGRESS_POISON_SEVERITY_DOWN 0xe8820c 7945 #define regEGRESS_POISON_SEVERITY_DOWN_BASE_IDX 8 7946 #define regEGRESS_POISON_SEVERITY_UPPER 0xe8820d 7947 #define regEGRESS_POISON_SEVERITY_UPPER_BASE_IDX 8 7948 #define regAPML_STATUS 0xe88370 7949 #define regAPML_STATUS_BASE_IDX 8 7950 #define regAPML_CONTROL 0xe88371 7951 #define regAPML_CONTROL_BASE_IDX 8 7952 #define regAPML_TRIGGER 0xe88372 7953 #define regAPML_TRIGGER_BASE_IDX 8 7954 7955 7956 // addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg0_devind_cfgdecp 7957 // base address: 0x13b31000 7958 #define regNB_PCIE0DEVINDCFG0_STEERING_CNTL 0xe8c403 7959 #define regNB_PCIE0DEVINDCFG0_STEERING_CNTL_BASE_IDX 8 7960 7961 7962 // addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg1_devind_cfgdecp 7963 // base address: 0x13b31400 7964 #define regNB_PCIE0DEVINDCFG1_STEERING_CNTL 0xe8c503 7965 #define regNB_PCIE0DEVINDCFG1_STEERING_CNTL_BASE_IDX 8 7966 7967 7968 // addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg2_devind_cfgdecp 7969 // base address: 0x13b31800 7970 #define regNB_PCIE0DEVINDCFG2_STEERING_CNTL 0xe8c603 7971 #define regNB_PCIE0DEVINDCFG2_STEERING_CNTL_BASE_IDX 8 7972 7973 7974 // addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg3_devind_cfgdecp 7975 // base address: 0x13b31c00 7976 #define regNB_PCIE0DEVINDCFG3_STEERING_CNTL 0xe8c703 7977 #define regNB_PCIE0DEVINDCFG3_STEERING_CNTL_BASE_IDX 8 7978 7979 7980 // addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg4_devind_cfgdecp 7981 // base address: 0x13b32000 7982 #define regNB_PCIE0DEVINDCFG4_STEERING_CNTL 0xe8c803 7983 #define regNB_PCIE0DEVINDCFG4_STEERING_CNTL_BASE_IDX 8 7984 7985 7986 // addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg5_devind_cfgdecp 7987 // base address: 0x13b32400 7988 #define regNB_PCIE0DEVINDCFG5_STEERING_CNTL 0xe8c903 7989 #define regNB_PCIE0DEVINDCFG5_STEERING_CNTL_BASE_IDX 8 7990 7991 7992 // addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg6_devind_cfgdecp 7993 // base address: 0x13b32800 7994 #define regNB_PCIE0DEVINDCFG6_STEERING_CNTL 0xe8ca03 7995 #define regNB_PCIE0DEVINDCFG6_STEERING_CNTL_BASE_IDX 8 7996 7997 7998 // addressBlock: aid_nbio_iohub_nb_NBIF1devindcfg0_devind_cfgdecp 7999 // base address: 0x13b38000 8000 #define regNB_NBIF1DEVINDCFG0_STEERING_CNTL 0xe8e003 8001 #define regNB_NBIF1DEVINDCFG0_STEERING_CNTL_BASE_IDX 8 8002 8003 8004 // addressBlock: aid_nbio_iohub_nb_intSBdevindcfg0_devind_cfgdecp 8005 // base address: 0x13b3c000 8006 #define regNB_INTSBDEVINDCFG0_STEERING_CNTL 0xe8f003 8007 #define regNB_INTSBDEVINDCFG0_STEERING_CNTL_BASE_IDX 8 8008 8009 8010 // addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg0_pciercbdgind_cfgdec 8011 // base address: 0x13b7d600 8012 #define regNB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION 0xe9f5b7 8013 #define regNB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION_BASE_IDX 8 8014 #define regNB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX 0xe9f5b8 8015 #define regNB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX_BASE_IDX 8 8016 #define regNB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA 0xe9f5b9 8017 #define regNB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA_BASE_IDX 8 8018 8019 8020 // addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg1_pciercbdgind_cfgdec 8021 // base address: 0x13b7d700 8022 #define regNB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX_EXTENSION 0xe9f5f7 8023 #define regNB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX_EXTENSION_BASE_IDX 8 8024 #define regNB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX 0xe9f5f8 8025 #define regNB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX_BASE_IDX 8 8026 #define regNB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA 0xe9f5f9 8027 #define regNB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA_BASE_IDX 8 8028 8029 8030 // addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg2_pciercbdgind_cfgdec 8031 // base address: 0x13b7d800 8032 #define regNB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX_EXTENSION 0xe9f637 8033 #define regNB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX_EXTENSION_BASE_IDX 8 8034 #define regNB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX 0xe9f638 8035 #define regNB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX_BASE_IDX 8 8036 #define regNB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA 0xe9f639 8037 #define regNB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA_BASE_IDX 8 8038 8039 8040 // addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg3_pciercbdgind_cfgdec 8041 // base address: 0x13b7d900 8042 #define regNB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX_EXTENSION 0xe9f677 8043 #define regNB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX_EXTENSION_BASE_IDX 8 8044 #define regNB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX 0xe9f678 8045 #define regNB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX_BASE_IDX 8 8046 #define regNB_PCIE0RCBDG_INDCFG3_RC_SMN_DATA 0xe9f679 8047 #define regNB_PCIE0RCBDG_INDCFG3_RC_SMN_DATA_BASE_IDX 8 8048 8049 8050 // addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg4_pciercbdgind_cfgdec 8051 // base address: 0x13b7da00 8052 #define regNB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX_EXTENSION 0xe9f6b7 8053 #define regNB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX_EXTENSION_BASE_IDX 8 8054 #define regNB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX 0xe9f6b8 8055 #define regNB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX_BASE_IDX 8 8056 #define regNB_PCIE0RCBDG_INDCFG4_RC_SMN_DATA 0xe9f6b9 8057 #define regNB_PCIE0RCBDG_INDCFG4_RC_SMN_DATA_BASE_IDX 8 8058 8059 8060 // addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg5_pciercbdgind_cfgdec 8061 // base address: 0x13b7db00 8062 #define regNB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX_EXTENSION 0xe9f6f7 8063 #define regNB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX_EXTENSION_BASE_IDX 8 8064 #define regNB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX 0xe9f6f8 8065 #define regNB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX_BASE_IDX 8 8066 #define regNB_PCIE0RCBDG_INDCFG5_RC_SMN_DATA 0xe9f6f9 8067 #define regNB_PCIE0RCBDG_INDCFG5_RC_SMN_DATA_BASE_IDX 8 8068 8069 8070 // addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg6_pciercbdgind_cfgdec 8071 // base address: 0x13b7dc00 8072 #define regNB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX_EXTENSION 0xe9f737 8073 #define regNB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX_EXTENSION_BASE_IDX 8 8074 #define regNB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX 0xe9f738 8075 #define regNB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX_BASE_IDX 8 8076 #define regNB_PCIE0RCBDG_INDCFG6_RC_SMN_DATA 0xe9f739 8077 #define regNB_PCIE0RCBDG_INDCFG6_RC_SMN_DATA_BASE_IDX 8 8078 8079 8080 // addressBlock: aid_nbio_iohub_nb_NBIF1rcbdg_indcfg0_pciercbdgind_cfgdec 8081 // base address: 0x13b7f200 8082 #define regNB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION 0xe9fcb7 8083 #define regNB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION_BASE_IDX 8 8084 #define regNB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX 0xe9fcb8 8085 #define regNB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX_BASE_IDX 8 8086 #define regNB_NBIF1RCBDG_INDCFG0_RC_SMN_DATA 0xe9fcb9 8087 #define regNB_NBIF1RCBDG_INDCFG0_RC_SMN_DATA_BASE_IDX 8 8088 8089 8090 // addressBlock: aid_nbio_iohub_iommu_l2a_l2acfg 8091 // base address: 0x15700000 8092 #define regL2_PERF_CNTL_0 0x1580000 8093 #define regL2_PERF_CNTL_0_BASE_IDX 8 8094 #define regL2_PERF_COUNT_0 0x1580001 8095 #define regL2_PERF_COUNT_0_BASE_IDX 8 8096 #define regL2_PERF_COUNT_1 0x1580002 8097 #define regL2_PERF_COUNT_1_BASE_IDX 8 8098 #define regL2_PERF_CNTL_1 0x1580003 8099 #define regL2_PERF_CNTL_1_BASE_IDX 8 8100 #define regL2_PERF_COUNT_2 0x1580004 8101 #define regL2_PERF_COUNT_2_BASE_IDX 8 8102 #define regL2_PERF_COUNT_3 0x1580005 8103 #define regL2_PERF_COUNT_3_BASE_IDX 8 8104 #define regL2_STATUS_0 0x1580008 8105 #define regL2_STATUS_0_BASE_IDX 8 8106 #define regL2_CONTROL_0 0x158000c 8107 #define regL2_CONTROL_0_BASE_IDX 8 8108 #define regL2_CONTROL_1 0x158000d 8109 #define regL2_CONTROL_1_BASE_IDX 8 8110 #define regL2_DTC_CONTROL 0x1580010 8111 #define regL2_DTC_CONTROL_BASE_IDX 8 8112 #define regL2_DTC_HASH_CONTROL 0x1580011 8113 #define regL2_DTC_HASH_CONTROL_BASE_IDX 8 8114 #define regL2_DTC_WAY_CONTROL 0x1580012 8115 #define regL2_DTC_WAY_CONTROL_BASE_IDX 8 8116 #define regL2_ITC_CONTROL 0x1580014 8117 #define regL2_ITC_CONTROL_BASE_IDX 8 8118 #define regL2_ITC_HASH_CONTROL 0x1580015 8119 #define regL2_ITC_HASH_CONTROL_BASE_IDX 8 8120 #define regL2_ITC_WAY_CONTROL 0x1580016 8121 #define regL2_ITC_WAY_CONTROL_BASE_IDX 8 8122 #define regL2_PTC_A_CONTROL 0x1580018 8123 #define regL2_PTC_A_CONTROL_BASE_IDX 8 8124 #define regL2_PTC_A_HASH_CONTROL 0x1580019 8125 #define regL2_PTC_A_HASH_CONTROL_BASE_IDX 8 8126 #define regL2_PTC_A_WAY_CONTROL 0x158001a 8127 #define regL2_PTC_A_WAY_CONTROL_BASE_IDX 8 8128 #define regL2A_UPDATE_FILTER_CNTL 0x1580022 8129 #define regL2A_UPDATE_FILTER_CNTL_BASE_IDX 8 8130 #define regL2_ERR_RULE_CONTROL_3 0x1580030 8131 #define regL2_ERR_RULE_CONTROL_3_BASE_IDX 8 8132 #define regL2_ERR_RULE_CONTROL_4 0x1580031 8133 #define regL2_ERR_RULE_CONTROL_4_BASE_IDX 8 8134 #define regL2_ERR_RULE_CONTROL_5 0x1580032 8135 #define regL2_ERR_RULE_CONTROL_5_BASE_IDX 8 8136 #define regL2_L2A_CK_GATE_CONTROL 0x1580033 8137 #define regL2_L2A_CK_GATE_CONTROL_BASE_IDX 8 8138 #define regL2_L2A_PGSIZE_CONTROL 0x1580034 8139 #define regL2_L2A_PGSIZE_CONTROL_BASE_IDX 8 8140 #define regL2_PWRGATE_CNTRL_REG_0 0x158003e 8141 #define regL2_PWRGATE_CNTRL_REG_0_BASE_IDX 8 8142 #define regL2_PWRGATE_CNTRL_REG_3 0x1580041 8143 #define regL2_PWRGATE_CNTRL_REG_3_BASE_IDX 8 8144 #define regL2_ECO_CNTRL_0 0x1580042 8145 #define regL2_ECO_CNTRL_0_BASE_IDX 8 8146 8147 8148 // addressBlock: aid_nbio_iohub_iommu_l2indx_l2indxcfg 8149 // base address: 0x13f01000 8150 #define regL2_STATUS_1 0xf80448 8151 #define regL2_STATUS_1_BASE_IDX 8 8152 #define regL2_SB_LOCATION 0xf8044b 8153 #define regL2_SB_LOCATION_BASE_IDX 8 8154 #define regL2_CONTROL_5 0xf8044c 8155 #define regL2_CONTROL_5_BASE_IDX 8 8156 #define regL2_CONTROL_6 0xf8044f 8157 #define regL2_CONTROL_6_BASE_IDX 8 8158 #define regL2_PDC_CONTROL 0xf80450 8159 #define regL2_PDC_CONTROL_BASE_IDX 8 8160 #define regL2_PDC_HASH_CONTROL 0xf80451 8161 #define regL2_PDC_HASH_CONTROL_BASE_IDX 8 8162 #define regL2_PDC_WAY_CONTROL 0xf80452 8163 #define regL2_PDC_WAY_CONTROL_BASE_IDX 8 8164 #define regL2B_UPDATE_FILTER_CNTL 0xf80453 8165 #define regL2B_UPDATE_FILTER_CNTL_BASE_IDX 8 8166 #define regL2_TW_CONTROL 0xf80454 8167 #define regL2_TW_CONTROL_BASE_IDX 8 8168 #define regL2_CP_CONTROL 0xf80456 8169 #define regL2_CP_CONTROL_BASE_IDX 8 8170 #define regL2_CP_CONTROL_1 0xf80457 8171 #define regL2_CP_CONTROL_1_BASE_IDX 8 8172 #define regL2_TW_CONTROL_1 0xf8045a 8173 #define regL2_TW_CONTROL_1_BASE_IDX 8 8174 #define regL2_TW_CONTROL_2 0xf80461 8175 #define regL2_TW_CONTROL_2_BASE_IDX 8 8176 #define regL2_TW_CONTROL_3 0xf80462 8177 #define regL2_TW_CONTROL_3_BASE_IDX 8 8178 #define regL2_CREDIT_CONTROL_0 0xf80470 8179 #define regL2_CREDIT_CONTROL_0_BASE_IDX 8 8180 #define regL2_CREDIT_CONTROL_1 0xf80471 8181 #define regL2_CREDIT_CONTROL_1_BASE_IDX 8 8182 #define regL2_ERR_RULE_CONTROL_0 0xf80480 8183 #define regL2_ERR_RULE_CONTROL_0_BASE_IDX 8 8184 #define regL2_ERR_RULE_CONTROL_1 0xf80481 8185 #define regL2_ERR_RULE_CONTROL_1_BASE_IDX 8 8186 #define regL2_ERR_RULE_CONTROL_2 0xf80482 8187 #define regL2_ERR_RULE_CONTROL_2_BASE_IDX 8 8188 #define regL2_L2B_CK_GATE_CONTROL 0xf80490 8189 #define regL2_L2B_CK_GATE_CONTROL_BASE_IDX 8 8190 #define regPPR_CONTROL 0xf80492 8191 #define regPPR_CONTROL_BASE_IDX 8 8192 #define regL2_L2B_PGSIZE_CONTROL 0xf80494 8193 #define regL2_L2B_PGSIZE_CONTROL_BASE_IDX 8 8194 #define regL2_PERF_CNTL_2 0xf80499 8195 #define regL2_PERF_CNTL_2_BASE_IDX 8 8196 #define regL2_PERF_COUNT_4 0xf8049a 8197 #define regL2_PERF_COUNT_4_BASE_IDX 8 8198 #define regL2_PERF_COUNT_5 0xf8049b 8199 #define regL2_PERF_COUNT_5_BASE_IDX 8 8200 #define regL2_PERF_CNTL_3 0xf8049c 8201 #define regL2_PERF_CNTL_3_BASE_IDX 8 8202 #define regL2_PERF_COUNT_6 0xf8049d 8203 #define regL2_PERF_COUNT_6_BASE_IDX 8 8204 #define regL2_PERF_COUNT_7 0xf8049e 8205 #define regL2_PERF_COUNT_7_BASE_IDX 8 8206 #define regL2B_SDP_PARITY_ERROR_EN 0xf804a2 8207 #define regL2B_SDP_PARITY_ERROR_EN_BASE_IDX 8 8208 #define regL2_ECO_CNTRL_1 0xf804a3 8209 #define regL2_ECO_CNTRL_1_BASE_IDX 8 8210 #define regL2_CP_CONTROL_2 0xf804bf 8211 #define regL2_CP_CONTROL_2_BASE_IDX 8 8212 #define regL2_CP_CONTROL_3 0xf804c0 8213 #define regL2_CP_CONTROL_3_BASE_IDX 8 8214 8215 8216 // addressBlock: aid_nbio_iohub_nb_ioapiccfg_ioapic_cfgdec 8217 // base address: 0x14300000 8218 #define regFEATURES_ENABLE 0x1080000 8219 #define regFEATURES_ENABLE_BASE_IDX 8 8220 8221 8222 // addressBlock: aid_nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp 8223 // base address: 0x0 8224 #define cfgBIF_CFG_DEV0_RC_VENDOR_ID 0x0000 8225 #define cfgBIF_CFG_DEV0_RC_DEVICE_ID 0x0002 8226 #define cfgBIF_CFG_DEV0_RC_COMMAND 0x0004 8227 #define cfgBIF_CFG_DEV0_RC_STATUS 0x0006 8228 #define cfgBIF_CFG_DEV0_RC_REVISION_ID 0x0008 8229 #define cfgBIF_CFG_DEV0_RC_PROG_INTERFACE 0x0009 8230 #define cfgBIF_CFG_DEV0_RC_SUB_CLASS 0x000a 8231 #define cfgBIF_CFG_DEV0_RC_BASE_CLASS 0x000b 8232 #define cfgBIF_CFG_DEV0_RC_CACHE_LINE 0x000c 8233 #define cfgBIF_CFG_DEV0_RC_LATENCY 0x000d 8234 #define cfgBIF_CFG_DEV0_RC_HEADER 0x000e 8235 #define cfgBIF_CFG_DEV0_RC_BIST 0x000f 8236 #define cfgBIF_CFG_DEV0_RC_BASE_ADDR_1 0x0010 8237 #define cfgBIF_CFG_DEV0_RC_BASE_ADDR_2 0x0014 8238 #define cfgBIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY 0x0018 8239 #define cfgBIF_CFG_DEV0_RC_IO_BASE_LIMIT 0x001c 8240 #define cfgBIF_CFG_DEV0_RC_SECONDARY_STATUS 0x001e 8241 #define cfgBIF_CFG_DEV0_RC_MEM_BASE_LIMIT 0x0020 8242 #define cfgBIF_CFG_DEV0_RC_PREF_BASE_LIMIT 0x0024 8243 #define cfgBIF_CFG_DEV0_RC_PREF_BASE_UPPER 0x0028 8244 #define cfgBIF_CFG_DEV0_RC_PREF_LIMIT_UPPER 0x002c 8245 #define cfgBIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI 0x0030 8246 #define cfgBIF_CFG_DEV0_RC_CAP_PTR 0x0034 8247 #define cfgBIF_CFG_DEV0_RC_ROM_BASE_ADDR 0x0038 8248 #define cfgBIF_CFG_DEV0_RC_INTERRUPT_LINE 0x003c 8249 #define cfgBIF_CFG_DEV0_RC_INTERRUPT_PIN 0x003d 8250 #define cfgIRQ_BRIDGE_CNTL 0x003e 8251 #define cfgBIF_CFG_DEV0_RC_EXT_BRIDGE_CNTL 0x0040 8252 #define cfgBIF_CFG_DEV0_RC_PMI_CAP_LIST 0x0050 8253 #define cfgBIF_CFG_DEV0_RC_PMI_CAP 0x0052 8254 #define cfgBIF_CFG_DEV0_RC_PMI_STATUS_CNTL 0x0054 8255 #define cfgBIF_CFG_DEV0_RC_PCIE_CAP_LIST 0x0058 8256 #define cfgBIF_CFG_DEV0_RC_PCIE_CAP 0x005a 8257 #define cfgBIF_CFG_DEV0_RC_DEVICE_CAP 0x005c 8258 #define cfgBIF_CFG_DEV0_RC_DEVICE_CNTL 0x0060 8259 #define cfgBIF_CFG_DEV0_RC_DEVICE_STATUS 0x0062 8260 #define cfgBIF_CFG_DEV0_RC_LINK_CAP 0x0064 8261 #define cfgBIF_CFG_DEV0_RC_LINK_CNTL 0x0068 8262 #define cfgBIF_CFG_DEV0_RC_LINK_STATUS 0x006a 8263 #define cfgBIF_CFG_DEV0_RC_SLOT_CAP 0x006c 8264 #define cfgBIF_CFG_DEV0_RC_SLOT_CNTL 0x0070 8265 #define cfgBIF_CFG_DEV0_RC_SLOT_STATUS 0x0072 8266 #define cfgBIF_CFG_DEV0_RC_ROOT_CNTL 0x0074 8267 #define cfgBIF_CFG_DEV0_RC_ROOT_CAP 0x0076 8268 #define cfgBIF_CFG_DEV0_RC_ROOT_STATUS 0x0078 8269 #define cfgBIF_CFG_DEV0_RC_DEVICE_CAP2 0x007c 8270 #define cfgBIF_CFG_DEV0_RC_DEVICE_CNTL2 0x0080 8271 #define cfgBIF_CFG_DEV0_RC_DEVICE_STATUS2 0x0082 8272 #define cfgBIF_CFG_DEV0_RC_LINK_CAP2 0x0084 8273 #define cfgBIF_CFG_DEV0_RC_LINK_CNTL2 0x0088 8274 #define cfgBIF_CFG_DEV0_RC_LINK_STATUS2 0x008a 8275 #define cfgBIF_CFG_DEV0_RC_SLOT_CAP2 0x008c 8276 #define cfgBIF_CFG_DEV0_RC_SLOT_CNTL2 0x0090 8277 #define cfgBIF_CFG_DEV0_RC_SLOT_STATUS2 0x0092 8278 #define cfgBIF_CFG_DEV0_RC_MSI_CAP_LIST 0x00a0 8279 #define cfgBIF_CFG_DEV0_RC_MSI_MSG_CNTL 0x00a2 8280 #define cfgBIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO 0x00a4 8281 #define cfgBIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI 0x00a8 8282 #define cfgBIF_CFG_DEV0_RC_MSI_MSG_DATA 0x00a8 8283 #define cfgBIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA 0x00aa 8284 #define cfgBIF_CFG_DEV0_RC_MSI_MSG_DATA_64 0x00ac 8285 #define cfgBIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64 0x00ae 8286 #define cfgBIF_CFG_DEV0_RC_SSID_CAP_LIST 0x00c0 8287 #define cfgBIF_CFG_DEV0_RC_SSID_CAP 0x00c4 8288 #define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 8289 #define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR 0x0104 8290 #define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1 0x0108 8291 #define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2 0x010c 8292 #define cfgBIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST 0x0110 8293 #define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1 0x0114 8294 #define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2 0x0118 8295 #define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL 0x011c 8296 #define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS 0x011e 8297 #define cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP 0x0120 8298 #define cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL 0x0124 8299 #define cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS 0x012a 8300 #define cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP 0x012c 8301 #define cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL 0x0130 8302 #define cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS 0x0136 8303 #define cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 8304 #define cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1 0x0144 8305 #define cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2 0x0148 8306 #define cfgBIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 8307 #define cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS 0x0154 8308 #define cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK 0x0158 8309 #define cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY 0x015c 8310 #define cfgBIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS 0x0160 8311 #define cfgBIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK 0x0164 8312 #define cfgBIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL 0x0168 8313 #define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG0 0x016c 8314 #define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG1 0x0170 8315 #define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG2 0x0174 8316 #define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG3 0x0178 8317 #define cfgBIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD 0x017c 8318 #define cfgBIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS 0x0180 8319 #define cfgBIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID 0x0184 8320 #define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0 0x0188 8321 #define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1 0x018c 8322 #define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2 0x0190 8323 #define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3 0x0194 8324 #define cfgBIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 8325 #define cfgBIF_CFG_DEV0_RC_PCIE_LINK_CNTL3 0x0274 8326 #define cfgBIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS 0x0278 8327 #define cfgBIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c 8328 #define cfgBIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e 8329 #define cfgBIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 8330 #define cfgBIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 8331 #define cfgBIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 8332 #define cfgBIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 8333 #define cfgBIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 8334 #define cfgBIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a 8335 #define cfgBIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c 8336 #define cfgBIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e 8337 #define cfgBIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 8338 #define cfgBIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 8339 #define cfgBIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 8340 #define cfgBIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 8341 #define cfgBIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 8342 #define cfgBIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a 8343 #define cfgBIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST 0x02a0 8344 #define cfgBIF_CFG_DEV0_RC_PCIE_ACS_CAP 0x02a4 8345 #define cfgBIF_CFG_DEV0_RC_PCIE_ACS_CNTL 0x02a6 8346 #define cfgBIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST 0x0400 8347 #define cfgBIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP 0x0404 8348 #define cfgBIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS 0x0408 8349 #define cfgBIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 8350 #define cfgBIF_CFG_DEV0_RC_LINK_CAP_16GT 0x0414 8351 #define cfgBIF_CFG_DEV0_RC_LINK_CNTL_16GT 0x0418 8352 #define cfgBIF_CFG_DEV0_RC_LINK_STATUS_16GT 0x041c 8353 #define cfgBIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 8354 #define cfgBIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 8355 #define cfgBIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 8356 #define cfgBIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 8357 #define cfgBIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 8358 #define cfgBIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 8359 #define cfgBIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 8360 #define cfgBIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 8361 #define cfgBIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 8362 #define cfgBIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 8363 #define cfgBIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 8364 #define cfgBIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 8365 #define cfgBIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 8366 #define cfgBIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT 0x043a 8367 #define cfgBIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT 0x043b 8368 #define cfgBIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT 0x043c 8369 #define cfgBIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT 0x043d 8370 #define cfgBIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT 0x043e 8371 #define cfgBIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT 0x043f 8372 #define cfgBIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST 0x0450 8373 #define cfgBIF_CFG_DEV0_RC_MARGINING_PORT_CAP 0x0454 8374 #define cfgBIF_CFG_DEV0_RC_MARGINING_PORT_STATUS 0x0456 8375 #define cfgBIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL 0x0458 8376 #define cfgBIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS 0x045a 8377 #define cfgBIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL 0x045c 8378 #define cfgBIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS 0x045e 8379 #define cfgBIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL 0x0460 8380 #define cfgBIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS 0x0462 8381 #define cfgBIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL 0x0464 8382 #define cfgBIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS 0x0466 8383 #define cfgBIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL 0x0468 8384 #define cfgBIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS 0x046a 8385 #define cfgBIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL 0x046c 8386 #define cfgBIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS 0x046e 8387 #define cfgBIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL 0x0470 8388 #define cfgBIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS 0x0472 8389 #define cfgBIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL 0x0474 8390 #define cfgBIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS 0x0476 8391 #define cfgBIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL 0x0478 8392 #define cfgBIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS 0x047a 8393 #define cfgBIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL 0x047c 8394 #define cfgBIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS 0x047e 8395 #define cfgBIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL 0x0480 8396 #define cfgBIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS 0x0482 8397 #define cfgBIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL 0x0484 8398 #define cfgBIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS 0x0486 8399 #define cfgBIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL 0x0488 8400 #define cfgBIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS 0x048a 8401 #define cfgBIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL 0x048c 8402 #define cfgBIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS 0x048e 8403 #define cfgBIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL 0x0490 8404 #define cfgBIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS 0x0492 8405 #define cfgBIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL 0x0494 8406 #define cfgBIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS 0x0496 8407 #define cfgBIF_CFG_DEV0_RC_LINK_CAP_32GT 0x0504 8408 #define cfgBIF_CFG_DEV0_RC_LINK_CNTL_32GT 0x0508 8409 #define cfgBIF_CFG_DEV0_RC_LINK_STATUS_32GT 0x050c 8410 8411 8412 // addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp 8413 // base address: 0x0 8414 #define cfgBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID 0x0000 8415 #define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID 0x0002 8416 #define cfgBIF_CFG_DEV0_EPF0_VF0_COMMAND 0x0004 8417 #define cfgBIF_CFG_DEV0_EPF0_VF0_STATUS 0x0006 8418 #define cfgBIF_CFG_DEV0_EPF0_VF0_REVISION_ID 0x0008 8419 #define cfgBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE 0x0009 8420 #define cfgBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS 0x000a 8421 #define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS 0x000b 8422 #define cfgBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE 0x000c 8423 #define cfgBIF_CFG_DEV0_EPF0_VF0_LATENCY 0x000d 8424 #define cfgBIF_CFG_DEV0_EPF0_VF0_HEADER 0x000e 8425 #define cfgBIF_CFG_DEV0_EPF0_VF0_BIST 0x000f 8426 #define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1 0x0010 8427 #define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2 0x0014 8428 #define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3 0x0018 8429 #define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4 0x001c 8430 #define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5 0x0020 8431 #define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6 0x0024 8432 #define cfgBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR 0x0028 8433 #define cfgBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID 0x002c 8434 #define cfgBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR 0x0030 8435 #define cfgBIF_CFG_DEV0_EPF0_VF0_CAP_PTR 0x0034 8436 #define cfgBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE 0x003c 8437 #define cfgBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN 0x003d 8438 #define cfgBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT 0x003e 8439 #define cfgBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY 0x003f 8440 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST 0x0064 8441 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP 0x0066 8442 #define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP 0x0068 8443 #define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL 0x006c 8444 #define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS 0x006e 8445 #define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CAP 0x0070 8446 #define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL 0x0074 8447 #define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS 0x0076 8448 #define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2 0x0088 8449 #define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2 0x008c 8450 #define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2 0x008e 8451 #define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2 0x0090 8452 #define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2 0x0094 8453 #define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2 0x0096 8454 #define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST 0x00a0 8455 #define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL 0x00a2 8456 #define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO 0x00a4 8457 #define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI 0x00a8 8458 #define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA 0x00a8 8459 #define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA 0x00aa 8460 #define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MASK 0x00ac 8461 #define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64 0x00ac 8462 #define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64 0x00ae 8463 #define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64 0x00b0 8464 #define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING 0x00b0 8465 #define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64 0x00b4 8466 #define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST 0x00c0 8467 #define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL 0x00c2 8468 #define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE 0x00c4 8469 #define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA 0x00c8 8470 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 8471 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 8472 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1 0x0108 8473 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2 0x010c 8474 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 8475 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS 0x0154 8476 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK 0x0158 8477 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY 0x015c 8478 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS 0x0160 8479 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK 0x0164 8480 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL 0x0168 8481 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0 0x016c 8482 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1 0x0170 8483 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2 0x0174 8484 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3 0x0178 8485 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0 0x0188 8486 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1 0x018c 8487 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2 0x0190 8488 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3 0x0194 8489 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST 0x02b0 8490 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP 0x02b4 8491 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL 0x02b6 8492 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST 0x0328 8493 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP 0x032c 8494 #define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL 0x032e 8495 8496 8497 // addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp 8498 // base address: 0x0 8499 #define cfgBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID 0x0000 8500 #define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID 0x0002 8501 #define cfgBIF_CFG_DEV0_EPF0_VF1_COMMAND 0x0004 8502 #define cfgBIF_CFG_DEV0_EPF0_VF1_STATUS 0x0006 8503 #define cfgBIF_CFG_DEV0_EPF0_VF1_REVISION_ID 0x0008 8504 #define cfgBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE 0x0009 8505 #define cfgBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS 0x000a 8506 #define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS 0x000b 8507 #define cfgBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE 0x000c 8508 #define cfgBIF_CFG_DEV0_EPF0_VF1_LATENCY 0x000d 8509 #define cfgBIF_CFG_DEV0_EPF0_VF1_HEADER 0x000e 8510 #define cfgBIF_CFG_DEV0_EPF0_VF1_BIST 0x000f 8511 #define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1 0x0010 8512 #define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2 0x0014 8513 #define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3 0x0018 8514 #define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4 0x001c 8515 #define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5 0x0020 8516 #define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6 0x0024 8517 #define cfgBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR 0x0028 8518 #define cfgBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID 0x002c 8519 #define cfgBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR 0x0030 8520 #define cfgBIF_CFG_DEV0_EPF0_VF1_CAP_PTR 0x0034 8521 #define cfgBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE 0x003c 8522 #define cfgBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN 0x003d 8523 #define cfgBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT 0x003e 8524 #define cfgBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY 0x003f 8525 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST 0x0064 8526 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP 0x0066 8527 #define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP 0x0068 8528 #define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL 0x006c 8529 #define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS 0x006e 8530 #define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CAP 0x0070 8531 #define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL 0x0074 8532 #define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS 0x0076 8533 #define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2 0x0088 8534 #define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2 0x008c 8535 #define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2 0x008e 8536 #define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2 0x0090 8537 #define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2 0x0094 8538 #define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2 0x0096 8539 #define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST 0x00a0 8540 #define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL 0x00a2 8541 #define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO 0x00a4 8542 #define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI 0x00a8 8543 #define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA 0x00a8 8544 #define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA 0x00aa 8545 #define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MASK 0x00ac 8546 #define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64 0x00ac 8547 #define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64 0x00ae 8548 #define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64 0x00b0 8549 #define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING 0x00b0 8550 #define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64 0x00b4 8551 #define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST 0x00c0 8552 #define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL 0x00c2 8553 #define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE 0x00c4 8554 #define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA 0x00c8 8555 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 8556 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 8557 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1 0x0108 8558 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2 0x010c 8559 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 8560 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS 0x0154 8561 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK 0x0158 8562 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY 0x015c 8563 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS 0x0160 8564 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK 0x0164 8565 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL 0x0168 8566 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0 0x016c 8567 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1 0x0170 8568 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2 0x0174 8569 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3 0x0178 8570 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0 0x0188 8571 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1 0x018c 8572 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2 0x0190 8573 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3 0x0194 8574 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST 0x02b0 8575 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP 0x02b4 8576 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL 0x02b6 8577 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST 0x0328 8578 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP 0x032c 8579 #define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL 0x032e 8580 8581 8582 // addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp 8583 // base address: 0x0 8584 #define cfgBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID 0x0000 8585 #define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID 0x0002 8586 #define cfgBIF_CFG_DEV0_EPF0_VF2_COMMAND 0x0004 8587 #define cfgBIF_CFG_DEV0_EPF0_VF2_STATUS 0x0006 8588 #define cfgBIF_CFG_DEV0_EPF0_VF2_REVISION_ID 0x0008 8589 #define cfgBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE 0x0009 8590 #define cfgBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS 0x000a 8591 #define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS 0x000b 8592 #define cfgBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE 0x000c 8593 #define cfgBIF_CFG_DEV0_EPF0_VF2_LATENCY 0x000d 8594 #define cfgBIF_CFG_DEV0_EPF0_VF2_HEADER 0x000e 8595 #define cfgBIF_CFG_DEV0_EPF0_VF2_BIST 0x000f 8596 #define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1 0x0010 8597 #define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2 0x0014 8598 #define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3 0x0018 8599 #define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4 0x001c 8600 #define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5 0x0020 8601 #define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6 0x0024 8602 #define cfgBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR 0x0028 8603 #define cfgBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID 0x002c 8604 #define cfgBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR 0x0030 8605 #define cfgBIF_CFG_DEV0_EPF0_VF2_CAP_PTR 0x0034 8606 #define cfgBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE 0x003c 8607 #define cfgBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN 0x003d 8608 #define cfgBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT 0x003e 8609 #define cfgBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY 0x003f 8610 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST 0x0064 8611 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP 0x0066 8612 #define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP 0x0068 8613 #define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL 0x006c 8614 #define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS 0x006e 8615 #define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CAP 0x0070 8616 #define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL 0x0074 8617 #define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS 0x0076 8618 #define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2 0x0088 8619 #define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2 0x008c 8620 #define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2 0x008e 8621 #define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2 0x0090 8622 #define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2 0x0094 8623 #define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2 0x0096 8624 #define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST 0x00a0 8625 #define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL 0x00a2 8626 #define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO 0x00a4 8627 #define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI 0x00a8 8628 #define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA 0x00a8 8629 #define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA 0x00aa 8630 #define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MASK 0x00ac 8631 #define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64 0x00ac 8632 #define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64 0x00ae 8633 #define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64 0x00b0 8634 #define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING 0x00b0 8635 #define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64 0x00b4 8636 #define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST 0x00c0 8637 #define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL 0x00c2 8638 #define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE 0x00c4 8639 #define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA 0x00c8 8640 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 8641 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR 0x0104 8642 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1 0x0108 8643 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2 0x010c 8644 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 8645 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS 0x0154 8646 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK 0x0158 8647 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY 0x015c 8648 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS 0x0160 8649 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK 0x0164 8650 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL 0x0168 8651 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0 0x016c 8652 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1 0x0170 8653 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2 0x0174 8654 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3 0x0178 8655 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0 0x0188 8656 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1 0x018c 8657 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2 0x0190 8658 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3 0x0194 8659 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST 0x02b0 8660 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP 0x02b4 8661 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL 0x02b6 8662 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST 0x0328 8663 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP 0x032c 8664 #define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL 0x032e 8665 8666 8667 // addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp 8668 // base address: 0x0 8669 #define cfgBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID 0x0000 8670 #define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID 0x0002 8671 #define cfgBIF_CFG_DEV0_EPF0_VF3_COMMAND 0x0004 8672 #define cfgBIF_CFG_DEV0_EPF0_VF3_STATUS 0x0006 8673 #define cfgBIF_CFG_DEV0_EPF0_VF3_REVISION_ID 0x0008 8674 #define cfgBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE 0x0009 8675 #define cfgBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS 0x000a 8676 #define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS 0x000b 8677 #define cfgBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE 0x000c 8678 #define cfgBIF_CFG_DEV0_EPF0_VF3_LATENCY 0x000d 8679 #define cfgBIF_CFG_DEV0_EPF0_VF3_HEADER 0x000e 8680 #define cfgBIF_CFG_DEV0_EPF0_VF3_BIST 0x000f 8681 #define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1 0x0010 8682 #define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2 0x0014 8683 #define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3 0x0018 8684 #define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4 0x001c 8685 #define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5 0x0020 8686 #define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6 0x0024 8687 #define cfgBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR 0x0028 8688 #define cfgBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID 0x002c 8689 #define cfgBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR 0x0030 8690 #define cfgBIF_CFG_DEV0_EPF0_VF3_CAP_PTR 0x0034 8691 #define cfgBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE 0x003c 8692 #define cfgBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN 0x003d 8693 #define cfgBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT 0x003e 8694 #define cfgBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY 0x003f 8695 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST 0x0064 8696 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP 0x0066 8697 #define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP 0x0068 8698 #define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL 0x006c 8699 #define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS 0x006e 8700 #define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CAP 0x0070 8701 #define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL 0x0074 8702 #define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS 0x0076 8703 #define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2 0x0088 8704 #define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2 0x008c 8705 #define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2 0x008e 8706 #define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2 0x0090 8707 #define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2 0x0094 8708 #define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2 0x0096 8709 #define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST 0x00a0 8710 #define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL 0x00a2 8711 #define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO 0x00a4 8712 #define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI 0x00a8 8713 #define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA 0x00a8 8714 #define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA 0x00aa 8715 #define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MASK 0x00ac 8716 #define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64 0x00ac 8717 #define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64 0x00ae 8718 #define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64 0x00b0 8719 #define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING 0x00b0 8720 #define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64 0x00b4 8721 #define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST 0x00c0 8722 #define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL 0x00c2 8723 #define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE 0x00c4 8724 #define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA 0x00c8 8725 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 8726 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR 0x0104 8727 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1 0x0108 8728 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2 0x010c 8729 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 8730 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS 0x0154 8731 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK 0x0158 8732 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY 0x015c 8733 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS 0x0160 8734 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK 0x0164 8735 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL 0x0168 8736 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0 0x016c 8737 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1 0x0170 8738 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2 0x0174 8739 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3 0x0178 8740 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0 0x0188 8741 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1 0x018c 8742 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2 0x0190 8743 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3 0x0194 8744 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST 0x02b0 8745 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP 0x02b4 8746 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL 0x02b6 8747 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST 0x0328 8748 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP 0x032c 8749 #define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL 0x032e 8750 8751 8752 // addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp 8753 // base address: 0x0 8754 #define cfgBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID 0x0000 8755 #define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID 0x0002 8756 #define cfgBIF_CFG_DEV0_EPF0_VF4_COMMAND 0x0004 8757 #define cfgBIF_CFG_DEV0_EPF0_VF4_STATUS 0x0006 8758 #define cfgBIF_CFG_DEV0_EPF0_VF4_REVISION_ID 0x0008 8759 #define cfgBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE 0x0009 8760 #define cfgBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS 0x000a 8761 #define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS 0x000b 8762 #define cfgBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE 0x000c 8763 #define cfgBIF_CFG_DEV0_EPF0_VF4_LATENCY 0x000d 8764 #define cfgBIF_CFG_DEV0_EPF0_VF4_HEADER 0x000e 8765 #define cfgBIF_CFG_DEV0_EPF0_VF4_BIST 0x000f 8766 #define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1 0x0010 8767 #define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2 0x0014 8768 #define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3 0x0018 8769 #define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4 0x001c 8770 #define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5 0x0020 8771 #define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6 0x0024 8772 #define cfgBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR 0x0028 8773 #define cfgBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID 0x002c 8774 #define cfgBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR 0x0030 8775 #define cfgBIF_CFG_DEV0_EPF0_VF4_CAP_PTR 0x0034 8776 #define cfgBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE 0x003c 8777 #define cfgBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN 0x003d 8778 #define cfgBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT 0x003e 8779 #define cfgBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY 0x003f 8780 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST 0x0064 8781 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP 0x0066 8782 #define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP 0x0068 8783 #define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL 0x006c 8784 #define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS 0x006e 8785 #define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CAP 0x0070 8786 #define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL 0x0074 8787 #define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS 0x0076 8788 #define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2 0x0088 8789 #define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2 0x008c 8790 #define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2 0x008e 8791 #define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2 0x0090 8792 #define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2 0x0094 8793 #define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2 0x0096 8794 #define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST 0x00a0 8795 #define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL 0x00a2 8796 #define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO 0x00a4 8797 #define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI 0x00a8 8798 #define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA 0x00a8 8799 #define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA 0x00aa 8800 #define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MASK 0x00ac 8801 #define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64 0x00ac 8802 #define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64 0x00ae 8803 #define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64 0x00b0 8804 #define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING 0x00b0 8805 #define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64 0x00b4 8806 #define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST 0x00c0 8807 #define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL 0x00c2 8808 #define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE 0x00c4 8809 #define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA 0x00c8 8810 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 8811 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR 0x0104 8812 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1 0x0108 8813 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2 0x010c 8814 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 8815 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS 0x0154 8816 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK 0x0158 8817 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY 0x015c 8818 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS 0x0160 8819 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK 0x0164 8820 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL 0x0168 8821 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0 0x016c 8822 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1 0x0170 8823 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2 0x0174 8824 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3 0x0178 8825 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0 0x0188 8826 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1 0x018c 8827 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2 0x0190 8828 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3 0x0194 8829 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST 0x02b0 8830 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP 0x02b4 8831 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL 0x02b6 8832 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST 0x0328 8833 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP 0x032c 8834 #define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL 0x032e 8835 8836 8837 // addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp 8838 // base address: 0x0 8839 #define cfgBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID 0x0000 8840 #define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID 0x0002 8841 #define cfgBIF_CFG_DEV0_EPF0_VF5_COMMAND 0x0004 8842 #define cfgBIF_CFG_DEV0_EPF0_VF5_STATUS 0x0006 8843 #define cfgBIF_CFG_DEV0_EPF0_VF5_REVISION_ID 0x0008 8844 #define cfgBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE 0x0009 8845 #define cfgBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS 0x000a 8846 #define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS 0x000b 8847 #define cfgBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE 0x000c 8848 #define cfgBIF_CFG_DEV0_EPF0_VF5_LATENCY 0x000d 8849 #define cfgBIF_CFG_DEV0_EPF0_VF5_HEADER 0x000e 8850 #define cfgBIF_CFG_DEV0_EPF0_VF5_BIST 0x000f 8851 #define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1 0x0010 8852 #define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2 0x0014 8853 #define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3 0x0018 8854 #define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4 0x001c 8855 #define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5 0x0020 8856 #define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6 0x0024 8857 #define cfgBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR 0x0028 8858 #define cfgBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID 0x002c 8859 #define cfgBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR 0x0030 8860 #define cfgBIF_CFG_DEV0_EPF0_VF5_CAP_PTR 0x0034 8861 #define cfgBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE 0x003c 8862 #define cfgBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN 0x003d 8863 #define cfgBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT 0x003e 8864 #define cfgBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY 0x003f 8865 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST 0x0064 8866 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP 0x0066 8867 #define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP 0x0068 8868 #define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL 0x006c 8869 #define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS 0x006e 8870 #define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CAP 0x0070 8871 #define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL 0x0074 8872 #define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS 0x0076 8873 #define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2 0x0088 8874 #define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2 0x008c 8875 #define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2 0x008e 8876 #define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2 0x0090 8877 #define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2 0x0094 8878 #define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2 0x0096 8879 #define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST 0x00a0 8880 #define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL 0x00a2 8881 #define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO 0x00a4 8882 #define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI 0x00a8 8883 #define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA 0x00a8 8884 #define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA 0x00aa 8885 #define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MASK 0x00ac 8886 #define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64 0x00ac 8887 #define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64 0x00ae 8888 #define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64 0x00b0 8889 #define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING 0x00b0 8890 #define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64 0x00b4 8891 #define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST 0x00c0 8892 #define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL 0x00c2 8893 #define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE 0x00c4 8894 #define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA 0x00c8 8895 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 8896 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR 0x0104 8897 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1 0x0108 8898 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2 0x010c 8899 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 8900 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS 0x0154 8901 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK 0x0158 8902 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY 0x015c 8903 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS 0x0160 8904 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK 0x0164 8905 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL 0x0168 8906 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0 0x016c 8907 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1 0x0170 8908 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2 0x0174 8909 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3 0x0178 8910 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0 0x0188 8911 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1 0x018c 8912 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2 0x0190 8913 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3 0x0194 8914 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST 0x02b0 8915 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP 0x02b4 8916 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL 0x02b6 8917 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST 0x0328 8918 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP 0x032c 8919 #define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL 0x032e 8920 8921 8922 // addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp 8923 // base address: 0x0 8924 #define cfgBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID 0x0000 8925 #define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID 0x0002 8926 #define cfgBIF_CFG_DEV0_EPF0_VF6_COMMAND 0x0004 8927 #define cfgBIF_CFG_DEV0_EPF0_VF6_STATUS 0x0006 8928 #define cfgBIF_CFG_DEV0_EPF0_VF6_REVISION_ID 0x0008 8929 #define cfgBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE 0x0009 8930 #define cfgBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS 0x000a 8931 #define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS 0x000b 8932 #define cfgBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE 0x000c 8933 #define cfgBIF_CFG_DEV0_EPF0_VF6_LATENCY 0x000d 8934 #define cfgBIF_CFG_DEV0_EPF0_VF6_HEADER 0x000e 8935 #define cfgBIF_CFG_DEV0_EPF0_VF6_BIST 0x000f 8936 #define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1 0x0010 8937 #define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2 0x0014 8938 #define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3 0x0018 8939 #define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4 0x001c 8940 #define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5 0x0020 8941 #define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6 0x0024 8942 #define cfgBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR 0x0028 8943 #define cfgBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID 0x002c 8944 #define cfgBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR 0x0030 8945 #define cfgBIF_CFG_DEV0_EPF0_VF6_CAP_PTR 0x0034 8946 #define cfgBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE 0x003c 8947 #define cfgBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN 0x003d 8948 #define cfgBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT 0x003e 8949 #define cfgBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY 0x003f 8950 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST 0x0064 8951 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP 0x0066 8952 #define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP 0x0068 8953 #define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL 0x006c 8954 #define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS 0x006e 8955 #define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CAP 0x0070 8956 #define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL 0x0074 8957 #define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS 0x0076 8958 #define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2 0x0088 8959 #define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2 0x008c 8960 #define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2 0x008e 8961 #define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2 0x0090 8962 #define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2 0x0094 8963 #define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2 0x0096 8964 #define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST 0x00a0 8965 #define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL 0x00a2 8966 #define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO 0x00a4 8967 #define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI 0x00a8 8968 #define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA 0x00a8 8969 #define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA 0x00aa 8970 #define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MASK 0x00ac 8971 #define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64 0x00ac 8972 #define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64 0x00ae 8973 #define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64 0x00b0 8974 #define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING 0x00b0 8975 #define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64 0x00b4 8976 #define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST 0x00c0 8977 #define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL 0x00c2 8978 #define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE 0x00c4 8979 #define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA 0x00c8 8980 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 8981 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR 0x0104 8982 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1 0x0108 8983 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2 0x010c 8984 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 8985 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS 0x0154 8986 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK 0x0158 8987 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY 0x015c 8988 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS 0x0160 8989 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK 0x0164 8990 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL 0x0168 8991 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0 0x016c 8992 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1 0x0170 8993 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2 0x0174 8994 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3 0x0178 8995 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0 0x0188 8996 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1 0x018c 8997 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2 0x0190 8998 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3 0x0194 8999 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST 0x02b0 9000 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP 0x02b4 9001 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL 0x02b6 9002 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST 0x0328 9003 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP 0x032c 9004 #define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL 0x032e 9005 9006 9007 // addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp 9008 // base address: 0x0 9009 #define cfgBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID 0x0000 9010 #define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID 0x0002 9011 #define cfgBIF_CFG_DEV0_EPF0_VF7_COMMAND 0x0004 9012 #define cfgBIF_CFG_DEV0_EPF0_VF7_STATUS 0x0006 9013 #define cfgBIF_CFG_DEV0_EPF0_VF7_REVISION_ID 0x0008 9014 #define cfgBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE 0x0009 9015 #define cfgBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS 0x000a 9016 #define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS 0x000b 9017 #define cfgBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE 0x000c 9018 #define cfgBIF_CFG_DEV0_EPF0_VF7_LATENCY 0x000d 9019 #define cfgBIF_CFG_DEV0_EPF0_VF7_HEADER 0x000e 9020 #define cfgBIF_CFG_DEV0_EPF0_VF7_BIST 0x000f 9021 #define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1 0x0010 9022 #define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2 0x0014 9023 #define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3 0x0018 9024 #define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4 0x001c 9025 #define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5 0x0020 9026 #define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6 0x0024 9027 #define cfgBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR 0x0028 9028 #define cfgBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID 0x002c 9029 #define cfgBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR 0x0030 9030 #define cfgBIF_CFG_DEV0_EPF0_VF7_CAP_PTR 0x0034 9031 #define cfgBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE 0x003c 9032 #define cfgBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN 0x003d 9033 #define cfgBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT 0x003e 9034 #define cfgBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY 0x003f 9035 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST 0x0064 9036 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP 0x0066 9037 #define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP 0x0068 9038 #define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL 0x006c 9039 #define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS 0x006e 9040 #define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CAP 0x0070 9041 #define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL 0x0074 9042 #define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS 0x0076 9043 #define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2 0x0088 9044 #define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2 0x008c 9045 #define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2 0x008e 9046 #define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2 0x0090 9047 #define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2 0x0094 9048 #define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2 0x0096 9049 #define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST 0x00a0 9050 #define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL 0x00a2 9051 #define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO 0x00a4 9052 #define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI 0x00a8 9053 #define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA 0x00a8 9054 #define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA 0x00aa 9055 #define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MASK 0x00ac 9056 #define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64 0x00ac 9057 #define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64 0x00ae 9058 #define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64 0x00b0 9059 #define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING 0x00b0 9060 #define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64 0x00b4 9061 #define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST 0x00c0 9062 #define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL 0x00c2 9063 #define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE 0x00c4 9064 #define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA 0x00c8 9065 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 9066 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR 0x0104 9067 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1 0x0108 9068 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2 0x010c 9069 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 9070 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS 0x0154 9071 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK 0x0158 9072 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY 0x015c 9073 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS 0x0160 9074 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK 0x0164 9075 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL 0x0168 9076 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0 0x016c 9077 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1 0x0170 9078 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2 0x0174 9079 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3 0x0178 9080 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0 0x0188 9081 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1 0x018c 9082 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2 0x0190 9083 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3 0x0194 9084 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST 0x02b0 9085 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP 0x02b4 9086 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL 0x02b6 9087 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST 0x0328 9088 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP 0x032c 9089 #define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL 0x032e 9090 9091 9092 // addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1 9093 // base address: 0x0 9094 #define regBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS 0x00eb 9095 #define regBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS_BASE_IDX 2 9096 #define regBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG 0x00ec 9097 #define regBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 9098 #define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 9099 #define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 9100 #define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 9101 #define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 9102 #define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 9103 #define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 9104 #define regBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 9105 #define regBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 9106 #define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 9107 #define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 9108 #define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 9109 #define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 9110 #define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 9111 #define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 9112 #define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ 0x0106 9113 #define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2 9114 #define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE 0x0107 9115 #define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2 9116 #define regBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING 0x0108 9117 #define regBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING_BASE_IDX 2 9118 #define regBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 9119 #define regBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 9120 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0 0x0136 9121 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 9122 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1 0x0137 9123 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 9124 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2 0x0138 9125 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 9126 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3 0x0139 9127 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 9128 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0 0x013a 9129 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 9130 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1 0x013b 9131 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 9132 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2 0x013c 9133 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 9134 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3 0x013d 9135 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 9136 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL 0x013e 9137 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL_BASE_IDX 2 9138 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL 0x013f 9139 #define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL_BASE_IDX 2 9140 #define regBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX 0x0140 9141 #define regBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX_BASE_IDX 2 9142 9143 9144 // addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC 9145 // base address: 0x0 9146 #define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX 0x0000 9147 #define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_BASE_IDX 0 9148 #define regBIF_BX_DEV0_EPF0_VF0_MM_DATA 0x0001 9149 #define regBIF_BX_DEV0_EPF0_VF0_MM_DATA_BASE_IDX 0 9150 #define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI 0x0006 9151 #define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI_BASE_IDX 0 9152 9153 9154 // addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1 9155 // base address: 0x0 9156 #define regRCC_DEV0_EPF0_VF0_RCC_ERR_LOG 0x0085 9157 #define regRCC_DEV0_EPF0_VF0_RCC_ERR_LOG_BASE_IDX 2 9158 #define regRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN 0x00c0 9159 #define regRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN_BASE_IDX 2 9160 #define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE 0x00c3 9161 #define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE_BASE_IDX 2 9162 #define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED 0x00c4 9163 #define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED_BASE_IDX 2 9164 #define regRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER 0x00c5 9165 #define regRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 9166 9167 9168 // addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf0_BIFDEC2 9169 // base address: 0x0 9170 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO 0x0400 9171 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 9172 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI 0x0401 9173 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 9174 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA 0x0402 9175 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 9176 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL 0x0403 9177 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 9178 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO 0x0404 9179 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 9180 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI 0x0405 9181 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 9182 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA 0x0406 9183 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 9184 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL 0x0407 9185 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 9186 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO 0x0408 9187 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 9188 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI 0x0409 9189 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 9190 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA 0x040a 9191 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 9192 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL 0x040b 9193 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 9194 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO 0x040c 9195 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 9196 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI 0x040d 9197 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 9198 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA 0x040e 9199 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 9200 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL 0x040f 9201 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 9202 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_PBA 0x0800 9203 #define regRCC_DEV0_EPF0_VF0_GFXMSIX_PBA_BASE_IDX 4 9204 9205 9206 // addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1 9207 // base address: 0x0 9208 #define regBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS 0x00eb 9209 #define regBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS_BASE_IDX 2 9210 #define regBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG 0x00ec 9211 #define regBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 9212 #define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 9213 #define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 9214 #define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 9215 #define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 9216 #define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 9217 #define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 9218 #define regBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 9219 #define regBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 9220 #define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 9221 #define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 9222 #define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 9223 #define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 9224 #define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 9225 #define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 9226 #define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ 0x0106 9227 #define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ_BASE_IDX 2 9228 #define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE 0x0107 9229 #define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE_BASE_IDX 2 9230 #define regBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING 0x0108 9231 #define regBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING_BASE_IDX 2 9232 #define regBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 9233 #define regBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 9234 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0 0x0136 9235 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 9236 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1 0x0137 9237 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 9238 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2 0x0138 9239 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 9240 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3 0x0139 9241 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 9242 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0 0x013a 9243 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 9244 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1 0x013b 9245 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 9246 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2 0x013c 9247 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 9248 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3 0x013d 9249 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 9250 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL 0x013e 9251 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL_BASE_IDX 2 9252 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL 0x013f 9253 #define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL_BASE_IDX 2 9254 #define regBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX 0x0140 9255 #define regBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX_BASE_IDX 2 9256 9257 9258 // addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC 9259 // base address: 0x0 9260 #define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX 0x0000 9261 #define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_BASE_IDX 0 9262 #define regBIF_BX_DEV0_EPF0_VF1_MM_DATA 0x0001 9263 #define regBIF_BX_DEV0_EPF0_VF1_MM_DATA_BASE_IDX 0 9264 #define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI 0x0006 9265 #define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI_BASE_IDX 0 9266 9267 9268 // addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1 9269 // base address: 0x0 9270 #define regRCC_DEV0_EPF0_VF1_RCC_ERR_LOG 0x0085 9271 #define regRCC_DEV0_EPF0_VF1_RCC_ERR_LOG_BASE_IDX 2 9272 #define regRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN 0x00c0 9273 #define regRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN_BASE_IDX 2 9274 #define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE 0x00c3 9275 #define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE_BASE_IDX 2 9276 #define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED 0x00c4 9277 #define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED_BASE_IDX 2 9278 #define regRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER 0x00c5 9279 #define regRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 9280 9281 9282 // addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf1_BIFDEC2 9283 // base address: 0x0 9284 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO 0x0400 9285 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 9286 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI 0x0401 9287 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 9288 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA 0x0402 9289 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 9290 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL 0x0403 9291 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 9292 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO 0x0404 9293 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 9294 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI 0x0405 9295 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 9296 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA 0x0406 9297 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 9298 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL 0x0407 9299 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 9300 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO 0x0408 9301 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 9302 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI 0x0409 9303 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 9304 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA 0x040a 9305 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 9306 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL 0x040b 9307 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 9308 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO 0x040c 9309 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 9310 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI 0x040d 9311 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 9312 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA 0x040e 9313 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 9314 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL 0x040f 9315 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 9316 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_PBA 0x0800 9317 #define regRCC_DEV0_EPF0_VF1_GFXMSIX_PBA_BASE_IDX 4 9318 9319 9320 // addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1 9321 // base address: 0x0 9322 #define regBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS 0x00eb 9323 #define regBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS_BASE_IDX 2 9324 #define regBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG 0x00ec 9325 #define regBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 9326 #define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 9327 #define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 9328 #define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 9329 #define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 9330 #define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 9331 #define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 9332 #define regBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 9333 #define regBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 9334 #define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 9335 #define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 9336 #define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 9337 #define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 9338 #define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 9339 #define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 9340 #define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ 0x0106 9341 #define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ_BASE_IDX 2 9342 #define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE 0x0107 9343 #define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE_BASE_IDX 2 9344 #define regBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING 0x0108 9345 #define regBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING_BASE_IDX 2 9346 #define regBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 9347 #define regBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 9348 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0 0x0136 9349 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 9350 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1 0x0137 9351 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 9352 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2 0x0138 9353 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 9354 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3 0x0139 9355 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 9356 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0 0x013a 9357 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 9358 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1 0x013b 9359 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 9360 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2 0x013c 9361 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 9362 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3 0x013d 9363 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 9364 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL 0x013e 9365 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL_BASE_IDX 2 9366 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL 0x013f 9367 #define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL_BASE_IDX 2 9368 #define regBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX 0x0140 9369 #define regBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX_BASE_IDX 2 9370 9371 9372 // addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC 9373 // base address: 0x0 9374 #define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX 0x0000 9375 #define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_BASE_IDX 0 9376 #define regBIF_BX_DEV0_EPF0_VF2_MM_DATA 0x0001 9377 #define regBIF_BX_DEV0_EPF0_VF2_MM_DATA_BASE_IDX 0 9378 #define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI 0x0006 9379 #define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI_BASE_IDX 0 9380 9381 9382 // addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1 9383 // base address: 0x0 9384 #define regRCC_DEV0_EPF0_VF2_RCC_ERR_LOG 0x0085 9385 #define regRCC_DEV0_EPF0_VF2_RCC_ERR_LOG_BASE_IDX 2 9386 #define regRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN 0x00c0 9387 #define regRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN_BASE_IDX 2 9388 #define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE 0x00c3 9389 #define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE_BASE_IDX 2 9390 #define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED 0x00c4 9391 #define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED_BASE_IDX 2 9392 #define regRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER 0x00c5 9393 #define regRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 9394 9395 9396 // addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf2_BIFDEC2 9397 // base address: 0x0 9398 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO 0x0400 9399 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 9400 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI 0x0401 9401 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 9402 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA 0x0402 9403 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 9404 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL 0x0403 9405 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 9406 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO 0x0404 9407 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 9408 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI 0x0405 9409 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 9410 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA 0x0406 9411 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 9412 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL 0x0407 9413 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 9414 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO 0x0408 9415 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 9416 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI 0x0409 9417 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 9418 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA 0x040a 9419 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 9420 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL 0x040b 9421 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 9422 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO 0x040c 9423 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 9424 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI 0x040d 9425 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 9426 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA 0x040e 9427 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 9428 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL 0x040f 9429 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 9430 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_PBA 0x0800 9431 #define regRCC_DEV0_EPF0_VF2_GFXMSIX_PBA_BASE_IDX 4 9432 9433 9434 // addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1 9435 // base address: 0x0 9436 #define regBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS 0x00eb 9437 #define regBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS_BASE_IDX 2 9438 #define regBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG 0x00ec 9439 #define regBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 9440 #define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 9441 #define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 9442 #define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 9443 #define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 9444 #define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 9445 #define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 9446 #define regBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 9447 #define regBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 9448 #define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 9449 #define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 9450 #define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 9451 #define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 9452 #define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 9453 #define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 9454 #define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ 0x0106 9455 #define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ_BASE_IDX 2 9456 #define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE 0x0107 9457 #define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE_BASE_IDX 2 9458 #define regBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING 0x0108 9459 #define regBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING_BASE_IDX 2 9460 #define regBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 9461 #define regBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 9462 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0 0x0136 9463 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 9464 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1 0x0137 9465 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 9466 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2 0x0138 9467 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 9468 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3 0x0139 9469 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 9470 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0 0x013a 9471 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 9472 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1 0x013b 9473 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 9474 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2 0x013c 9475 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 9476 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3 0x013d 9477 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 9478 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL 0x013e 9479 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL_BASE_IDX 2 9480 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL 0x013f 9481 #define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL_BASE_IDX 2 9482 #define regBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX 0x0140 9483 #define regBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX_BASE_IDX 2 9484 9485 9486 // addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC 9487 // base address: 0x0 9488 #define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX 0x0000 9489 #define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_BASE_IDX 0 9490 #define regBIF_BX_DEV0_EPF0_VF3_MM_DATA 0x0001 9491 #define regBIF_BX_DEV0_EPF0_VF3_MM_DATA_BASE_IDX 0 9492 #define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI 0x0006 9493 #define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI_BASE_IDX 0 9494 9495 9496 // addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1 9497 // base address: 0x0 9498 #define regRCC_DEV0_EPF0_VF3_RCC_ERR_LOG 0x0085 9499 #define regRCC_DEV0_EPF0_VF3_RCC_ERR_LOG_BASE_IDX 2 9500 #define regRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN 0x00c0 9501 #define regRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN_BASE_IDX 2 9502 #define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE 0x00c3 9503 #define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE_BASE_IDX 2 9504 #define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED 0x00c4 9505 #define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED_BASE_IDX 2 9506 #define regRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER 0x00c5 9507 #define regRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 9508 9509 9510 // addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf3_BIFDEC2 9511 // base address: 0x0 9512 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO 0x0400 9513 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 9514 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI 0x0401 9515 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 9516 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA 0x0402 9517 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 9518 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL 0x0403 9519 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 9520 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO 0x0404 9521 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 9522 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI 0x0405 9523 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 9524 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA 0x0406 9525 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 9526 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL 0x0407 9527 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 9528 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO 0x0408 9529 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 9530 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI 0x0409 9531 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 9532 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA 0x040a 9533 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 9534 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL 0x040b 9535 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 9536 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO 0x040c 9537 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 9538 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI 0x040d 9539 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 9540 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA 0x040e 9541 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 9542 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL 0x040f 9543 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 9544 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_PBA 0x0800 9545 #define regRCC_DEV0_EPF0_VF3_GFXMSIX_PBA_BASE_IDX 4 9546 9547 9548 // addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1 9549 // base address: 0x0 9550 #define regBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS 0x00eb 9551 #define regBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS_BASE_IDX 2 9552 #define regBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG 0x00ec 9553 #define regBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 9554 #define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 9555 #define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 9556 #define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 9557 #define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 9558 #define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 9559 #define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 9560 #define regBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 9561 #define regBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 9562 #define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 9563 #define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 9564 #define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 9565 #define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 9566 #define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 9567 #define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 9568 #define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ 0x0106 9569 #define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ_BASE_IDX 2 9570 #define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE 0x0107 9571 #define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE_BASE_IDX 2 9572 #define regBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING 0x0108 9573 #define regBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING_BASE_IDX 2 9574 #define regBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 9575 #define regBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 9576 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0 0x0136 9577 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 9578 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1 0x0137 9579 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 9580 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2 0x0138 9581 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 9582 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3 0x0139 9583 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 9584 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0 0x013a 9585 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 9586 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1 0x013b 9587 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 9588 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2 0x013c 9589 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 9590 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3 0x013d 9591 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 9592 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL 0x013e 9593 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL_BASE_IDX 2 9594 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL 0x013f 9595 #define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL_BASE_IDX 2 9596 #define regBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX 0x0140 9597 #define regBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX_BASE_IDX 2 9598 9599 9600 // addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC 9601 // base address: 0x0 9602 #define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX 0x0000 9603 #define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_BASE_IDX 0 9604 #define regBIF_BX_DEV0_EPF0_VF4_MM_DATA 0x0001 9605 #define regBIF_BX_DEV0_EPF0_VF4_MM_DATA_BASE_IDX 0 9606 #define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI 0x0006 9607 #define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI_BASE_IDX 0 9608 9609 9610 // addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1 9611 // base address: 0x0 9612 #define regRCC_DEV0_EPF0_VF4_RCC_ERR_LOG 0x0085 9613 #define regRCC_DEV0_EPF0_VF4_RCC_ERR_LOG_BASE_IDX 2 9614 #define regRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN 0x00c0 9615 #define regRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN_BASE_IDX 2 9616 #define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE 0x00c3 9617 #define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE_BASE_IDX 2 9618 #define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED 0x00c4 9619 #define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED_BASE_IDX 2 9620 #define regRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER 0x00c5 9621 #define regRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 9622 9623 9624 // addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf4_BIFDEC2 9625 // base address: 0x0 9626 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO 0x0400 9627 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 9628 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI 0x0401 9629 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 9630 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA 0x0402 9631 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 9632 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL 0x0403 9633 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 9634 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO 0x0404 9635 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 9636 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI 0x0405 9637 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 9638 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA 0x0406 9639 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 9640 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL 0x0407 9641 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 9642 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO 0x0408 9643 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 9644 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI 0x0409 9645 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 9646 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA 0x040a 9647 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 9648 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL 0x040b 9649 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 9650 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO 0x040c 9651 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 9652 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI 0x040d 9653 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 9654 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA 0x040e 9655 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 9656 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL 0x040f 9657 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 9658 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_PBA 0x0800 9659 #define regRCC_DEV0_EPF0_VF4_GFXMSIX_PBA_BASE_IDX 4 9660 9661 9662 // addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1 9663 // base address: 0x0 9664 #define regBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS 0x00eb 9665 #define regBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS_BASE_IDX 2 9666 #define regBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG 0x00ec 9667 #define regBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 9668 #define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 9669 #define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 9670 #define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 9671 #define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 9672 #define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 9673 #define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 9674 #define regBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 9675 #define regBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 9676 #define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 9677 #define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 9678 #define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 9679 #define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 9680 #define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 9681 #define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 9682 #define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ 0x0106 9683 #define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ_BASE_IDX 2 9684 #define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE 0x0107 9685 #define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE_BASE_IDX 2 9686 #define regBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING 0x0108 9687 #define regBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING_BASE_IDX 2 9688 #define regBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 9689 #define regBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 9690 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0 0x0136 9691 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 9692 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1 0x0137 9693 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 9694 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2 0x0138 9695 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 9696 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3 0x0139 9697 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 9698 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0 0x013a 9699 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 9700 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1 0x013b 9701 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 9702 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2 0x013c 9703 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 9704 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3 0x013d 9705 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 9706 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL 0x013e 9707 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL_BASE_IDX 2 9708 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL 0x013f 9709 #define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL_BASE_IDX 2 9710 #define regBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX 0x0140 9711 #define regBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX_BASE_IDX 2 9712 9713 9714 // addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC 9715 // base address: 0x0 9716 #define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX 0x0000 9717 #define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_BASE_IDX 0 9718 #define regBIF_BX_DEV0_EPF0_VF5_MM_DATA 0x0001 9719 #define regBIF_BX_DEV0_EPF0_VF5_MM_DATA_BASE_IDX 0 9720 #define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI 0x0006 9721 #define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI_BASE_IDX 0 9722 9723 9724 // addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1 9725 // base address: 0x0 9726 #define regRCC_DEV0_EPF0_VF5_RCC_ERR_LOG 0x0085 9727 #define regRCC_DEV0_EPF0_VF5_RCC_ERR_LOG_BASE_IDX 2 9728 #define regRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN 0x00c0 9729 #define regRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN_BASE_IDX 2 9730 #define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE 0x00c3 9731 #define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE_BASE_IDX 2 9732 #define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED 0x00c4 9733 #define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED_BASE_IDX 2 9734 #define regRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER 0x00c5 9735 #define regRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 9736 9737 9738 // addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf5_BIFDEC2 9739 // base address: 0x0 9740 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO 0x0400 9741 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 9742 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI 0x0401 9743 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 9744 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA 0x0402 9745 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 9746 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL 0x0403 9747 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 9748 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO 0x0404 9749 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 9750 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI 0x0405 9751 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 9752 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA 0x0406 9753 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 9754 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL 0x0407 9755 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 9756 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO 0x0408 9757 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 9758 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI 0x0409 9759 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 9760 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA 0x040a 9761 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 9762 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL 0x040b 9763 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 9764 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO 0x040c 9765 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 9766 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI 0x040d 9767 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 9768 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA 0x040e 9769 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 9770 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL 0x040f 9771 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 9772 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_PBA 0x0800 9773 #define regRCC_DEV0_EPF0_VF5_GFXMSIX_PBA_BASE_IDX 4 9774 9775 9776 // addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1 9777 // base address: 0x0 9778 #define regBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS 0x00eb 9779 #define regBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS_BASE_IDX 2 9780 #define regBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG 0x00ec 9781 #define regBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 9782 #define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 9783 #define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 9784 #define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 9785 #define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 9786 #define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 9787 #define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 9788 #define regBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 9789 #define regBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 9790 #define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 9791 #define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 9792 #define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 9793 #define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 9794 #define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 9795 #define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 9796 #define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ 0x0106 9797 #define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ_BASE_IDX 2 9798 #define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE 0x0107 9799 #define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE_BASE_IDX 2 9800 #define regBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING 0x0108 9801 #define regBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING_BASE_IDX 2 9802 #define regBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 9803 #define regBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 9804 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0 0x0136 9805 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 9806 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1 0x0137 9807 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 9808 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2 0x0138 9809 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 9810 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3 0x0139 9811 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 9812 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0 0x013a 9813 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 9814 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1 0x013b 9815 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 9816 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2 0x013c 9817 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 9818 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3 0x013d 9819 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 9820 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL 0x013e 9821 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL_BASE_IDX 2 9822 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL 0x013f 9823 #define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL_BASE_IDX 2 9824 #define regBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX 0x0140 9825 #define regBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX_BASE_IDX 2 9826 9827 9828 // addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC 9829 // base address: 0x0 9830 #define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX 0x0000 9831 #define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_BASE_IDX 0 9832 #define regBIF_BX_DEV0_EPF0_VF6_MM_DATA 0x0001 9833 #define regBIF_BX_DEV0_EPF0_VF6_MM_DATA_BASE_IDX 0 9834 #define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI 0x0006 9835 #define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI_BASE_IDX 0 9836 9837 9838 // addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1 9839 // base address: 0x0 9840 #define regRCC_DEV0_EPF0_VF6_RCC_ERR_LOG 0x0085 9841 #define regRCC_DEV0_EPF0_VF6_RCC_ERR_LOG_BASE_IDX 2 9842 #define regRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN 0x00c0 9843 #define regRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN_BASE_IDX 2 9844 #define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE 0x00c3 9845 #define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE_BASE_IDX 2 9846 #define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED 0x00c4 9847 #define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED_BASE_IDX 2 9848 #define regRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER 0x00c5 9849 #define regRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 9850 9851 9852 // addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf6_BIFDEC2 9853 // base address: 0x0 9854 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO 0x0400 9855 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 9856 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI 0x0401 9857 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 9858 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA 0x0402 9859 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 9860 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL 0x0403 9861 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 9862 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO 0x0404 9863 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 9864 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI 0x0405 9865 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 9866 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA 0x0406 9867 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 9868 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL 0x0407 9869 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 9870 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO 0x0408 9871 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 9872 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI 0x0409 9873 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 9874 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA 0x040a 9875 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 9876 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL 0x040b 9877 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 9878 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO 0x040c 9879 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 9880 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI 0x040d 9881 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 9882 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA 0x040e 9883 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 9884 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL 0x040f 9885 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 9886 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_PBA 0x0800 9887 #define regRCC_DEV0_EPF0_VF6_GFXMSIX_PBA_BASE_IDX 4 9888 9889 9890 // addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1 9891 // base address: 0x0 9892 #define regBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS 0x00eb 9893 #define regBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS_BASE_IDX 2 9894 #define regBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG 0x00ec 9895 #define regBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 9896 #define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 9897 #define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 9898 #define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 9899 #define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 9900 #define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 9901 #define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 9902 #define regBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 9903 #define regBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 9904 #define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 9905 #define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 9906 #define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 9907 #define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 9908 #define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa 9909 #define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 9910 #define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ 0x0106 9911 #define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ_BASE_IDX 2 9912 #define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE 0x0107 9913 #define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE_BASE_IDX 2 9914 #define regBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING 0x0108 9915 #define regBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING_BASE_IDX 2 9916 #define regBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 9917 #define regBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 9918 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0 0x0136 9919 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 9920 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1 0x0137 9921 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 9922 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2 0x0138 9923 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 9924 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3 0x0139 9925 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 9926 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0 0x013a 9927 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 9928 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1 0x013b 9929 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 9930 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2 0x013c 9931 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 9932 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3 0x013d 9933 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 9934 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL 0x013e 9935 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL_BASE_IDX 2 9936 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL 0x013f 9937 #define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL_BASE_IDX 2 9938 #define regBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX 0x0140 9939 #define regBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX_BASE_IDX 2 9940 9941 9942 // addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC 9943 // base address: 0x0 9944 #define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX 0x0000 9945 #define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_BASE_IDX 0 9946 #define regBIF_BX_DEV0_EPF0_VF7_MM_DATA 0x0001 9947 #define regBIF_BX_DEV0_EPF0_VF7_MM_DATA_BASE_IDX 0 9948 #define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI 0x0006 9949 #define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI_BASE_IDX 0 9950 9951 9952 // addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1 9953 // base address: 0x0 9954 #define regRCC_DEV0_EPF0_VF7_RCC_ERR_LOG 0x0085 9955 #define regRCC_DEV0_EPF0_VF7_RCC_ERR_LOG_BASE_IDX 2 9956 #define regRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN 0x00c0 9957 #define regRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN_BASE_IDX 2 9958 #define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE 0x00c3 9959 #define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE_BASE_IDX 2 9960 #define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED 0x00c4 9961 #define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED_BASE_IDX 2 9962 #define regRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER 0x00c5 9963 #define regRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 9964 9965 9966 // addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf7_BIFDEC2 9967 // base address: 0x0 9968 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO 0x0400 9969 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 9970 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI 0x0401 9971 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 9972 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA 0x0402 9973 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 9974 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL 0x0403 9975 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 9976 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO 0x0404 9977 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 9978 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI 0x0405 9979 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 9980 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA 0x0406 9981 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 9982 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL 0x0407 9983 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 9984 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO 0x0408 9985 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 9986 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI 0x0409 9987 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 9988 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA 0x040a 9989 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 9990 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL 0x040b 9991 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 9992 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO 0x040c 9993 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 9994 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI 0x040d 9995 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 9996 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA 0x040e 9997 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 9998 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL 0x040f 9999 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 10000 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_PBA 0x0800 10001 #define regRCC_DEV0_EPF0_VF7_GFXMSIX_PBA_BASE_IDX 4 10002 10003 10004 #endif 10005