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Searched refs:rd32 (Results 1 – 25 of 103) sorted by relevance

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/linux/drivers/net/ethernet/intel/igb/
H A De1000_mac.c58 reg = rd32(E1000_STATUS); in igb_get_bus_info_pcie()
153 bits = rd32(E1000_VLVF(regindex)) & E1000_VLVF_VLANID_MASK; in igb_find_vlvf_slot()
224 bits = rd32(E1000_VLVF(vlvf_index)); in igb_vfta_set()
560 rd32(E1000_CRCERRS); in igb_clear_hw_cntrs_base()
561 rd32(E1000_SYMERRS); in igb_clear_hw_cntrs_base()
562 rd32(E1000_MPC); in igb_clear_hw_cntrs_base()
563 rd32(E1000_SCC); in igb_clear_hw_cntrs_base()
564 rd32(E1000_ECOL); in igb_clear_hw_cntrs_base()
565 rd32(E1000_MCC); in igb_clear_hw_cntrs_base()
566 rd32(E1000_LATECOL); in igb_clear_hw_cntrs_base()
[all …]
H A De1000_82575.c96 reg = rd32(E1000_MDIC); in igb_sgmii_uses_mdio_82575()
104 reg = rd32(E1000_MDICNFG); in igb_sgmii_uses_mdio_82575()
192 ctrl_ext = rd32(E1000_CTRL_EXT); in igb_init_phy_params_82575()
225 hw->bus.func = FIELD_GET(E1000_STATUS_FUNC_MASK, rd32(E1000_STATUS)); in igb_init_phy_params_82575()
329 u32 eecd = rd32(E1000_EECD); in igb_init_nvm_params_82575()
451 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK) in igb_init_mac_params_82575()
500 ctrl_ext = rd32(E1000_CTRL_EXT); in igb_set_sfp_media_type_82575()
625 ctrl_ext = rd32(E1000_CTRL_EXT); in igb_get_invariants_82575()
849 mdic = rd32(E1000_MDIC); in igb_get_phy_id_82575()
858 mdic = rd32(E1000_MDICNFG); in igb_get_phy_id_82575()
[all …]
H A Digb_ethtool.c147 0 : rd32(E1000_STATUS); in igb_get_link_ksettings()
477 regs_buff[0] = rd32(E1000_CTRL); in igb_get_regs()
478 regs_buff[1] = rd32(E1000_STATUS); in igb_get_regs()
479 regs_buff[2] = rd32(E1000_CTRL_EXT); in igb_get_regs()
480 regs_buff[3] = rd32(E1000_MDIC); in igb_get_regs()
481 regs_buff[4] = rd32(E1000_SCTL); in igb_get_regs()
482 regs_buff[5] = rd32(E1000_CONNSW); in igb_get_regs()
483 regs_buff[6] = rd32(E1000_VET); in igb_get_regs()
484 regs_buff[7] = rd32(E1000_LEDCTL); in igb_get_regs()
485 regs_buff[8] = rd32(E1000_PBA); in igb_get_regs()
[all …]
H A Digb_ptp.c83 lo = rd32(E1000_SYSTIML); in igb_ptp_read_82576()
84 hi = rd32(E1000_SYSTIMH); in igb_ptp_read_82576()
104 rd32(E1000_SYSTIMR); in igb_ptp_read_82580()
105 lo = rd32(E1000_SYSTIML); in igb_ptp_read_82580()
106 hi = rd32(E1000_SYSTIMH); in igb_ptp_read_82580()
125 rd32(E1000_SYSTIMR); in igb_ptp_read_i210()
126 nsec = rd32(E1000_SYSTIML); in igb_ptp_read_i210()
127 sec = rd32(E1000_SYSTIMH); in igb_ptp_read_i210()
273 lo = rd32(E1000_SYSTIML); in igb_ptp_gettimex_82576()
275 hi = rd32(E1000_SYSTIMH); in igb_ptp_gettimex_82576()
[all …]
H A De1000_i210.c30 swsm = rd32(E1000_SWSM); in igb_get_hw_semaphore_i210()
46 swsm = rd32(E1000_SWSM); in igb_get_hw_semaphore_i210()
63 swsm = rd32(E1000_SWSM); in igb_get_hw_semaphore_i210()
67 if (rd32(E1000_SWSM) & E1000_SWSM_SWESMBI) in igb_get_hw_semaphore_i210()
131 swfw_sync = rd32(E1000_SW_FW_SYNC); in igb_acquire_swfw_sync_i210()
170 swfw_sync = rd32(E1000_SW_FW_SYNC); in igb_release_swfw_sync_i210()
254 rd32(E1000_SRWR)) { in igb_write_nvm_srwr()
332 invm_dword = rd32(E1000_INVM_DATA_REG(i)); in igb_read_invm_word_i210()
458 invm_dword = rd32(E1000_INVM_DATA_REG(i)); in igb_read_invm_version()
635 reg = rd32(E1000_EECD); in igb_pool_flash_update_done_i210()
[all …]
H A Digb_main.c266 regs[n] = rd32(E1000_RDLEN(n)); in igb_regdump()
270 regs[n] = rd32(E1000_RDH(n)); in igb_regdump()
274 regs[n] = rd32(E1000_RDT(n)); in igb_regdump()
278 regs[n] = rd32(E1000_RXDCTL(n)); in igb_regdump()
282 regs[n] = rd32(E1000_RDBAL(n)); in igb_regdump()
286 regs[n] = rd32(E1000_RDBAH(n)); in igb_regdump()
290 regs[n] = rd32(E1000_TDBAL(n)); in igb_regdump()
294 regs[n] = rd32(E1000_TDBAH(n)); in igb_regdump()
298 regs[n] = rd32(E1000_TDLEN(n)); in igb_regdump()
302 regs[n] = rd32(E1000_TDH(n)); in igb_regdump()
[all …]
H A De1000_nvm.c53 u32 eecd = rd32(E1000_EECD); in igb_shift_out_eec_bits()
98 eecd = rd32(E1000_EECD); in igb_shift_in_eec_bits()
107 eecd = rd32(E1000_EECD); in igb_shift_in_eec_bits()
135 reg = rd32(E1000_EERD); in igb_poll_eerd_eewr_done()
137 reg = rd32(E1000_EEWR); in igb_poll_eerd_eewr_done()
160 u32 eecd = rd32(E1000_EECD); in igb_acquire_nvm()
166 eecd = rd32(E1000_EECD); in igb_acquire_nvm()
172 eecd = rd32(E1000_EECD); in igb_acquire_nvm()
195 u32 eecd = rd32(E1000_EECD); in igb_standby_nvm()
220 eecd = rd32(E1000_EECD); in e1000_stop_nvm()
[all …]
/linux/drivers/net/ethernet/intel/igc/
H A Digc_i225.c49 swsm = rd32(IGC_SWSM); in igc_get_hw_semaphore_i225()
65 swsm = rd32(IGC_SWSM); in igc_get_hw_semaphore_i225()
82 swsm = rd32(IGC_SWSM); in igc_get_hw_semaphore_i225()
86 if (rd32(IGC_SWSM) & IGC_SWSM_SWESMBI) in igc_get_hw_semaphore_i225()
124 swfw_sync = rd32(IGC_SW_FW_SYNC); in igc_acquire_swfw_sync_i225()
170 swfw_sync = rd32(IGC_SW_FW_SYNC); in igc_release_swfw_sync_i225()
253 rd32(IGC_SRWR)) { in igc_write_nvm_srwr()
357 reg = rd32(IGC_EECD); in igc_pool_flash_update_done_i225()
383 flup = rd32(IGC_EECD) | IGC_EECD_FLUPD_I225; in igc_update_flash_i225()
464 eec = rd32(IGC_EECD); in igc_get_flash_presence_i225()
[all …]
H A Digc_tsn.c59 return !!(rd32(IGC_TQAVCTRL) & IGC_TQAVCTRL_TRANSMIT_MODE_TSN); in igc_tsn_is_tx_mode_in_tsn()
96 retxctl = rd32(IGC_RETX_CTL) & IGC_RETX_CTL_WATERMARK_MASK; in igc_tsn_restore_retx_default()
104 return (rd32(IGC_BASET_H) || rd32(IGC_BASET_L)) && in igc_tsn_is_taprio_activated_by_user()
113 txarb = rd32(IGC_TXARB); in igc_tsn_tx_arb()
145 tqavctrl = rd32(IGC_TQAVCTRL); in igc_tsn_disable_offload()
185 retxctl = rd32(IGC_RETX_CTL); in igc_tsn_set_retx_qbvfullthreshold()
234 tqavctrl = rd32(IGC_TQAVCTRL); in igc_tsn_enable_offload()
340 tqavcc = rd32(IGC_TQAVCC(i)); in igc_tsn_enable_offload()
352 tqavcc = rd32(IGC_TQAVCC(i)); in igc_tsn_enable_offload()
364 tqavctrl = rd32(IGC_TQAVCTRL) & ~IGC_TQAVCTRL_FUTSCDDIS; in igc_tsn_enable_offload()
[all …]
H A Digc_ptp.c31 nsec = rd32(IGC_SYSTIML); in igc_ptp_read()
32 sec = rd32(IGC_SYSTIMH); in igc_ptp_read()
103 ts->tv_nsec = rd32(IGC_SYSTIML); in igc_ptp_gettimex64_i225()
104 ts->tv_sec = rd32(IGC_SYSTIMH); in igc_ptp_gettimex64_i225()
178 ctrl = rd32(IGC_CTRL); in igc_pin_perout()
179 ctrl_ext = rd32(IGC_CTRL_EXT); in igc_pin_perout()
180 tssdp = rd32(IGC_TSSDP); in igc_pin_perout()
224 ctrl = rd32(IGC_CTRL); in igc_pin_extts()
225 ctrl_ext = rd32(IGC_CTRL_EXT); in igc_pin_extts()
226 tssdp = rd32(IGC_TSSDP); in igc_pin_extts()
[all …]
H A Digc_base.c40 ctrl = rd32(IGC_CTRL); in igc_reset_hw_base()
56 rd32(IGC_ICR); in igc_reset_hw_base()
68 u32 eecd = rd32(IGC_EECD); in igc_init_nvm_params_base()
112 ctrl = rd32(IGC_CTRL); in igc_setup_copper_link_base()
164 hw->bus.func = FIELD_GET(IGC_STATUS_FUNC_MASK, rd32(IGC_STATUS)); in igc_init_phy_params_base()
336 rfctl = rd32(IGC_RFCTL); in igc_rx_fifo_flush_base()
340 if (!(rd32(IGC_MANC) & IGC_MANC_RCV_TCO_EN)) in igc_rx_fifo_flush_base()
345 rxdctl[i] = rd32(IGC_RXDCTL(i)); in igc_rx_fifo_flush_base()
354 rx_enabled |= rd32(IGC_RXDCTL(i)); in igc_rx_fifo_flush_base()
368 rlpml = rd32(IGC_RLPML); in igc_rx_fifo_flush_base()
[all …]
H A Digc_dump.c54 regs[n] = rd32(IGC_RDLEN(n)); in igc_regdump()
58 regs[n] = rd32(IGC_RDH(n)); in igc_regdump()
62 regs[n] = rd32(IGC_RDT(n)); in igc_regdump()
66 regs[n] = rd32(IGC_RXDCTL(n)); in igc_regdump()
70 regs[n] = rd32(IGC_RDBAL(n)); in igc_regdump()
74 regs[n] = rd32(IGC_RDBAH(n)); in igc_regdump()
78 regs[n] = rd32(IGC_TDBAL(n)); in igc_regdump()
82 regs[n] = rd32(IGC_TDBAH(n)); in igc_regdump()
86 regs[n] = rd32(IGC_TDLEN(n)); in igc_regdump()
90 regs[n] = rd32(IGC_TDH(n)); in igc_regdump()
[all …]
H A Digc_nvm.c23 reg = rd32(IGC_EERD); in igc_poll_eerd_eewr_done()
25 reg = rd32(IGC_EEWR); in igc_poll_eerd_eewr_done()
49 u32 eecd = rd32(IGC_EECD); in igc_acquire_nvm()
53 eecd = rd32(IGC_EECD); in igc_acquire_nvm()
59 eecd = rd32(IGC_EECD); in igc_acquire_nvm()
83 eecd = rd32(IGC_EECD); in igc_release_nvm()
122 data[i] = (rd32(IGC_EERD) >> IGC_NVM_RW_REG_DATA); in igc_read_nvm_eerd()
139 rar_high = rd32(IGC_RAH(0)); in igc_read_mac_addr()
140 rar_low = rd32(IGC_RAL(0)); in igc_read_mac_addr()
H A Digc_ethtool.c180 regs_buff[0] = rd32(IGC_CTRL); in igc_ethtool_get_regs()
181 regs_buff[1] = rd32(IGC_STATUS); in igc_ethtool_get_regs()
182 regs_buff[2] = rd32(IGC_CTRL_EXT); in igc_ethtool_get_regs()
183 regs_buff[3] = rd32(IGC_MDIC); in igc_ethtool_get_regs()
184 regs_buff[4] = rd32(IGC_CONNSW); in igc_ethtool_get_regs()
187 regs_buff[5] = rd32(IGC_EECD); in igc_ethtool_get_regs()
193 regs_buff[6] = rd32(IGC_EICS); in igc_ethtool_get_regs()
194 regs_buff[7] = rd32(IGC_EICS); in igc_ethtool_get_regs()
195 regs_buff[8] = rd32(IGC_EIMS); in igc_ethtool_get_regs()
196 regs_buff[9] = rd32(IGC_EIMC); in igc_ethtool_get_regs()
[all …]
H A Digc_main.c158 ctrl_ext = rd32(IGC_CTRL_EXT); in igc_release_hw_control()
177 ctrl_ext = rd32(IGC_CTRL_EXT); in igc_get_hw_control()
325 txdctl = rd32(IGC_TXDCTL(idx)); in igc_disable_tx_ring_hw()
677 srrctl = rd32(IGC_SRRCTL(reg_idx)); in igc_configure_rx_ring()
803 rxcsum = rd32(IGC_RXCSUM); in igc_setup_mrqc()
840 rctl = rd32(IGC_RCTL); in igc_setup_rctl()
891 tctl = rd32(IGC_TCTL); in igc_setup_tctl()
1838 ctrl = rd32(IGC_CTRL); in igc_vlan_mode()
3164 !(rd32(IGC_STATUS) & IGC_STATUS_TXOFF) && in igc_clean_tx_irq()
3165 (rd32(IGC_TDH(tx_ring->reg_idx)) != readl(tx_ring->tail)) && in igc_clean_tx_irq()
[all …]
H A Digc_phy.c19 manc = rd32(IGC_MANC); in igc_check_reset_block()
177 phpm = rd32(IGC_I225_PHPM); in igc_phy_hw_reset()
179 ctrl = rd32(IGC_CTRL); in igc_phy_hw_reset()
191 phpm = rd32(IGC_I225_PHPM); in igc_phy_hw_reset()
560 mdic = rd32(IGC_MDIC); in igc_read_phy_reg_mdic()
617 mdic = rd32(IGC_MDIC); in igc_write_phy_reg_mdic()
/linux/drivers/net/ethernet/wangxun/libwx/
H A Dwx_hw.c33 ret = read_poll_timeout(rd32, val, !(val & WX_MSCC_BUSY), 1000, in wx_phy_read_reg_mdi()
40 return (u16)rd32(wx, WX_MSCC); in wx_phy_read_reg_mdi()
62 ret = read_poll_timeout(rd32, val, !(val & WX_MSCC_BUSY), 1000, in wx_phy_write_reg_mdi()
174 return read_poll_timeout(rd32, val, (val & 0x1), 10, 100000, in wx_fmgr_cmd_op()
186 *data = rd32(wx, WX_SPI_DATA); in wx_flash_read_dword()
197 if (!(rd32(hw, WX_SPI_STATUS) & in wx_check_flash_load()
200 err = read_poll_timeout(rd32, reg, !(reg & check_bit), 20000, 2000000, in wx_check_flash_load()
228 fwsm = rd32(wx, WX_MIS_ST); in wx_mng_present()
268 ret = read_poll_timeout(rd32, sem, !(sem & mask), in wx_acquire_sw_sync()
334 status = read_poll_timeout(rd32, hicr, hicr & WX_MNG_MBOX_CTL_FWRDY, 1000, in wx_host_interface_command()
[all …]
/linux/drivers/net/ethernet/intel/i40e/
H A Di40e_ptp.c163 lo = rd32(hw, I40E_PRTTSYN_EVNT_L(0)); in i40e_ptp_extts0_work()
164 hi = rd32(hw, I40E_PRTTSYN_EVNT_H(0)); in i40e_ptp_extts0_work()
232 rd32(&pf->hw, I40E_PRTTSYN_RXTIME_L(i)); in i40_ptp_reset_timing_events()
233 rd32(&pf->hw, I40E_PRTTSYN_RXTIME_H(i)); in i40_ptp_reset_timing_events()
237 rd32(&pf->hw, I40E_PRTTSYN_TXTIME_L); in i40_ptp_reset_timing_events()
238 rd32(&pf->hw, I40E_PRTTSYN_TXTIME_H); in i40_ptp_reset_timing_events()
290 lo = rd32(hw, I40E_PRTTSYN_TIME_L); in i40e_ptp_read()
292 hi = rd32(hw, I40E_PRTTSYN_TIME_H); in i40e_ptp_read()
641 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1); in i40e_ptp_get_rx_events()
700 rd32(hw, I40E_PRTTSYN_RXTIME_H(i)); in i40e_ptp_rx_hang()
[all …]
H A Di40e_dcb.c24 reg = rd32(hw, I40E_PRTDCB_GENS); in i40e_get_dcbx_status()
1283 u32 reg = rd32(hw, I40E_PRTDCB_RETSC); in i40e_dcb_hw_rx_fifo_config()
1348 reg = rd32(hw, I40E_PRT_SWR_PM_THR); in i40e_dcb_hw_rx_cmd_monitor_config()
1353 reg = rd32(hw, I40E_PRTDCB_RPPMC); in i40e_dcb_hw_rx_cmd_monitor_config()
1391 reg = rd32(hw, I40E_PRTDCB_MFLCN); in i40e_dcb_hw_pfc_config()
1403 reg = rd32(hw, I40E_PRTDCB_FCCFG); in i40e_dcb_hw_pfc_config()
1413 reg = rd32(hw, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP); in i40e_dcb_hw_pfc_config()
1417 reg = rd32(hw, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP); in i40e_dcb_hw_pfc_config()
1423 reg = rd32(hw, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE); in i40e_dcb_hw_pfc_config()
1429 reg = rd32(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE); in i40e_dcb_hw_pfc_config()
[all …]
H A Di40e_diag.c22 orig_val = rd32(hw, reg); in i40e_diag_reg_pattern_test()
26 val = rd32(hw, reg); in i40e_diag_reg_pattern_test()
36 val = rd32(hw, reg); in i40e_diag_reg_pattern_test()
/linux/drivers/net/ethernet/meta/fbnic/
H A Dfbnic_hw_stats.c14 stat->u.old_reg_value_32 = rd32(fbd, reg); in fbnic_hw_stat_rst32()
22 new_reg_value = rd32(fbd, reg); in fbnic_hw_stat_rd32()
31 prev_upper = rd32(fbd, reg + offset); in fbnic_stat_rd64()
32 lower = rd32(fbd, reg); in fbnic_stat_rd64()
33 upper = rd32(fbd, reg + offset); in fbnic_stat_rd64()
H A Dfbnic_mac.c14 u32 val = rd32(fbd, offset); in fbnic_init_readrq()
30 u32 val = rd32(fbd, offset); in fbnic_init_mps()
181 rx_enable = !!(rd32(fbd, FBNIC_RPC_RMI_CONFIG) & in fbnic_mac_init_rxb()
195 rd32(fbd, FBNIC_RXB_PBUF_CFG(i))); in fbnic_mac_init_rxb()
426 rxb_pause_ctrl = rd32(fbd, FBNIC_RXB_PAUSE_DROP_CTRL); in fbnic_mac_tx_pause_config()
437 u32 pcs_intr_mask = rd32(fbd, FBNIC_SIG_PCS_INTR_STS); in fbnic_pcs_get_link_event_asic()
472 pcs_status = rd32(fbd, FBNIC_SIG_PCS_OUT0); in fbnic_mac_get_pcs_link_status()
514 rd32(fbd, FBNIC_SIG_PCS_OUT1)); in fbnic_mac_get_pcs_link_status()
623 mac_ctrl = rd32(fbd, FBNIC_SIG_MAC_IN0); in fbnic_mac_link_down_asic()
642 mac_ctrl = rd32(fbd, FBNIC_SIG_MAC_IN0); in fbnic_mac_link_up_asic()
/linux/drivers/net/ethernet/wangxun/ngbe/
H A Dngbe_mdio.c20 return (u16)rd32(wx, NGBE_PHY_CONFIG(regnum)); in ngbe_phy_read_reg_internal()
95 reg = rd32(wx, WX_MAC_TX_CFG); in ngbe_mac_link_up()
101 reg = rd32(wx, WX_MAC_RX_CFG); in ngbe_mac_link_up()
104 reg = rd32(wx, WX_MAC_WDG_TIMEOUT); in ngbe_mac_link_up()
/linux/drivers/net/ethernet/intel/ice/
H A Dice_osdep.h23 #define rd32(a, reg) readl((a)->hw_addr + (reg)) macro
28 read_poll_timeout(rd32, val, cond, delay_us, timeout_us, false, a, addr)
30 #define ice_flush(a) rd32((a), GLGEN_STAT)
/linux/drivers/gpu/drm/nouveau/nvkm/core/
H A Dgpuobj.c76 .rd32 = nvkm_gpuobj_rd32_fast,
84 .rd32 = nvkm_gpuobj_heap_rd32,
139 .rd32 = nvkm_gpuobj_rd32_fast,
147 .rd32 = nvkm_gpuobj_rd32,

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