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Searched refs:rd32 (Results 1 – 25 of 81) sorted by relevance

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/linux/drivers/net/ethernet/intel/igc/
H A Digc_mac.c27 ctrl = rd32(IGC_CTRL); in igc_disable_pcie_master()
32 if (!(rd32(IGC_STATUS) & in igc_disable_pcie_master()
181 ctrl = rd32(IGC_CTRL); in igc_force_mac_fc()
237 rd32(IGC_CRCERRS); in igc_clear_hw_cntrs_base()
238 rd32(IGC_MPC); in igc_clear_hw_cntrs_base()
239 rd32(IGC_SCC); in igc_clear_hw_cntrs_base()
240 rd32(IGC_ECOL); in igc_clear_hw_cntrs_base()
241 rd32(IGC_MCC); in igc_clear_hw_cntrs_base()
242 rd32(IGC_LATECOL); in igc_clear_hw_cntrs_base()
243 rd32(IGC_COLC); in igc_clear_hw_cntrs_base()
[all …]
H A Digc_base.c40 ctrl = rd32(IGC_CTRL); in igc_reset_hw_base()
56 rd32(IGC_ICR); in igc_reset_hw_base()
68 u32 eecd = rd32(IGC_EECD); in igc_init_nvm_params_base()
116 ctrl = rd32(IGC_CTRL); in igc_setup_copper_link_base()
192 hw->bus.func = FIELD_GET(IGC_STATUS_FUNC_MASK, rd32(IGC_STATUS)); in igc_init_phy_params_base()
366 rfctl = rd32(IGC_RFCTL); in igc_rx_fifo_flush_base()
370 if (!(rd32(IGC_MANC) & IGC_MANC_RCV_TCO_EN)) in igc_rx_fifo_flush_base()
375 rxdctl[i] = rd32(IGC_RXDCTL(i)); in igc_rx_fifo_flush_base()
384 rx_enabled |= rd32(IGC_RXDCTL(i)); in igc_rx_fifo_flush_base()
398 rlpml = rd32(IGC_RLPML); in igc_rx_fifo_flush_base()
[all …]
H A Digc_dump.c54 regs[n] = rd32(IGC_RDLEN(n)); in igc_regdump()
58 regs[n] = rd32(IGC_RDH(n)); in igc_regdump()
62 regs[n] = rd32(IGC_RDT(n)); in igc_regdump()
66 regs[n] = rd32(IGC_RXDCTL(n)); in igc_regdump()
70 regs[n] = rd32(IGC_RDBAL(n)); in igc_regdump()
74 regs[n] = rd32(IGC_RDBAH(n)); in igc_regdump()
78 regs[n] = rd32(IGC_TDBAL(n)); in igc_regdump()
82 regs[n] = rd32(IGC_TDBAH(n)); in igc_regdump()
86 regs[n] = rd32(IGC_TDLEN(n)); in igc_regdump()
90 regs[n] = rd32(IGC_TDH(n)); in igc_regdump()
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H A Digc_tsn.c264 return !!(rd32(IGC_TQAVCTRL) & IGC_TQAVCTRL_TRANSMIT_MODE_TSN); in igc_tsn_is_tx_mode_in_tsn()
301 retxctl = rd32(IGC_RETX_CTL) & IGC_RETX_CTL_WATERMARK_MASK; in igc_tsn_restore_retx_default()
309 return (rd32(IGC_BASET_H) || rd32(IGC_BASET_L)) && in igc_tsn_is_taprio_activated_by_user()
318 txarb = rd32(IGC_TXARB); in igc_tsn_tx_arb()
354 u32 rxpbs = rd32(IGC_RXPBS); in igc_tsn_set_rxpbsize()
381 tqavctrl = rd32(IGC_TQAVCTRL); in igc_tsn_disable_offload()
396 txdctl = rd32(IGC_TXDCTL(reg_idx)); in igc_tsn_disable_offload()
425 retxctl = rd32(IGC_RETX_CTL); in igc_tsn_set_retx_qbvfullthreshold()
479 u32 txdctl = rd32(IGC_TXDCTL(ring->reg_idx)); in igc_tsn_enable_offload()
592 tqavcc = rd32(IGC_TQAVCC(i)); in igc_tsn_enable_offload()
[all …]
H A Digc_ethtool.c183 regs_buff[0] = rd32(IGC_CTRL); in igc_ethtool_get_regs()
184 regs_buff[1] = rd32(IGC_STATUS); in igc_ethtool_get_regs()
185 regs_buff[2] = rd32(IGC_CTRL_EXT); in igc_ethtool_get_regs()
186 regs_buff[3] = rd32(IGC_MDIC); in igc_ethtool_get_regs()
187 regs_buff[4] = rd32(IGC_CONNSW); in igc_ethtool_get_regs()
190 regs_buff[5] = rd32(IGC_EECD); in igc_ethtool_get_regs()
196 regs_buff[6] = rd32(IGC_EICS); in igc_ethtool_get_regs()
197 regs_buff[7] = rd32(IGC_EICS); in igc_ethtool_get_regs()
198 regs_buff[8] = rd32(IGC_EIMS); in igc_ethtool_get_regs()
199 regs_buff[9] = rd32(IGC_EIMC); in igc_ethtool_get_regs()
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H A Digc_main.c158 ctrl_ext = rd32(IGC_CTRL_EXT); in igc_release_hw_control()
177 ctrl_ext = rd32(IGC_CTRL_EXT); in igc_get_hw_control()
332 txdctl = rd32(IGC_TXDCTL(idx)); in igc_disable_tx_ring_hw()
684 srrctl = rd32(IGC_SRRCTL(reg_idx)); in igc_configure_rx_ring()
805 rxcsum = rd32(IGC_RXCSUM); in igc_setup_mrqc()
842 rctl = rd32(IGC_RCTL); in igc_setup_rctl()
893 tctl = rd32(IGC_TCTL); in igc_setup_tctl()
1866 ctrl = rd32(IGC_CTRL); in igc_vlan_mode()
3259 !(rd32(IGC_STATUS) & IGC_STATUS_TXOFF) && in igc_clean_tx_irq()
3260 (rd32(IGC_TDH(tx_ring->reg_idx)) != readl(tx_ring->tail)) && in igc_clean_tx_irq()
[all …]
H A Digc_phy.c19 manc = rd32(IGC_MANC); in igc_check_reset_block()
177 phpm = rd32(IGC_I225_PHPM); in igc_phy_hw_reset()
179 ctrl = rd32(IGC_CTRL); in igc_phy_hw_reset()
191 phpm = rd32(IGC_I225_PHPM); in igc_phy_hw_reset()
568 mdic = rd32(IGC_MDIC); in igc_read_phy_reg_mdic()
625 mdic = rd32(IGC_MDIC); in igc_write_phy_reg_mdic()
/linux/drivers/net/ethernet/intel/igb/
H A Digb_ethtool.c147 0 : rd32(E1000_STATUS); in igb_get_link_ksettings()
477 regs_buff[0] = rd32(E1000_CTRL); in igb_get_regs()
478 regs_buff[1] = rd32(E1000_STATUS); in igb_get_regs()
479 regs_buff[2] = rd32(E1000_CTRL_EXT); in igb_get_regs()
480 regs_buff[3] = rd32(E1000_MDIC); in igb_get_regs()
481 regs_buff[4] = rd32(E1000_SCTL); in igb_get_regs()
482 regs_buff[5] = rd32(E1000_CONNSW); in igb_get_regs()
483 regs_buff[6] = rd32(E1000_VET); in igb_get_regs()
484 regs_buff[7] = rd32(E1000_LEDCTL); in igb_get_regs()
485 regs_buff[8] = rd32(E1000_PBA); in igb_get_regs()
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H A De1000_i210.c30 swsm = rd32(E1000_SWSM); in igb_get_hw_semaphore_i210()
46 swsm = rd32(E1000_SWSM); in igb_get_hw_semaphore_i210()
63 swsm = rd32(E1000_SWSM); in igb_get_hw_semaphore_i210()
67 if (rd32(E1000_SWSM) & E1000_SWSM_SWESMBI) in igb_get_hw_semaphore_i210()
131 swfw_sync = rd32(E1000_SW_FW_SYNC); in igb_acquire_swfw_sync_i210()
170 swfw_sync = rd32(E1000_SW_FW_SYNC); in igb_release_swfw_sync_i210()
254 rd32(E1000_SRWR)) { in igb_write_nvm_srwr()
332 invm_dword = rd32(E1000_INVM_DATA_REG(i)); in igb_read_invm_word_i210()
458 invm_dword = rd32(E1000_INVM_DATA_REG(i)); in igb_read_invm_version()
635 reg = rd32(E1000_EECD); in igb_pool_flash_update_done_i210()
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H A Digb_main.c263 regs[n] = rd32(E1000_RDLEN(n)); in igb_regdump()
267 regs[n] = rd32(E1000_RDH(n)); in igb_regdump()
271 regs[n] = rd32(E1000_RDT(n)); in igb_regdump()
275 regs[n] = rd32(E1000_RXDCTL(n)); in igb_regdump()
279 regs[n] = rd32(E1000_RDBAL(n)); in igb_regdump()
283 regs[n] = rd32(E1000_RDBAH(n)); in igb_regdump()
287 regs[n] = rd32(E1000_TDBAL(n)); in igb_regdump()
291 regs[n] = rd32(E1000_TDBAH(n)); in igb_regdump()
295 regs[n] = rd32(E1000_TDLEN(n)); in igb_regdump()
299 regs[n] = rd32(E1000_TDH(n)); in igb_regdump()
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H A De1000_mbx.c244 u32 mbvficr = rd32(E1000_MBVFICR); in igb_check_for_bit_pf()
302 u32 vflre = rd32(E1000_VFLRE); in igb_check_for_rst_pf()
332 p2v_mailbox = rd32(E1000_P2VMAILBOX(vf_number)); in igb_obtain_mbx_lock_pf()
355 p2v_mailbox = rd32(E1000_P2VMAILBOX(vf_number)); in igb_release_mbx_lock_pf()
/linux/drivers/net/ethernet/wangxun/libwx/
H A Dwx_hw.c35 ret = read_poll_timeout(rd32, val, !(val & WX_MSCC_BUSY), 1000, in wx_phy_read_reg_mdi()
42 return (u16)rd32(wx, WX_MSCC); in wx_phy_read_reg_mdi()
64 ret = read_poll_timeout(rd32, val, !(val & WX_MSCC_BUSY), 1000, in wx_phy_write_reg_mdi()
182 return read_poll_timeout(rd32, val, (val & 0x1), 10, 100000, in wx_fmgr_cmd_op()
194 *data = rd32(wx, WX_SPI_DATA); in wx_flash_read_dword()
205 if (!(rd32(hw, WX_SPI_STATUS) & in wx_check_flash_load()
208 err = read_poll_timeout(rd32, reg, !(reg & check_bit), 20000, 2000000, in wx_check_flash_load()
236 fwsm = rd32(wx, WX_MIS_ST); in wx_mng_present()
276 ret = read_poll_timeout(rd32, sem, !(sem & mask), in wx_acquire_sw_sync()
316 status = read_poll_timeout(rd32, hicr, hicr & WX_MNG_MBOX_CTL_FWRDY, 1000, in wx_host_interface_command_s()
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H A Dwx_err.c227 h = rd32(wx, WX_PX_TR_RP_PV(q_per_pool, i, j)); in wx_vf_tx_pending()
228 t = rd32(wx, WX_PX_TR_WP_PV(q_per_pool, i, j)); in wx_vf_tx_pending()
324 rd32(wx, WX_PX_TR_RP(tx_ring->reg_idx)), in wx_handle_tx_hang()
325 rd32(wx, WX_PX_TR_WP(tx_ring->reg_idx)), in wx_handle_tx_hang()
H A Dwx_vf.c26 rd32(wx, WX_VXSTATUS); in wx_virt_clr_reg()
85 rd32(wx, WX_VXSTATUS); in wx_reset_hw_vf()
153 reg_val = rd32(wx, WX_VXRXDCTL(i)); in wx_stop_adapter_vf()
161 rd32(wx, WX_VXSTATUS); in wx_stop_adapter_vf()
523 ret = read_poll_timeout_atomic(rd32, val, val & GENMASK(4, 1), in wx_check_physical_link()
526 ret = read_poll_timeout_atomic(rd32, val, val & BIT(0), 100, in wx_check_physical_link()
H A Dwx_mbx.c25 mailbox = rd32(wx, WX_PXMAILBOX(vf)); in wx_obtain_mbx_lock_pf()
38 u32 mbvficr = rd32(wx, WX_MBVFICR(index)); in wx_check_for_bit_pf()
170 vflre = rd32(wx, WX_VFLRE(reg_offset)); in wx_check_for_rst_pf()
180 u32 mailbox = rd32(wx, WX_VXMAILBOX); in wx_read_v2p_mailbox()
H A Dwx_vf_lib.c48 ivar = rd32(wx, WX_VXIVAR_MISC); in wx_set_ivar_vf()
56 ivar = rd32(wx, WX_VXIVAR(queue >> 1)); in wx_set_ivar_vf()
161 ret = read_poll_timeout(rd32, txdctl, txdctl & WX_VXTXDCTL_ENABLE, in wx_configure_tx_ring_vf()
255 rxdctl = rd32(wx, WX_VXRXDCTL(reg_idx)); in wx_configure_rx_ring_vf()
/linux/drivers/net/ethernet/intel/i40e/
H A Di40e_dcb.c24 reg = rd32(hw, I40E_PRTDCB_GENS); in i40e_get_dcbx_status()
1283 u32 reg = rd32(hw, I40E_PRTDCB_RETSC); in i40e_dcb_hw_rx_fifo_config()
1348 reg = rd32(hw, I40E_PRT_SWR_PM_THR); in i40e_dcb_hw_rx_cmd_monitor_config()
1353 reg = rd32(hw, I40E_PRTDCB_RPPMC); in i40e_dcb_hw_rx_cmd_monitor_config()
1391 reg = rd32(hw, I40E_PRTDCB_MFLCN); in i40e_dcb_hw_pfc_config()
1403 reg = rd32(hw, I40E_PRTDCB_FCCFG); in i40e_dcb_hw_pfc_config()
1413 reg = rd32(hw, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP); in i40e_dcb_hw_pfc_config()
1417 reg = rd32(hw, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP); in i40e_dcb_hw_pfc_config()
1423 reg = rd32(hw, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE); in i40e_dcb_hw_pfc_config()
1429 reg = rd32(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE); in i40e_dcb_hw_pfc_config()
[all …]
H A Di40e_diag.c22 orig_val = rd32(hw, reg); in i40e_diag_reg_pattern_test()
26 val = rd32(hw, reg); in i40e_diag_reg_pattern_test()
36 val = rd32(hw, reg); in i40e_diag_reg_pattern_test()
H A Di40e_adminq.c246 reg = rd32(hw, I40E_PF_ATQBAL); in i40e_config_asq_regs()
278 reg = rd32(hw, I40E_PF_ARQBAL); in i40e_config_arq_regs()
525 if (rd32(hw, I40E_GLQF_FDEVICTENA(1)) != in i40e_set_hw_caps()
699 while (rd32(hw, I40E_PF_ATQH) != ntc) { in i40e_clean_asq()
701 "ntc %d head %d.\n", ntc, rd32(hw, I40E_PF_ATQH)); in i40e_clean_asq()
735 return rd32(hw, I40E_PF_ATQH) == hw->aq.asq.next_to_use; in i40e_asq_done()
776 val = rd32(hw, I40E_PF_ATQH); in i40e_asq_send_command_atomic_exec()
928 if (rd32(hw, I40E_PF_ATQLEN) & I40E_GL_ATQLEN_ATQCRIT_MASK) { in i40e_asq_send_command_atomic_exec()
1072 ntu = rd32(hw, I40E_PF_ARQH) & I40E_PF_ARQH_ARQH_MASK; in i40e_clean_arq_element()
H A Di40e_common.c143 return !!(rd32(hw, I40E_PF_ATQLEN) & I40E_PF_ATQLEN_ATQENABLE_MASK); in i40e_check_asq_alive()
355 rd32(hw, I40E_PFGEN_PORTNUM)); in i40e_init_shared_code()
358 rd32(hw, I40E_GLPCI_CAPSUP)); in i40e_init_shared_code()
359 func_rid = rd32(hw, I40E_PF_FUNC_RID); in i40e_init_shared_code()
493 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); in i40e_pre_tx_queue_cfg()
644 reg = rd32(hw, I40E_GLGEN_RSTAT); in i40e_poll_globr()
677 rd32(hw, I40E_GLGEN_RSTCTL)); in i40e_pf_reset()
685 reg = rd32(hw, I40E_GLGEN_RSTAT); in i40e_pf_reset()
697 reg = rd32(hw, I40E_GLNVM_ULD); in i40e_pf_reset()
723 reg = rd32(hw, I40E_PFGEN_CTRL); in i40e_pf_reset()
[all …]
/linux/drivers/net/ethernet/intel/ice/
H A Dice_osdep.h23 #define rd32(a, reg) readl((a)->hw_addr + (reg)) macro
28 read_poll_timeout(rd32, val, cond, delay_us, timeout_us, false, a, addr)
30 #define ice_flush(a) rd32((a), GLGEN_STAT)
/linux/drivers/net/ethernet/wangxun/txgbe/
H A Dtxgbe_aml.c30 status = rd32(wx, WX_GPIO_INTSTATUS); in txgbe_gpio_init_aml()
49 status = rd32(wx, WX_GPIO_INTSTATUS); in txgbe_gpio_irq_handler_aml()
178 status = rd32(wx, TXGBE_CFG_PORT_ST); in txgbe_get_mac_link()
347 gpio = rd32(wx, WX_GPIO_EXT); in txgbe_identify_module()
397 wdg = rd32(wx, WX_MAC_WDG_TIMEOUT); in txgbe_reconfig_mac()
398 fc = rd32(wx, WX_MAC_RX_FLOW_CTRL); in txgbe_reconfig_mac()
427 txcfg = rd32(wx, TXGBE_AML_MAC_TX_CFG); in txgbe_mac_link_up_aml()
/linux/drivers/gpu/drm/nouveau/nvkm/core/
H A Dgpuobj.c76 .rd32 = nvkm_gpuobj_rd32_fast,
84 .rd32 = nvkm_gpuobj_heap_rd32,
139 .rd32 = nvkm_gpuobj_rd32_fast,
147 .rd32 = nvkm_gpuobj_rd32,
/linux/drivers/net/ethernet/wangxun/ngbe/
H A Dngbe_hw.c76 wr32(wx, WX_MIS_RST, val | rd32(wx, WX_MIS_RST)); in ngbe_reset_hw()
78 ret = read_poll_timeout(rd32, val, in ngbe_reset_hw()
/linux/drivers/net/ethernet/intel/iavf/
H A Diavf_adminq.c251 reg = rd32(hw, IAVF_VF_ATQBAL1); in iavf_config_asq_regs()
283 reg = rd32(hw, IAVF_VF_ARQBAL1); in iavf_config_arq_regs()
566 while (rd32(hw, IAVF_VF_ATQH1) != ntc) { in iavf_clean_asq()
568 "ntc %d head %d.\n", ntc, rd32(hw, IAVF_VF_ATQH1)); in iavf_clean_asq()
603 return rd32(hw, IAVF_VF_ATQH1) == hw->aq.asq.next_to_use; in iavf_asq_done()
642 val = rd32(hw, IAVF_VF_ATQH1); in iavf_asq_send_command()
789 if (rd32(hw, IAVF_VF_ATQLEN1) & IAVF_VF_ATQLEN1_ATQCRIT_MASK) { in iavf_asq_send_command()
857 ntu = rd32(hw, IAVF_VF_ARQH1) & IAVF_VF_ARQH1_ARQH_MASK; in iavf_clean_arq_element()

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