Home
last modified time | relevance | path

Searched refs:ras (Results 1 – 25 of 47) sorted by relevance

12

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_mmhub.c27 struct amdgpu_mmhub_ras *ras; in amdgpu_mmhub_ras_sw_init() local
29 if (!adev->mmhub.ras) in amdgpu_mmhub_ras_sw_init()
32 ras = adev->mmhub.ras; in amdgpu_mmhub_ras_sw_init()
33 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_mmhub_ras_sw_init()
39 strcpy(ras->ras_block.ras_comm.name, "mmhub"); in amdgpu_mmhub_ras_sw_init()
40 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MMHUB; in amdgpu_mmhub_ras_sw_init()
41 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_mmhub_ras_sw_init()
42 adev->mmhub.ras_if = &ras->ras_block.ras_comm; in amdgpu_mmhub_ras_sw_init()
H A Damdgpu_umc.c125 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_handle_bad_pages()
126 adev->umc.ras->ras_block.hw_ops->query_ras_error_count) in amdgpu_umc_handle_bad_pages()
127 adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, in amdgpu_umc_handle_bad_pages()
130 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_handle_bad_pages()
131 adev->umc.ras->ras_block.hw_ops->query_ras_error_address && in amdgpu_umc_handle_bad_pages()
151 adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, in amdgpu_umc_handle_bad_pages()
156 if (adev->umc.ras && in amdgpu_umc_handle_bad_pages()
157 adev->umc.ras->ecc_info_query_ras_error_count) in amdgpu_umc_handle_bad_pages()
158 adev->umc.ras->ecc_info_query_ras_error_count(adev, in amdgpu_umc_handle_bad_pages()
161 if (adev->umc.ras && in amdgpu_umc_handle_bad_pages()
[all …]
H A Damdgpu_nbio.c28 struct amdgpu_nbio_ras *ras; in amdgpu_nbio_ras_sw_init() local
30 if (!adev->nbio.ras) in amdgpu_nbio_ras_sw_init()
33 ras = adev->nbio.ras; in amdgpu_nbio_ras_sw_init()
34 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_nbio_ras_sw_init()
40 strcpy(ras->ras_block.ras_comm.name, "pcie_bif"); in amdgpu_nbio_ras_sw_init()
41 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__PCIE_BIF; in amdgpu_nbio_ras_sw_init()
42 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_nbio_ras_sw_init()
43 adev->nbio.ras_if = &ras->ras_block.ras_comm; in amdgpu_nbio_ras_sw_init()
H A Damdgpu_mca.c33 if (adev->umc.ras->check_ecc_err_status) in amdgpu_mca_is_deferred_error()
34 return adev->umc.ras->check_ecc_err_status(adev, in amdgpu_mca_is_deferred_error()
87 struct amdgpu_mca_ras_block *ras; in amdgpu_mca_mp0_ras_sw_init() local
89 if (!adev->mca.mp0.ras) in amdgpu_mca_mp0_ras_sw_init()
92 ras = adev->mca.mp0.ras; in amdgpu_mca_mp0_ras_sw_init()
94 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_mca_mp0_ras_sw_init()
100 strcpy(ras->ras_block.ras_comm.name, "mca.mp0"); in amdgpu_mca_mp0_ras_sw_init()
101 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MCA; in amdgpu_mca_mp0_ras_sw_init()
102 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_mca_mp0_ras_sw_init()
103 adev->mca.mp0.ras_if = &ras->ras_block.ras_comm; in amdgpu_mca_mp0_ras_sw_init()
[all …]
H A Damdgpu_ras_eeprom.c782 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in amdgpu_ras_eeprom_update_header() local
790 control->ras_num_bad_pages > ras->bad_page_cnt_threshold) { in amdgpu_ras_eeprom_update_header()
793 control->ras_num_bad_pages, ras->bad_page_cnt_threshold); in amdgpu_ras_eeprom_update_header()
806 ras->is_rma = true; in amdgpu_ras_eeprom_update_header()
854 control->ras_num_bad_pages <= ras->bad_page_cnt_threshold) in amdgpu_ras_eeprom_update_header()
855 control->tbl_rai.health_percent = ((ras->bad_page_cnt_threshold - in amdgpu_ras_eeprom_update_header()
857 ras->bad_page_cnt_threshold; in amdgpu_ras_eeprom_update_header()
1058 if (!adev->umc.ras || !adev->umc.ras->mca_ipid_parse) in amdgpu_ras_eeprom_read_idx()
1081 adev->umc.ras->mca_ipid_parse(adev, ipid, in amdgpu_ras_eeprom_read_idx()
1210 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in amdgpu_ras_debugfs_eeprom_size_read() local
[all …]
H A Damdgpu_sdma.c314 struct amdgpu_sdma_ras *ras = NULL; in amdgpu_sdma_ras_sw_init() local
319 if (!adev->sdma.ras) in amdgpu_sdma_ras_sw_init()
322 ras = adev->sdma.ras; in amdgpu_sdma_ras_sw_init()
324 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_sdma_ras_sw_init()
330 strcpy(ras->ras_block.ras_comm.name, "sdma"); in amdgpu_sdma_ras_sw_init()
331 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__SDMA; in amdgpu_sdma_ras_sw_init()
332 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_sdma_ras_sw_init()
333 adev->sdma.ras_if = &ras->ras_block.ras_comm; in amdgpu_sdma_ras_sw_init()
336 if (!ras->ras_block.ras_late_init) in amdgpu_sdma_ras_sw_init()
337 ras->ras_block.ras_late_init = amdgpu_sdma_ras_late_init; in amdgpu_sdma_ras_sw_init()
[all …]
H A Dumc_v6_7.c101 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v6_7_ecc_info_query_correctable_error_count() local
109 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v6_7_ecc_info_query_correctable_error_count()
116 if (ras->umc_ecc.record_ce_addr_supported) { in umc_v6_7_ecc_info_query_correctable_error_count()
121 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_ceumc_addr; in umc_v6_7_ecc_info_query_correctable_error_count()
143 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v6_7_ecc_info_querry_uncorrectable_error_count() local
150 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v6_7_ecc_info_querry_uncorrectable_error_count()
228 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v6_7_ecc_info_query_error_address() local
232 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v6_7_ecc_info_query_error_address()
244 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr; in umc_v6_7_ecc_info_query_error_address()
H A Damdgpu_jpeg.c317 struct amdgpu_jpeg_ras *ras; in amdgpu_jpeg_ras_sw_init() local
319 if (!adev->jpeg.ras) in amdgpu_jpeg_ras_sw_init()
322 ras = adev->jpeg.ras; in amdgpu_jpeg_ras_sw_init()
323 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_jpeg_ras_sw_init()
329 strcpy(ras->ras_block.ras_comm.name, "jpeg"); in amdgpu_jpeg_ras_sw_init()
330 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__JPEG; in amdgpu_jpeg_ras_sw_init()
331 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; in amdgpu_jpeg_ras_sw_init()
332 adev->jpeg.ras_if = &ras->ras_block.ras_comm; in amdgpu_jpeg_ras_sw_init()
334 if (!ras->ras_block.ras_late_init) in amdgpu_jpeg_ras_sw_init()
335 ras->ras_block.ras_late_init = amdgpu_jpeg_ras_late_init; in amdgpu_jpeg_ras_sw_init()
H A Dumc_v8_7.c56 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_7_ecc_info_query_correctable_error_count() local
63 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_7_ecc_info_query_correctable_error_count()
75 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_7_ecc_info_querry_uncorrectable_error_count() local
80 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_7_ecc_info_querry_uncorrectable_error_count()
137 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_7_ecc_info_query_error_address() local
140 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_7_ecc_info_query_error_address()
152 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr; in umc_v8_7_ecc_info_query_error_address()
H A Dumc_v8_10.c341 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_10_ecc_info_query_correctable_error_count() local
349 ecc_ce_cnt = ras->umc_ecc.ecc[eccinfo_table_idx].ce_count_lo_chip; in umc_v8_10_ecc_info_query_correctable_error_count()
360 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_10_ecc_info_query_uncorrectable_error_count() local
368 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_10_ecc_info_query_uncorrectable_error_count()
408 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_10_ecc_info_query_error_address() local
415 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_10_ecc_info_query_error_address()
428 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr; in umc_v8_10_ecc_info_query_error_address()
H A Dgfx_v11_0_3.c95 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in gfx_v11_0_3_poison_consumption_handler() local
97 ras->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE2_RESET; in gfx_v11_0_3_poison_consumption_handler()
H A Damdgpu_gfx.c1014 struct amdgpu_gfx_ras *ras = NULL; in amdgpu_gfx_ras_sw_init() local
1019 if (!adev->gfx.ras) in amdgpu_gfx_ras_sw_init()
1022 ras = adev->gfx.ras; in amdgpu_gfx_ras_sw_init()
1024 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_gfx_ras_sw_init()
1030 strcpy(ras->ras_block.ras_comm.name, "gfx"); in amdgpu_gfx_ras_sw_init()
1031 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__GFX; in amdgpu_gfx_ras_sw_init()
1032 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_gfx_ras_sw_init()
1033 adev->gfx.ras_if = &ras->ras_block.ras_comm; in amdgpu_gfx_ras_sw_init()
1036 if (!ras->ras_block.ras_late_init) in amdgpu_gfx_ras_sw_init()
1037 ras->ras_block.ras_late_init = amdgpu_gfx_ras_late_init; in amdgpu_gfx_ras_sw_init()
[all …]
H A Dgmc_v9_0.c1362 adev->umc.ras = &umc_v6_1_ras; in gmc_v9_0_set_umc_funcs()
1371 adev->umc.ras = &umc_v6_1_ras; in gmc_v9_0_set_umc_funcs()
1381 adev->umc.ras = &umc_v6_7_ras; in gmc_v9_0_set_umc_funcs()
1396 adev->umc.ras = &umc_v12_0_ras; in gmc_v9_0_set_umc_funcs()
1474 adev->mmhub.ras = &mmhub_v1_0_ras; in gmc_v9_0_set_mmhub_ras_funcs()
1477 adev->mmhub.ras = &mmhub_v9_4_ras; in gmc_v9_0_set_mmhub_ras_funcs()
1480 adev->mmhub.ras = &mmhub_v1_7_ras; in gmc_v9_0_set_mmhub_ras_funcs()
1484 adev->mmhub.ras = &mmhub_v1_8_ras; in gmc_v9_0_set_mmhub_ras_funcs()
1502 adev->hdp.ras = &hdp_v4_0_ras; in gmc_v9_0_set_hdp_ras_funcs()
1513 mca->mp0.ras = &mca_v3_0_mp0_ras; in gmc_v9_0_set_mca_ras_funcs()
[all …]
H A Damdgpu_vcn.c1322 struct amdgpu_vcn_ras *ras; in amdgpu_vcn_ras_sw_init() local
1324 if (!adev->vcn.ras) in amdgpu_vcn_ras_sw_init()
1327 ras = adev->vcn.ras; in amdgpu_vcn_ras_sw_init()
1328 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_vcn_ras_sw_init()
1334 strcpy(ras->ras_block.ras_comm.name, "vcn"); in amdgpu_vcn_ras_sw_init()
1335 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__VCN; in amdgpu_vcn_ras_sw_init()
1336 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; in amdgpu_vcn_ras_sw_init()
1337 adev->vcn.ras_if = &ras->ras_block.ras_comm; in amdgpu_vcn_ras_sw_init()
1339 if (!ras->ras_block.ras_late_init) in amdgpu_vcn_ras_sw_init()
1340 ras->ras_block.ras_late_init = amdgpu_vcn_ras_late_init; in amdgpu_vcn_ras_sw_init()
H A Damdgpu_mca.h77 struct amdgpu_mca_ras_block *ras; member
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega20_baco.c75 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in vega20_baco_set_state() local
86 if (!ras || !adev->ras_enabled) { in vega20_baco_set_state()
/linux/drivers/edac/
H A Di5100_edac.c433 unsigned ras, in i5100_handle_ce() argument
441 bank, cas, ras); in i5100_handle_ce()
455 unsigned ras, in i5100_handle_ue() argument
463 bank, cas, ras); in i5100_handle_ue()
483 unsigned ras; in i5100_read_log() local
503 ras = i5100_recmemb_ras(dw2); in i5100_read_log()
512 i5100_handle_ce(mci, chan, bank, rank, syndrome, cas, ras, msg); in i5100_read_log()
525 ras = i5100_nrecmemb_ras(dw2); in i5100_read_log()
534 i5100_handle_ue(mci, chan, bank, rank, syndrome, cas, ras, msg); in i5100_read_log()
/linux/net/netfilter/
H A Dnf_conntrack_h323_main.c1626 unsigned char **data, RasMessage *ras) in process_ras() argument
1628 switch (ras->choice) { in process_ras()
1631 &ras->gatekeeperRequest); in process_ras()
1634 &ras->gatekeeperConfirm); in process_ras()
1637 &ras->registrationRequest); in process_ras()
1640 &ras->registrationConfirm); in process_ras()
1643 &ras->unregistrationRequest); in process_ras()
1646 &ras->admissionRequest); in process_ras()
1649 &ras->admissionConfirm); in process_ras()
1652 &ras->locationRequest); in process_ras()
[all …]
/linux/drivers/ras/
H A DKconfig34 source "arch/x86/ras/Kconfig"
35 source "drivers/ras/amd/atl/Kconfig"
H A DMakefile2 obj-$(CONFIG_RAS) += ras.o
/linux/include/linux/netfilter/
H A Dnf_conntrack_h323_asn1.h91 int DecodeRasMessage(unsigned char *buf, size_t sz, RasMessage * ras);
/linux/arch/x86/ras/
H A DKconfig20 Add extra files to (debugfs)/ras/cec to test the correctable error
/linux/Documentation/translations/zh_CN/admin-guide/
H A Dindex.rst117 * ras
/linux/Documentation/translations/zh_TW/admin-guide/
H A Dindex.rst120 * ras
/linux/tools/testing/cxl/
H A DKbuild70 cxl_core-$(CONFIG_CXL_RAS) += $(CXL_CORE_SRC)/ras.o

12