/linux/drivers/gpu/drm/radeon/ |
H A D | radeon_cursor.c | 35 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_lock_cursor() local 39 cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset); in radeon_lock_cursor() 44 WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); in radeon_lock_cursor() 46 cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset); in radeon_lock_cursor() 51 WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); in radeon_lock_cursor() 53 cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset); in radeon_lock_cursor() 58 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock); in radeon_lock_cursor() 64 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_hide_cursor() local 68 WREG32_IDX(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset, in radeon_hide_cursor() 72 WREG32_IDX(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, in radeon_hide_cursor() [all …]
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H A D | atombios_crtc.c | 44 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_overscan_setup() local 51 args.ucCRTC = radeon_crtc->crtc_id; in atombios_overscan_setup() 53 switch (radeon_crtc->rmx_type) { in atombios_overscan_setup() 74 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border); in atombios_overscan_setup() 75 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border); in atombios_overscan_setup() 76 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border); in atombios_overscan_setup() 77 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border); in atombios_overscan_setup() 87 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_scaler_setup() local 91 to_radeon_encoder(radeon_crtc->encoder); in atombios_scaler_setup() 96 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) in atombios_scaler_setup() [all …]
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H A D | radeon_display.c | 51 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in avivo_crtc_load_lut() local 57 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); in avivo_crtc_load_lut() 58 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut() 60 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut() 61 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut() 62 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut() 64 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); in avivo_crtc_load_lut() 65 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); in avivo_crtc_load_lut() 66 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); in avivo_crtc_load_lut() 68 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); in avivo_crtc_load_lut() [all …]
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H A D | radeon_legacy_crtc.c | 42 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_overscan_setup() local 44 WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup() 45 WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup() 46 WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup() 54 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_legacy_rmx_mode_set() local 66 struct drm_display_mode *native_mode = &radeon_crtc->native_mode; in radeon_legacy_rmx_mode_set() 129 switch (radeon_crtc->rmx_type) { in radeon_legacy_rmx_mode_set() 299 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_crtc_dpms() local 305 if (radeon_crtc->crtc_id) in radeon_crtc_dpms() 327 radeon_crtc->enabled = true; in radeon_crtc_dpms() [all …]
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H A D | rs600.c | 121 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rs600_page_flip() local 122 struct drm_framebuffer *fb = radeon_crtc->base.primary->fb; in rs600_page_flip() 123 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rs600_page_flip() 128 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rs600_page_flip() 131 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, in rs600_page_flip() 134 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, in rs600_page_flip() 137 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rs600_page_flip() 139 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rs600_page_flip() 144 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) in rs600_page_flip() 152 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rs600_page_flip() [all …]
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H A D | radeon_legacy_encoders.c | 192 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in radeon_legacy_lvds_mode_set() local 230 if (radeon_crtc->crtc_id == 0) { in radeon_legacy_lvds_mode_set() 251 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); in radeon_legacy_lvds_mode_set() 253 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); in radeon_legacy_lvds_mode_set() 583 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in radeon_legacy_primary_dac_mode_set() local 589 if (radeon_crtc->crtc_id == 0) { in radeon_legacy_primary_dac_mode_set() 629 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); in radeon_legacy_primary_dac_mode_set() 631 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); in radeon_legacy_primary_dac_mode_set() 780 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in radeon_legacy_tmds_int_mode_set() local 847 if (radeon_crtc->crtc_id == 0) { in radeon_legacy_tmds_int_mode_set() [all …]
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H A D | dce6_afmt.h | 32 struct radeon_crtc; 48 struct radeon_crtc *crtc, unsigned int clock); 50 struct radeon_crtc *crtc, unsigned int clock);
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H A D | evergreen_hdmi.h | 37 struct radeon_crtc; 60 struct radeon_crtc *crtc, unsigned int clock); 62 struct radeon_crtc *crtc, unsigned int clock);
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H A D | atombios_encoders.c | 457 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in radeon_atom_get_bpc() local 458 bpc = radeon_crtc->bpc; in radeon_atom_get_bpc() 1043 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in atombios_dig_transmitter_setup2() local 1044 pll_id = radeon_crtc->pll_id; in atombios_dig_transmitter_setup2() 1531 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in atombios_yuv_setup() local 1547 (radeon_crtc->crtc_id << 18))); in atombios_yuv_setup() 1549 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); in atombios_yuv_setup() 1555 args.ucCRTC = radeon_crtc->crtc_id; in atombios_yuv_setup() 1850 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in atombios_set_encoder_crtc_source() local 1867 args.v1.ucCRTC = radeon_crtc->crtc_id; in atombios_set_encoder_crtc_source() [all …]
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H A D | r600.h | 34 struct radeon_crtc; 47 struct radeon_crtc *crtc, unsigned int clock);
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H A D | evergreen.c | 1297 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in dce4_program_fmt() local 1345 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce4_program_fmt() 1419 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in evergreen_page_flip() local 1420 struct drm_framebuffer *fb = radeon_crtc->base.primary->fb; in evergreen_page_flip() 1423 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, in evergreen_page_flip() 1426 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, in evergreen_page_flip() 1429 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, in evergreen_page_flip() 1431 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in evergreen_page_flip() 1434 RREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset); in evergreen_page_flip() 1447 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in evergreen_page_flip_pending() local [all …]
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H A D | radeon_legacy_tv.c | 241 struct radeon_crtc *radeon_crtc; in radeon_legacy_tv_get_std_mode() local 246 radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc); in radeon_legacy_tv_get_std_mode() 247 if (radeon_crtc->crtc_id == 1) in radeon_legacy_tv_get_std_mode() 532 struct radeon_crtc *radeon_crtc; in radeon_legacy_tv_mode_set() local 549 radeon_crtc = to_radeon_crtc(encoder->crtc); in radeon_legacy_tv_mode_set() 595 if (radeon_crtc->crtc_id == 1) in radeon_legacy_tv_mode_set() 598 if (radeon_crtc->rmx_type != RMX_OFF) in radeon_legacy_tv_mode_set()
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H A D | radeon_mode.h | 49 #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) 248 struct radeon_crtc *crtcs[RADEON_MAX_CRTCS]; 321 struct radeon_crtc { struct 900 struct radeon_crtc *radeon_crtc); 902 struct radeon_crtc *radeon_crtc); 917 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
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H A D | rv770.c | 802 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rv770_page_flip() local 803 struct drm_framebuffer *fb = radeon_crtc->base.primary->fb; in rv770_page_flip() 804 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rv770_page_flip() 809 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rv770_page_flip() 812 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, in rv770_page_flip() 815 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, in rv770_page_flip() 818 if (radeon_crtc->crtc_id) { in rv770_page_flip() 825 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rv770_page_flip() 827 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rv770_page_flip() 832 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) in rv770_page_flip() [all …]
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H A D | r600_dpm.c | 158 struct radeon_crtc *radeon_crtc; in r600_dpm_get_vblank_time() local 164 radeon_crtc = to_radeon_crtc(crtc); in r600_dpm_get_vblank_time() 165 if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) { in r600_dpm_get_vblank_time() 167 radeon_crtc->hw_mode.crtc_htotal * in r600_dpm_get_vblank_time() 168 (radeon_crtc->hw_mode.crtc_vblank_end - in r600_dpm_get_vblank_time() 169 radeon_crtc->hw_mode.crtc_vdisplay + in r600_dpm_get_vblank_time() 170 (radeon_crtc->v_border * 2)); in r600_dpm_get_vblank_time() 172 vblank_time_us = vblank_in_pixels * 1000 / radeon_crtc->hw_mode.clock; in r600_dpm_get_vblank_time() 185 struct radeon_crtc *radeon_crtc; in r600_dpm_get_vrefresh() local 190 radeon_crtc = to_radeon_crtc(crtc); in r600_dpm_get_vrefresh() [all …]
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H A D | evergreen_hdmi.c | 77 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in evergreen_hdmi_update_acr() local 78 bpc = radeon_crtc->bpc; in evergreen_hdmi_update_acr() 230 struct radeon_crtc *crtc, unsigned int clock) in dce4_hdmi_audio_set_dto() 273 struct radeon_crtc *crtc, unsigned int clock) in dce4_dp_audio_set_dto()
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H A D | radeon_audio.h | 55 struct radeon_crtc *crtc, unsigned int clock); 91 struct radeon_crtc *crtc, unsigned int clock);
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H A D | radeon_device.c | 1575 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_suspend_kms() local 1579 if (radeon_crtc->cursor_bo) { in radeon_suspend_kms() 1580 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo); in radeon_suspend_kms() 1700 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_resume_kms() local 1702 if (radeon_crtc->cursor_bo) { in radeon_resume_kms() 1703 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo); in radeon_resume_kms() 1711 &radeon_crtc->cursor_addr); in radeon_resume_kms()
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H A D | r100.c | 166 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in r100_page_flip() local 168 struct drm_framebuffer *fb = radeon_crtc->base.primary->fb; in r100_page_flip() 174 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); in r100_page_flip() 181 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); in r100_page_flip() 185 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) in r100_page_flip() 193 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); in r100_page_flip() 208 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in r100_page_flip_pending() local 211 return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & in r100_page_flip_pending() 464 struct radeon_crtc *radeon_crtc; in r100_pm_prepare() local 469 radeon_crtc = to_radeon_crtc(crtc); in r100_pm_prepare() [all …]
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H A D | si.c | 1948 struct radeon_crtc *radeon_crtc, in dce6_line_buffer_adjust() argument 1953 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; in dce6_line_buffer_adjust() 1967 if (radeon_crtc->base.enabled && mode) { in dce6_line_buffer_adjust() 1980 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, in dce6_line_buffer_adjust() 1992 if (radeon_crtc->base.enabled && mode) { in dce6_line_buffer_adjust() 2275 struct radeon_crtc *radeon_crtc, in dce6_program_watermarks() argument 2278 struct drm_display_mode *mode = &radeon_crtc->base.mode; in dce6_program_watermarks() 2290 if (radeon_crtc->base.enabled && num_heads && mode) { in dce6_program_watermarks() 2322 wm_high.vsc = radeon_crtc->vsc; in dce6_program_watermarks() 2324 if (radeon_crtc->rmx_type != RMX_OFF) in dce6_program_watermarks() [all …]
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H A D | radeon_pm.c | 1697 struct radeon_crtc *radeon_crtc; in radeon_pm_compute_clocks_old() local 1709 radeon_crtc = to_radeon_crtc(crtc); in radeon_pm_compute_clocks_old() 1710 if (radeon_crtc->enabled) { in radeon_pm_compute_clocks_old() 1711 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id); in radeon_pm_compute_clocks_old() 1770 struct radeon_crtc *radeon_crtc; in radeon_pm_compute_clocks_dpm() local 1785 radeon_crtc = to_radeon_crtc(crtc); in radeon_pm_compute_clocks_dpm() 1787 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id); in radeon_pm_compute_clocks_dpm() 1789 if (!radeon_crtc->connector) in radeon_pm_compute_clocks_dpm() 1792 radeon_connector = to_radeon_connector(radeon_crtc->connector); in radeon_pm_compute_clocks_dpm()
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H A D | dce6_afmt.c | 271 struct radeon_crtc *crtc, unsigned int clock) in dce6_hdmi_audio_set_dto() 290 struct radeon_crtc *crtc, unsigned int clock) in dce6_dp_audio_set_dto()
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H A D | cik.c | 8728 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in dce8_program_fmt() local 8784 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce8_program_fmt() 8801 struct radeon_crtc *radeon_crtc, in dce8_line_buffer_adjust() argument 8805 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; in dce8_line_buffer_adjust() 8814 if (radeon_crtc->base.enabled && mode) { in dce8_line_buffer_adjust() 8834 WREG32(LB_MEMORY_CTRL + radeon_crtc->crtc_offset, in dce8_line_buffer_adjust() 8846 if (radeon_crtc->base.enabled && mode) { in dce8_line_buffer_adjust() 9230 struct radeon_crtc *radeon_crtc, in dce8_program_watermarks() argument 9233 struct drm_display_mode *mode = &radeon_crtc->base.mode; in dce8_program_watermarks() 9240 if (radeon_crtc->base.enabled && num_heads && mode) { in dce8_program_watermarks() [all …]
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H A D | radeon_kms.c | 271 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_info_ioctl() local 272 *value = radeon_crtc->crtc_id; in radeon_info_ioctl()
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H A D | rs780_dpm.c | 54 struct radeon_crtc *radeon_crtc; in rs780_get_pm_mode_parameters() local 64 radeon_crtc = to_radeon_crtc(crtc); in rs780_get_pm_mode_parameters() 65 pi->crtc_id = radeon_crtc->crtc_id; in rs780_get_pm_mode_parameters()
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