1297 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);  in dce4_program_fmt()  local
1345 	WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);  in dce4_program_fmt()
1419 	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];  in evergreen_page_flip()  local
1420 	struct drm_framebuffer *fb = radeon_crtc->base.primary->fb;  in evergreen_page_flip()
1423 	WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,  in evergreen_page_flip()
1426 	WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset,  in evergreen_page_flip()
1429 	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,  in evergreen_page_flip()
1431 	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,  in evergreen_page_flip()
1434 	RREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset);  in evergreen_page_flip()
1447 	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];  in evergreen_page_flip_pending()  local
1450 	return !!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) &  in evergreen_page_flip_pending()
1678 	struct radeon_crtc *radeon_crtc;  in evergreen_pm_prepare()  local
1683 		radeon_crtc = to_radeon_crtc(crtc);  in evergreen_pm_prepare()
1684 		if (radeon_crtc->enabled) {  in evergreen_pm_prepare()
1685 			tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);  in evergreen_pm_prepare()
1687 			WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);  in evergreen_pm_prepare()
1703 	struct radeon_crtc *radeon_crtc;  in evergreen_pm_finish()  local
1708 		radeon_crtc = to_radeon_crtc(crtc);  in evergreen_pm_finish()
1709 		if (radeon_crtc->enabled) {  in evergreen_pm_finish()
1710 			tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);  in evergreen_pm_finish()
1712 			WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);  in evergreen_pm_finish()
1827 					struct radeon_crtc *radeon_crtc,  in evergreen_line_buffer_adjust()  argument
1832 	u32 pipe_offset = radeon_crtc->crtc_id * 0x20;  in evergreen_line_buffer_adjust()
1854 	if (radeon_crtc->base.enabled && mode) {  in evergreen_line_buffer_adjust()
1868 	if (radeon_crtc->crtc_id % 2)  in evergreen_line_buffer_adjust()
1870 	WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);  in evergreen_line_buffer_adjust()
1883 	if (radeon_crtc->base.enabled && mode) {  in evergreen_line_buffer_adjust()
2156 					 struct radeon_crtc *radeon_crtc,  in evergreen_program_watermarks()  argument
2159 	struct drm_display_mode *mode = &radeon_crtc->base.mode;  in evergreen_program_watermarks()
2168 	u32 pipe_offset = radeon_crtc->crtc_id * 16;  in evergreen_program_watermarks()
2172 	if (radeon_crtc->base.enabled && num_heads && mode) {  in evergreen_program_watermarks()
2200 		wm_high.vsc = radeon_crtc->vsc;  in evergreen_program_watermarks()
2202 		if (radeon_crtc->rmx_type != RMX_OFF)  in evergreen_program_watermarks()
2227 		wm_low.vsc = radeon_crtc->vsc;  in evergreen_program_watermarks()
2229 		if (radeon_crtc->rmx_type != RMX_OFF)  in evergreen_program_watermarks()
2263 		c.full = dfixed_mul(c, radeon_crtc->hsc);  in evergreen_program_watermarks()
2275 		c.full = dfixed_mul(c, radeon_crtc->hsc);  in evergreen_program_watermarks()
2283 		radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);  in evergreen_program_watermarks()
2307 	WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);  in evergreen_program_watermarks()
2308 	WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);  in evergreen_program_watermarks()
2311 	radeon_crtc->line_time = line_time;  in evergreen_program_watermarks()
2312 	radeon_crtc->wm_high = latency_watermark_a;  in evergreen_program_watermarks()
2313 	radeon_crtc->wm_low = latency_watermark_b;  in evergreen_program_watermarks()