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Searched refs:queue_mask (Results 1 – 15 of 15) sorted by relevance

/linux/Documentation/networking/device_drivers/ethernet/intel/
H A Didpf.rst121 # ethtool --per-queue <ethX> queue_mask 0xa --coalesce adaptive-rx off
126 # ethtool --per-queue <ethX> queue_mask 0xa --show-coalesce
H A Dice.rst1159 # ethtool --per-queue <ethX> queue_mask 0xa --coalesce adaptive-rx off
1164 # ethtool --per-queue <ethX> queue_mask 0xa --show-coalesce
/linux/drivers/gpu/drm/panthor/
H A Dpanthor_sched.c1421 u32 queue_mask = 0, i; in csg_slot_prog_locked() local
1442 queue_mask |= BIT(i); in csg_slot_prog_locked()
1470 panthor_fw_toggle_reqs(csg_iface, doorbell_req, doorbell_ack, queue_mask); in csg_slot_prog_locked()
2687 static void group_schedule_locked(struct panthor_group *group, u32 queue_mask) in group_schedule_locked() argument
2698 if ((queue_mask & group->blocked_queues) == queue_mask) in group_schedule_locked()
2702 group->idle_queues &= ~queue_mask; in group_schedule_locked()
3376 u32 queue_mask = BIT(job->queue_idx); in queue_run_job() local
3378 (group->idle_queues & queue_mask) && in queue_run_job()
3379 !(group->blocked_queues & queue_mask) in queue_run_job()
[all...]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_gfx.c702 uint64_t queue_mask = ~0ULL; in amdgpu_gfx_mes_enable_kcq() local
716 kiq->pmf->kiq_set_resources(kiq_ring, queue_mask); in amdgpu_gfx_mes_enable_kcq()
741 uint64_t queue_mask = 0; in amdgpu_gfx_enable_kcq() local
757 if (WARN_ON(i > (sizeof(queue_mask)*8))) { in amdgpu_gfx_enable_kcq()
762 queue_mask |= (1ull << amdgpu_queue_mask_bit_to_set_resource_bit(adev, i)); in amdgpu_gfx_enable_kcq()
780 kiq->pmf->kiq_set_resources(kiq_ring, queue_mask); in amdgpu_gfx_enable_kcq()
H A Dgfx_v8_0.c4320 uint64_t queue_mask = 0; in gfx_v8_0_kiq_kcq_enable() local
4330 if (WARN_ON(i >= (sizeof(queue_mask)*8))) { in gfx_v8_0_kiq_kcq_enable()
4335 queue_mask |= (1ull << i); in gfx_v8_0_kiq_kcq_enable()
4346 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ in gfx_v8_0_kiq_kcq_enable()
4347 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ in gfx_v8_0_kiq_kcq_enable()
H A Dgfx_v9_4_3.c175 uint64_t queue_mask) in gfx_v9_4_3_kiq_set_resources() argument
189 lower_32_bits(queue_mask)); /* queue mask lo */ in gfx_v9_4_3_kiq_set_resources()
191 upper_32_bits(queue_mask)); /* queue mask hi */ in gfx_v9_4_3_kiq_set_resources()
H A Dgfx_v12_1.c219 uint64_t queue_mask) in gfx_v12_1_kiq_set_resources() argument
224 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ in gfx_v12_1_kiq_set_resources()
225 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ in gfx_v12_1_kiq_set_resources()
H A Dgfx_v12_0.c294 uint64_t queue_mask) in gfx_v12_0_kiq_set_resources() argument
299 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ in gfx_v12_0_kiq_set_resources()
300 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ in gfx_v12_0_kiq_set_resources()
H A Dgfx_v9_0.c928 uint64_t queue_mask) in gfx_v9_0_kiq_set_resources() argument
942 lower_32_bits(queue_mask)); /* queue mask lo */ in gfx_v9_0_kiq_set_resources()
944 upper_32_bits(queue_mask)); /* queue mask hi */ in gfx_v9_0_kiq_set_resources()
H A Dgfx_v11_0.c369 static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) in gfx11_kiq_set_resources() argument
381 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ in gfx11_kiq_set_resources()
382 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ in gfx11_kiq_set_resources()
H A Dgfx_v10_0.c3707 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) in gfx10_kiq_set_resources() argument
3718 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ in gfx10_kiq_set_resources()
3719 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ in gfx10_kiq_set_resources()
/linux/drivers/net/ethernet/cadence/
H A Dmacb_main.c4337 u32 queue_mask; in macb_taprio_setup_replace()
4454 queue_mask = BIT_U32(bp->num_queues) - 1; in macb_taprio_setup_replace()
4456 queue_mask << GEM_ENST_DISABLE_QUEUE_OFFSET); in macb_taprio_setup_replace()
4485 u32 queue_mask; in macb_taprio_destroy()
4489 queue_mask = BIT_U32(bp->num_queues) - 1; in macb_setup_taprio()
4494 queue_mask << GEM_ENST_DISABLE_QUEUE_OFFSET); in macb_setup_taprio()
4627 unsigned int queue_mask = 0x1; in macb_clks_disable()
4632 queue_mask |= __raw_readl(mem + GEM_DCFG6) & 0xFF; in macb_clks_disable()
4634 queue_mask |= readl_relaxed(mem + GEM_DCFG6) & 0xFF; in macb_clks_disable()
4636 if (fls(queue_mask) ! in macb_clks_disable()
4319 u32 queue_mask; macb_taprio_setup_replace() local
4467 u32 queue_mask; macb_taprio_destroy() local
4609 unsigned int queue_mask = 0x1; macb_probe_queues() local
[all...]
/linux/net/sched/
H A Dsch_taprio.c1443 u32 i, queue_mask = 0; in tc_map_to_queue_mask() local
1453 queue_mask |= GENMASK(res.offset + res.count - 1, res.offset); in tc_map_to_queue_mask()
1456 return queue_mask; in tc_map_to_queue_mask()
/linux/include/uapi/linux/
H A Dethtool.h1796 __u32 queue_mask[__KERNEL_DIV_ROUND_UP(MAX_NUM_QUEUE, 32)]; member
/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_device_queue_manager.c1972 res.queue_mask = 0; in set_sched_resources()
1986 * definition of res.queue_mask needs updating in set_sched_resources()
1988 if (WARN_ON(i >= (sizeof(res.queue_mask)*8))) { in initialize_cpsch()
1993 res.queue_mask |= 1ull in initialize_cpsch()
2003 res.vmid_mask, res.queue_mask); in initialize_cpsch()