1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * QLogic Fibre Channel HBA Driver
4 * Copyright (c) 2003-2014 QLogic Corporation
5 */
6 #include "qla_def.h"
7
8 #include <linux/bitfield.h>
9 #include <linux/moduleparam.h>
10 #include <linux/vmalloc.h>
11 #include <linux/delay.h>
12 #include <linux/kthread.h>
13 #include <linux/mutex.h>
14 #include <linux/kobject.h>
15 #include <linux/slab.h>
16 #include <linux/refcount.h>
17 #include <linux/crash_dump.h>
18 #include <linux/trace_events.h>
19 #include <linux/trace.h>
20 #include <linux/irq.h>
21
22 #include <scsi/scsi_tcq.h>
23 #include <scsi/scsicam.h>
24 #include <scsi/scsi_transport.h>
25 #include <scsi/scsi_transport_fc.h>
26
27 #include "qla_target.h"
28
29 /*
30 * Driver version
31 */
32 char qla2x00_version_str[40];
33
34 static int apidev_major;
35
36 /*
37 * SRB allocation cache
38 */
39 struct kmem_cache *srb_cachep;
40
41 static struct trace_array *qla_trc_array;
42
43 int ql2xfulldump_on_mpifail;
44 module_param(ql2xfulldump_on_mpifail, int, S_IRUGO | S_IWUSR);
45 MODULE_PARM_DESC(ql2xfulldump_on_mpifail,
46 "Set this to take full dump on MPI hang.");
47
48 int ql2xenforce_iocb_limit = 2;
49 module_param(ql2xenforce_iocb_limit, int, S_IRUGO | S_IWUSR);
50 MODULE_PARM_DESC(ql2xenforce_iocb_limit,
51 "Enforce IOCB throttling, to avoid FW congestion. (default: 2) "
52 "1: track usage per queue, 2: track usage per adapter");
53
54 /*
55 * CT6 CTX allocation cache
56 */
57 static struct kmem_cache *ctx_cachep;
58 /*
59 * error level for logging
60 */
61 uint ql_errlev = 0x8001;
62
63 int ql2xsecenable;
64 module_param(ql2xsecenable, int, S_IRUGO);
65 MODULE_PARM_DESC(ql2xsecenable,
66 "Enable/disable security. 0(Default) - Security disabled. 1 - Security enabled.");
67
68 static int ql2xenableclass2;
69 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
70 MODULE_PARM_DESC(ql2xenableclass2,
71 "Specify if Class 2 operations are supported from the very "
72 "beginning. Default is 0 - class 2 not supported.");
73
74
75 int ql2xlogintimeout = 20;
76 module_param(ql2xlogintimeout, int, S_IRUGO);
77 MODULE_PARM_DESC(ql2xlogintimeout,
78 "Login timeout value in seconds.");
79
80 int qlport_down_retry;
81 module_param(qlport_down_retry, int, S_IRUGO);
82 MODULE_PARM_DESC(qlport_down_retry,
83 "Maximum number of command retries to a port that returns "
84 "a PORT-DOWN status.");
85
86 int ql2xplogiabsentdevice;
87 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
88 MODULE_PARM_DESC(ql2xplogiabsentdevice,
89 "Option to enable PLOGI to devices that are not present after "
90 "a Fabric scan. This is needed for several broken switches. "
91 "Default is 0 - no PLOGI. 1 - perform PLOGI.");
92
93 int ql2xloginretrycount;
94 module_param(ql2xloginretrycount, int, S_IRUGO);
95 MODULE_PARM_DESC(ql2xloginretrycount,
96 "Specify an alternate value for the NVRAM login retry count.");
97
98 int ql2xallocfwdump = 1;
99 module_param(ql2xallocfwdump, int, S_IRUGO);
100 MODULE_PARM_DESC(ql2xallocfwdump,
101 "Option to enable allocation of memory for a firmware dump "
102 "during HBA initialization. Memory allocation requirements "
103 "vary by ISP type. Default is 1 - allocate memory.");
104
105 int ql2xextended_error_logging;
106 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
107 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
108 MODULE_PARM_DESC(ql2xextended_error_logging,
109 "Option to enable extended error logging,\n"
110 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
111 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
112 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
113 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
114 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
115 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
116 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
117 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
118 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
119 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
120 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
121 "\t\t0x1e400000 - Preferred value for capturing essential "
122 "debug information (equivalent to old "
123 "ql2xextended_error_logging=1).\n"
124 "\t\tDo LOGICAL OR of the value to enable more than one level");
125
126 int ql2xextended_error_logging_ktrace = 1;
127 module_param(ql2xextended_error_logging_ktrace, int, S_IRUGO|S_IWUSR);
128 MODULE_PARM_DESC(ql2xextended_error_logging_ktrace,
129 "Same BIT definition as ql2xextended_error_logging, but used to control logging to kernel trace buffer (default=1).\n");
130
131 int ql2xshiftctondsd = 6;
132 module_param(ql2xshiftctondsd, int, S_IRUGO);
133 MODULE_PARM_DESC(ql2xshiftctondsd,
134 "Set to control shifting of command type processing "
135 "based on total number of SG elements.");
136
137 int ql2xfdmienable = 1;
138 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
139 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
140 MODULE_PARM_DESC(ql2xfdmienable,
141 "Enables FDMI registrations. "
142 "0 - no FDMI registrations. "
143 "1 - provide FDMI registrations (default).");
144
145 #define MAX_Q_DEPTH 64
146 static int ql2xmaxqdepth = MAX_Q_DEPTH;
147 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
148 MODULE_PARM_DESC(ql2xmaxqdepth,
149 "Maximum queue depth to set for each LUN. "
150 "Default is 64.");
151
152 int ql2xenabledif = 2;
153 module_param(ql2xenabledif, int, S_IRUGO);
154 MODULE_PARM_DESC(ql2xenabledif,
155 " Enable T10-CRC-DIF:\n"
156 " Default is 2.\n"
157 " 0 -- No DIF Support\n"
158 " 1 -- Enable DIF for all types\n"
159 " 2 -- Enable DIF for all types, except Type 0.\n");
160
161 #if (IS_ENABLED(CONFIG_NVME_FC))
162 int ql2xnvmeenable = 1;
163 #else
164 int ql2xnvmeenable;
165 #endif
166 module_param(ql2xnvmeenable, int, 0644);
167 MODULE_PARM_DESC(ql2xnvmeenable,
168 "Enables NVME support. "
169 "0 - no NVMe. Default is Y");
170
171 int ql2xenablehba_err_chk = 2;
172 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
173 MODULE_PARM_DESC(ql2xenablehba_err_chk,
174 " Enable T10-CRC-DIF Error isolation by HBA:\n"
175 " Default is 2.\n"
176 " 0 -- Error isolation disabled\n"
177 " 1 -- Error isolation enabled only for DIX Type 0\n"
178 " 2 -- Error isolation enabled for all Types\n");
179
180 int ql2xmqsupport = 1;
181 module_param(ql2xmqsupport, int, S_IRUGO);
182 MODULE_PARM_DESC(ql2xmqsupport,
183 "Enable on demand multiple queue pairs support "
184 "Default is 1 for supported. "
185 "Set it to 0 to turn off mq qpair support.");
186
187 int ql2xfwloadbin;
188 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
189 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
190 MODULE_PARM_DESC(ql2xfwloadbin,
191 "Option to specify location from which to load ISP firmware:.\n"
192 " 2 -- load firmware via the request_firmware() (hotplug).\n"
193 " interface.\n"
194 " 1 -- load firmware from flash.\n"
195 " 0 -- use default semantics.\n");
196
197 int ql2xdbwr = 1;
198 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
199 MODULE_PARM_DESC(ql2xdbwr,
200 "Option to specify scheme for request queue posting.\n"
201 " 0 -- Regular doorbell.\n"
202 " 1 -- CAMRAM doorbell (faster).\n");
203
204 int ql2xgffidenable;
205 module_param(ql2xgffidenable, int, S_IRUGO);
206 MODULE_PARM_DESC(ql2xgffidenable,
207 "Enables GFF_ID checks of port type. "
208 "Default is 0 - Do not use GFF_ID information.");
209
210 int ql2xasynctmfenable = 1;
211 module_param(ql2xasynctmfenable, int, S_IRUGO);
212 MODULE_PARM_DESC(ql2xasynctmfenable,
213 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
214 "Default is 1 - Issue TM IOCBs via mailbox mechanism.");
215
216 int ql2xdontresethba;
217 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
218 MODULE_PARM_DESC(ql2xdontresethba,
219 "Option to specify reset behaviour.\n"
220 " 0 (Default) -- Reset on failure.\n"
221 " 1 -- Do not reset on failure.\n");
222
223 uint64_t ql2xmaxlun = MAX_LUNS;
224 module_param(ql2xmaxlun, ullong, S_IRUGO);
225 MODULE_PARM_DESC(ql2xmaxlun,
226 "Defines the maximum LU number to register with the SCSI "
227 "midlayer. Default is 65535.");
228
229 int ql2xmdcapmask = 0x1F;
230 module_param(ql2xmdcapmask, int, S_IRUGO);
231 MODULE_PARM_DESC(ql2xmdcapmask,
232 "Set the Minidump driver capture mask level. "
233 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
234
235 int ql2xmdenable = 1;
236 module_param(ql2xmdenable, int, S_IRUGO);
237 MODULE_PARM_DESC(ql2xmdenable,
238 "Enable/disable MiniDump. "
239 "0 - MiniDump disabled. "
240 "1 (Default) - MiniDump enabled.");
241
242 int ql2xexlogins;
243 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
244 MODULE_PARM_DESC(ql2xexlogins,
245 "Number of extended Logins. "
246 "0 (Default)- Disabled.");
247
248 int ql2xexchoffld = 1024;
249 module_param(ql2xexchoffld, uint, 0644);
250 MODULE_PARM_DESC(ql2xexchoffld,
251 "Number of target exchanges.");
252
253 int ql2xiniexchg = 1024;
254 module_param(ql2xiniexchg, uint, 0644);
255 MODULE_PARM_DESC(ql2xiniexchg,
256 "Number of initiator exchanges.");
257
258 int ql2xfwholdabts;
259 module_param(ql2xfwholdabts, int, S_IRUGO);
260 MODULE_PARM_DESC(ql2xfwholdabts,
261 "Allow FW to hold status IOCB until ABTS rsp received. "
262 "0 (Default) Do not set fw option. "
263 "1 - Set fw option to hold ABTS.");
264
265 int ql2xmvasynctoatio = 1;
266 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
267 MODULE_PARM_DESC(ql2xmvasynctoatio,
268 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
269 "0 (Default). Do not move IOCBs"
270 "1 - Move IOCBs.");
271
272 int ql2xautodetectsfp = 1;
273 module_param(ql2xautodetectsfp, int, 0444);
274 MODULE_PARM_DESC(ql2xautodetectsfp,
275 "Detect SFP range and set appropriate distance.\n"
276 "1 (Default): Enable\n");
277
278 int ql2xenablemsix = 1;
279 module_param(ql2xenablemsix, int, 0444);
280 MODULE_PARM_DESC(ql2xenablemsix,
281 "Set to enable MSI or MSI-X interrupt mechanism.\n"
282 " Default is 1, enable MSI-X interrupt mechanism.\n"
283 " 0 -- enable traditional pin-based mechanism.\n"
284 " 1 -- enable MSI-X interrupt mechanism.\n"
285 " 2 -- enable MSI interrupt mechanism.\n");
286
287 int qla2xuseresexchforels;
288 module_param(qla2xuseresexchforels, int, 0444);
289 MODULE_PARM_DESC(qla2xuseresexchforels,
290 "Reserve 1/2 of emergency exchanges for ELS.\n"
291 " 0 (default): disabled");
292
293 static int ql2xprotmask;
294 module_param(ql2xprotmask, int, 0644);
295 MODULE_PARM_DESC(ql2xprotmask,
296 "Override DIF/DIX protection capabilities mask\n"
297 "Default is 0 which sets protection mask based on "
298 "capabilities reported by HBA firmware.\n");
299
300 static int ql2xprotguard;
301 module_param(ql2xprotguard, int, 0644);
302 MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n"
303 " 0 -- Let HBA firmware decide\n"
304 " 1 -- Force T10 CRC\n"
305 " 2 -- Force IP checksum\n");
306
307 int ql2xdifbundlinginternalbuffers;
308 module_param(ql2xdifbundlinginternalbuffers, int, 0644);
309 MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers,
310 "Force using internal buffers for DIF information\n"
311 "0 (Default). Based on check.\n"
312 "1 Force using internal buffers\n");
313
314 int ql2xsmartsan;
315 module_param(ql2xsmartsan, int, 0444);
316 module_param_named(smartsan, ql2xsmartsan, int, 0444);
317 MODULE_PARM_DESC(ql2xsmartsan,
318 "Send SmartSAN Management Attributes for FDMI Registration."
319 " Default is 0 - No SmartSAN registration,"
320 " 1 - Register SmartSAN Management Attributes.");
321
322 int ql2xrdpenable;
323 module_param(ql2xrdpenable, int, 0444);
324 module_param_named(rdpenable, ql2xrdpenable, int, 0444);
325 MODULE_PARM_DESC(ql2xrdpenable,
326 "Enables RDP responses. "
327 "0 - no RDP responses (default). "
328 "1 - provide RDP responses.");
329 int ql2xabts_wait_nvme = 1;
330 module_param(ql2xabts_wait_nvme, int, 0444);
331 MODULE_PARM_DESC(ql2xabts_wait_nvme,
332 "To wait for ABTS response on I/O timeouts for NVMe. (default: 1)");
333
334
335 static u32 ql2xdelay_before_pci_error_handling = 5;
336 module_param(ql2xdelay_before_pci_error_handling, uint, 0644);
337 MODULE_PARM_DESC(ql2xdelay_before_pci_error_handling,
338 "Number of seconds delayed before qla begin PCI error self-handling (default: 5).\n");
339
340 static void qla2x00_clear_drv_active(struct qla_hw_data *);
341 static void qla2x00_free_device(scsi_qla_host_t *);
342 static void qla2xxx_map_queues(struct Scsi_Host *shost);
343 static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
344
345 u32 ql2xnvme_queues = DEF_NVME_HW_QUEUES;
346 module_param(ql2xnvme_queues, uint, S_IRUGO);
347 MODULE_PARM_DESC(ql2xnvme_queues,
348 "Number of NVMe Queues that can be configured.\n"
349 "Final value will be min(ql2xnvme_queues, num_cpus,num_chip_queues)\n"
350 "1 - Minimum number of queues supported\n"
351 "8 - Default value");
352
353 int ql2xfc2target = 1;
354 module_param(ql2xfc2target, int, 0444);
355 MODULE_PARM_DESC(ql2xfc2target,
356 "Enables FC2 Target support. "
357 "0 - FC2 Target support is disabled. "
358 "1 - FC2 Target support is enabled (default).");
359
360 static struct scsi_transport_template *qla2xxx_transport_template = NULL;
361 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
362
363 /* TODO Convert to inlines
364 *
365 * Timer routines
366 */
367
368 __inline__ void
qla2x00_start_timer(scsi_qla_host_t * vha,unsigned long interval)369 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval)
370 {
371 timer_setup(&vha->timer, qla2x00_timer, 0);
372 vha->timer.expires = jiffies + interval * HZ;
373 add_timer(&vha->timer);
374 vha->timer_active = 1;
375 }
376
377 static inline void
qla2x00_restart_timer(scsi_qla_host_t * vha,unsigned long interval)378 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
379 {
380 /* Currently used for 82XX only. */
381 if (vha->device_flags & DFLG_DEV_FAILED) {
382 ql_dbg(ql_dbg_timer, vha, 0x600d,
383 "Device in a failed state, returning.\n");
384 return;
385 }
386
387 mod_timer(&vha->timer, jiffies + interval * HZ);
388 }
389
390 static __inline__ void
qla2x00_stop_timer(scsi_qla_host_t * vha)391 qla2x00_stop_timer(scsi_qla_host_t *vha)
392 {
393 timer_delete_sync(&vha->timer);
394 vha->timer_active = 0;
395 }
396
397 static int qla2x00_do_dpc(void *data);
398
399 static void qla2x00_rst_aen(scsi_qla_host_t *);
400
401 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
402 struct req_que **, struct rsp_que **);
403 static void qla2x00_free_fw_dump(struct qla_hw_data *);
404 static void qla2x00_mem_free(struct qla_hw_data *);
405 static enum scsi_qc_status qla2xxx_mqueuecommand(struct Scsi_Host *host,
406 struct scsi_cmnd *cmd,
407 struct qla_qpair *qpair);
408
409 /* -------------------------------------------------------------------------- */
qla_init_base_qpair(struct scsi_qla_host * vha,struct req_que * req,struct rsp_que * rsp)410 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
411 struct rsp_que *rsp)
412 {
413 struct qla_hw_data *ha = vha->hw;
414
415 rsp->qpair = ha->base_qpair;
416 rsp->req = req;
417 ha->base_qpair->hw = ha;
418 ha->base_qpair->req = req;
419 ha->base_qpair->rsp = rsp;
420 ha->base_qpair->vha = vha;
421 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
422 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
423 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
424 ha->base_qpair->srb_mempool = ha->srb_mempool;
425 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
426 INIT_LIST_HEAD(&ha->base_qpair->dsd_list);
427 ha->base_qpair->enable_class_2 = ql2xenableclass2;
428 /* init qpair to this cpu. Will adjust at run time. */
429 qla_cpu_update(rsp->qpair, raw_smp_processor_id());
430 ha->base_qpair->pdev = ha->pdev;
431
432 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha) ||
433 IS_QLA29XX(ha))
434 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
435 }
436
qla2x00_alloc_queues(struct qla_hw_data * ha,struct req_que * req,struct rsp_que * rsp)437 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
438 struct rsp_que *rsp)
439 {
440 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
441
442 ha->req_q_map = kzalloc_objs(struct req_que *, ha->max_req_queues);
443 if (!ha->req_q_map) {
444 ql_log(ql_log_fatal, vha, 0x003b,
445 "Unable to allocate memory for request queue ptrs.\n");
446 goto fail_req_map;
447 }
448
449 ha->rsp_q_map = kzalloc_objs(struct rsp_que *, ha->max_rsp_queues);
450 if (!ha->rsp_q_map) {
451 ql_log(ql_log_fatal, vha, 0x003c,
452 "Unable to allocate memory for response queue ptrs.\n");
453 goto fail_rsp_map;
454 }
455
456 ha->base_qpair = kzalloc_obj(struct qla_qpair);
457 if (ha->base_qpair == NULL) {
458 ql_log(ql_log_warn, vha, 0x00e0,
459 "Failed to allocate base queue pair memory.\n");
460 goto fail_base_qpair;
461 }
462
463 qla_init_base_qpair(vha, req, rsp);
464
465 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) {
466 ha->queue_pair_map = kzalloc_objs(struct qla_qpair *,
467 ha->max_qpairs);
468 if (!ha->queue_pair_map) {
469 ql_log(ql_log_fatal, vha, 0x0180,
470 "Unable to allocate memory for queue pair ptrs.\n");
471 goto fail_qpair_map;
472 }
473 if (qla_mapq_alloc_qp_cpu_map(ha) != 0) {
474 kfree(ha->queue_pair_map);
475 ha->queue_pair_map = NULL;
476 goto fail_qpair_map;
477 }
478 }
479
480 /*
481 * Make sure we record at least the request and response queue zero in
482 * case we need to free them if part of the probe fails.
483 */
484 ha->rsp_q_map[0] = rsp;
485 ha->req_q_map[0] = req;
486 set_bit(0, ha->rsp_qid_map);
487 set_bit(0, ha->req_qid_map);
488 return 0;
489
490 fail_qpair_map:
491 kfree(ha->base_qpair);
492 ha->base_qpair = NULL;
493 fail_base_qpair:
494 kfree(ha->rsp_q_map);
495 ha->rsp_q_map = NULL;
496 fail_rsp_map:
497 kfree(ha->req_q_map);
498 ha->req_q_map = NULL;
499 fail_req_map:
500 return -ENOMEM;
501 }
502
qla2x00_free_req_que(struct qla_hw_data * ha,struct req_que * req)503 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
504 {
505 size_t req_entry_size = qla_req_entry_size(ha);
506
507 if (IS_QLAFX00(ha)) {
508 if (req && req->ring_fx00)
509 dma_free_coherent(&ha->pdev->dev,
510 (req->length_fx00 + 1) * sizeof(request_t),
511 req->ring_fx00, req->dma_fx00);
512 } else if (req && req->ring)
513 dma_free_coherent(&ha->pdev->dev,
514 (req->length + 1) * req_entry_size,
515 req->ring, req->dma);
516
517 if (req)
518 kfree(req->outstanding_cmds);
519
520 kfree(req);
521 }
522
qla2x00_free_rsp_que(struct qla_hw_data * ha,struct rsp_que * rsp)523 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
524 {
525 size_t rsp_entry_size = qla_rsp_entry_size(ha);
526
527 if (IS_QLAFX00(ha)) {
528 if (rsp && rsp->ring_fx00)
529 dma_free_coherent(&ha->pdev->dev,
530 (rsp->length_fx00 + 1) * sizeof(request_t),
531 rsp->ring_fx00, rsp->dma_fx00);
532 } else if (rsp && rsp->ring) {
533 dma_free_coherent(&ha->pdev->dev,
534 (rsp->length + 1) * rsp_entry_size,
535 rsp->ring, rsp->dma);
536 }
537 kfree(rsp);
538 }
539
qla2x00_free_queues(struct qla_hw_data * ha)540 static void qla2x00_free_queues(struct qla_hw_data *ha)
541 {
542 struct req_que *req;
543 struct rsp_que *rsp;
544 int cnt;
545 unsigned long flags;
546
547 if (ha->queue_pair_map) {
548 kfree(ha->queue_pair_map);
549 ha->queue_pair_map = NULL;
550 }
551 if (ha->base_qpair) {
552 kfree(ha->base_qpair);
553 ha->base_qpair = NULL;
554 }
555
556 qla_mapq_free_qp_cpu_map(ha);
557 spin_lock_irqsave(&ha->hardware_lock, flags);
558 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
559 if (!test_bit(cnt, ha->req_qid_map))
560 continue;
561
562 req = ha->req_q_map[cnt];
563 clear_bit(cnt, ha->req_qid_map);
564 ha->req_q_map[cnt] = NULL;
565
566 spin_unlock_irqrestore(&ha->hardware_lock, flags);
567 qla2x00_free_req_que(ha, req);
568 spin_lock_irqsave(&ha->hardware_lock, flags);
569 }
570 spin_unlock_irqrestore(&ha->hardware_lock, flags);
571
572 kfree(ha->req_q_map);
573 ha->req_q_map = NULL;
574
575
576 spin_lock_irqsave(&ha->hardware_lock, flags);
577 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
578 if (!test_bit(cnt, ha->rsp_qid_map))
579 continue;
580
581 rsp = ha->rsp_q_map[cnt];
582 clear_bit(cnt, ha->rsp_qid_map);
583 ha->rsp_q_map[cnt] = NULL;
584 spin_unlock_irqrestore(&ha->hardware_lock, flags);
585 qla2x00_free_rsp_que(ha, rsp);
586 spin_lock_irqsave(&ha->hardware_lock, flags);
587 }
588 spin_unlock_irqrestore(&ha->hardware_lock, flags);
589
590 kfree(ha->rsp_q_map);
591 ha->rsp_q_map = NULL;
592 }
593
594 static char *
qla2x00_pci_info_str(struct scsi_qla_host * vha,char * str,size_t str_len)595 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
596 {
597 struct qla_hw_data *ha = vha->hw;
598 static const char *const pci_bus_modes[] = {
599 "33", "66", "100", "133",
600 };
601 uint16_t pci_bus;
602
603 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
604 if (pci_bus) {
605 snprintf(str, str_len, "PCI-X (%s MHz)",
606 pci_bus_modes[pci_bus]);
607 } else {
608 pci_bus = (ha->pci_attr & BIT_8) >> 8;
609 snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]);
610 }
611
612 return str;
613 }
614
615 static char *
qla24xx_pci_info_str(struct scsi_qla_host * vha,char * str,size_t str_len)616 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
617 {
618 static const char *const pci_bus_modes[] = {
619 "33", "66", "100", "133",
620 };
621 struct qla_hw_data *ha = vha->hw;
622 uint32_t pci_bus;
623
624 if (pci_is_pcie(ha->pdev)) {
625 uint32_t lstat, lspeed, lwidth;
626 const char *speed_str;
627
628 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
629 lspeed = FIELD_GET(PCI_EXP_LNKCAP_SLS, lstat);
630 lwidth = FIELD_GET(PCI_EXP_LNKCAP_MLW, lstat);
631
632 switch (lspeed) {
633 case 1:
634 speed_str = "2.5GT/s";
635 break;
636 case 2:
637 speed_str = "5.0GT/s";
638 break;
639 case 3:
640 speed_str = "8.0GT/s";
641 break;
642 case 4:
643 speed_str = "16.0GT/s";
644 break;
645 default:
646 speed_str = "<unknown>";
647 break;
648 }
649 snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth);
650
651 return str;
652 }
653
654 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
655 if (pci_bus == 0 || pci_bus == 8)
656 snprintf(str, str_len, "PCI (%s MHz)",
657 pci_bus_modes[pci_bus >> 3]);
658 else
659 snprintf(str, str_len, "PCI-X Mode %d (%s MHz)",
660 pci_bus & 4 ? 2 : 1,
661 pci_bus_modes[pci_bus & 3]);
662
663 return str;
664 }
665
666 static char *
qla2x00_fw_version_str(struct scsi_qla_host * vha,char * str,size_t size)667 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
668 {
669 char un_str[10];
670 struct qla_hw_data *ha = vha->hw;
671
672 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
673 ha->fw_minor_version, ha->fw_subminor_version);
674
675 if (ha->fw_attributes & BIT_9) {
676 strcat(str, "FLX");
677 return (str);
678 }
679
680 switch (ha->fw_attributes & 0xFF) {
681 case 0x7:
682 strcat(str, "EF");
683 break;
684 case 0x17:
685 strcat(str, "TP");
686 break;
687 case 0x37:
688 strcat(str, "IP");
689 break;
690 case 0x77:
691 strcat(str, "VI");
692 break;
693 default:
694 sprintf(un_str, "(%x)", ha->fw_attributes);
695 strcat(str, un_str);
696 break;
697 }
698 if (ha->fw_attributes & 0x100)
699 strcat(str, "X");
700
701 return (str);
702 }
703
704 static char *
qla24xx_fw_version_str(struct scsi_qla_host * vha,char * str,size_t size)705 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
706 {
707 struct qla_hw_data *ha = vha->hw;
708
709 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
710 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
711 return str;
712 }
713
qla2x00_sp_free_dma(srb_t * sp)714 void qla2x00_sp_free_dma(srb_t *sp)
715 {
716 struct qla_hw_data *ha = sp->vha->hw;
717 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
718
719 if (sp->flags & SRB_DMA_VALID) {
720 scsi_dma_unmap(cmd);
721 sp->flags &= ~SRB_DMA_VALID;
722 }
723
724 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
725 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
726 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
727 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
728 }
729
730 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
731 /* List assured to be having elements */
732 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
733 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
734 }
735
736 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
737 struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
738
739 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
740 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
741 }
742
743 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
744 struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx;
745
746 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
747 ctx1->fcp_cmnd_dma);
748 list_splice(&ctx1->dsd_list, &sp->qpair->dsd_list);
749 sp->qpair->dsd_inuse -= ctx1->dsd_use_cnt;
750 sp->qpair->dsd_avail += ctx1->dsd_use_cnt;
751 }
752
753 if (sp->flags & SRB_GOT_BUF)
754 qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc);
755 }
756
qla2x00_sp_compl(srb_t * sp,int res)757 void qla2x00_sp_compl(srb_t *sp, int res)
758 {
759 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
760 struct completion *comp = sp->comp;
761
762 /* kref: INIT */
763 kref_put(&sp->cmd_kref, qla2x00_sp_release);
764 cmd->result = res;
765 sp->type = 0;
766 scsi_done(cmd);
767 if (comp)
768 complete(comp);
769 }
770
qla2xxx_qpair_sp_free_dma(srb_t * sp)771 void qla2xxx_qpair_sp_free_dma(srb_t *sp)
772 {
773 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
774 struct qla_hw_data *ha = sp->fcport->vha->hw;
775
776 if (sp->flags & SRB_DMA_VALID) {
777 scsi_dma_unmap(cmd);
778 sp->flags &= ~SRB_DMA_VALID;
779 }
780
781 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
782 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
783 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
784 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
785 }
786
787 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
788 /* List assured to be having elements */
789 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
790 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
791 }
792
793 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) {
794 struct crc_context *difctx = sp->u.scmd.crc_ctx;
795 struct dsd_dma *dif_dsd, *nxt_dsd;
796
797 list_for_each_entry_safe(dif_dsd, nxt_dsd,
798 &difctx->ldif_dma_hndl_list, list) {
799 list_del(&dif_dsd->list);
800 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr,
801 dif_dsd->dsd_list_dma);
802 kfree(dif_dsd);
803 difctx->no_dif_bundl--;
804 }
805
806 list_for_each_entry_safe(dif_dsd, nxt_dsd,
807 &difctx->ldif_dsd_list, list) {
808 list_del(&dif_dsd->list);
809 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr,
810 dif_dsd->dsd_list_dma);
811 kfree(dif_dsd);
812 difctx->no_ldif_dsd--;
813 }
814
815 if (difctx->no_ldif_dsd) {
816 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
817 "%s: difctx->no_ldif_dsd=%x\n",
818 __func__, difctx->no_ldif_dsd);
819 }
820
821 if (difctx->no_dif_bundl) {
822 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
823 "%s: difctx->no_dif_bundl=%x\n",
824 __func__, difctx->no_dif_bundl);
825 }
826 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID;
827 }
828
829 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
830 struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx;
831
832 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
833 ctx1->fcp_cmnd_dma);
834 list_splice(&ctx1->dsd_list, &sp->qpair->dsd_list);
835 sp->qpair->dsd_inuse -= ctx1->dsd_use_cnt;
836 sp->qpair->dsd_avail += ctx1->dsd_use_cnt;
837 sp->flags &= ~SRB_FCP_CMND_DMA_VALID;
838 }
839
840 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
841 struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
842
843 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
844 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
845 }
846
847 if (sp->flags & SRB_GOT_BUF)
848 qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc);
849 }
850
qla2xxx_qpair_sp_compl(srb_t * sp,int res)851 void qla2xxx_qpair_sp_compl(srb_t *sp, int res)
852 {
853 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
854 struct completion *comp = sp->comp;
855
856 /* ref: INIT */
857 kref_put(&sp->cmd_kref, qla2x00_sp_release);
858 cmd->result = res;
859 sp->type = 0;
860 scsi_done(cmd);
861 if (comp)
862 complete(comp);
863 }
864
qla2xxx_queuecommand(struct Scsi_Host * host,struct scsi_cmnd * cmd)865 static enum scsi_qc_status qla2xxx_queuecommand(struct Scsi_Host *host,
866 struct scsi_cmnd *cmd)
867 {
868 scsi_qla_host_t *vha = shost_priv(host);
869 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
870 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
871 struct qla_hw_data *ha = vha->hw;
872 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
873 srb_t *sp;
874 int rval;
875
876 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) ||
877 WARN_ON_ONCE(!rport)) {
878 cmd->result = DID_NO_CONNECT << 16;
879 goto qc24_fail_command;
880 }
881
882 if (ha->mqenable) {
883 uint32_t tag;
884 uint16_t hwq;
885 struct qla_qpair *qpair = NULL;
886
887 tag = blk_mq_unique_tag(scsi_cmd_to_rq(cmd));
888 hwq = blk_mq_unique_tag_to_hwq(tag);
889 qpair = ha->queue_pair_map[hwq];
890
891 if (qpair)
892 return qla2xxx_mqueuecommand(host, cmd, qpair);
893 }
894
895 if (ha->flags.eeh_busy) {
896 if (ha->flags.pci_channel_io_perm_failure) {
897 ql_dbg(ql_dbg_aer, vha, 0x9010,
898 "PCI Channel IO permanent failure, exiting "
899 "cmd=%p.\n", cmd);
900 cmd->result = DID_NO_CONNECT << 16;
901 } else {
902 ql_dbg(ql_dbg_aer, vha, 0x9011,
903 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
904 cmd->result = DID_REQUEUE << 16;
905 }
906 goto qc24_fail_command;
907 }
908
909 rval = fc_remote_port_chkready(rport);
910 if (rval) {
911 cmd->result = rval;
912 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
913 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
914 cmd, rval);
915 goto qc24_fail_command;
916 }
917
918 if (!vha->flags.difdix_supported &&
919 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
920 ql_dbg(ql_dbg_io, vha, 0x3004,
921 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
922 cmd);
923 cmd->result = DID_NO_CONNECT << 16;
924 goto qc24_fail_command;
925 }
926
927 if (!fcport || fcport->deleted) {
928 cmd->result = DID_IMM_RETRY << 16;
929 goto qc24_fail_command;
930 }
931
932 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) {
933 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
934 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
935 ql_dbg(ql_dbg_io, vha, 0x3005,
936 "Returning DNC, fcport_state=%d loop_state=%d.\n",
937 atomic_read(&fcport->state),
938 atomic_read(&base_vha->loop_state));
939 cmd->result = DID_NO_CONNECT << 16;
940 goto qc24_fail_command;
941 }
942 goto qc24_target_busy;
943 }
944
945 /*
946 * Return target busy if we've received a non-zero retry_delay_timer
947 * in a FCP_RSP.
948 */
949 if (fcport->retry_delay_timestamp == 0) {
950 /* retry delay not set */
951 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
952 fcport->retry_delay_timestamp = 0;
953 else
954 goto qc24_target_busy;
955
956 sp = scsi_cmd_priv(cmd);
957 /* ref: INIT */
958 qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport);
959
960 sp->u.scmd.cmd = cmd;
961 sp->type = SRB_SCSI_CMD;
962 sp->free = qla2x00_sp_free_dma;
963 sp->done = qla2x00_sp_compl;
964
965 rval = ha->isp_ops->start_scsi(sp);
966 if (rval != QLA_SUCCESS) {
967 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
968 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
969 goto qc24_host_busy_free_sp;
970 }
971
972 return 0;
973
974 qc24_host_busy_free_sp:
975 /* ref: INIT */
976 kref_put(&sp->cmd_kref, qla2x00_sp_release);
977
978 qc24_target_busy:
979 return SCSI_MLQUEUE_TARGET_BUSY;
980
981 qc24_fail_command:
982 scsi_done(cmd);
983
984 return 0;
985 }
986
987 /* For MQ supported I/O */
988 static enum scsi_qc_status
qla2xxx_mqueuecommand(struct Scsi_Host * host,struct scsi_cmnd * cmd,struct qla_qpair * qpair)989 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
990 struct qla_qpair *qpair)
991 {
992 scsi_qla_host_t *vha = shost_priv(host);
993 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
994 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
995 struct qla_hw_data *ha = vha->hw;
996 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
997 srb_t *sp;
998 int rval;
999
1000 rval = rport ? fc_remote_port_chkready(rport) : (DID_NO_CONNECT << 16);
1001 if (rval) {
1002 cmd->result = rval;
1003 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
1004 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
1005 cmd, rval);
1006 goto qc24_fail_command;
1007 }
1008
1009 if (!qpair->online) {
1010 ql_dbg(ql_dbg_io, vha, 0x3077,
1011 "qpair not online. eeh_busy=%d.\n", ha->flags.eeh_busy);
1012 cmd->result = DID_NO_CONNECT << 16;
1013 goto qc24_fail_command;
1014 }
1015
1016 if (!fcport || fcport->deleted) {
1017 cmd->result = DID_IMM_RETRY << 16;
1018 goto qc24_fail_command;
1019 }
1020
1021 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) {
1022 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
1023 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
1024 ql_dbg(ql_dbg_io, vha, 0x3077,
1025 "Returning DNC, fcport_state=%d loop_state=%d.\n",
1026 atomic_read(&fcport->state),
1027 atomic_read(&base_vha->loop_state));
1028 cmd->result = DID_NO_CONNECT << 16;
1029 goto qc24_fail_command;
1030 }
1031 goto qc24_target_busy;
1032 }
1033
1034 /*
1035 * Return target busy if we've received a non-zero retry_delay_timer
1036 * in a FCP_RSP.
1037 */
1038 if (fcport->retry_delay_timestamp == 0) {
1039 /* retry delay not set */
1040 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
1041 fcport->retry_delay_timestamp = 0;
1042 else
1043 goto qc24_target_busy;
1044
1045 sp = scsi_cmd_priv(cmd);
1046 /* ref: INIT */
1047 qla2xxx_init_sp(sp, vha, qpair, fcport);
1048
1049 sp->u.scmd.cmd = cmd;
1050 sp->type = SRB_SCSI_CMD;
1051 sp->free = qla2xxx_qpair_sp_free_dma;
1052 sp->done = qla2xxx_qpair_sp_compl;
1053
1054 rval = ha->isp_ops->start_scsi_mq(sp);
1055 if (rval != QLA_SUCCESS) {
1056 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1057 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1058 goto qc24_host_busy_free_sp;
1059 }
1060
1061 return 0;
1062
1063 qc24_host_busy_free_sp:
1064 /* ref: INIT */
1065 kref_put(&sp->cmd_kref, qla2x00_sp_release);
1066
1067 qc24_target_busy:
1068 return SCSI_MLQUEUE_TARGET_BUSY;
1069
1070 qc24_fail_command:
1071 scsi_done(cmd);
1072
1073 return 0;
1074 }
1075
1076 /*
1077 * qla2x00_wait_for_hba_online
1078 * Wait till the HBA is online after going through
1079 * <= MAX_RETRIES_OF_ISP_ABORT or
1080 * finally HBA is disabled ie marked offline
1081 *
1082 * Input:
1083 * ha - pointer to host adapter structure
1084 *
1085 * Note:
1086 * Does context switching-Release SPIN_LOCK
1087 * (if any) before calling this routine.
1088 *
1089 * Return:
1090 * Success (Adapter is online) : 0
1091 * Failed (Adapter is offline/disabled) : 1
1092 */
1093 int
qla2x00_wait_for_hba_online(scsi_qla_host_t * vha)1094 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1095 {
1096 int return_status;
1097 unsigned long wait_online;
1098 struct qla_hw_data *ha = vha->hw;
1099 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1100
1101 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1102 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1103 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1104 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1105 ha->dpc_active) && time_before(jiffies, wait_online)) {
1106
1107 msleep(1000);
1108 }
1109 if (base_vha->flags.online)
1110 return_status = QLA_SUCCESS;
1111 else
1112 return_status = QLA_FUNCTION_FAILED;
1113
1114 return (return_status);
1115 }
1116
test_fcport_count(scsi_qla_host_t * vha)1117 static inline int test_fcport_count(scsi_qla_host_t *vha)
1118 {
1119 struct qla_hw_data *ha = vha->hw;
1120 unsigned long flags;
1121 int res;
1122 /* Return 0 = sleep, x=wake */
1123
1124 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
1125 ql_dbg(ql_dbg_init, vha, 0x00ec,
1126 "tgt %p, fcport_count=%d\n",
1127 vha, vha->fcport_count);
1128 res = (vha->fcport_count == 0);
1129 if (res) {
1130 struct fc_port *fcport;
1131
1132 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1133 if (fcport->deleted != QLA_SESS_DELETED) {
1134 /* session(s) may not be fully logged in
1135 * (ie fcport_count=0), but session
1136 * deletion thread(s) may be inflight.
1137 */
1138
1139 res = 0;
1140 break;
1141 }
1142 }
1143 }
1144 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1145
1146 return res;
1147 }
1148
1149 /*
1150 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1151 * it has dependency on UNLOADING flag to stop device discovery
1152 */
1153 void
qla2x00_wait_for_sess_deletion(scsi_qla_host_t * vha)1154 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1155 {
1156 u8 i;
1157
1158 qla2x00_mark_all_devices_lost(vha);
1159
1160 for (i = 0; i < 10; i++) {
1161 if (wait_event_timeout(vha->fcport_waitQ,
1162 test_fcport_count(vha), HZ) > 0)
1163 break;
1164 }
1165
1166 flush_workqueue(vha->hw->wq);
1167 }
1168
1169 /*
1170 * qla2x00_wait_for_hba_ready
1171 * Wait till the HBA is ready before doing driver unload
1172 *
1173 * Input:
1174 * ha - pointer to host adapter structure
1175 *
1176 * Note:
1177 * Does context switching-Release SPIN_LOCK
1178 * (if any) before calling this routine.
1179 *
1180 */
1181 static void
qla2x00_wait_for_hba_ready(scsi_qla_host_t * vha)1182 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
1183 {
1184 struct qla_hw_data *ha = vha->hw;
1185 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1186
1187 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1188 ha->flags.mbox_busy) ||
1189 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1190 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags) ||
1191 (vha->scan.scan_flags & SF_SCANNING)) {
1192 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1193 break;
1194 msleep(1000);
1195 }
1196 }
1197
1198 int
qla2x00_wait_for_chip_reset(scsi_qla_host_t * vha)1199 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1200 {
1201 int return_status;
1202 unsigned long wait_reset;
1203 struct qla_hw_data *ha = vha->hw;
1204 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1205
1206 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1207 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1208 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1209 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1210 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1211
1212 msleep(1000);
1213
1214 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1215 ha->flags.chip_reset_done)
1216 break;
1217 }
1218 if (ha->flags.chip_reset_done)
1219 return_status = QLA_SUCCESS;
1220 else
1221 return_status = QLA_FUNCTION_FAILED;
1222
1223 return return_status;
1224 }
1225
1226 /**************************************************************************
1227 * qla2xxx_eh_abort
1228 *
1229 * Description:
1230 * The abort function will abort the specified command.
1231 *
1232 * Input:
1233 * cmd = Linux SCSI command packet to be aborted.
1234 *
1235 * Returns:
1236 * Either SUCCESS or FAILED.
1237 *
1238 * Note:
1239 * Only return FAILED if command not returned by firmware.
1240 **************************************************************************/
1241 static int
qla2xxx_eh_abort(struct scsi_cmnd * cmd)1242 qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1243 {
1244 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1245 DECLARE_COMPLETION_ONSTACK(comp);
1246 srb_t *sp;
1247 int ret;
1248 unsigned int id;
1249 uint64_t lun;
1250 int rval;
1251 struct qla_hw_data *ha = vha->hw;
1252 uint32_t ratov_j;
1253 struct qla_qpair *qpair;
1254 unsigned long flags;
1255 int fast_fail_status = SUCCESS;
1256
1257 if (qla2x00_isp_reg_stat(ha)) {
1258 ql_log(ql_log_info, vha, 0x8042,
1259 "PCI/Register disconnect, exiting.\n");
1260 qla_pci_set_eeh_busy(vha);
1261 return FAILED;
1262 }
1263
1264 /* Save any FAST_IO_FAIL value to return later if abort succeeds */
1265 ret = fc_block_scsi_eh(cmd);
1266 if (ret != 0)
1267 fast_fail_status = ret;
1268
1269 sp = scsi_cmd_priv(cmd);
1270 qpair = sp->qpair;
1271
1272 vha->cmd_timeout_cnt++;
1273
1274 if ((sp->fcport && sp->fcport->deleted) || !qpair)
1275 return fast_fail_status != SUCCESS ? fast_fail_status : FAILED;
1276
1277 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1278 sp->comp = ∁
1279 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1280
1281
1282 id = cmd->device->id;
1283 lun = cmd->device->lun;
1284
1285 ql_dbg(ql_dbg_taskm, vha, 0x8002,
1286 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1287 vha->host_no, id, lun, sp, cmd, sp->handle);
1288
1289 /*
1290 * Abort will release the original Command/sp from FW. Let the
1291 * original command call scsi_done. In return, he will wakeup
1292 * this sleeping thread.
1293 */
1294 rval = ha->isp_ops->abort_command(sp);
1295
1296 ql_dbg(ql_dbg_taskm, vha, 0x8003,
1297 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval);
1298
1299 /* Wait for the command completion. */
1300 ratov_j = ha->r_a_tov / 10 * 4;
1301 ratov_j = secs_to_jiffies(ratov_j);
1302 switch (rval) {
1303 case QLA_SUCCESS:
1304 if (!wait_for_completion_timeout(&comp, ratov_j)) {
1305 ql_dbg(ql_dbg_taskm, vha, 0xffff,
1306 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1307 __func__, ha->r_a_tov/10);
1308 ret = FAILED;
1309 } else {
1310 ret = fast_fail_status;
1311 }
1312 break;
1313 default:
1314 ret = FAILED;
1315 break;
1316 }
1317
1318 sp->comp = NULL;
1319
1320 ql_log(ql_log_info, vha, 0x801c,
1321 "Abort command issued nexus=%ld:%d:%llu -- %x.\n",
1322 vha->host_no, id, lun, ret);
1323
1324 return ret;
1325 }
1326
1327 #define ABORT_POLLING_PERIOD 1000
1328 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
1329
1330 /*
1331 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED.
1332 */
1333 static int
__qla2x00_eh_wait_for_pending_commands(struct qla_qpair * qpair,unsigned int t,uint64_t l,enum nexus_wait_type type)1334 __qla2x00_eh_wait_for_pending_commands(struct qla_qpair *qpair, unsigned int t,
1335 uint64_t l, enum nexus_wait_type type)
1336 {
1337 int cnt, match, status;
1338 unsigned long flags;
1339 scsi_qla_host_t *vha = qpair->vha;
1340 struct req_que *req = qpair->req;
1341 srb_t *sp;
1342 struct scsi_cmnd *cmd;
1343 unsigned long wait_iter = ABORT_WAIT_ITER;
1344 bool found;
1345 struct qla_hw_data *ha = vha->hw;
1346
1347 status = QLA_SUCCESS;
1348
1349 while (wait_iter--) {
1350 found = false;
1351
1352 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1353 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1354 sp = req->outstanding_cmds[cnt];
1355 if (!sp)
1356 continue;
1357 if (sp->type != SRB_SCSI_CMD)
1358 continue;
1359 if (vha->vp_idx != sp->vha->vp_idx)
1360 continue;
1361 match = 0;
1362 cmd = GET_CMD_SP(sp);
1363 switch (type) {
1364 case WAIT_HOST:
1365 match = 1;
1366 break;
1367 case WAIT_TARGET:
1368 if (sp->fcport)
1369 match = sp->fcport->d_id.b24 == t;
1370 else
1371 match = 0;
1372 break;
1373 case WAIT_LUN:
1374 if (sp->fcport)
1375 match = (sp->fcport->d_id.b24 == t &&
1376 cmd->device->lun == l);
1377 else
1378 match = 0;
1379 break;
1380 }
1381 if (!match)
1382 continue;
1383
1384 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1385
1386 if (unlikely(pci_channel_offline(ha->pdev)) ||
1387 ha->flags.eeh_busy) {
1388 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1389 "Return:eh_wait.\n");
1390 return status;
1391 }
1392
1393 /*
1394 * SRB_SCSI_CMD is still in the outstanding_cmds array.
1395 * it means scsi_done has not called. Wait for it to
1396 * clear from outstanding_cmds.
1397 */
1398 msleep(ABORT_POLLING_PERIOD);
1399 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1400 found = true;
1401 }
1402 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1403
1404 if (!found)
1405 break;
1406 }
1407
1408 if (wait_iter == -1)
1409 status = QLA_FUNCTION_FAILED;
1410
1411 return status;
1412 }
1413
1414 int
qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t * vha,unsigned int t,uint64_t l,enum nexus_wait_type type)1415 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
1416 uint64_t l, enum nexus_wait_type type)
1417 {
1418 struct qla_qpair *qpair;
1419 struct qla_hw_data *ha = vha->hw;
1420 int i, status = QLA_SUCCESS;
1421
1422 status = __qla2x00_eh_wait_for_pending_commands(ha->base_qpair, t, l,
1423 type);
1424 for (i = 0; status == QLA_SUCCESS && i < ha->max_qpairs; i++) {
1425 qpair = ha->queue_pair_map[i];
1426 if (!qpair)
1427 continue;
1428 status = __qla2x00_eh_wait_for_pending_commands(qpair, t, l,
1429 type);
1430 }
1431 return status;
1432 }
1433
1434 static char *reset_errors[] = {
1435 "HBA not online",
1436 "HBA not ready",
1437 "Task management failed",
1438 "Waiting for command completions",
1439 };
1440
1441 static int
qla2xxx_eh_device_reset(struct scsi_cmnd * cmd)1442 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1443 {
1444 struct scsi_device *sdev = cmd->device;
1445 scsi_qla_host_t *vha = shost_priv(sdev->host);
1446 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1447 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1448 struct qla_hw_data *ha = vha->hw;
1449 int err;
1450
1451 if (qla2x00_isp_reg_stat(ha)) {
1452 ql_log(ql_log_info, vha, 0x803e,
1453 "PCI/Register disconnect, exiting.\n");
1454 qla_pci_set_eeh_busy(vha);
1455 return FAILED;
1456 }
1457
1458 if (!fcport) {
1459 return FAILED;
1460 }
1461
1462 err = fc_block_rport(rport);
1463 if (err != 0)
1464 return err;
1465
1466 if (fcport->deleted)
1467 return FAILED;
1468
1469 ql_log(ql_log_info, vha, 0x8009,
1470 "DEVICE RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", vha->host_no,
1471 sdev->id, sdev->lun, cmd);
1472
1473 err = 0;
1474 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1475 ql_log(ql_log_warn, vha, 0x800a,
1476 "Wait for hba online failed for cmd=%p.\n", cmd);
1477 goto eh_reset_failed;
1478 }
1479 err = 2;
1480 if (ha->isp_ops->lun_reset(fcport, sdev->lun, 1)
1481 != QLA_SUCCESS) {
1482 ql_log(ql_log_warn, vha, 0x800c,
1483 "do_reset failed for cmd=%p.\n", cmd);
1484 goto eh_reset_failed;
1485 }
1486 err = 3;
1487 if (qla2x00_eh_wait_for_pending_commands(vha, fcport->d_id.b24,
1488 cmd->device->lun,
1489 WAIT_LUN) != QLA_SUCCESS) {
1490 ql_log(ql_log_warn, vha, 0x800d,
1491 "wait for pending cmds failed for cmd=%p.\n", cmd);
1492 goto eh_reset_failed;
1493 }
1494
1495 ql_log(ql_log_info, vha, 0x800e,
1496 "DEVICE RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n",
1497 vha->host_no, sdev->id, sdev->lun, cmd);
1498
1499 return SUCCESS;
1500
1501 eh_reset_failed:
1502 ql_log(ql_log_info, vha, 0x800f,
1503 "DEVICE RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n",
1504 reset_errors[err], vha->host_no, sdev->id, sdev->lun,
1505 cmd);
1506 vha->reset_cmd_err_cnt++;
1507 return FAILED;
1508 }
1509
1510 static int
qla2xxx_eh_target_reset(struct scsi_cmnd * cmd)1511 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1512 {
1513 struct scsi_device *sdev = cmd->device;
1514 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1515 scsi_qla_host_t *vha = shost_priv(rport_to_shost(rport));
1516 struct qla_hw_data *ha = vha->hw;
1517 fc_port_t *fcport = *(fc_port_t **)rport->dd_data;
1518 int err;
1519
1520 if (qla2x00_isp_reg_stat(ha)) {
1521 ql_log(ql_log_info, vha, 0x803f,
1522 "PCI/Register disconnect, exiting.\n");
1523 qla_pci_set_eeh_busy(vha);
1524 return FAILED;
1525 }
1526
1527 if (!fcport) {
1528 return FAILED;
1529 }
1530
1531 err = fc_block_rport(rport);
1532 if (err != 0)
1533 return err;
1534
1535 if (fcport->deleted)
1536 return FAILED;
1537
1538 ql_log(ql_log_info, vha, 0x8009,
1539 "TARGET RESET ISSUED nexus=%ld:%d cmd=%p.\n", vha->host_no,
1540 sdev->id, cmd);
1541
1542 err = 0;
1543 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1544 ql_log(ql_log_warn, vha, 0x800a,
1545 "Wait for hba online failed for cmd=%p.\n", cmd);
1546 goto eh_reset_failed;
1547 }
1548 err = 2;
1549 if (ha->isp_ops->target_reset(fcport, 0, 0) != QLA_SUCCESS) {
1550 ql_log(ql_log_warn, vha, 0x800c,
1551 "target_reset failed for cmd=%p.\n", cmd);
1552 goto eh_reset_failed;
1553 }
1554 err = 3;
1555 if (qla2x00_eh_wait_for_pending_commands(vha, fcport->d_id.b24, 0,
1556 WAIT_TARGET) != QLA_SUCCESS) {
1557 ql_log(ql_log_warn, vha, 0x800d,
1558 "wait for pending cmds failed for cmd=%p.\n", cmd);
1559 goto eh_reset_failed;
1560 }
1561
1562 ql_log(ql_log_info, vha, 0x800e,
1563 "TARGET RESET SUCCEEDED nexus:%ld:%d cmd=%p.\n",
1564 vha->host_no, sdev->id, cmd);
1565
1566 return SUCCESS;
1567
1568 eh_reset_failed:
1569 ql_log(ql_log_info, vha, 0x800f,
1570 "TARGET RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n",
1571 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1572 cmd);
1573 vha->reset_cmd_err_cnt++;
1574 return FAILED;
1575 }
1576
1577 /**************************************************************************
1578 * qla2xxx_eh_bus_reset
1579 *
1580 * Description:
1581 * The bus reset function will reset the bus and abort any executing
1582 * commands.
1583 *
1584 * Input:
1585 * cmd = Linux SCSI command packet of the command that cause the
1586 * bus reset.
1587 *
1588 * Returns:
1589 * SUCCESS/FAILURE (defined as macro in scsi.h).
1590 *
1591 **************************************************************************/
1592 static int
qla2xxx_eh_bus_reset(struct scsi_cmnd * cmd)1593 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1594 {
1595 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1596 int ret = FAILED;
1597 unsigned int id;
1598 uint64_t lun;
1599 struct qla_hw_data *ha = vha->hw;
1600
1601 if (qla2x00_isp_reg_stat(ha)) {
1602 ql_log(ql_log_info, vha, 0x8040,
1603 "PCI/Register disconnect, exiting.\n");
1604 qla_pci_set_eeh_busy(vha);
1605 return FAILED;
1606 }
1607
1608 id = cmd->device->id;
1609 lun = cmd->device->lun;
1610
1611 if (qla2x00_chip_is_down(vha))
1612 return ret;
1613
1614 ql_log(ql_log_info, vha, 0x8012,
1615 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1616
1617 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1618 ql_log(ql_log_fatal, vha, 0x8013,
1619 "Wait for hba online failed board disabled.\n");
1620 goto eh_bus_reset_done;
1621 }
1622
1623 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1624 ret = SUCCESS;
1625
1626 if (ret == FAILED)
1627 goto eh_bus_reset_done;
1628
1629 /* Flush outstanding commands. */
1630 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
1631 QLA_SUCCESS) {
1632 ql_log(ql_log_warn, vha, 0x8014,
1633 "Wait for pending commands failed.\n");
1634 ret = FAILED;
1635 }
1636
1637 eh_bus_reset_done:
1638 ql_log(ql_log_warn, vha, 0x802b,
1639 "BUS RESET %s nexus=%ld:%d:%llu.\n",
1640 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1641
1642 return ret;
1643 }
1644
1645 /**************************************************************************
1646 * qla2xxx_eh_host_reset
1647 *
1648 * Description:
1649 * The reset function will reset the Adapter.
1650 *
1651 * Input:
1652 * cmd = Linux SCSI command packet of the command that cause the
1653 * adapter reset.
1654 *
1655 * Returns:
1656 * Either SUCCESS or FAILED.
1657 *
1658 * Note:
1659 **************************************************************************/
1660 static int
qla2xxx_eh_host_reset(struct scsi_cmnd * cmd)1661 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1662 {
1663 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1664 struct qla_hw_data *ha = vha->hw;
1665 int ret = FAILED;
1666 unsigned int id;
1667 uint64_t lun;
1668 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1669
1670 if (qla2x00_isp_reg_stat(ha)) {
1671 ql_log(ql_log_info, vha, 0x8041,
1672 "PCI/Register disconnect, exiting.\n");
1673 qla_pci_set_eeh_busy(vha);
1674 return SUCCESS;
1675 }
1676
1677 id = cmd->device->id;
1678 lun = cmd->device->lun;
1679
1680 ql_log(ql_log_info, vha, 0x8018,
1681 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1682
1683 /*
1684 * No point in issuing another reset if one is active. Also do not
1685 * attempt a reset if we are updating flash.
1686 */
1687 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
1688 goto eh_host_reset_lock;
1689
1690 if (vha != base_vha) {
1691 if (qla2x00_vp_abort_isp(vha))
1692 goto eh_host_reset_lock;
1693 } else {
1694 if (IS_P3P_TYPE(vha->hw)) {
1695 if (!qla82xx_fcoe_ctx_reset(vha)) {
1696 /* Ctx reset success */
1697 ret = SUCCESS;
1698 goto eh_host_reset_lock;
1699 }
1700 /* fall thru if ctx reset failed */
1701 }
1702 if (ha->wq)
1703 flush_workqueue(ha->wq);
1704
1705 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1706 if (ha->isp_ops->abort_isp(base_vha)) {
1707 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1708 /* failed. schedule dpc to try */
1709 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1710
1711 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1712 ql_log(ql_log_warn, vha, 0x802a,
1713 "wait for hba online failed.\n");
1714 goto eh_host_reset_lock;
1715 }
1716 }
1717 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1718 }
1719
1720 /* Waiting for command to be returned to OS.*/
1721 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
1722 QLA_SUCCESS)
1723 ret = SUCCESS;
1724
1725 eh_host_reset_lock:
1726 ql_log(ql_log_info, vha, 0x8017,
1727 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
1728 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1729
1730 return ret;
1731 }
1732
1733 /*
1734 * qla2x00_loop_reset
1735 * Issue loop reset.
1736 *
1737 * Input:
1738 * ha = adapter block pointer.
1739 *
1740 * Returns:
1741 * 0 = success
1742 */
1743 int
qla2x00_loop_reset(scsi_qla_host_t * vha)1744 qla2x00_loop_reset(scsi_qla_host_t *vha)
1745 {
1746 int ret;
1747 struct qla_hw_data *ha = vha->hw;
1748
1749 if (IS_QLAFX00(ha))
1750 return QLA_SUCCESS;
1751
1752 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
1753 atomic_set(&vha->loop_state, LOOP_DOWN);
1754 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1755 qla2x00_mark_all_devices_lost(vha);
1756 ret = qla2x00_full_login_lip(vha);
1757 if (ret != QLA_SUCCESS) {
1758 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1759 "full_login_lip=%d.\n", ret);
1760 }
1761 }
1762
1763 if (ha->flags.enable_lip_reset) {
1764 ret = qla2x00_lip_reset(vha);
1765 if (ret != QLA_SUCCESS)
1766 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1767 "lip_reset failed (%d).\n", ret);
1768 }
1769
1770 /* Issue marker command only when we are going to start the I/O */
1771 vha->marker_needed = 1;
1772
1773 return QLA_SUCCESS;
1774 }
1775
1776 /*
1777 * The caller must ensure that no completion interrupts will happen
1778 * while this function is in progress.
1779 */
qla2x00_abort_srb(struct qla_qpair * qp,srb_t * sp,const int res,unsigned long * flags)1780 static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res,
1781 unsigned long *flags)
1782 __releases(qp->qp_lock_ptr)
1783 __acquires(qp->qp_lock_ptr)
1784 {
1785 DECLARE_COMPLETION_ONSTACK(comp);
1786 scsi_qla_host_t *vha = qp->vha;
1787 struct qla_hw_data *ha = vha->hw;
1788 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
1789 int rval;
1790 bool ret_cmd;
1791 uint32_t ratov_j;
1792
1793 lockdep_assert_held(qp->qp_lock_ptr);
1794
1795 if (qla2x00_chip_is_down(vha)) {
1796 sp->done(sp, res);
1797 return;
1798 }
1799
1800 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS ||
1801 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy &&
1802 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
1803 !qla2x00_isp_reg_stat(ha))) {
1804 if (sp->comp) {
1805 sp->done(sp, res);
1806 return;
1807 }
1808
1809 sp->comp = ∁
1810 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags);
1811
1812 rval = ha->isp_ops->abort_command(sp);
1813 /* Wait for command completion. */
1814 ret_cmd = false;
1815 ratov_j = ha->r_a_tov / 10 * 4;
1816 ratov_j = secs_to_jiffies(ratov_j);
1817 switch (rval) {
1818 case QLA_SUCCESS:
1819 if (wait_for_completion_timeout(&comp, ratov_j)) {
1820 ql_dbg(ql_dbg_taskm, vha, 0xffff,
1821 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1822 __func__, ha->r_a_tov/10);
1823 ret_cmd = true;
1824 }
1825 /* else FW return SP to driver */
1826 break;
1827 default:
1828 ret_cmd = true;
1829 break;
1830 }
1831
1832 spin_lock_irqsave(qp->qp_lock_ptr, *flags);
1833 switch (sp->type) {
1834 case SRB_SCSI_CMD:
1835 if (ret_cmd && blk_mq_request_started(scsi_cmd_to_rq(cmd)))
1836 sp->done(sp, res);
1837 break;
1838 default:
1839 if (ret_cmd)
1840 sp->done(sp, res);
1841 break;
1842 }
1843 } else {
1844 sp->done(sp, res);
1845 }
1846 }
1847
1848 /*
1849 * The caller must ensure that no completion interrupts will happen
1850 * while this function is in progress.
1851 */
1852 static void
__qla2x00_abort_all_cmds(struct qla_qpair * qp,int res)1853 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res)
1854 {
1855 int cnt;
1856 unsigned long flags;
1857 srb_t *sp;
1858 scsi_qla_host_t *vha = qp->vha;
1859 struct qla_hw_data *ha = vha->hw;
1860 struct req_que *req;
1861 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1862 struct qla_tgt_cmd *cmd;
1863
1864 if (!ha->req_q_map)
1865 return;
1866 spin_lock_irqsave(qp->qp_lock_ptr, flags);
1867 req = qp->req;
1868 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1869 sp = req->outstanding_cmds[cnt];
1870 if (sp) {
1871 switch (sp->cmd_type) {
1872 case TYPE_SRB:
1873 qla2x00_abort_srb(qp, sp, res, &flags);
1874 break;
1875 case TYPE_TGT_CMD:
1876 if (!vha->hw->tgt.tgt_ops || !tgt ||
1877 qla_ini_mode_enabled(vha)) {
1878 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003,
1879 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1880 vha->dpc_flags);
1881 continue;
1882 }
1883 cmd = (struct qla_tgt_cmd *)sp;
1884
1885 if (cmd->sg_mapped)
1886 qlt_unmap_sg(vha, cmd);
1887
1888 if (cmd->state == QLA_TGT_STATE_NEED_DATA) {
1889 cmd->aborted = 1;
1890 cmd->write_data_transferred = 0;
1891 cmd->state = QLA_TGT_STATE_DATA_IN;
1892 ha->tgt.tgt_ops->handle_data(cmd);
1893 } else {
1894 ha->tgt.tgt_ops->free_cmd(cmd);
1895 }
1896 break;
1897 case TYPE_TGT_TMCMD:
1898 /*
1899 * Currently, only ABTS response gets on the
1900 * outstanding_cmds[]
1901 */
1902 qlt_free_ul_mcmd(ha,
1903 (struct qla_tgt_mgmt_cmd *) sp);
1904 break;
1905 default:
1906 break;
1907 }
1908 req->outstanding_cmds[cnt] = NULL;
1909 }
1910 }
1911 spin_unlock_irqrestore(qp->qp_lock_ptr, flags);
1912 }
1913
1914 /*
1915 * The caller must ensure that no completion interrupts will happen
1916 * while this function is in progress.
1917 */
1918 void
qla2x00_abort_all_cmds(scsi_qla_host_t * vha,int res)1919 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1920 {
1921 int que;
1922 struct qla_hw_data *ha = vha->hw;
1923
1924 /* Continue only if initialization complete. */
1925 if (!ha->base_qpair)
1926 return;
1927 __qla2x00_abort_all_cmds(ha->base_qpair, res);
1928
1929 if (!ha->queue_pair_map)
1930 return;
1931 for (que = 0; que < ha->max_qpairs; que++) {
1932 if (!ha->queue_pair_map[que])
1933 continue;
1934
1935 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res);
1936 }
1937 }
1938
1939 static int
qla2xxx_sdev_init(struct scsi_device * sdev)1940 qla2xxx_sdev_init(struct scsi_device *sdev)
1941 {
1942 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1943
1944 if (!rport || fc_remote_port_chkready(rport))
1945 return -ENXIO;
1946
1947 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1948
1949 return 0;
1950 }
1951
1952 static int
qla2xxx_sdev_configure(struct scsi_device * sdev,struct queue_limits * lim)1953 qla2xxx_sdev_configure(struct scsi_device *sdev, struct queue_limits *lim)
1954 {
1955 scsi_qla_host_t *vha = shost_priv(sdev->host);
1956 struct req_que *req = vha->req;
1957
1958 scsi_change_queue_depth(sdev, req->max_q_depth);
1959 return 0;
1960 }
1961
1962 static void
qla2xxx_sdev_destroy(struct scsi_device * sdev)1963 qla2xxx_sdev_destroy(struct scsi_device *sdev)
1964 {
1965 sdev->hostdata = NULL;
1966 }
1967
1968 /**
1969 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1970 * @ha: HA context
1971 *
1972 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1973 * supported addressing method.
1974 */
1975 static void
qla2x00_config_dma_addressing(struct qla_hw_data * ha)1976 qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1977 {
1978 /* Assume a 32bit DMA mask. */
1979 ha->flags.enable_64bit_addressing = 0;
1980
1981 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1982 /* Any upper-dword bits set? */
1983 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
1984 !dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1985 /* Ok, a 64bit DMA mask is applicable. */
1986 ha->flags.enable_64bit_addressing = 1;
1987 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1988 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
1989 return;
1990 }
1991 }
1992
1993 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1994 dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1995 }
1996
1997 static void
qla2x00_enable_intrs(struct qla_hw_data * ha)1998 qla2x00_enable_intrs(struct qla_hw_data *ha)
1999 {
2000 unsigned long flags = 0;
2001 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2002
2003 spin_lock_irqsave(&ha->hardware_lock, flags);
2004 ha->interrupts_on = 1;
2005 /* enable risc and host interrupts */
2006 wrt_reg_word(®->ictrl, ICR_EN_INT | ICR_EN_RISC);
2007 rd_reg_word(®->ictrl);
2008 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2009
2010 }
2011
2012 static void
qla2x00_disable_intrs(struct qla_hw_data * ha)2013 qla2x00_disable_intrs(struct qla_hw_data *ha)
2014 {
2015 unsigned long flags = 0;
2016 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2017
2018 spin_lock_irqsave(&ha->hardware_lock, flags);
2019 ha->interrupts_on = 0;
2020 /* disable risc and host interrupts */
2021 wrt_reg_word(®->ictrl, 0);
2022 rd_reg_word(®->ictrl);
2023 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2024 }
2025
2026 static void
qla24xx_enable_intrs(struct qla_hw_data * ha)2027 qla24xx_enable_intrs(struct qla_hw_data *ha)
2028 {
2029 unsigned long flags = 0;
2030 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2031
2032 spin_lock_irqsave(&ha->hardware_lock, flags);
2033 ha->interrupts_on = 1;
2034 wrt_reg_dword(®->ictrl, ICRX_EN_RISC_INT);
2035 rd_reg_dword(®->ictrl);
2036 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2037 }
2038
2039 static void
qla24xx_disable_intrs(struct qla_hw_data * ha)2040 qla24xx_disable_intrs(struct qla_hw_data *ha)
2041 {
2042 unsigned long flags = 0;
2043 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2044
2045 if (IS_NOPOLLING_TYPE(ha))
2046 return;
2047 spin_lock_irqsave(&ha->hardware_lock, flags);
2048 ha->interrupts_on = 0;
2049 wrt_reg_dword(®->ictrl, 0);
2050 rd_reg_dword(®->ictrl);
2051 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2052 }
2053
2054 static int
qla2x00_iospace_config(struct qla_hw_data * ha)2055 qla2x00_iospace_config(struct qla_hw_data *ha)
2056 {
2057 resource_size_t pio;
2058 uint16_t msix;
2059
2060 if (pci_request_selected_regions(ha->pdev, ha->bars,
2061 QLA2XXX_DRIVER_NAME)) {
2062 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
2063 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2064 pci_name(ha->pdev));
2065 goto iospace_error_exit;
2066 }
2067 if (!(ha->bars & 1))
2068 goto skip_pio;
2069
2070 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
2071 pio = pci_resource_start(ha->pdev, 0);
2072 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
2073 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2074 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
2075 "Invalid pci I/O region size (%s).\n",
2076 pci_name(ha->pdev));
2077 pio = 0;
2078 }
2079 } else {
2080 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
2081 "Region #0 no a PIO resource (%s).\n",
2082 pci_name(ha->pdev));
2083 pio = 0;
2084 }
2085 ha->pio_address = pio;
2086 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
2087 "PIO address=%llu.\n",
2088 (unsigned long long)ha->pio_address);
2089
2090 skip_pio:
2091 /* Use MMIO operations for all accesses. */
2092 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
2093 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
2094 "Region #1 not an MMIO resource (%s), aborting.\n",
2095 pci_name(ha->pdev));
2096 goto iospace_error_exit;
2097 }
2098 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
2099 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
2100 "Invalid PCI mem region size (%s), aborting.\n",
2101 pci_name(ha->pdev));
2102 goto iospace_error_exit;
2103 }
2104
2105 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
2106 if (!ha->iobase) {
2107 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
2108 "Cannot remap MMIO (%s), aborting.\n",
2109 pci_name(ha->pdev));
2110 goto iospace_error_exit;
2111 }
2112
2113 /* Determine queue resources */
2114 ha->max_req_queues = ha->max_rsp_queues = 1;
2115 ha->msix_count = QLA_BASE_VECTORS;
2116
2117 /* Check if FW supports MQ or not */
2118 if (!(ha->fw_attributes & BIT_6))
2119 goto mqiobase_exit;
2120
2121 if (!ql2xmqsupport || !ql2xnvmeenable ||
2122 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
2123 goto mqiobase_exit;
2124
2125 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
2126 pci_resource_len(ha->pdev, 3));
2127 if (ha->mqiobase) {
2128 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
2129 "MQIO Base=%p.\n", ha->mqiobase);
2130 /* Read MSIX vector size of the board */
2131 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
2132 ha->msix_count = msix + 1;
2133 /* Max queues are bounded by available msix vectors */
2134 /* MB interrupt uses 1 vector */
2135 ha->max_req_queues = qla_calc_queue_count(ha->msix_count);
2136 ha->max_rsp_queues = ha->max_req_queues;
2137 /* Queue pairs is the max value minus the base queue pair */
2138 ha->max_qpairs = ha->max_rsp_queues - 1;
2139 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
2140 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2141
2142 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
2143 "MSI-X vector count: %d.\n", ha->msix_count);
2144 } else
2145 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
2146 "BAR 3 not enabled.\n");
2147
2148 mqiobase_exit:
2149 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
2150 "MSIX Count: %d.\n", ha->msix_count);
2151 return (0);
2152
2153 iospace_error_exit:
2154 return (-ENOMEM);
2155 }
2156
2157
2158 static int
qla83xx_iospace_config(struct qla_hw_data * ha)2159 qla83xx_iospace_config(struct qla_hw_data *ha)
2160 {
2161 if (pci_request_selected_regions(ha->pdev, ha->bars,
2162 QLA2XXX_DRIVER_NAME)) {
2163 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2164 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2165 pci_name(ha->pdev));
2166
2167 goto iospace_error_exit;
2168 }
2169
2170 /* Use MMIO operations for all accesses. */
2171 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2172 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2173 "Invalid pci I/O region size (%s).\n",
2174 pci_name(ha->pdev));
2175 goto iospace_error_exit;
2176 }
2177 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2178 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2179 "Invalid PCI mem region size (%s), aborting\n",
2180 pci_name(ha->pdev));
2181 goto iospace_error_exit;
2182 }
2183
2184 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2185 if (!ha->iobase) {
2186 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2187 "Cannot remap MMIO (%s), aborting.\n",
2188 pci_name(ha->pdev));
2189 goto iospace_error_exit;
2190 }
2191
2192 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2193 /* 83XX 26XX always use MQ type access for queues
2194 * - mbar 2, a.k.a region 4 */
2195 ha->max_req_queues = ha->max_rsp_queues = 1;
2196 ha->msix_count = QLA_BASE_VECTORS;
2197 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2198 pci_resource_len(ha->pdev, 4));
2199
2200 if (!ha->mqiobase) {
2201 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2202 "BAR2/region4 not enabled\n");
2203 goto mqiobase_exit;
2204 }
2205
2206 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2207 pci_resource_len(ha->pdev, 2));
2208 if (ha->msixbase) {
2209 int msix_cnt;
2210
2211 /* Read MSIX vector size of the board */
2212 msix_cnt = pci_msix_vec_count(ha->pdev);
2213 if (msix_cnt <= 0) {
2214 ql_log_pci(ql_log_warn, ha->pdev, 0x0120,
2215 "Failed to read MSI-X count (%d), falling back to base vectors.\n",
2216 msix_cnt);
2217 goto mqiobase_exit;
2218 }
2219 ha->msix_count = msix_cnt;
2220
2221 /*
2222 * By default, driver uses at least two msix vectors
2223 * (default & rspq)
2224 */
2225 if (ql2xmqsupport || ql2xnvmeenable) {
2226 /* MB interrupt uses 1 vector */
2227 ha->max_req_queues = qla_calc_queue_count(ha->msix_count);
2228
2229 /* ATIOQ needs 1 vector. That's 1 less QPair */
2230 if (QLA_TGT_MODE_ENABLED() && ha->max_req_queues > 1)
2231 ha->max_req_queues--;
2232
2233 ha->max_rsp_queues = ha->max_req_queues;
2234
2235 /* Queue pairs is the max value minus
2236 * the base queue pair */
2237 ha->max_qpairs = ha->max_req_queues - 1;
2238 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
2239 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2240 }
2241 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
2242 "MSI-X vector count: %d.\n", ha->msix_count);
2243 } else
2244 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2245 "BAR 1 not enabled.\n");
2246
2247 mqiobase_exit:
2248 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
2249 "MSIX Count: %d.\n", ha->msix_count);
2250 return 0;
2251
2252 iospace_error_exit:
2253 return -ENOMEM;
2254 }
2255
2256 static struct isp_operations qla2100_isp_ops = {
2257 .pci_config = qla2100_pci_config,
2258 .reset_chip = qla2x00_reset_chip,
2259 .chip_diag = qla2x00_chip_diag,
2260 .config_rings = qla2x00_config_rings,
2261 .reset_adapter = qla2x00_reset_adapter,
2262 .nvram_config = qla2x00_nvram_config,
2263 .update_fw_options = qla2x00_update_fw_options,
2264 .load_risc = qla2x00_load_risc,
2265 .pci_info_str = qla2x00_pci_info_str,
2266 .fw_version_str = qla2x00_fw_version_str,
2267 .intr_handler = qla2100_intr_handler,
2268 .enable_intrs = qla2x00_enable_intrs,
2269 .disable_intrs = qla2x00_disable_intrs,
2270 .abort_command = qla2x00_abort_command,
2271 .target_reset = qla2x00_abort_target,
2272 .lun_reset = qla2x00_lun_reset,
2273 .fabric_login = qla2x00_login_fabric,
2274 .fabric_logout = qla2x00_fabric_logout,
2275 .calc_req_entries = qla2x00_calc_iocbs_32,
2276 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2277 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2278 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2279 .read_nvram = qla2x00_read_nvram_data,
2280 .write_nvram = qla2x00_write_nvram_data,
2281 .fw_dump = qla2100_fw_dump,
2282 .beacon_on = NULL,
2283 .beacon_off = NULL,
2284 .beacon_blink = NULL,
2285 .read_optrom = qla2x00_read_optrom_data,
2286 .write_optrom = qla2x00_write_optrom_data,
2287 .get_flash_version = qla2x00_get_flash_version,
2288 .start_scsi = qla2x00_start_scsi,
2289 .start_scsi_mq = NULL,
2290 .abort_isp = qla2x00_abort_isp,
2291 .iospace_config = qla2x00_iospace_config,
2292 .initialize_adapter = qla2x00_initialize_adapter,
2293 };
2294
2295 static struct isp_operations qla2300_isp_ops = {
2296 .pci_config = qla2300_pci_config,
2297 .reset_chip = qla2x00_reset_chip,
2298 .chip_diag = qla2x00_chip_diag,
2299 .config_rings = qla2x00_config_rings,
2300 .reset_adapter = qla2x00_reset_adapter,
2301 .nvram_config = qla2x00_nvram_config,
2302 .update_fw_options = qla2x00_update_fw_options,
2303 .load_risc = qla2x00_load_risc,
2304 .pci_info_str = qla2x00_pci_info_str,
2305 .fw_version_str = qla2x00_fw_version_str,
2306 .intr_handler = qla2300_intr_handler,
2307 .enable_intrs = qla2x00_enable_intrs,
2308 .disable_intrs = qla2x00_disable_intrs,
2309 .abort_command = qla2x00_abort_command,
2310 .target_reset = qla2x00_abort_target,
2311 .lun_reset = qla2x00_lun_reset,
2312 .fabric_login = qla2x00_login_fabric,
2313 .fabric_logout = qla2x00_fabric_logout,
2314 .calc_req_entries = qla2x00_calc_iocbs_32,
2315 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2316 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2317 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2318 .read_nvram = qla2x00_read_nvram_data,
2319 .write_nvram = qla2x00_write_nvram_data,
2320 .fw_dump = qla2300_fw_dump,
2321 .beacon_on = qla2x00_beacon_on,
2322 .beacon_off = qla2x00_beacon_off,
2323 .beacon_blink = qla2x00_beacon_blink,
2324 .read_optrom = qla2x00_read_optrom_data,
2325 .write_optrom = qla2x00_write_optrom_data,
2326 .get_flash_version = qla2x00_get_flash_version,
2327 .start_scsi = qla2x00_start_scsi,
2328 .start_scsi_mq = NULL,
2329 .abort_isp = qla2x00_abort_isp,
2330 .iospace_config = qla2x00_iospace_config,
2331 .initialize_adapter = qla2x00_initialize_adapter,
2332 };
2333
2334 static struct isp_operations qla24xx_isp_ops = {
2335 .pci_config = qla24xx_pci_config,
2336 .reset_chip = qla24xx_reset_chip,
2337 .chip_diag = qla24xx_chip_diag,
2338 .config_rings = qla24xx_config_rings,
2339 .reset_adapter = qla24xx_reset_adapter,
2340 .nvram_config = qla24xx_nvram_config,
2341 .update_fw_options = qla24xx_update_fw_options,
2342 .load_risc = qla24xx_load_risc,
2343 .pci_info_str = qla24xx_pci_info_str,
2344 .fw_version_str = qla24xx_fw_version_str,
2345 .intr_handler = qla24xx_intr_handler,
2346 .enable_intrs = qla24xx_enable_intrs,
2347 .disable_intrs = qla24xx_disable_intrs,
2348 .abort_command = qla24xx_abort_command,
2349 .target_reset = qla24xx_abort_target,
2350 .lun_reset = qla24xx_lun_reset,
2351 .fabric_login = qla24xx_login_fabric,
2352 .fabric_logout = qla24xx_fabric_logout,
2353 .calc_req_entries = NULL,
2354 .build_iocbs = NULL,
2355 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2356 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2357 .read_nvram = qla24xx_read_nvram_data,
2358 .write_nvram = qla24xx_write_nvram_data,
2359 .fw_dump = qla24xx_fw_dump,
2360 .beacon_on = qla24xx_beacon_on,
2361 .beacon_off = qla24xx_beacon_off,
2362 .beacon_blink = qla24xx_beacon_blink,
2363 .read_optrom = qla24xx_read_optrom_data,
2364 .write_optrom = qla24xx_write_optrom_data,
2365 .get_flash_version = qla24xx_get_flash_version,
2366 .start_scsi = qla24xx_start_scsi,
2367 .start_scsi_mq = NULL,
2368 .abort_isp = qla2x00_abort_isp,
2369 .iospace_config = qla2x00_iospace_config,
2370 .initialize_adapter = qla2x00_initialize_adapter,
2371 };
2372
2373 static struct isp_operations qla25xx_isp_ops = {
2374 .pci_config = qla25xx_pci_config,
2375 .reset_chip = qla24xx_reset_chip,
2376 .chip_diag = qla24xx_chip_diag,
2377 .config_rings = qla24xx_config_rings,
2378 .reset_adapter = qla24xx_reset_adapter,
2379 .nvram_config = qla24xx_nvram_config,
2380 .update_fw_options = qla24xx_update_fw_options,
2381 .load_risc = qla24xx_load_risc,
2382 .pci_info_str = qla24xx_pci_info_str,
2383 .fw_version_str = qla24xx_fw_version_str,
2384 .intr_handler = qla24xx_intr_handler,
2385 .enable_intrs = qla24xx_enable_intrs,
2386 .disable_intrs = qla24xx_disable_intrs,
2387 .abort_command = qla24xx_abort_command,
2388 .target_reset = qla24xx_abort_target,
2389 .lun_reset = qla24xx_lun_reset,
2390 .fabric_login = qla24xx_login_fabric,
2391 .fabric_logout = qla24xx_fabric_logout,
2392 .calc_req_entries = NULL,
2393 .build_iocbs = NULL,
2394 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2395 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2396 .read_nvram = qla25xx_read_nvram_data,
2397 .write_nvram = qla25xx_write_nvram_data,
2398 .fw_dump = qla25xx_fw_dump,
2399 .beacon_on = qla24xx_beacon_on,
2400 .beacon_off = qla24xx_beacon_off,
2401 .beacon_blink = qla24xx_beacon_blink,
2402 .read_optrom = qla25xx_read_optrom_data,
2403 .write_optrom = qla24xx_write_optrom_data,
2404 .get_flash_version = qla24xx_get_flash_version,
2405 .start_scsi = qla24xx_dif_start_scsi,
2406 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2407 .abort_isp = qla2x00_abort_isp,
2408 .iospace_config = qla2x00_iospace_config,
2409 .initialize_adapter = qla2x00_initialize_adapter,
2410 };
2411
2412 static struct isp_operations qla81xx_isp_ops = {
2413 .pci_config = qla25xx_pci_config,
2414 .reset_chip = qla24xx_reset_chip,
2415 .chip_diag = qla24xx_chip_diag,
2416 .config_rings = qla24xx_config_rings,
2417 .reset_adapter = qla24xx_reset_adapter,
2418 .nvram_config = qla81xx_nvram_config,
2419 .update_fw_options = qla24xx_update_fw_options,
2420 .load_risc = qla81xx_load_risc,
2421 .pci_info_str = qla24xx_pci_info_str,
2422 .fw_version_str = qla24xx_fw_version_str,
2423 .intr_handler = qla24xx_intr_handler,
2424 .enable_intrs = qla24xx_enable_intrs,
2425 .disable_intrs = qla24xx_disable_intrs,
2426 .abort_command = qla24xx_abort_command,
2427 .target_reset = qla24xx_abort_target,
2428 .lun_reset = qla24xx_lun_reset,
2429 .fabric_login = qla24xx_login_fabric,
2430 .fabric_logout = qla24xx_fabric_logout,
2431 .calc_req_entries = NULL,
2432 .build_iocbs = NULL,
2433 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2434 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2435 .read_nvram = NULL,
2436 .write_nvram = NULL,
2437 .fw_dump = qla81xx_fw_dump,
2438 .beacon_on = qla24xx_beacon_on,
2439 .beacon_off = qla24xx_beacon_off,
2440 .beacon_blink = qla83xx_beacon_blink,
2441 .read_optrom = qla25xx_read_optrom_data,
2442 .write_optrom = qla24xx_write_optrom_data,
2443 .get_flash_version = qla24xx_get_flash_version,
2444 .start_scsi = qla24xx_dif_start_scsi,
2445 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2446 .abort_isp = qla2x00_abort_isp,
2447 .iospace_config = qla2x00_iospace_config,
2448 .initialize_adapter = qla2x00_initialize_adapter,
2449 };
2450
2451 static struct isp_operations qla82xx_isp_ops = {
2452 .pci_config = qla82xx_pci_config,
2453 .reset_chip = qla82xx_reset_chip,
2454 .chip_diag = qla24xx_chip_diag,
2455 .config_rings = qla82xx_config_rings,
2456 .reset_adapter = qla24xx_reset_adapter,
2457 .nvram_config = qla81xx_nvram_config,
2458 .update_fw_options = qla24xx_update_fw_options,
2459 .load_risc = qla82xx_load_risc,
2460 .pci_info_str = qla24xx_pci_info_str,
2461 .fw_version_str = qla24xx_fw_version_str,
2462 .intr_handler = qla82xx_intr_handler,
2463 .enable_intrs = qla82xx_enable_intrs,
2464 .disable_intrs = qla82xx_disable_intrs,
2465 .abort_command = qla24xx_abort_command,
2466 .target_reset = qla24xx_abort_target,
2467 .lun_reset = qla24xx_lun_reset,
2468 .fabric_login = qla24xx_login_fabric,
2469 .fabric_logout = qla24xx_fabric_logout,
2470 .calc_req_entries = NULL,
2471 .build_iocbs = NULL,
2472 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2473 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2474 .read_nvram = qla24xx_read_nvram_data,
2475 .write_nvram = qla24xx_write_nvram_data,
2476 .fw_dump = qla82xx_fw_dump,
2477 .beacon_on = qla82xx_beacon_on,
2478 .beacon_off = qla82xx_beacon_off,
2479 .beacon_blink = NULL,
2480 .read_optrom = qla82xx_read_optrom_data,
2481 .write_optrom = qla82xx_write_optrom_data,
2482 .get_flash_version = qla82xx_get_flash_version,
2483 .start_scsi = qla82xx_start_scsi,
2484 .start_scsi_mq = NULL,
2485 .abort_isp = qla82xx_abort_isp,
2486 .iospace_config = qla82xx_iospace_config,
2487 .initialize_adapter = qla2x00_initialize_adapter,
2488 };
2489
2490 static struct isp_operations qla8044_isp_ops = {
2491 .pci_config = qla82xx_pci_config,
2492 .reset_chip = qla82xx_reset_chip,
2493 .chip_diag = qla24xx_chip_diag,
2494 .config_rings = qla82xx_config_rings,
2495 .reset_adapter = qla24xx_reset_adapter,
2496 .nvram_config = qla81xx_nvram_config,
2497 .update_fw_options = qla24xx_update_fw_options,
2498 .load_risc = qla82xx_load_risc,
2499 .pci_info_str = qla24xx_pci_info_str,
2500 .fw_version_str = qla24xx_fw_version_str,
2501 .intr_handler = qla8044_intr_handler,
2502 .enable_intrs = qla82xx_enable_intrs,
2503 .disable_intrs = qla82xx_disable_intrs,
2504 .abort_command = qla24xx_abort_command,
2505 .target_reset = qla24xx_abort_target,
2506 .lun_reset = qla24xx_lun_reset,
2507 .fabric_login = qla24xx_login_fabric,
2508 .fabric_logout = qla24xx_fabric_logout,
2509 .calc_req_entries = NULL,
2510 .build_iocbs = NULL,
2511 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2512 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2513 .read_nvram = NULL,
2514 .write_nvram = NULL,
2515 .fw_dump = qla8044_fw_dump,
2516 .beacon_on = qla82xx_beacon_on,
2517 .beacon_off = qla82xx_beacon_off,
2518 .beacon_blink = NULL,
2519 .read_optrom = qla8044_read_optrom_data,
2520 .write_optrom = qla8044_write_optrom_data,
2521 .get_flash_version = qla82xx_get_flash_version,
2522 .start_scsi = qla82xx_start_scsi,
2523 .start_scsi_mq = NULL,
2524 .abort_isp = qla8044_abort_isp,
2525 .iospace_config = qla82xx_iospace_config,
2526 .initialize_adapter = qla2x00_initialize_adapter,
2527 };
2528
2529 static struct isp_operations qla83xx_isp_ops = {
2530 .pci_config = qla25xx_pci_config,
2531 .reset_chip = qla24xx_reset_chip,
2532 .chip_diag = qla24xx_chip_diag,
2533 .config_rings = qla24xx_config_rings,
2534 .reset_adapter = qla24xx_reset_adapter,
2535 .nvram_config = qla81xx_nvram_config,
2536 .update_fw_options = qla24xx_update_fw_options,
2537 .load_risc = qla81xx_load_risc,
2538 .pci_info_str = qla24xx_pci_info_str,
2539 .fw_version_str = qla24xx_fw_version_str,
2540 .intr_handler = qla24xx_intr_handler,
2541 .enable_intrs = qla24xx_enable_intrs,
2542 .disable_intrs = qla24xx_disable_intrs,
2543 .abort_command = qla24xx_abort_command,
2544 .target_reset = qla24xx_abort_target,
2545 .lun_reset = qla24xx_lun_reset,
2546 .fabric_login = qla24xx_login_fabric,
2547 .fabric_logout = qla24xx_fabric_logout,
2548 .calc_req_entries = NULL,
2549 .build_iocbs = NULL,
2550 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2551 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2552 .read_nvram = NULL,
2553 .write_nvram = NULL,
2554 .fw_dump = qla83xx_fw_dump,
2555 .beacon_on = qla24xx_beacon_on,
2556 .beacon_off = qla24xx_beacon_off,
2557 .beacon_blink = qla83xx_beacon_blink,
2558 .read_optrom = qla25xx_read_optrom_data,
2559 .write_optrom = qla24xx_write_optrom_data,
2560 .get_flash_version = qla24xx_get_flash_version,
2561 .start_scsi = qla24xx_dif_start_scsi,
2562 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2563 .abort_isp = qla2x00_abort_isp,
2564 .iospace_config = qla83xx_iospace_config,
2565 .initialize_adapter = qla2x00_initialize_adapter,
2566 };
2567
2568 static struct isp_operations qlafx00_isp_ops = {
2569 .pci_config = qlafx00_pci_config,
2570 .reset_chip = qlafx00_soft_reset,
2571 .chip_diag = qlafx00_chip_diag,
2572 .config_rings = qlafx00_config_rings,
2573 .reset_adapter = qlafx00_soft_reset,
2574 .nvram_config = NULL,
2575 .update_fw_options = NULL,
2576 .load_risc = NULL,
2577 .pci_info_str = qlafx00_pci_info_str,
2578 .fw_version_str = qlafx00_fw_version_str,
2579 .intr_handler = qlafx00_intr_handler,
2580 .enable_intrs = qlafx00_enable_intrs,
2581 .disable_intrs = qlafx00_disable_intrs,
2582 .abort_command = qla24xx_async_abort_command,
2583 .target_reset = qlafx00_abort_target,
2584 .lun_reset = qlafx00_lun_reset,
2585 .fabric_login = NULL,
2586 .fabric_logout = NULL,
2587 .calc_req_entries = NULL,
2588 .build_iocbs = NULL,
2589 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2590 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2591 .read_nvram = qla24xx_read_nvram_data,
2592 .write_nvram = qla24xx_write_nvram_data,
2593 .fw_dump = NULL,
2594 .beacon_on = qla24xx_beacon_on,
2595 .beacon_off = qla24xx_beacon_off,
2596 .beacon_blink = NULL,
2597 .read_optrom = qla24xx_read_optrom_data,
2598 .write_optrom = qla24xx_write_optrom_data,
2599 .get_flash_version = qla24xx_get_flash_version,
2600 .start_scsi = qlafx00_start_scsi,
2601 .start_scsi_mq = NULL,
2602 .abort_isp = qlafx00_abort_isp,
2603 .iospace_config = qlafx00_iospace_config,
2604 .initialize_adapter = qlafx00_initialize_adapter,
2605 };
2606
2607 static struct isp_operations qla27xx_isp_ops = {
2608 .pci_config = qla25xx_pci_config,
2609 .reset_chip = qla24xx_reset_chip,
2610 .chip_diag = qla24xx_chip_diag,
2611 .config_rings = qla24xx_config_rings,
2612 .reset_adapter = qla24xx_reset_adapter,
2613 .nvram_config = qla81xx_nvram_config,
2614 .update_fw_options = qla24xx_update_fw_options,
2615 .load_risc = qla81xx_load_risc,
2616 .pci_info_str = qla24xx_pci_info_str,
2617 .fw_version_str = qla24xx_fw_version_str,
2618 .intr_handler = qla24xx_intr_handler,
2619 .enable_intrs = qla24xx_enable_intrs,
2620 .disable_intrs = qla24xx_disable_intrs,
2621 .abort_command = qla24xx_abort_command,
2622 .target_reset = qla24xx_abort_target,
2623 .lun_reset = qla24xx_lun_reset,
2624 .fabric_login = qla24xx_login_fabric,
2625 .fabric_logout = qla24xx_fabric_logout,
2626 .calc_req_entries = NULL,
2627 .build_iocbs = NULL,
2628 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2629 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2630 .read_nvram = NULL,
2631 .write_nvram = NULL,
2632 .fw_dump = qla27xx_fwdump,
2633 .mpi_fw_dump = qla27xx_mpi_fwdump,
2634 .beacon_on = qla24xx_beacon_on,
2635 .beacon_off = qla24xx_beacon_off,
2636 .beacon_blink = qla83xx_beacon_blink,
2637 .read_optrom = qla25xx_read_optrom_data,
2638 .write_optrom = qla24xx_write_optrom_data,
2639 .get_flash_version = qla24xx_get_flash_version,
2640 .start_scsi = qla24xx_dif_start_scsi,
2641 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2642 .abort_isp = qla2x00_abort_isp,
2643 .iospace_config = qla83xx_iospace_config,
2644 .initialize_adapter = qla2x00_initialize_adapter,
2645 };
2646
2647 static void *
qla29xx_read_optrom_stub(struct scsi_qla_host * vha,void * buf,uint32_t offset,uint32_t length)2648 qla29xx_read_optrom_stub(struct scsi_qla_host *vha, void *buf,
2649 uint32_t offset, uint32_t length)
2650 {
2651 ql_dbg(ql_dbg_init, vha, 0x0191,
2652 "read_optrom not supported on 29xx, use read_optrom_region.\n");
2653 return NULL;
2654 }
2655
2656 static int
qla29xx_write_optrom_stub(struct scsi_qla_host * vha,void * buf,uint32_t offset,uint32_t length)2657 qla29xx_write_optrom_stub(struct scsi_qla_host *vha, void *buf,
2658 uint32_t offset, uint32_t length)
2659 {
2660 ql_dbg(ql_dbg_init, vha, 0x0192,
2661 "write_optrom not supported on 29xx, use write_optrom_region.\n");
2662 return QLA_FUNCTION_FAILED;
2663 }
2664
2665 static struct isp_operations qla29xx_isp_ops = {
2666 .pci_config = qla25xx_pci_config,
2667 .reset_chip = qla24xx_reset_chip,
2668 .chip_diag = qla24xx_chip_diag,
2669 .config_rings = qla24xx_config_rings,
2670 .reset_adapter = qla24xx_reset_adapter,
2671 .nvram_config = qla81xx_nvram_config,
2672 .update_fw_options = qla24xx_update_fw_options,
2673 .load_risc = qla29xx_load_risc,
2674 .pci_info_str = qla24xx_pci_info_str,
2675 .fw_version_str = qla24xx_fw_version_str,
2676 .intr_handler = qla24xx_intr_handler,
2677 .enable_intrs = qla24xx_enable_intrs,
2678 .disable_intrs = qla24xx_disable_intrs,
2679 .abort_command = qla24xx_abort_command,
2680 .target_reset = qla24xx_abort_target,
2681 .lun_reset = qla24xx_lun_reset,
2682 .fabric_login = qla24xx_login_fabric,
2683 .fabric_logout = qla24xx_fabric_logout,
2684 .calc_req_entries = NULL,
2685 .build_iocbs = NULL,
2686 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2687 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2688 .read_nvram = NULL,
2689 .write_nvram = NULL,
2690 .fw_dump = qla27xx_fwdump,
2691 .mpi_fw_dump = qla27xx_mpi_fwdump,
2692 .beacon_on = qla24xx_beacon_on,
2693 .beacon_off = qla24xx_beacon_off,
2694 .beacon_blink = qla83xx_beacon_blink,
2695 .read_optrom = qla29xx_read_optrom_stub,
2696 .write_optrom = qla29xx_write_optrom_stub,
2697 .read_optrom_region = qla29xx_read_optrom_data,
2698 .write_optrom_region = qla29xx_write_optrom_data,
2699 .get_flash_version = qla24xx_get_flash_version,
2700 .start_scsi = qla24xx_dif_start_scsi,
2701 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2702 .abort_isp = qla2x00_abort_isp,
2703 .iospace_config = qla83xx_iospace_config,
2704 .initialize_adapter = qla2x00_initialize_adapter,
2705 };
2706
2707 static inline void
qla2x00_set_isp_flags(struct qla_hw_data * ha)2708 qla2x00_set_isp_flags(struct qla_hw_data *ha)
2709 {
2710 ha->device_type = DT_EXTENDED_IDS;
2711 switch (ha->pdev->device) {
2712 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2713 ha->isp_type |= DT_ISP2100;
2714 ha->device_type &= ~DT_EXTENDED_IDS;
2715 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2716 break;
2717 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2718 ha->isp_type |= DT_ISP2200;
2719 ha->device_type &= ~DT_EXTENDED_IDS;
2720 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2721 break;
2722 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2723 ha->isp_type |= DT_ISP2300;
2724 ha->device_type |= DT_ZIO_SUPPORTED;
2725 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2726 break;
2727 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2728 ha->isp_type |= DT_ISP2312;
2729 ha->device_type |= DT_ZIO_SUPPORTED;
2730 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2731 break;
2732 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2733 ha->isp_type |= DT_ISP2322;
2734 ha->device_type |= DT_ZIO_SUPPORTED;
2735 if (ha->pdev->subsystem_vendor == 0x1028 &&
2736 ha->pdev->subsystem_device == 0x0170)
2737 ha->device_type |= DT_OEM_001;
2738 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2739 break;
2740 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2741 ha->isp_type |= DT_ISP6312;
2742 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2743 break;
2744 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2745 ha->isp_type |= DT_ISP6322;
2746 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2747 break;
2748 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2749 ha->isp_type |= DT_ISP2422;
2750 ha->device_type |= DT_ZIO_SUPPORTED;
2751 ha->device_type |= DT_FWI2;
2752 ha->device_type |= DT_IIDMA;
2753 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2754 break;
2755 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2756 ha->isp_type |= DT_ISP2432;
2757 ha->device_type |= DT_ZIO_SUPPORTED;
2758 ha->device_type |= DT_FWI2;
2759 ha->device_type |= DT_IIDMA;
2760 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2761 break;
2762 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2763 ha->isp_type |= DT_ISP8432;
2764 ha->device_type |= DT_ZIO_SUPPORTED;
2765 ha->device_type |= DT_FWI2;
2766 ha->device_type |= DT_IIDMA;
2767 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2768 break;
2769 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2770 ha->isp_type |= DT_ISP5422;
2771 ha->device_type |= DT_FWI2;
2772 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2773 break;
2774 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2775 ha->isp_type |= DT_ISP5432;
2776 ha->device_type |= DT_FWI2;
2777 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2778 break;
2779 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2780 ha->isp_type |= DT_ISP2532;
2781 ha->device_type |= DT_ZIO_SUPPORTED;
2782 ha->device_type |= DT_FWI2;
2783 ha->device_type |= DT_IIDMA;
2784 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2785 break;
2786 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2787 ha->isp_type |= DT_ISP8001;
2788 ha->device_type |= DT_ZIO_SUPPORTED;
2789 ha->device_type |= DT_FWI2;
2790 ha->device_type |= DT_IIDMA;
2791 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2792 break;
2793 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2794 ha->isp_type |= DT_ISP8021;
2795 ha->device_type |= DT_ZIO_SUPPORTED;
2796 ha->device_type |= DT_FWI2;
2797 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2798 /* Initialize 82XX ISP flags */
2799 qla82xx_init_flags(ha);
2800 break;
2801 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2802 ha->isp_type |= DT_ISP8044;
2803 ha->device_type |= DT_ZIO_SUPPORTED;
2804 ha->device_type |= DT_FWI2;
2805 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2806 /* Initialize 82XX ISP flags */
2807 qla82xx_init_flags(ha);
2808 break;
2809 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2810 ha->isp_type |= DT_ISP2031;
2811 ha->device_type |= DT_ZIO_SUPPORTED;
2812 ha->device_type |= DT_FWI2;
2813 ha->device_type |= DT_IIDMA;
2814 ha->device_type |= DT_T10_PI;
2815 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2816 break;
2817 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2818 ha->isp_type |= DT_ISP8031;
2819 ha->device_type |= DT_ZIO_SUPPORTED;
2820 ha->device_type |= DT_FWI2;
2821 ha->device_type |= DT_IIDMA;
2822 ha->device_type |= DT_T10_PI;
2823 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2824 break;
2825 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2826 ha->isp_type |= DT_ISPFX00;
2827 break;
2828 case PCI_DEVICE_ID_QLOGIC_ISP2071:
2829 ha->isp_type |= DT_ISP2071;
2830 ha->device_type |= DT_ZIO_SUPPORTED;
2831 ha->device_type |= DT_FWI2;
2832 ha->device_type |= DT_IIDMA;
2833 ha->device_type |= DT_T10_PI;
2834 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2835 break;
2836 case PCI_DEVICE_ID_QLOGIC_ISP2271:
2837 ha->isp_type |= DT_ISP2271;
2838 ha->device_type |= DT_ZIO_SUPPORTED;
2839 ha->device_type |= DT_FWI2;
2840 ha->device_type |= DT_IIDMA;
2841 ha->device_type |= DT_T10_PI;
2842 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2843 break;
2844 case PCI_DEVICE_ID_QLOGIC_ISP2261:
2845 ha->isp_type |= DT_ISP2261;
2846 ha->device_type |= DT_ZIO_SUPPORTED;
2847 ha->device_type |= DT_FWI2;
2848 ha->device_type |= DT_IIDMA;
2849 ha->device_type |= DT_T10_PI;
2850 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2851 break;
2852 case PCI_DEVICE_ID_QLOGIC_ISP2081:
2853 case PCI_DEVICE_ID_QLOGIC_ISP2089:
2854 ha->isp_type |= DT_ISP2081;
2855 ha->device_type |= DT_ZIO_SUPPORTED;
2856 ha->device_type |= DT_FWI2;
2857 ha->device_type |= DT_IIDMA;
2858 ha->device_type |= DT_T10_PI;
2859 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2860 break;
2861 case PCI_DEVICE_ID_QLOGIC_ISP2281:
2862 case PCI_DEVICE_ID_QLOGIC_ISP2289:
2863 ha->isp_type |= DT_ISP2281;
2864 ha->device_type |= DT_ZIO_SUPPORTED;
2865 ha->device_type |= DT_FWI2;
2866 ha->device_type |= DT_IIDMA;
2867 ha->device_type |= DT_T10_PI;
2868 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2869 break;
2870 case PCI_DEVICE_ID_QLOGIC_ISP2099:
2871 case PCI_DEVICE_ID_QLOGIC_ISP2299:
2872 case PCI_DEVICE_ID_QLOGIC_ISP2091:
2873 case PCI_DEVICE_ID_QLOGIC_ISP2291:
2874 ha->isp_type |= DT_ISP2299;
2875 ha->isp_type |= DT_ISP2099;
2876 ha->isp_type |= DT_ISP2091;
2877 ha->isp_type |= DT_ISP2291;
2878 ha->device_type |= DT_ZIO_SUPPORTED;
2879 ha->device_type |= DT_FWI2;
2880 ha->device_type |= DT_IIDMA;
2881 ha->device_type |= DT_T10_PI;
2882 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2883 break;
2884 }
2885
2886 if (IS_QLA82XX(ha))
2887 ha->port_no = ha->portnum & 1;
2888 else {
2889 /* Get adapter physical port no from interrupt pin register. */
2890 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2891 if (ha->port_no == 0) {
2892 /* None of INT[A|B|C|D] may be virtualized by vfio */
2893 ha->port_no = PCI_FUNC(ha->pdev->devfn);
2894 } else if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
2895 IS_QLA28XX(ha) || IS_QLA29XX(ha)) {
2896 ha->port_no--;
2897 } else {
2898 ha->port_no = !(ha->port_no & 1);
2899 }
2900 }
2901
2902 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
2903 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
2904 ha->device_type, ha->port_no, ha->fw_srisc_address);
2905 }
2906
2907 static void
qla2xxx_scan_start(struct Scsi_Host * shost)2908 qla2xxx_scan_start(struct Scsi_Host *shost)
2909 {
2910 scsi_qla_host_t *vha = shost_priv(shost);
2911
2912 if (vha->hw->flags.running_gold_fw)
2913 return;
2914
2915 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2916 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2917 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2918 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
2919 }
2920
2921 static int
qla2xxx_scan_finished(struct Scsi_Host * shost,unsigned long time)2922 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2923 {
2924 scsi_qla_host_t *vha = shost_priv(shost);
2925
2926 if (test_bit(UNLOADING, &vha->dpc_flags))
2927 return 1;
2928 if (!vha->host)
2929 return 1;
2930 if (time > vha->hw->loop_reset_delay * HZ)
2931 return 1;
2932
2933 return atomic_read(&vha->loop_state) == LOOP_READY;
2934 }
2935
qla_heartbeat_work_fn(struct work_struct * work)2936 static void qla_heartbeat_work_fn(struct work_struct *work)
2937 {
2938 struct qla_hw_data *ha = container_of(work,
2939 struct qla_hw_data, heartbeat_work);
2940 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2941
2942 if (!ha->flags.mbox_busy && base_vha->flags.init_done)
2943 qla_no_op_mb(base_vha);
2944 }
2945
qla2x00_iocb_work_fn(struct work_struct * work)2946 static void qla2x00_iocb_work_fn(struct work_struct *work)
2947 {
2948 struct scsi_qla_host *vha = container_of(work,
2949 struct scsi_qla_host, iocb_work);
2950 struct qla_hw_data *ha = vha->hw;
2951 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2952 int i = 2;
2953 unsigned long flags;
2954
2955 if (test_bit(UNLOADING, &base_vha->dpc_flags))
2956 return;
2957
2958 while (!list_empty(&vha->work_list) && i > 0) {
2959 qla2x00_do_work(vha);
2960 i--;
2961 }
2962
2963 spin_lock_irqsave(&vha->work_lock, flags);
2964 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags);
2965 spin_unlock_irqrestore(&vha->work_lock, flags);
2966 }
2967
2968 static void
qla_trace_init(void)2969 qla_trace_init(void)
2970 {
2971 qla_trc_array = trace_array_get_by_name("qla2xxx", NULL);
2972 if (!qla_trc_array) {
2973 ql_log(ql_log_fatal, NULL, 0x0001,
2974 "Unable to create qla2xxx trace instance, instance logging will be disabled.\n");
2975 return;
2976 }
2977
2978 QLA_TRACE_ENABLE(qla_trc_array);
2979 }
2980
2981 static void
qla_trace_uninit(void)2982 qla_trace_uninit(void)
2983 {
2984 if (!qla_trc_array)
2985 return;
2986 trace_array_put(qla_trc_array);
2987 }
2988
2989 /*
2990 * PCI driver interface
2991 */
2992 static int
qla2x00_probe_one(struct pci_dev * pdev,const struct pci_device_id * id)2993 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
2994 {
2995 int ret = -ENODEV;
2996 struct Scsi_Host *host;
2997 scsi_qla_host_t *base_vha = NULL;
2998 struct qla_hw_data *ha;
2999 char pci_info[30];
3000 char fw_str[30], wq_name[30];
3001 struct scsi_host_template *sht;
3002 int bars, mem_only = 0;
3003 uint16_t req_length = 0, rsp_length = 0;
3004 struct req_que *req = NULL;
3005 struct rsp_que *rsp = NULL;
3006 int i;
3007
3008 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
3009 sht = &qla2xxx_driver_template;
3010 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
3011 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
3012 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
3013 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
3014 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3015 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
3016 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
3017 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
3018 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
3019 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
3020 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
3021 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
3022 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
3023 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
3024 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 ||
3025 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 ||
3026 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 ||
3027 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 ||
3028 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289 ||
3029 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2099 ||
3030 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2299 ||
3031 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2091 ||
3032 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2291) {
3033 bars = pci_select_bars(pdev, IORESOURCE_MEM);
3034 mem_only = 1;
3035 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
3036 "Mem only adapter.\n");
3037 }
3038 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
3039 "Bars=%d.\n", bars);
3040
3041 if (mem_only) {
3042 if (pci_enable_device_mem(pdev))
3043 return ret;
3044 } else {
3045 if (pci_enable_device(pdev))
3046 return ret;
3047 }
3048
3049 if (is_kdump_kernel()) {
3050 ql2xmqsupport = 0;
3051 ql2xallocfwdump = 0;
3052 }
3053
3054 ha = kzalloc_obj(struct qla_hw_data);
3055 if (!ha) {
3056 ql_log_pci(ql_log_fatal, pdev, 0x0009,
3057 "Unable to allocate memory for ha.\n");
3058 goto disable_device;
3059 }
3060 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
3061 "Memory allocated for ha=%p.\n", ha);
3062 ha->pdev = pdev;
3063 INIT_LIST_HEAD(&ha->tgt.q_full_list);
3064 spin_lock_init(&ha->tgt.q_full_lock);
3065 spin_lock_init(&ha->tgt.sess_lock);
3066 spin_lock_init(&ha->tgt.atio_lock);
3067
3068 spin_lock_init(&ha->sadb_lock);
3069 INIT_LIST_HEAD(&ha->sadb_tx_index_list);
3070 INIT_LIST_HEAD(&ha->sadb_rx_index_list);
3071
3072 spin_lock_init(&ha->sadb_fp_lock);
3073
3074 if (qla_edif_sadb_build_free_pool(ha)) {
3075 kfree(ha);
3076 goto disable_device;
3077 }
3078
3079 atomic_set(&ha->nvme_active_aen_cnt, 0);
3080
3081 /* Clear our data area */
3082 ha->bars = bars;
3083 ha->mem_only = mem_only;
3084 spin_lock_init(&ha->hardware_lock);
3085 spin_lock_init(&ha->vport_slock);
3086 mutex_init(&ha->selflogin_lock);
3087 mutex_init(&ha->optrom_mutex);
3088
3089 /* Set ISP-type information. */
3090 qla2x00_set_isp_flags(ha);
3091
3092 /* Set EEH reset type to fundamental if required by hba */
3093 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
3094 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha) ||
3095 IS_QLA29XX(ha))
3096 pdev->needs_freset = 1;
3097
3098 ha->prev_topology = 0;
3099 ha->init_cb_size = sizeof(init_cb_t);
3100 ha->link_data_rate = PORT_SPEED_UNKNOWN;
3101 ha->optrom_size = OPTROM_SIZE_2300;
3102 ha->max_exchg = FW_MAX_EXCHANGES_CNT;
3103 atomic_set(&ha->num_pend_mbx_stage1, 0);
3104 atomic_set(&ha->num_pend_mbx_stage2, 0);
3105 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD);
3106 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD;
3107 INIT_LIST_HEAD(&ha->tmf_pending);
3108 INIT_LIST_HEAD(&ha->tmf_active);
3109
3110 /* Assign ISP specific operations. */
3111 if (IS_QLA2100(ha)) {
3112 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
3113 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
3114 req_length = REQUEST_ENTRY_CNT_2100;
3115 rsp_length = RESPONSE_ENTRY_CNT_2100;
3116 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
3117 ha->gid_list_info_size = 4;
3118 ha->flash_conf_off = ~0;
3119 ha->flash_data_off = ~0;
3120 ha->nvram_conf_off = ~0;
3121 ha->nvram_data_off = ~0;
3122 ha->isp_ops = &qla2100_isp_ops;
3123 } else if (IS_QLA2200(ha)) {
3124 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
3125 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
3126 req_length = REQUEST_ENTRY_CNT_2200;
3127 rsp_length = RESPONSE_ENTRY_CNT_2100;
3128 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
3129 ha->gid_list_info_size = 4;
3130 ha->flash_conf_off = ~0;
3131 ha->flash_data_off = ~0;
3132 ha->nvram_conf_off = ~0;
3133 ha->nvram_data_off = ~0;
3134 ha->isp_ops = &qla2100_isp_ops;
3135 } else if (IS_QLA23XX(ha)) {
3136 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
3137 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3138 req_length = REQUEST_ENTRY_CNT_2200;
3139 rsp_length = RESPONSE_ENTRY_CNT_2300;
3140 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3141 ha->gid_list_info_size = 6;
3142 if (IS_QLA2322(ha) || IS_QLA6322(ha))
3143 ha->optrom_size = OPTROM_SIZE_2322;
3144 ha->flash_conf_off = ~0;
3145 ha->flash_data_off = ~0;
3146 ha->nvram_conf_off = ~0;
3147 ha->nvram_data_off = ~0;
3148 ha->isp_ops = &qla2300_isp_ops;
3149 } else if (IS_QLA24XX_TYPE(ha)) {
3150 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3151 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3152 req_length = REQUEST_ENTRY_CNT_24XX;
3153 rsp_length = RESPONSE_ENTRY_CNT_2300;
3154 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3155 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3156 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
3157 ha->gid_list_info_size = 8;
3158 ha->optrom_size = OPTROM_SIZE_24XX;
3159 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
3160 ha->isp_ops = &qla24xx_isp_ops;
3161 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3162 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3163 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3164 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3165 } else if (IS_QLA25XX(ha)) {
3166 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3167 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3168 req_length = REQUEST_ENTRY_CNT_24XX;
3169 rsp_length = RESPONSE_ENTRY_CNT_2300;
3170 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3171 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3172 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
3173 ha->gid_list_info_size = 8;
3174 ha->optrom_size = OPTROM_SIZE_25XX;
3175 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3176 ha->isp_ops = &qla25xx_isp_ops;
3177 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3178 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3179 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3180 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3181 } else if (IS_QLA81XX(ha)) {
3182 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3183 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3184 req_length = REQUEST_ENTRY_CNT_24XX;
3185 rsp_length = RESPONSE_ENTRY_CNT_2300;
3186 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3187 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3188 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3189 ha->gid_list_info_size = 8;
3190 ha->optrom_size = OPTROM_SIZE_81XX;
3191 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3192 ha->isp_ops = &qla81xx_isp_ops;
3193 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3194 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3195 ha->nvram_conf_off = ~0;
3196 ha->nvram_data_off = ~0;
3197 } else if (IS_QLA82XX(ha)) {
3198 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3199 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3200 req_length = REQUEST_ENTRY_CNT_82XX;
3201 rsp_length = RESPONSE_ENTRY_CNT_82XX;
3202 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3203 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3204 ha->gid_list_info_size = 8;
3205 ha->optrom_size = OPTROM_SIZE_82XX;
3206 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3207 ha->isp_ops = &qla82xx_isp_ops;
3208 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3209 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3210 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3211 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3212 } else if (IS_QLA8044(ha)) {
3213 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3214 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3215 req_length = REQUEST_ENTRY_CNT_82XX;
3216 rsp_length = RESPONSE_ENTRY_CNT_82XX;
3217 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3218 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3219 ha->gid_list_info_size = 8;
3220 ha->optrom_size = OPTROM_SIZE_83XX;
3221 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3222 ha->isp_ops = &qla8044_isp_ops;
3223 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3224 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3225 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3226 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3227 } else if (IS_QLA83XX(ha)) {
3228 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3229 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3230 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3231 req_length = REQUEST_ENTRY_CNT_83XX;
3232 rsp_length = RESPONSE_ENTRY_CNT_83XX;
3233 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3234 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3235 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3236 ha->gid_list_info_size = 8;
3237 ha->optrom_size = OPTROM_SIZE_83XX;
3238 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3239 ha->isp_ops = &qla83xx_isp_ops;
3240 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3241 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3242 ha->nvram_conf_off = ~0;
3243 ha->nvram_data_off = ~0;
3244 } else if (IS_QLAFX00(ha)) {
3245 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
3246 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
3247 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
3248 req_length = REQUEST_ENTRY_CNT_FX00;
3249 rsp_length = RESPONSE_ENTRY_CNT_FX00;
3250 ha->isp_ops = &qlafx00_isp_ops;
3251 ha->port_down_retry_count = 30; /* default value */
3252 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
3253 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
3254 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
3255 ha->mr.fw_hbt_en = 1;
3256 ha->mr.host_info_resend = false;
3257 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
3258 } else if (IS_QLA27XX(ha)) {
3259 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3260 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3261 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3262 req_length = REQUEST_ENTRY_CNT_83XX;
3263 rsp_length = RESPONSE_ENTRY_CNT_83XX;
3264 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3265 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3266 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3267 ha->gid_list_info_size = 8;
3268 ha->optrom_size = OPTROM_SIZE_83XX;
3269 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3270 ha->isp_ops = &qla27xx_isp_ops;
3271 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3272 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3273 ha->nvram_conf_off = ~0;
3274 ha->nvram_data_off = ~0;
3275 } else if (IS_QLA28XX(ha)) {
3276 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3277 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3278 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3279 req_length = REQUEST_ENTRY_CNT_83XX;
3280 rsp_length = RESPONSE_ENTRY_CNT_83XX;
3281 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3282 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3283 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3284 ha->gid_list_info_size = 8;
3285 ha->optrom_size = OPTROM_SIZE_28XX;
3286 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3287 ha->isp_ops = &qla27xx_isp_ops;
3288 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX;
3289 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX;
3290 ha->nvram_conf_off = ~0;
3291 ha->nvram_data_off = ~0;
3292 } else if (IS_QLA29XX(ha)) {
3293 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3294 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3295 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3296 req_length = REQUEST_ENTRY_CNT_83XX;
3297 rsp_length = RESPONSE_ENTRY_CNT_83XX;
3298 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3299 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3300 ha->gid_list_info_size = 8;
3301 ha->optrom_size = OPTROM_SIZE_28XX;
3302 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3303 ha->isp_ops = &qla29xx_isp_ops;
3304 ha->flash_conf_off = ~0;
3305 ha->flash_data_off = ~0;
3306 ha->nvram_conf_off = ~0;
3307 ha->nvram_data_off = ~0;
3308 ha->flt_segment_length = QLA_SEGMENT_LENGTH;
3309 }
3310
3311 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
3312 "mbx_count=%d, req_length=%d, "
3313 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
3314 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
3315 "max_fibre_devices=%d.\n",
3316 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
3317 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
3318 ha->nvram_npiv_size, ha->max_fibre_devices);
3319 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
3320 "isp_ops=%p, flash_conf_off=%d, "
3321 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
3322 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
3323 ha->nvram_conf_off, ha->nvram_data_off);
3324
3325 /* Configure PCI I/O space */
3326 ret = ha->isp_ops->iospace_config(ha);
3327 if (ret)
3328 goto iospace_config_failed;
3329
3330 ql_log_pci(ql_log_info, pdev, 0x001d,
3331 "Found an ISP%04X irq %d iobase 0x%p.\n",
3332 pdev->device, pdev->irq, ha->iobase);
3333 mutex_init(&ha->vport_lock);
3334 mutex_init(&ha->mq_lock);
3335 init_completion(&ha->mbx_cmd_comp);
3336 complete(&ha->mbx_cmd_comp);
3337 init_completion(&ha->mbx_intr_comp);
3338 init_completion(&ha->dcbx_comp);
3339 init_completion(&ha->lb_portup_comp);
3340
3341 set_bit(0, (unsigned long *) ha->vp_idx_map);
3342
3343 qla2x00_config_dma_addressing(ha);
3344 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
3345 "64 Bit addressing is %s.\n",
3346 ha->flags.enable_64bit_addressing ? "enable" :
3347 "disable");
3348 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
3349 if (ret) {
3350 ql_log_pci(ql_log_fatal, pdev, 0x0031,
3351 "Failed to allocate memory for adapter, aborting.\n");
3352
3353 goto probe_hw_failed;
3354 }
3355
3356 req->max_q_depth = MAX_Q_DEPTH;
3357 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
3358 req->max_q_depth = ql2xmaxqdepth;
3359
3360
3361 base_vha = qla2x00_create_host(sht, ha);
3362 if (!base_vha) {
3363 ret = -ENOMEM;
3364 goto probe_hw_failed;
3365 }
3366
3367 pci_set_drvdata(pdev, base_vha);
3368 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3369
3370 host = base_vha->host;
3371 base_vha->req = req;
3372 if (IS_QLA2XXX_MIDTYPE(ha))
3373 base_vha->mgmt_svr_loop_id =
3374 qla2x00_reserve_mgmt_server_loop_id(base_vha);
3375 else
3376 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3377 base_vha->vp_idx;
3378
3379 /* Setup fcport template structure. */
3380 ha->mr.fcport.vha = base_vha;
3381 ha->mr.fcport.port_type = FCT_UNKNOWN;
3382 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3383 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3384 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3385 ha->mr.fcport.scan_state = 1;
3386
3387 qla2xxx_reset_stats(host, QLA2XX_HW_ERROR | QLA2XX_SHT_LNK_DWN |
3388 QLA2XX_INT_ERR | QLA2XX_CMD_TIMEOUT |
3389 QLA2XX_RESET_CMD_ERR | QLA2XX_TGT_SHT_LNK_DOWN);
3390
3391 /* Set the SG table size based on ISP type */
3392 if (!IS_FWI2_CAPABLE(ha)) {
3393 if (IS_QLA2100(ha))
3394 host->sg_tablesize = 32;
3395 } else {
3396 if (!IS_QLA82XX(ha))
3397 host->sg_tablesize = QLA_SG_ALL;
3398 }
3399 host->max_id = ha->max_fibre_devices;
3400 host->cmd_per_lun = 3;
3401 host->unique_id = host->host_no;
3402
3403 if (ql2xenabledif && ql2xenabledif != 2) {
3404 ql_log(ql_log_warn, base_vha, 0x302d,
3405 "Invalid value for ql2xenabledif, resetting it to default (2)\n");
3406 ql2xenabledif = 2;
3407 }
3408
3409 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
3410 host->max_cmd_len = 32;
3411 else
3412 host->max_cmd_len = MAX_CMDSZ;
3413 host->max_channel = MAX_BUSES - 1;
3414 /* Older HBAs support only 16-bit LUNs */
3415 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3416 ql2xmaxlun > 0xffff)
3417 host->max_lun = 0xffff;
3418 else
3419 host->max_lun = ql2xmaxlun;
3420 host->transportt = qla2xxx_transport_template;
3421 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
3422
3423 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3424 "max_id=%d this_id=%d "
3425 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
3426 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
3427 host->this_id, host->cmd_per_lun, host->unique_id,
3428 host->max_cmd_len, host->max_channel, host->max_lun,
3429 host->transportt, sht->vendor_id);
3430
3431 INIT_WORK(&ha->heartbeat_work, qla_heartbeat_work_fn);
3432
3433 /* Set up the irqs */
3434 ret = qla2x00_request_irqs(ha, rsp);
3435 if (ret)
3436 goto probe_failed;
3437
3438 /* Alloc arrays of request and response ring ptrs */
3439 ret = qla2x00_alloc_queues(ha, req, rsp);
3440 if (ret) {
3441 ql_log(ql_log_fatal, base_vha, 0x003d,
3442 "Failed to allocate memory for queue pointers..."
3443 "aborting.\n");
3444 ret = -ENODEV;
3445 goto probe_failed;
3446 }
3447
3448 if (ha->mqenable) {
3449 /* number of hardware queues supported by blk/scsi-mq*/
3450 host->nr_hw_queues = ha->max_qpairs;
3451
3452 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3453 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
3454 } else {
3455 if (ql2xnvmeenable) {
3456 host->nr_hw_queues = ha->max_qpairs;
3457 ql_dbg(ql_dbg_init, base_vha, 0x0194,
3458 "FC-NVMe support is enabled, HW queues=%d\n",
3459 host->nr_hw_queues);
3460 } else {
3461 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3462 "blk/scsi-mq disabled.\n");
3463 }
3464 }
3465
3466 qlt_probe_one_stage1(base_vha, ha);
3467
3468 pci_save_state(pdev);
3469
3470 /* Assign back pointers */
3471 rsp->req = req;
3472 req->rsp = rsp;
3473
3474 if (IS_QLAFX00(ha)) {
3475 ha->rsp_q_map[0] = rsp;
3476 ha->req_q_map[0] = req;
3477 set_bit(0, ha->req_qid_map);
3478 set_bit(0, ha->rsp_qid_map);
3479 }
3480
3481 /* FWI2-capable only. */
3482 req->req_q_in = &ha->iobase->isp24.req_q_in;
3483 req->req_q_out = &ha->iobase->isp24.req_q_out;
3484 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3485 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
3486 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
3487 IS_QLA28XX(ha) || IS_QLA29XX(ha)) {
3488 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3489 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3490 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3491 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
3492 }
3493
3494 if (IS_QLAFX00(ha)) {
3495 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3496 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3497 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3498 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3499 }
3500
3501 if (IS_P3P_TYPE(ha)) {
3502 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3503 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3504 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3505 }
3506
3507 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3508 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3509 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3510 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3511 "req->req_q_in=%p req->req_q_out=%p "
3512 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3513 req->req_q_in, req->req_q_out,
3514 rsp->rsp_q_in, rsp->rsp_q_out);
3515 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3516 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3517 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3518 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3519 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3520 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
3521
3522 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM | WQ_PERCPU, 0);
3523 if (unlikely(!ha->wq)) {
3524 ret = -ENOMEM;
3525 goto probe_failed;
3526 }
3527
3528 if (ha->isp_ops->initialize_adapter(base_vha)) {
3529 ql_log(ql_log_fatal, base_vha, 0x00d6,
3530 "Failed to initialize adapter - Adapter flags %x.\n",
3531 base_vha->device_flags);
3532
3533 if (IS_QLA82XX(ha)) {
3534 qla82xx_idc_lock(ha);
3535 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3536 QLA8XXX_DEV_FAILED);
3537 qla82xx_idc_unlock(ha);
3538 ql_log(ql_log_fatal, base_vha, 0x00d7,
3539 "HW State: FAILED.\n");
3540 } else if (IS_QLA8044(ha)) {
3541 qla8044_idc_lock(ha);
3542 qla8044_wr_direct(base_vha,
3543 QLA8044_CRB_DEV_STATE_INDEX,
3544 QLA8XXX_DEV_FAILED);
3545 qla8044_idc_unlock(ha);
3546 ql_log(ql_log_fatal, base_vha, 0x0150,
3547 "HW State: FAILED.\n");
3548 }
3549
3550 ret = -ENODEV;
3551 goto probe_failed;
3552 }
3553
3554 if (IS_QLAFX00(ha))
3555 host->can_queue = QLAFX00_MAX_CANQUEUE;
3556 else
3557 host->can_queue = req->num_outstanding_cmds - 10;
3558
3559 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3560 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3561 host->can_queue, base_vha->req,
3562 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3563
3564 /* Check if FW supports MQ or not for ISP25xx */
3565 if (IS_QLA25XX(ha) && !(ha->fw_attributes & BIT_6))
3566 ha->mqenable = 0;
3567
3568 if (ha->mqenable) {
3569 bool startit = !!(host->active_mode & MODE_INITIATOR);
3570
3571 /* Create start of day qpairs for Block MQ */
3572 for (i = 0; i < ha->max_qpairs; i++)
3573 qla2xxx_create_qpair(base_vha, 5, 0, startit);
3574 }
3575 qla_init_iocb_limit(base_vha);
3576
3577 if (ha->flags.running_gold_fw)
3578 goto skip_dpc;
3579
3580 /*
3581 * Startup the kernel thread for this host adapter
3582 */
3583 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
3584 "%s_dpc", base_vha->host_str);
3585 if (IS_ERR(ha->dpc_thread)) {
3586 ql_log(ql_log_fatal, base_vha, 0x00ed,
3587 "Failed to start DPC thread.\n");
3588 ret = PTR_ERR(ha->dpc_thread);
3589 ha->dpc_thread = NULL;
3590 goto probe_failed;
3591 }
3592 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3593 "DPC thread started successfully.\n");
3594
3595 /*
3596 * If we're not coming up in initiator mode, we might sit for
3597 * a while without waking up the dpc thread, which leads to a
3598 * stuck process warning. So just kick the dpc once here and
3599 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3600 */
3601 qla2xxx_wake_dpc(base_vha);
3602
3603 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3604
3605 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3606 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3607 ha->dpc_lp_wq =
3608 alloc_ordered_workqueue("%s", WQ_MEM_RECLAIM, wq_name);
3609 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3610
3611 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3612 ha->dpc_hp_wq =
3613 alloc_ordered_workqueue("%s", WQ_MEM_RECLAIM, wq_name);
3614 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3615 INIT_WORK(&ha->idc_state_handler,
3616 qla83xx_idc_state_handler_work);
3617 INIT_WORK(&ha->nic_core_unrecoverable,
3618 qla83xx_nic_core_unrecoverable_work);
3619 }
3620
3621 skip_dpc:
3622 list_add_tail(&base_vha->list, &ha->vp_list);
3623 base_vha->host->irq = ha->pdev->irq;
3624
3625 /* Initialized the timer */
3626 qla2x00_start_timer(base_vha, WATCH_INTERVAL);
3627 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3628 "Started qla2x00_timer with "
3629 "interval=%d.\n", WATCH_INTERVAL);
3630 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3631 "Detected hba at address=%p.\n",
3632 ha);
3633
3634 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
3635 if (ha->fw_attributes & BIT_4) {
3636 int prot = 0, guard;
3637
3638 base_vha->flags.difdix_supported = 1;
3639 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3640 "Registering for DIF/DIX type 1 and 3 protection.\n");
3641 if (ql2xprotmask)
3642 scsi_host_set_prot(host, ql2xprotmask);
3643 else
3644 scsi_host_set_prot(host,
3645 prot | SHOST_DIF_TYPE1_PROTECTION
3646 | SHOST_DIF_TYPE2_PROTECTION
3647 | SHOST_DIF_TYPE3_PROTECTION
3648 | SHOST_DIX_TYPE1_PROTECTION
3649 | SHOST_DIX_TYPE2_PROTECTION
3650 | SHOST_DIX_TYPE3_PROTECTION);
3651
3652 guard = SHOST_DIX_GUARD_CRC;
3653
3654 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3655 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3656 guard |= SHOST_DIX_GUARD_IP;
3657
3658 if (ql2xprotguard)
3659 scsi_host_set_guard(host, ql2xprotguard);
3660 else
3661 scsi_host_set_guard(host, guard);
3662 } else
3663 base_vha->flags.difdix_supported = 0;
3664 }
3665
3666 ha->isp_ops->enable_intrs(ha);
3667
3668 if (IS_QLAFX00(ha)) {
3669 ret = qlafx00_fx_disc(base_vha,
3670 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3671 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3672 QLA_SG_ALL : 128;
3673 }
3674
3675 if (IS_T10_PI_CAPABLE(base_vha->hw))
3676 host->dma_alignment = 0x7;
3677
3678 ret = scsi_add_host(host, &pdev->dev);
3679 if (ret)
3680 goto probe_failed;
3681
3682 base_vha->flags.init_done = 1;
3683 base_vha->flags.online = 1;
3684 ha->prev_minidump_failed = 0;
3685
3686 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3687 "Init done and hba is online.\n");
3688
3689 if (qla_ini_mode_enabled(base_vha) ||
3690 qla_dual_mode_enabled(base_vha))
3691 scsi_scan_host(host);
3692 else
3693 ql_log(ql_log_info, base_vha, 0x0122,
3694 "skipping scsi_scan_host() for non-initiator port\n");
3695
3696 qla2x00_alloc_sysfs_attr(base_vha);
3697
3698 if (IS_QLAFX00(ha)) {
3699 ret = qlafx00_fx_disc(base_vha,
3700 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3701
3702 /* Register system information */
3703 ret = qlafx00_fx_disc(base_vha,
3704 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3705 }
3706
3707 qla2x00_init_host_attr(base_vha);
3708
3709 qla2x00_dfs_setup(base_vha);
3710
3711 ql_log(ql_log_info, base_vha, 0x00fb,
3712 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
3713 ql_log(ql_log_info, base_vha, 0x00fc,
3714 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3715 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info,
3716 sizeof(pci_info)),
3717 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3718 base_vha->host_no,
3719 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
3720
3721 qlt_add_target(ha, base_vha);
3722
3723 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3724
3725 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3726 return -ENODEV;
3727
3728 /*
3729 * FW dump can happens before sysfs nodes are created. If sysfs nodes
3730 * are unavailable then udev script will not be able to read the fw dump.
3731 * Notify udev to read again, now that sysfs nodes are available.
3732 */
3733 if (ha->fw_dumped || ha->mpi_fw_dumped)
3734 qla2x00_post_uevent_work(base_vha, QLA_UEVENT_CODE_FW_DUMP);
3735
3736 return 0;
3737
3738 probe_failed:
3739 qla_enode_stop(base_vha);
3740 qla_edb_stop(base_vha);
3741 vfree(base_vha->scan.l);
3742 if (base_vha->gnl.l) {
3743 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3744 base_vha->gnl.l, base_vha->gnl.ldma);
3745 base_vha->gnl.l = NULL;
3746 }
3747
3748 if (base_vha->timer_active)
3749 qla2x00_stop_timer(base_vha);
3750 base_vha->flags.online = 0;
3751 if (ha->dpc_thread) {
3752 struct task_struct *t = ha->dpc_thread;
3753
3754 ha->dpc_thread = NULL;
3755 kthread_stop(t);
3756 }
3757
3758 qla2x00_free_device(base_vha);
3759 scsi_host_put(base_vha->host);
3760 /*
3761 * Need to NULL out local req/rsp after
3762 * qla2x00_free_device => qla2x00_free_queues frees
3763 * what these are pointing to. Or else we'll
3764 * fall over below in qla2x00_free_req/rsp_que.
3765 */
3766 req = NULL;
3767 rsp = NULL;
3768
3769 probe_hw_failed:
3770 qla2x00_mem_free(ha);
3771 qla2x00_free_req_que(ha, req);
3772 qla2x00_free_rsp_que(ha, rsp);
3773 qla2x00_clear_drv_active(ha);
3774
3775 iospace_config_failed:
3776 if (IS_P3P_TYPE(ha)) {
3777 if (!ha->nx_pcibase)
3778 iounmap((device_reg_t *)ha->nx_pcibase);
3779 if (!ql2xdbwr)
3780 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3781 } else {
3782 if (ha->iobase)
3783 iounmap(ha->iobase);
3784 if (ha->cregbase)
3785 iounmap(ha->cregbase);
3786 }
3787 pci_release_selected_regions(ha->pdev, ha->bars);
3788 kfree(ha);
3789
3790 disable_device:
3791 pci_disable_device(pdev);
3792 return ret;
3793 }
3794
__qla_set_remove_flag(scsi_qla_host_t * base_vha)3795 static void __qla_set_remove_flag(scsi_qla_host_t *base_vha)
3796 {
3797 scsi_qla_host_t *vp;
3798 unsigned long flags;
3799 struct qla_hw_data *ha;
3800
3801 if (!base_vha)
3802 return;
3803
3804 ha = base_vha->hw;
3805
3806 spin_lock_irqsave(&ha->vport_slock, flags);
3807 list_for_each_entry(vp, &ha->vp_list, list)
3808 set_bit(PFLG_DRIVER_REMOVING, &vp->pci_flags);
3809
3810 /*
3811 * Indicate device removal to prevent future board_disable
3812 * and wait until any pending board_disable has completed.
3813 */
3814 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3815 spin_unlock_irqrestore(&ha->vport_slock, flags);
3816 }
3817
3818 static void
qla2x00_shutdown(struct pci_dev * pdev)3819 qla2x00_shutdown(struct pci_dev *pdev)
3820 {
3821 scsi_qla_host_t *vha;
3822 struct qla_hw_data *ha;
3823
3824 vha = pci_get_drvdata(pdev);
3825 ha = vha->hw;
3826
3827 ql_log(ql_log_info, vha, 0xfffa,
3828 "Adapter shutdown\n");
3829
3830 /*
3831 * Prevent future board_disable and wait
3832 * until any pending board_disable has completed.
3833 */
3834 __qla_set_remove_flag(vha);
3835 cancel_work_sync(&ha->board_disable);
3836
3837 if (!atomic_read(&pdev->enable_cnt))
3838 return;
3839
3840 /* Notify ISPFX00 firmware */
3841 if (IS_QLAFX00(ha))
3842 qlafx00_driver_shutdown(vha, 20);
3843
3844 /* Turn-off FCE trace */
3845 if (ha->flags.fce_enabled) {
3846 qla2x00_disable_fce_trace(vha, NULL, NULL);
3847 ha->flags.fce_enabled = 0;
3848 }
3849
3850 /* Turn-off EFT trace */
3851 if (ha->eft)
3852 qla2x00_disable_eft_trace(vha);
3853
3854 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3855 IS_QLA28XX(ha) || IS_QLA29XX(ha)) {
3856 if (ha->flags.fw_started)
3857 qla2x00_abort_isp_cleanup(vha);
3858 } else {
3859 /* Stop currently executing firmware. */
3860 qla2x00_try_to_stop_firmware(vha);
3861 }
3862
3863 /* Disable timer */
3864 if (vha->timer_active)
3865 qla2x00_stop_timer(vha);
3866
3867 /* Turn adapter off line */
3868 vha->flags.online = 0;
3869
3870 /* turn-off interrupts on the card */
3871 if (ha->interrupts_on) {
3872 vha->flags.init_done = 0;
3873 ha->isp_ops->disable_intrs(ha);
3874 }
3875
3876 qla2x00_free_irqs(vha);
3877
3878 qla2x00_free_fw_dump(ha);
3879
3880 pci_disable_device(pdev);
3881 ql_log(ql_log_info, vha, 0xfffe,
3882 "Adapter shutdown successfully.\n");
3883 }
3884
3885 /* Deletes all the virtual ports for a given ha */
3886 static void
qla2x00_delete_all_vps(struct qla_hw_data * ha,scsi_qla_host_t * base_vha)3887 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
3888 {
3889 scsi_qla_host_t *vha;
3890 unsigned long flags;
3891
3892 mutex_lock(&ha->vport_lock);
3893 while (ha->cur_vport_count) {
3894 spin_lock_irqsave(&ha->vport_slock, flags);
3895
3896 BUG_ON(base_vha->list.next == &ha->vp_list);
3897 /* This assumes first entry in ha->vp_list is always base vha */
3898 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
3899 scsi_host_get(vha->host);
3900
3901 spin_unlock_irqrestore(&ha->vport_slock, flags);
3902 mutex_unlock(&ha->vport_lock);
3903
3904 qla_nvme_delete(vha);
3905
3906 fc_vport_terminate(vha->fc_vport);
3907 scsi_host_put(vha->host);
3908
3909 mutex_lock(&ha->vport_lock);
3910 }
3911 mutex_unlock(&ha->vport_lock);
3912 }
3913
3914 /* Stops all deferred work threads */
3915 static void
qla2x00_destroy_deferred_work(struct qla_hw_data * ha)3916 qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3917 {
3918 /* Cancel all work and destroy DPC workqueues */
3919 if (ha->dpc_lp_wq) {
3920 cancel_work_sync(&ha->idc_aen);
3921 destroy_workqueue(ha->dpc_lp_wq);
3922 ha->dpc_lp_wq = NULL;
3923 }
3924
3925 if (ha->dpc_hp_wq) {
3926 cancel_work_sync(&ha->nic_core_reset);
3927 cancel_work_sync(&ha->idc_state_handler);
3928 cancel_work_sync(&ha->nic_core_unrecoverable);
3929 destroy_workqueue(ha->dpc_hp_wq);
3930 ha->dpc_hp_wq = NULL;
3931 }
3932
3933 /* Kill the kernel thread for this host */
3934 if (ha->dpc_thread) {
3935 struct task_struct *t = ha->dpc_thread;
3936
3937 /*
3938 * qla2xxx_wake_dpc checks for ->dpc_thread
3939 * so we need to zero it out.
3940 */
3941 ha->dpc_thread = NULL;
3942 kthread_stop(t);
3943 }
3944 }
3945
3946 static void
qla2x00_unmap_iobases(struct qla_hw_data * ha)3947 qla2x00_unmap_iobases(struct qla_hw_data *ha)
3948 {
3949 if (IS_QLA82XX(ha)) {
3950
3951 iounmap((device_reg_t *)ha->nx_pcibase);
3952 if (!ql2xdbwr)
3953 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3954 } else {
3955 if (ha->iobase)
3956 iounmap(ha->iobase);
3957
3958 if (ha->cregbase)
3959 iounmap(ha->cregbase);
3960
3961 if (ha->mqiobase)
3962 iounmap(ha->mqiobase);
3963
3964 if (ha->msixbase)
3965 iounmap(ha->msixbase);
3966 }
3967 }
3968
3969 static void
qla2x00_clear_drv_active(struct qla_hw_data * ha)3970 qla2x00_clear_drv_active(struct qla_hw_data *ha)
3971 {
3972 if (IS_QLA8044(ha)) {
3973 qla8044_idc_lock(ha);
3974 qla8044_clear_drv_active(ha);
3975 qla8044_idc_unlock(ha);
3976 } else if (IS_QLA82XX(ha)) {
3977 qla82xx_idc_lock(ha);
3978 qla82xx_clear_drv_active(ha);
3979 qla82xx_idc_unlock(ha);
3980 }
3981 }
3982
3983 static void
qla2x00_remove_one(struct pci_dev * pdev)3984 qla2x00_remove_one(struct pci_dev *pdev)
3985 {
3986 scsi_qla_host_t *base_vha;
3987 struct qla_hw_data *ha;
3988
3989 base_vha = pci_get_drvdata(pdev);
3990 ha = base_vha->hw;
3991 ql_log(ql_log_info, base_vha, 0xb079,
3992 "Removing driver\n");
3993 __qla_set_remove_flag(base_vha);
3994 cancel_work_sync(&ha->board_disable);
3995
3996 /*
3997 * If the PCI device is disabled then there was a PCI-disconnect and
3998 * qla2x00_disable_board_on_pci_error has taken care of most of the
3999 * resources.
4000 */
4001 if (!atomic_read(&pdev->enable_cnt)) {
4002 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
4003 base_vha->gnl.l, base_vha->gnl.ldma);
4004 base_vha->gnl.l = NULL;
4005 scsi_host_put(base_vha->host);
4006 kfree(ha);
4007 pci_set_drvdata(pdev, NULL);
4008 return;
4009 }
4010 qla2x00_wait_for_hba_ready(base_vha);
4011
4012 /*
4013 * if UNLOADING flag is already set, then continue unload,
4014 * where it was set first.
4015 */
4016 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags))
4017 return;
4018
4019 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
4020 IS_QLA28XX(ha) || IS_QLA29XX(ha)) {
4021 if (ha->flags.fw_started)
4022 qla2x00_abort_isp_cleanup(base_vha);
4023 } else if (!IS_QLAFX00(ha)) {
4024 if (IS_QLA8031(ha)) {
4025 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
4026 "Clearing fcoe driver presence.\n");
4027 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
4028 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
4029 "Error while clearing DRV-Presence.\n");
4030 }
4031
4032 qla2x00_try_to_stop_firmware(base_vha);
4033 }
4034
4035 qla2x00_wait_for_sess_deletion(base_vha);
4036
4037 qla_nvme_delete(base_vha);
4038
4039 dma_free_coherent(&ha->pdev->dev,
4040 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
4041
4042 base_vha->gnl.l = NULL;
4043 qla_enode_stop(base_vha);
4044 qla_edb_stop(base_vha);
4045
4046 vfree(base_vha->scan.l);
4047
4048 if (IS_QLAFX00(ha))
4049 qlafx00_driver_shutdown(base_vha, 20);
4050
4051 qla2x00_delete_all_vps(ha, base_vha);
4052
4053 qla2x00_dfs_remove(base_vha);
4054
4055 /* Disable timer */
4056 if (base_vha->timer_active)
4057 qla2x00_stop_timer(base_vha);
4058
4059 base_vha->flags.online = 0;
4060
4061 /* free DMA memory */
4062 if (ha->exlogin_buf)
4063 qla2x00_free_exlogin_buffer(ha);
4064
4065 /* free DMA memory */
4066 if (ha->exchoffld_buf)
4067 qla2x00_free_exchoffld_buffer(ha);
4068
4069 qla2x00_destroy_deferred_work(ha);
4070
4071 qlt_remove_target(ha, base_vha);
4072
4073 qla2x00_free_sysfs_attr(base_vha, true);
4074
4075 fc_remove_host(base_vha->host);
4076
4077 scsi_remove_host(base_vha->host);
4078
4079 qla84xx_put_chip(base_vha);
4080
4081 qla2x00_free_device(base_vha);
4082
4083 qla2x00_clear_drv_active(ha);
4084
4085 scsi_host_put(base_vha->host);
4086
4087 qla2x00_unmap_iobases(ha);
4088
4089 pci_release_selected_regions(ha->pdev, ha->bars);
4090 kfree(ha);
4091
4092 pci_disable_device(pdev);
4093 }
4094
4095 static inline void
qla24xx_free_purex_list(struct purex_list * list)4096 qla24xx_free_purex_list(struct purex_list *list)
4097 {
4098 struct purex_item *item, *next;
4099 ulong flags;
4100
4101 spin_lock_irqsave(&list->lock, flags);
4102 list_for_each_entry_safe(item, next, &list->head, list) {
4103 list_del(&item->list);
4104 if (item == &item->vha->default_item)
4105 continue;
4106 kfree(item);
4107 }
4108 spin_unlock_irqrestore(&list->lock, flags);
4109 }
4110
4111 static void
qla2x00_free_device(scsi_qla_host_t * vha)4112 qla2x00_free_device(scsi_qla_host_t *vha)
4113 {
4114 struct qla_hw_data *ha = vha->hw;
4115
4116 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
4117
4118 /* Disable timer */
4119 if (vha->timer_active)
4120 qla2x00_stop_timer(vha);
4121
4122 qla25xx_delete_queues(vha);
4123 vha->flags.online = 0;
4124
4125 /* turn-off interrupts on the card */
4126 if (ha->interrupts_on) {
4127 vha->flags.init_done = 0;
4128 ha->isp_ops->disable_intrs(ha);
4129 }
4130
4131 qla2x00_free_fcports(vha);
4132
4133 qla2x00_free_irqs(vha);
4134
4135 /* Flush the work queue and remove it */
4136 if (ha->wq) {
4137 destroy_workqueue(ha->wq);
4138 ha->wq = NULL;
4139 }
4140
4141
4142 qla24xx_free_purex_list(&vha->purex_list);
4143
4144 qla2x00_mem_free(ha);
4145
4146 qla82xx_md_free(vha);
4147
4148 qla_edif_sadb_release_free_pool(ha);
4149 qla_edif_sadb_release(ha);
4150
4151 qla2x00_free_queues(ha);
4152 }
4153
qla2x00_free_fcports(struct scsi_qla_host * vha)4154 void qla2x00_free_fcports(struct scsi_qla_host *vha)
4155 {
4156 fc_port_t *fcport, *tfcport;
4157
4158 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list)
4159 qla2x00_free_fcport(fcport);
4160 }
4161
4162 static inline void
qla2x00_schedule_rport_del(struct scsi_qla_host * vha,fc_port_t * fcport)4163 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport)
4164 {
4165 int now;
4166
4167 if (!fcport->rport)
4168 return;
4169
4170 if (fcport->rport) {
4171 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
4172 "%s %8phN. rport %p roles %x\n",
4173 __func__, fcport->port_name, fcport->rport,
4174 fcport->rport->roles);
4175 fc_remote_port_delete(fcport->rport);
4176 }
4177 qlt_do_generation_tick(vha, &now);
4178 }
4179
4180 /*
4181 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
4182 *
4183 * Input: ha = adapter block pointer. fcport = port structure pointer.
4184 *
4185 * Return: None.
4186 *
4187 * Context:
4188 */
qla2x00_mark_device_lost(scsi_qla_host_t * vha,fc_port_t * fcport,int do_login)4189 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
4190 int do_login)
4191 {
4192 if (IS_QLAFX00(vha->hw)) {
4193 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
4194 qla2x00_schedule_rport_del(vha, fcport);
4195 return;
4196 }
4197
4198 if (atomic_read(&fcport->state) == FCS_ONLINE &&
4199 vha->vp_idx == fcport->vha->vp_idx) {
4200 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
4201 qla2x00_schedule_rport_del(vha, fcport);
4202 }
4203
4204 /*
4205 * We may need to retry the login, so don't change the state of the
4206 * port but do the retries.
4207 */
4208 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
4209 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
4210
4211 if (!do_login)
4212 return;
4213
4214 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4215 }
4216
4217 void
qla2x00_mark_all_devices_lost(scsi_qla_host_t * vha)4218 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha)
4219 {
4220 fc_port_t *fcport;
4221
4222 ql_dbg(ql_dbg_disc, vha, 0x20f1,
4223 "Mark all dev lost\n");
4224
4225 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4226 if (ql2xfc2target &&
4227 fcport->loop_id != FC_NO_LOOP_ID &&
4228 (fcport->flags & FCF_FCP2_DEVICE) &&
4229 fcport->port_type == FCT_TARGET &&
4230 !qla2x00_reset_active(vha)) {
4231 ql_dbg(ql_dbg_disc, vha, 0x211a,
4232 "Delaying session delete for FCP2 flags 0x%x port_type = 0x%x port_id=%06x %phC",
4233 fcport->flags, fcport->port_type,
4234 fcport->d_id.b24, fcport->port_name);
4235 continue;
4236 }
4237 fcport->scan_state = 0;
4238 qlt_schedule_sess_for_deletion(fcport);
4239 }
4240 }
4241
qla2x00_set_reserved_loop_ids(struct qla_hw_data * ha)4242 static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha)
4243 {
4244 int i;
4245
4246 if (IS_FWI2_CAPABLE(ha))
4247 return;
4248
4249 for (i = 0; i < SNS_FIRST_LOOP_ID; i++)
4250 set_bit(i, ha->loop_id_map);
4251 set_bit(MANAGEMENT_SERVER, ha->loop_id_map);
4252 set_bit(BROADCAST, ha->loop_id_map);
4253 }
4254
4255 /*
4256 * qla2x00_mem_alloc
4257 * Allocates adapter memory.
4258 *
4259 * Returns:
4260 * 0 = success.
4261 * !0 = failure.
4262 */
4263 static int
qla2x00_mem_alloc(struct qla_hw_data * ha,uint16_t req_len,uint16_t rsp_len,struct req_que ** req,struct rsp_que ** rsp)4264 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
4265 struct req_que **req, struct rsp_que **rsp)
4266 {
4267 char name[16];
4268 int rc;
4269 size_t req_entry_size = qla_req_entry_size(ha);
4270 size_t rsp_entry_size = qla_rsp_entry_size(ha);
4271
4272 if (QLA_TGT_MODE_ENABLED() || EDIF_CAP(ha)) {
4273 ha->vp_map = kzalloc_objs(struct qla_vp_map,
4274 MAX_MULTI_ID_FABRIC);
4275 if (!ha->vp_map)
4276 goto fail;
4277 }
4278
4279 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
4280 &ha->init_cb_dma, GFP_KERNEL);
4281 if (!ha->init_cb)
4282 goto fail_free_vp_map;
4283
4284 rc = btree_init32(&ha->host_map);
4285 if (rc)
4286 goto fail_free_init_cb;
4287
4288 if (qlt_mem_alloc(ha) < 0)
4289 goto fail_free_btree;
4290
4291 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
4292 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
4293 if (!ha->gid_list)
4294 goto fail_free_tgt_mem;
4295
4296 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
4297 if (!ha->srb_mempool)
4298 goto fail_free_gid_list;
4299
4300 if (IS_P3P_TYPE(ha) || IS_QLA27XX(ha) ||
4301 (ql2xsecenable && (IS_QLA28XX(ha) || IS_QLA29XX(ha)))) {
4302 /* Allocate cache for CT6 Ctx. */
4303 if (!ctx_cachep) {
4304 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
4305 sizeof(struct ct6_dsd), 0,
4306 SLAB_HWCACHE_ALIGN, NULL);
4307 if (!ctx_cachep)
4308 goto fail_free_srb_mempool;
4309 }
4310 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
4311 ctx_cachep);
4312 if (!ha->ctx_mempool)
4313 goto fail_free_srb_mempool;
4314 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
4315 "ctx_cachep=%p ctx_mempool=%p.\n",
4316 ctx_cachep, ha->ctx_mempool);
4317 }
4318
4319 /* Get memory for cached NVRAM */
4320 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
4321 if (!ha->nvram)
4322 goto fail_free_ctx_mempool;
4323
4324 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
4325 ha->pdev->device);
4326 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4327 DMA_POOL_SIZE, 8, 0);
4328 if (!ha->s_dma_pool)
4329 goto fail_free_nvram;
4330
4331 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
4332 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
4333 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
4334
4335 if (IS_P3P_TYPE(ha) || ql2xenabledif ||
4336 ((IS_QLA28XX(ha) || IS_QLA29XX(ha)) && ql2xsecenable)) {
4337 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4338 DSD_LIST_DMA_POOL_SIZE, 8, 0);
4339 if (!ha->dl_dma_pool) {
4340 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
4341 "Failed to allocate memory for dl_dma_pool.\n");
4342 goto fail_s_dma_pool;
4343 }
4344
4345 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4346 FCP_CMND_DMA_POOL_SIZE, 8, 0);
4347 if (!ha->fcp_cmnd_dma_pool) {
4348 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
4349 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
4350 goto fail_dl_dma_pool;
4351 }
4352
4353 if (ql2xenabledif) {
4354 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE;
4355 struct dsd_dma *dsd, *nxt;
4356 uint i;
4357 /* Creata a DMA pool of buffers for DIF bundling */
4358 ha->dif_bundl_pool = dma_pool_create(name,
4359 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0);
4360 if (!ha->dif_bundl_pool) {
4361 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4362 "%s: failed create dif_bundl_pool\n",
4363 __func__);
4364 goto fail_dif_bundl_dma_pool;
4365 }
4366
4367 INIT_LIST_HEAD(&ha->pool.good.head);
4368 INIT_LIST_HEAD(&ha->pool.unusable.head);
4369 ha->pool.good.count = 0;
4370 ha->pool.unusable.count = 0;
4371 for (i = 0; i < 128; i++) {
4372 dsd = kzalloc_obj(*dsd, GFP_ATOMIC);
4373 if (!dsd) {
4374 ql_dbg_pci(ql_dbg_init, ha->pdev,
4375 0xe0ee, "%s: failed alloc dsd\n",
4376 __func__);
4377 return -ENOMEM;
4378 }
4379 ha->dif_bundle_kallocs++;
4380
4381 dsd->dsd_addr = dma_pool_alloc(
4382 ha->dif_bundl_pool, GFP_ATOMIC,
4383 &dsd->dsd_list_dma);
4384 if (!dsd->dsd_addr) {
4385 ql_dbg_pci(ql_dbg_init, ha->pdev,
4386 0xe0ee,
4387 "%s: failed alloc ->dsd_addr\n",
4388 __func__);
4389 kfree(dsd);
4390 ha->dif_bundle_kallocs--;
4391 continue;
4392 }
4393 ha->dif_bundle_dma_allocs++;
4394
4395 /*
4396 * if DMA buffer crosses 4G boundary,
4397 * put it on bad list
4398 */
4399 if (MSD(dsd->dsd_list_dma) ^
4400 MSD(dsd->dsd_list_dma + bufsize)) {
4401 list_add_tail(&dsd->list,
4402 &ha->pool.unusable.head);
4403 ha->pool.unusable.count++;
4404 } else {
4405 list_add_tail(&dsd->list,
4406 &ha->pool.good.head);
4407 ha->pool.good.count++;
4408 }
4409 }
4410
4411 /* return the good ones back to the pool */
4412 list_for_each_entry_safe(dsd, nxt,
4413 &ha->pool.good.head, list) {
4414 list_del(&dsd->list);
4415 dma_pool_free(ha->dif_bundl_pool,
4416 dsd->dsd_addr, dsd->dsd_list_dma);
4417 ha->dif_bundle_dma_allocs--;
4418 kfree(dsd);
4419 ha->dif_bundle_kallocs--;
4420 }
4421
4422 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4423 "%s: dif dma pool (good=%u unusable=%u)\n",
4424 __func__, ha->pool.good.count,
4425 ha->pool.unusable.count);
4426 }
4427
4428 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
4429 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n",
4430 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool,
4431 ha->dif_bundl_pool);
4432 }
4433
4434 /* Allocate memory for SNS commands */
4435 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
4436 /* Get consistent memory allocated for SNS commands */
4437 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
4438 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
4439 if (!ha->sns_cmd)
4440 goto fail_dma_pool;
4441 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
4442 "sns_cmd: %p.\n", ha->sns_cmd);
4443 } else {
4444 /* Get consistent memory allocated for MS IOCB */
4445 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4446 &ha->ms_iocb_dma);
4447 if (!ha->ms_iocb)
4448 goto fail_dma_pool;
4449 /* Get consistent memory allocated for CT SNS commands */
4450 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
4451 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
4452 if (!ha->ct_sns)
4453 goto fail_free_ms_iocb;
4454 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
4455 "ms_iocb=%p ct_sns=%p.\n",
4456 ha->ms_iocb, ha->ct_sns);
4457 }
4458
4459 /* Allocate memory for request ring */
4460 *req = kzalloc_obj(struct req_que);
4461 if (!*req) {
4462 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
4463 "Failed to allocate memory for req.\n");
4464 goto fail_req;
4465 }
4466 (*req)->length = req_len;
4467 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
4468 ((*req)->length + 1) * req_entry_size,
4469 &(*req)->dma, GFP_KERNEL);
4470 if (!(*req)->ring) {
4471 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
4472 "Failed to allocate memory for req_ring.\n");
4473 goto fail_req_ring;
4474 }
4475 if (IS_QLA29XX(ha)) {
4476 (*req)->ring_ext = (struct request_ext *)(*req)->ring;
4477 (*req)->ring_ext_ptr = (*req)->ring_ext;
4478 }
4479 /* Allocate memory for response ring */
4480 *rsp = kzalloc_obj(struct rsp_que);
4481 if (!*rsp) {
4482 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
4483 "Failed to allocate memory for rsp.\n");
4484 goto fail_rsp;
4485 }
4486 (*rsp)->hw = ha;
4487 (*rsp)->length = rsp_len;
4488 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
4489 ((*rsp)->length + 1) * rsp_entry_size,
4490 &(*rsp)->dma, GFP_KERNEL);
4491 if (!(*rsp)->ring) {
4492 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
4493 "Failed to allocate memory for rsp_ring.\n");
4494 goto fail_rsp_ring;
4495 }
4496 if (IS_QLA29XX(ha)) {
4497 (*rsp)->ring_ext = (struct response_ext *)(*rsp)->ring;
4498 (*rsp)->ring_ext_ptr = (*rsp)->ring_ext;
4499 }
4500 (*req)->rsp = *rsp;
4501 (*rsp)->req = *req;
4502 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
4503 "req=%p req->length=%d req->ring=%p rsp=%p "
4504 "rsp->length=%d rsp->ring=%p.\n",
4505 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
4506 (*rsp)->ring);
4507 /* Allocate memory for NVRAM data for vports */
4508 if (ha->nvram_npiv_size) {
4509 ha->npiv_info = kzalloc_objs(struct qla_npiv_entry,
4510 ha->nvram_npiv_size);
4511 if (!ha->npiv_info) {
4512 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
4513 "Failed to allocate memory for npiv_info.\n");
4514 goto fail_npiv_info;
4515 }
4516 } else
4517 ha->npiv_info = NULL;
4518
4519 /* Get consistent memory allocated for EX-INIT-CB. */
4520 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
4521 IS_QLA28XX(ha) || IS_QLA29XX(ha)) {
4522 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4523 &ha->ex_init_cb_dma);
4524 if (!ha->ex_init_cb)
4525 goto fail_ex_init_cb;
4526 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4527 "ex_init_cb=%p.\n", ha->ex_init_cb);
4528 }
4529
4530 /* Get consistent memory allocated for Special Features-CB. */
4531 if (IS_QLA27XX(ha) || IS_QLA28XX(ha) || IS_QLA29XX(ha)) {
4532 ha->sf_init_cb = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL,
4533 &ha->sf_init_cb_dma);
4534 if (!ha->sf_init_cb)
4535 goto fail_sf_init_cb;
4536 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0199,
4537 "sf_init_cb=%p.\n", ha->sf_init_cb);
4538 }
4539
4540
4541 /* Get consistent memory allocated for Async Port-Database. */
4542 if (!IS_FWI2_CAPABLE(ha)) {
4543 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4544 &ha->async_pd_dma);
4545 if (!ha->async_pd)
4546 goto fail_async_pd;
4547 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4548 "async_pd=%p.\n", ha->async_pd);
4549 }
4550
4551 INIT_LIST_HEAD(&ha->vp_list);
4552
4553 /* Allocate memory for our loop_id bitmap */
4554 ha->loop_id_map = kzalloc_objs(long, BITS_TO_LONGS(LOOPID_MAP_SIZE));
4555 if (!ha->loop_id_map)
4556 goto fail_loop_id_map;
4557 else {
4558 qla2x00_set_reserved_loop_ids(ha);
4559 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
4560 "loop_id_map=%p.\n", ha->loop_id_map);
4561 }
4562
4563 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4564 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4565 if (!ha->sfp_data) {
4566 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4567 "Unable to allocate memory for SFP read-data.\n");
4568 goto fail_sfp_data;
4569 }
4570
4571 ha->flt = dma_alloc_coherent(&ha->pdev->dev,
4572 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma,
4573 GFP_KERNEL);
4574 if (!ha->flt) {
4575 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4576 "Unable to allocate memory for FLT.\n");
4577 goto fail_flt_buffer;
4578 }
4579
4580 ha->flt_data = vzalloc(sizeof(struct qla_flash_layout) +
4581 (sizeof(struct qla_flt_region_data) * FLT_MAX_REGIONS));
4582 if (!ha->flt_data) {
4583 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001a,
4584 "Unable to allocate memory for mini FLT data.\n");
4585 goto fail_flt;
4586 }
4587
4588 /* allocate the purex dma pool */
4589 ha->purex_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4590 ELS_MAX_PAYLOAD, 8, 0);
4591
4592 if (!ha->purex_dma_pool) {
4593 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4594 "Unable to allocate purex_dma_pool.\n");
4595 goto fail_flt_data;
4596 }
4597
4598 ha->elsrej.size = sizeof(struct fc_els_ls_rjt) + 16;
4599 ha->elsrej.c = dma_alloc_coherent(&ha->pdev->dev,
4600 ha->elsrej.size,
4601 &ha->elsrej.cdma,
4602 GFP_KERNEL);
4603 if (!ha->elsrej.c) {
4604 ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff,
4605 "Alloc failed for els reject cmd.\n");
4606 goto fail_elsrej;
4607 }
4608 ha->elsrej.c->er_cmd = ELS_LS_RJT;
4609 ha->elsrej.c->er_reason = ELS_RJT_LOGIC;
4610 ha->elsrej.c->er_explan = ELS_EXPL_UNAB_DATA;
4611
4612 ha->lsrjt.size = sizeof(struct fcnvme_ls_rjt);
4613 ha->lsrjt.c = dma_alloc_coherent(&ha->pdev->dev, ha->lsrjt.size,
4614 &ha->lsrjt.cdma, GFP_KERNEL);
4615 if (!ha->lsrjt.c) {
4616 ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff,
4617 "Alloc failed for nvme fc reject cmd.\n");
4618 goto fail_lsrjt;
4619 }
4620
4621 return 0;
4622
4623 fail_lsrjt:
4624 dma_free_coherent(&ha->pdev->dev, ha->elsrej.size,
4625 ha->elsrej.c, ha->elsrej.cdma);
4626 ha->elsrej.c = NULL;
4627 ha->elsrej.cdma = 0;
4628 fail_elsrej:
4629 dma_pool_destroy(ha->purex_dma_pool);
4630 ha->purex_dma_pool = NULL;
4631 fail_flt_data:
4632 vfree(ha->flt_data);
4633 ha->flt_data = NULL;
4634 fail_flt:
4635 dma_free_coherent(&ha->pdev->dev, sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE,
4636 ha->flt, ha->flt_dma);
4637 ha->flt = NULL;
4638 ha->flt_dma = 0;
4639
4640 fail_flt_buffer:
4641 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4642 ha->sfp_data, ha->sfp_data_dma);
4643 ha->sfp_data = NULL;
4644 ha->sfp_data_dma = 0;
4645 fail_sfp_data:
4646 kfree(ha->loop_id_map);
4647 ha->loop_id_map = NULL;
4648 fail_loop_id_map:
4649 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4650 ha->async_pd = NULL;
4651 ha->async_pd_dma = 0;
4652 fail_async_pd:
4653 dma_pool_free(ha->s_dma_pool, ha->sf_init_cb, ha->sf_init_cb_dma);
4654 ha->sf_init_cb = NULL;
4655 ha->sf_init_cb_dma = 0;
4656 fail_sf_init_cb:
4657 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
4658 ha->ex_init_cb = NULL;
4659 ha->ex_init_cb_dma = 0;
4660 fail_ex_init_cb:
4661 kfree(ha->npiv_info);
4662 ha->npiv_info = NULL;
4663 fail_npiv_info:
4664 dma_free_coherent(&ha->pdev->dev,
4665 ((*rsp)->length + 1) * rsp_entry_size,
4666 (*rsp)->ring, (*rsp)->dma);
4667 (*rsp)->ring = NULL;
4668 (*rsp)->dma = 0;
4669 fail_rsp_ring:
4670 kfree(*rsp);
4671 *rsp = NULL;
4672 fail_rsp:
4673 dma_free_coherent(&ha->pdev->dev,
4674 ((*req)->length + 1) * req_entry_size,
4675 (*req)->ring, (*req)->dma);
4676 (*req)->ring = NULL;
4677 (*req)->dma = 0;
4678 fail_req_ring:
4679 kfree(*req);
4680 *req = NULL;
4681 fail_req:
4682 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4683 ha->ct_sns, ha->ct_sns_dma);
4684 ha->ct_sns = NULL;
4685 ha->ct_sns_dma = 0;
4686 fail_free_ms_iocb:
4687 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4688 ha->ms_iocb = NULL;
4689 ha->ms_iocb_dma = 0;
4690
4691 if (ha->sns_cmd)
4692 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4693 ha->sns_cmd, ha->sns_cmd_dma);
4694 fail_dma_pool:
4695 if (ql2xenabledif) {
4696 struct dsd_dma *dsd, *nxt;
4697
4698 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4699 list) {
4700 list_del(&dsd->list);
4701 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4702 dsd->dsd_list_dma);
4703 ha->dif_bundle_dma_allocs--;
4704 kfree(dsd);
4705 ha->dif_bundle_kallocs--;
4706 ha->pool.unusable.count--;
4707 }
4708 dma_pool_destroy(ha->dif_bundl_pool);
4709 ha->dif_bundl_pool = NULL;
4710 }
4711
4712 fail_dif_bundl_dma_pool:
4713 if (IS_QLA82XX(ha) || IS_QLA29XX(ha) || ql2xenabledif) {
4714 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4715 ha->fcp_cmnd_dma_pool = NULL;
4716 }
4717 fail_dl_dma_pool:
4718 if (IS_QLA82XX(ha) || IS_QLA29XX(ha) || ql2xenabledif) {
4719 dma_pool_destroy(ha->dl_dma_pool);
4720 ha->dl_dma_pool = NULL;
4721 }
4722 fail_s_dma_pool:
4723 dma_pool_destroy(ha->s_dma_pool);
4724 ha->s_dma_pool = NULL;
4725 fail_free_nvram:
4726 kfree(ha->nvram);
4727 ha->nvram = NULL;
4728 ha->fiv = NULL;
4729 fail_free_ctx_mempool:
4730 mempool_destroy(ha->ctx_mempool);
4731 ha->ctx_mempool = NULL;
4732 fail_free_srb_mempool:
4733 mempool_destroy(ha->srb_mempool);
4734 ha->srb_mempool = NULL;
4735 fail_free_gid_list:
4736 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4737 ha->gid_list,
4738 ha->gid_list_dma);
4739 ha->gid_list = NULL;
4740 ha->gid_list_dma = 0;
4741 fail_free_tgt_mem:
4742 qlt_mem_free(ha);
4743 fail_free_btree:
4744 btree_destroy32(&ha->host_map);
4745 fail_free_init_cb:
4746 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4747 ha->init_cb_dma);
4748 ha->init_cb = NULL;
4749 ha->init_cb_dma = 0;
4750 fail_free_vp_map:
4751 kfree(ha->vp_map);
4752 ha->vp_map = NULL;
4753 fail:
4754 ql_log(ql_log_fatal, NULL, 0x0030,
4755 "Memory allocation failure.\n");
4756 return -ENOMEM;
4757 }
4758
4759 int
qla2x00_set_exlogins_buffer(scsi_qla_host_t * vha)4760 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4761 {
4762 int rval;
4763 uint16_t size, max_cnt;
4764 uint32_t temp;
4765 struct qla_hw_data *ha = vha->hw;
4766
4767 /* Return if we don't need to alloacate any extended logins */
4768 if (ql2xexlogins <= MAX_FIBRE_DEVICES_2400)
4769 return QLA_SUCCESS;
4770
4771 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4772 return QLA_SUCCESS;
4773
4774 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4775 max_cnt = 0;
4776 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4777 if (rval != QLA_SUCCESS) {
4778 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4779 "Failed to get exlogin status.\n");
4780 return rval;
4781 }
4782
4783 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
4784 temp *= size;
4785
4786 if (temp != ha->exlogin_size) {
4787 qla2x00_free_exlogin_buffer(ha);
4788 ha->exlogin_size = temp;
4789
4790 ql_log(ql_log_info, vha, 0xd024,
4791 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4792 max_cnt, size, temp);
4793
4794 ql_log(ql_log_info, vha, 0xd025,
4795 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4796
4797 /* Get consistent memory for extended logins */
4798 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4799 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4800 if (!ha->exlogin_buf) {
4801 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
4802 "Failed to allocate memory for exlogin_buf_dma.\n");
4803 return -ENOMEM;
4804 }
4805 }
4806
4807 /* Now configure the dma buffer */
4808 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4809 if (rval) {
4810 ql_log(ql_log_fatal, vha, 0xd033,
4811 "Setup extended login buffer ****FAILED****.\n");
4812 qla2x00_free_exlogin_buffer(ha);
4813 }
4814
4815 return rval;
4816 }
4817
4818 /*
4819 * qla2x00_free_exlogin_buffer
4820 *
4821 * Input:
4822 * ha = adapter block pointer
4823 */
4824 void
qla2x00_free_exlogin_buffer(struct qla_hw_data * ha)4825 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4826 {
4827 if (ha->exlogin_buf) {
4828 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4829 ha->exlogin_buf, ha->exlogin_buf_dma);
4830 ha->exlogin_buf = NULL;
4831 ha->exlogin_size = 0;
4832 }
4833 }
4834
4835 static void
qla2x00_number_of_exch(scsi_qla_host_t * vha,u32 * ret_cnt,u16 max_cnt)4836 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4837 {
4838 u32 temp;
4839 struct init_cb_81xx *icb = (struct init_cb_81xx *)vha->hw->init_cb;
4840 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4841
4842 if (max_cnt > vha->hw->max_exchg)
4843 max_cnt = vha->hw->max_exchg;
4844
4845 if (qla_ini_mode_enabled(vha)) {
4846 if (vha->ql2xiniexchg > max_cnt)
4847 vha->ql2xiniexchg = max_cnt;
4848
4849 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4850 *ret_cnt = vha->ql2xiniexchg;
4851
4852 } else if (qla_tgt_mode_enabled(vha)) {
4853 if (vha->ql2xexchoffld > max_cnt) {
4854 vha->ql2xexchoffld = max_cnt;
4855 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4856 }
4857
4858 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4859 *ret_cnt = vha->ql2xexchoffld;
4860 } else if (qla_dual_mode_enabled(vha)) {
4861 temp = vha->ql2xiniexchg + vha->ql2xexchoffld;
4862 if (temp > max_cnt) {
4863 vha->ql2xiniexchg -= (temp - max_cnt)/2;
4864 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
4865 temp = max_cnt;
4866 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4867 }
4868
4869 if (temp > FW_DEF_EXCHANGES_CNT)
4870 *ret_cnt = temp;
4871 }
4872 }
4873
4874 int
qla2x00_set_exchoffld_buffer(scsi_qla_host_t * vha)4875 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4876 {
4877 int rval;
4878 u16 size, max_cnt;
4879 u32 actual_cnt, totsz;
4880 struct qla_hw_data *ha = vha->hw;
4881
4882 if (!ha->flags.exchoffld_enabled)
4883 return QLA_SUCCESS;
4884
4885 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
4886 return QLA_SUCCESS;
4887
4888 max_cnt = 0;
4889 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4890 if (rval != QLA_SUCCESS) {
4891 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4892 "Failed to get exlogin status.\n");
4893 return rval;
4894 }
4895
4896 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt);
4897 ql_log(ql_log_info, vha, 0xd014,
4898 "Actual exchange offload count: %d.\n", actual_cnt);
4899
4900 totsz = actual_cnt * size;
4901
4902 if (totsz != ha->exchoffld_size) {
4903 qla2x00_free_exchoffld_buffer(ha);
4904 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) {
4905 ha->exchoffld_size = 0;
4906 ha->flags.exchoffld_enabled = 0;
4907 return QLA_SUCCESS;
4908 }
4909
4910 ha->exchoffld_size = totsz;
4911
4912 ql_log(ql_log_info, vha, 0xd016,
4913 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n",
4914 max_cnt, actual_cnt, size, totsz);
4915
4916 ql_log(ql_log_info, vha, 0xd017,
4917 "Exchange Buffers requested size = 0x%x\n",
4918 ha->exchoffld_size);
4919
4920 /* Get consistent memory for extended logins */
4921 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4922 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4923 if (!ha->exchoffld_buf) {
4924 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4925 "Failed to allocate memory for Exchange Offload.\n");
4926
4927 if (ha->max_exchg >
4928 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) {
4929 ha->max_exchg -= REDUCE_EXCHANGES_CNT;
4930 } else if (ha->max_exchg >
4931 (FW_DEF_EXCHANGES_CNT + 512)) {
4932 ha->max_exchg -= 512;
4933 } else {
4934 ha->flags.exchoffld_enabled = 0;
4935 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4936 "Disabling Exchange offload due to lack of memory\n");
4937 }
4938 ha->exchoffld_size = 0;
4939
4940 return -ENOMEM;
4941 }
4942 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) {
4943 /* pathological case */
4944 qla2x00_free_exchoffld_buffer(ha);
4945 ha->exchoffld_size = 0;
4946 ha->flags.exchoffld_enabled = 0;
4947 ql_log(ql_log_info, vha, 0xd016,
4948 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n",
4949 ha->exchoffld_size, actual_cnt, size, totsz);
4950 return 0;
4951 }
4952
4953 /* Now configure the dma buffer */
4954 rval = qla_set_exchoffld_mem_cfg(vha);
4955 if (rval) {
4956 ql_log(ql_log_fatal, vha, 0xd02e,
4957 "Setup exchange offload buffer ****FAILED****.\n");
4958 qla2x00_free_exchoffld_buffer(ha);
4959 } else {
4960 /* re-adjust number of target exchange */
4961 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4962
4963 if (qla_ini_mode_enabled(vha))
4964 icb->exchange_count = 0;
4965 else
4966 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4967 }
4968
4969 return rval;
4970 }
4971
4972 /*
4973 * qla2x00_free_exchoffld_buffer
4974 *
4975 * Input:
4976 * ha = adapter block pointer
4977 */
4978 void
qla2x00_free_exchoffld_buffer(struct qla_hw_data * ha)4979 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4980 {
4981 if (ha->exchoffld_buf) {
4982 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4983 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4984 ha->exchoffld_buf = NULL;
4985 ha->exchoffld_size = 0;
4986 }
4987 }
4988
4989 /*
4990 * qla2x00_free_fw_dump
4991 * Frees fw dump stuff.
4992 *
4993 * Input:
4994 * ha = adapter block pointer
4995 */
4996 static void
qla2x00_free_fw_dump(struct qla_hw_data * ha)4997 qla2x00_free_fw_dump(struct qla_hw_data *ha)
4998 {
4999 struct fwdt *fwdt = ha->fwdt;
5000 uint j;
5001
5002 if (ha->fce)
5003 dma_free_coherent(&ha->pdev->dev,
5004 FCE_SIZE, ha->fce, ha->fce_dma);
5005
5006 if (ha->eft)
5007 dma_free_coherent(&ha->pdev->dev,
5008 EFT_SIZE, ha->eft, ha->eft_dma);
5009
5010 vfree(ha->fw_dump);
5011
5012 ha->fce = NULL;
5013 ha->fce_dma = 0;
5014 ha->flags.fce_enabled = 0;
5015 ha->eft = NULL;
5016 ha->eft_dma = 0;
5017 ha->fw_dumped = false;
5018 ha->fw_dump_cap_flags = 0;
5019 ha->fw_dump_reading = 0;
5020 ha->fw_dump = NULL;
5021 ha->fw_dump_len = 0;
5022
5023 for (j = 0; j < 2; j++, fwdt++) {
5024 vfree(fwdt->template);
5025 fwdt->template = NULL;
5026 fwdt->length = 0;
5027 }
5028 }
5029
5030 /*
5031 * qla2x00_mem_free
5032 * Frees all adapter allocated memory.
5033 *
5034 * Input:
5035 * ha = adapter block pointer.
5036 */
5037 static void
qla2x00_mem_free(struct qla_hw_data * ha)5038 qla2x00_mem_free(struct qla_hw_data *ha)
5039 {
5040 qla2x00_free_fw_dump(ha);
5041
5042 if (ha->mctp_dump)
5043 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
5044 ha->mctp_dump_dma);
5045 ha->mctp_dump = NULL;
5046
5047 mempool_destroy(ha->srb_mempool);
5048 ha->srb_mempool = NULL;
5049
5050 if (ha->dcbx_tlv)
5051 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
5052 ha->dcbx_tlv, ha->dcbx_tlv_dma);
5053 ha->dcbx_tlv = NULL;
5054
5055 if (ha->xgmac_data)
5056 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
5057 ha->xgmac_data, ha->xgmac_data_dma);
5058 ha->xgmac_data = NULL;
5059
5060 if (ha->sns_cmd)
5061 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
5062 ha->sns_cmd, ha->sns_cmd_dma);
5063 ha->sns_cmd = NULL;
5064 ha->sns_cmd_dma = 0;
5065
5066 if (ha->ct_sns)
5067 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
5068 ha->ct_sns, ha->ct_sns_dma);
5069 ha->ct_sns = NULL;
5070 ha->ct_sns_dma = 0;
5071
5072 if (ha->sfp_data)
5073 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
5074 ha->sfp_data_dma);
5075 ha->sfp_data = NULL;
5076
5077 if (ha->flt)
5078 dma_free_coherent(&ha->pdev->dev,
5079 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE,
5080 ha->flt, ha->flt_dma);
5081 ha->flt = NULL;
5082 ha->flt_dma = 0;
5083
5084 if (ha->flt_data)
5085 vfree(ha->flt_data);
5086 ha->flt_data = NULL;
5087
5088 if (ha->ms_iocb)
5089 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
5090 ha->ms_iocb = NULL;
5091 ha->ms_iocb_dma = 0;
5092
5093 if (ha->sf_init_cb)
5094 dma_pool_free(ha->s_dma_pool,
5095 ha->sf_init_cb, ha->sf_init_cb_dma);
5096
5097 if (ha->ex_init_cb)
5098 dma_pool_free(ha->s_dma_pool,
5099 ha->ex_init_cb, ha->ex_init_cb_dma);
5100 ha->ex_init_cb = NULL;
5101 ha->ex_init_cb_dma = 0;
5102
5103 if (ha->async_pd)
5104 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5105 ha->async_pd = NULL;
5106 ha->async_pd_dma = 0;
5107
5108 dma_pool_destroy(ha->s_dma_pool);
5109 ha->s_dma_pool = NULL;
5110
5111 if (ha->gid_list)
5112 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
5113 ha->gid_list, ha->gid_list_dma);
5114 ha->gid_list = NULL;
5115 ha->gid_list_dma = 0;
5116
5117 if (ha->base_qpair && !list_empty(&ha->base_qpair->dsd_list)) {
5118 struct dsd_dma *dsd_ptr, *tdsd_ptr;
5119
5120 /* clean up allocated prev pool */
5121 list_for_each_entry_safe(dsd_ptr, tdsd_ptr,
5122 &ha->base_qpair->dsd_list, list) {
5123 dma_pool_free(ha->dl_dma_pool, dsd_ptr->dsd_addr,
5124 dsd_ptr->dsd_list_dma);
5125 list_del(&dsd_ptr->list);
5126 kfree(dsd_ptr);
5127 }
5128 }
5129
5130 dma_pool_destroy(ha->dl_dma_pool);
5131 ha->dl_dma_pool = NULL;
5132
5133 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
5134 ha->fcp_cmnd_dma_pool = NULL;
5135
5136 mempool_destroy(ha->ctx_mempool);
5137 ha->ctx_mempool = NULL;
5138
5139 if (ql2xenabledif && ha->dif_bundl_pool) {
5140 struct dsd_dma *dsd, *nxt;
5141
5142 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
5143 list) {
5144 list_del(&dsd->list);
5145 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
5146 dsd->dsd_list_dma);
5147 ha->dif_bundle_dma_allocs--;
5148 kfree(dsd);
5149 ha->dif_bundle_kallocs--;
5150 ha->pool.unusable.count--;
5151 }
5152 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) {
5153 list_del(&dsd->list);
5154 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
5155 dsd->dsd_list_dma);
5156 ha->dif_bundle_dma_allocs--;
5157 kfree(dsd);
5158 ha->dif_bundle_kallocs--;
5159 }
5160 }
5161
5162 dma_pool_destroy(ha->dif_bundl_pool);
5163 ha->dif_bundl_pool = NULL;
5164
5165 qlt_mem_free(ha);
5166 qla_remove_hostmap(ha);
5167
5168 if (ha->init_cb)
5169 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
5170 ha->init_cb, ha->init_cb_dma);
5171
5172 dma_pool_destroy(ha->purex_dma_pool);
5173 ha->purex_dma_pool = NULL;
5174
5175 if (ha->elsrej.c) {
5176 dma_free_coherent(&ha->pdev->dev, ha->elsrej.size,
5177 ha->elsrej.c, ha->elsrej.cdma);
5178 ha->elsrej.c = NULL;
5179 }
5180
5181 if (ha->lsrjt.c) {
5182 dma_free_coherent(&ha->pdev->dev, ha->lsrjt.size, ha->lsrjt.c,
5183 ha->lsrjt.cdma);
5184 ha->lsrjt.c = NULL;
5185 }
5186
5187 ha->init_cb = NULL;
5188 ha->init_cb_dma = 0;
5189
5190 vfree(ha->optrom_buffer);
5191 ha->optrom_buffer = NULL;
5192 kfree(ha->nvram);
5193 ha->nvram = NULL;
5194 ha->fiv = NULL;
5195 kfree(ha->npiv_info);
5196 ha->npiv_info = NULL;
5197 kfree(ha->swl);
5198 ha->swl = NULL;
5199 kfree(ha->loop_id_map);
5200 ha->sf_init_cb = NULL;
5201 ha->sf_init_cb_dma = 0;
5202 ha->loop_id_map = NULL;
5203
5204 kfree(ha->vp_map);
5205 ha->vp_map = NULL;
5206 }
5207
qla2x00_create_host(const struct scsi_host_template * sht,struct qla_hw_data * ha)5208 struct scsi_qla_host *qla2x00_create_host(const struct scsi_host_template *sht,
5209 struct qla_hw_data *ha)
5210 {
5211 struct Scsi_Host *host;
5212 struct scsi_qla_host *vha = NULL;
5213
5214 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
5215 if (!host) {
5216 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
5217 "Failed to allocate host from the scsi layer, aborting.\n");
5218 return NULL;
5219 }
5220
5221 /* Clear our data area */
5222 vha = shost_priv(host);
5223 memset(vha, 0, sizeof(scsi_qla_host_t));
5224
5225 vha->host = host;
5226 vha->host_no = host->host_no;
5227 vha->hw = ha;
5228
5229 vha->qlini_mode = ql2x_ini_mode;
5230 vha->ql2xexchoffld = ql2xexchoffld;
5231 vha->ql2xiniexchg = ql2xiniexchg;
5232
5233 INIT_LIST_HEAD(&vha->vp_fcports);
5234 INIT_LIST_HEAD(&vha->work_list);
5235 INIT_LIST_HEAD(&vha->list);
5236 INIT_LIST_HEAD(&vha->qla_cmd_list);
5237 INIT_LIST_HEAD(&vha->logo_list);
5238 INIT_LIST_HEAD(&vha->plogi_ack_list);
5239 INIT_LIST_HEAD(&vha->qp_list);
5240 INIT_LIST_HEAD(&vha->gnl.fcports);
5241 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn);
5242
5243 INIT_LIST_HEAD(&vha->purex_list.head);
5244 spin_lock_init(&vha->purex_list.lock);
5245
5246 spin_lock_init(&vha->work_lock);
5247 spin_lock_init(&vha->cmd_list_lock);
5248 init_waitqueue_head(&vha->fcport_waitQ);
5249 init_waitqueue_head(&vha->vref_waitq);
5250 qla_enode_init(vha);
5251 qla_edb_init(vha);
5252
5253
5254 vha->gnl.size = sizeof(struct get_name_list_extended) *
5255 (ha->max_loop_id + 1);
5256 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
5257 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
5258 if (!vha->gnl.l) {
5259 ql_log(ql_log_fatal, vha, 0xd04a,
5260 "Alloc failed for name list.\n");
5261 scsi_host_put(vha->host);
5262 return NULL;
5263 }
5264
5265 /* todo: what about ext login? */
5266 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp);
5267 vha->scan.l = vmalloc(vha->scan.size);
5268 if (!vha->scan.l) {
5269 ql_log(ql_log_fatal, vha, 0xd04a,
5270 "Alloc failed for scan database.\n");
5271 dma_free_coherent(&ha->pdev->dev, vha->gnl.size,
5272 vha->gnl.l, vha->gnl.ldma);
5273 vha->gnl.l = NULL;
5274 scsi_host_put(vha->host);
5275 return NULL;
5276 }
5277 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn);
5278
5279 snprintf(vha->host_str, sizeof(vha->host_str), "%s_%lu",
5280 QLA2XXX_DRIVER_NAME, vha->host_no);
5281 ql_dbg(ql_dbg_init, vha, 0x0041,
5282 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
5283 vha->host, vha->hw, vha,
5284 dev_name(&(ha->pdev->dev)));
5285
5286 return vha;
5287 }
5288
5289 struct qla_work_evt *
qla2x00_alloc_work(struct scsi_qla_host * vha,enum qla_work_type type)5290 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
5291 {
5292 struct qla_work_evt *e;
5293
5294 if (test_bit(UNLOADING, &vha->dpc_flags))
5295 return NULL;
5296
5297 if (qla_vha_mark_busy(vha))
5298 return NULL;
5299
5300 e = kzalloc_obj(struct qla_work_evt, GFP_ATOMIC);
5301 if (!e) {
5302 QLA_VHA_MARK_NOT_BUSY(vha);
5303 return NULL;
5304 }
5305
5306 INIT_LIST_HEAD(&e->list);
5307 e->type = type;
5308 e->flags = QLA_EVT_FLAG_FREE;
5309 return e;
5310 }
5311
5312 int
qla2x00_post_work(struct scsi_qla_host * vha,struct qla_work_evt * e)5313 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
5314 {
5315 unsigned long flags;
5316 bool q = false;
5317
5318 spin_lock_irqsave(&vha->work_lock, flags);
5319 list_add_tail(&e->list, &vha->work_list);
5320
5321 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
5322 q = true;
5323
5324 spin_unlock_irqrestore(&vha->work_lock, flags);
5325
5326 if (q)
5327 queue_work(vha->hw->wq, &vha->iocb_work);
5328
5329 return QLA_SUCCESS;
5330 }
5331
5332 int
qla2x00_post_aen_work(struct scsi_qla_host * vha,enum fc_host_event_code code,u32 data)5333 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
5334 u32 data)
5335 {
5336 struct qla_work_evt *e;
5337
5338 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
5339 if (!e)
5340 return QLA_FUNCTION_FAILED;
5341
5342 e->u.aen.code = code;
5343 e->u.aen.data = data;
5344 return qla2x00_post_work(vha, e);
5345 }
5346
5347 int
qla2x00_post_idc_ack_work(struct scsi_qla_host * vha,uint16_t * mb)5348 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
5349 {
5350 struct qla_work_evt *e;
5351
5352 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
5353 if (!e)
5354 return QLA_FUNCTION_FAILED;
5355
5356 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
5357 return qla2x00_post_work(vha, e);
5358 }
5359
5360 #define qla2x00_post_async_work(name, type) \
5361 int qla2x00_post_async_##name##_work( \
5362 struct scsi_qla_host *vha, \
5363 fc_port_t *fcport, uint16_t *data) \
5364 { \
5365 struct qla_work_evt *e; \
5366 \
5367 e = qla2x00_alloc_work(vha, type); \
5368 if (!e) \
5369 return QLA_FUNCTION_FAILED; \
5370 \
5371 e->u.logio.fcport = fcport; \
5372 if (data) { \
5373 e->u.logio.data[0] = data[0]; \
5374 e->u.logio.data[1] = data[1]; \
5375 } \
5376 fcport->flags |= FCF_ASYNC_ACTIVE; \
5377 return qla2x00_post_work(vha, e); \
5378 }
5379
5380 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
5381 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
5382 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
5383 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO);
5384 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE);
5385
5386 int
qla2x00_post_uevent_work(struct scsi_qla_host * vha,u32 code)5387 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
5388 {
5389 struct qla_work_evt *e;
5390
5391 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
5392 if (!e)
5393 return QLA_FUNCTION_FAILED;
5394
5395 e->u.uevent.code = code;
5396 return qla2x00_post_work(vha, e);
5397 }
5398
5399 static void
qla2x00_uevent_emit(struct scsi_qla_host * vha,u32 code)5400 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
5401 {
5402 char event_string[40];
5403 char *envp[] = { event_string, NULL };
5404
5405 switch (code) {
5406 case QLA_UEVENT_CODE_FW_DUMP:
5407 snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu",
5408 vha->host_no);
5409 break;
5410 default:
5411 /* do nothing */
5412 break;
5413 }
5414 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
5415 }
5416
5417 int
qlafx00_post_aenfx_work(struct scsi_qla_host * vha,uint32_t evtcode,uint32_t * data,int cnt)5418 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
5419 uint32_t *data, int cnt)
5420 {
5421 struct qla_work_evt *e;
5422
5423 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
5424 if (!e)
5425 return QLA_FUNCTION_FAILED;
5426
5427 e->u.aenfx.evtcode = evtcode;
5428 e->u.aenfx.count = cnt;
5429 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
5430 return qla2x00_post_work(vha, e);
5431 }
5432
qla24xx_sched_upd_fcport(fc_port_t * fcport)5433 void qla24xx_sched_upd_fcport(fc_port_t *fcport)
5434 {
5435 unsigned long flags;
5436
5437 if (IS_SW_RESV_ADDR(fcport->d_id))
5438 return;
5439
5440 spin_lock_irqsave(&fcport->vha->work_lock, flags);
5441 if (fcport->disc_state == DSC_UPD_FCPORT) {
5442 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5443 return;
5444 }
5445 fcport->jiffies_at_registration = jiffies;
5446 fcport->sec_since_registration = 0;
5447 fcport->next_disc_state = DSC_DELETED;
5448 qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT);
5449 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5450
5451 queue_work(system_dfl_wq, &fcport->reg_work);
5452 }
5453
5454 static
qla24xx_create_new_sess(struct scsi_qla_host * vha,struct qla_work_evt * e)5455 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
5456 {
5457 unsigned long flags;
5458 fc_port_t *fcport = NULL, *tfcp;
5459 struct qlt_plogi_ack_t *pla =
5460 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
5461 uint8_t free_fcport = 0;
5462
5463 ql_dbg(ql_dbg_disc, vha, 0xffff,
5464 "%s %d %8phC enter\n",
5465 __func__, __LINE__, e->u.new_sess.port_name);
5466
5467 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5468 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
5469 if (fcport) {
5470 fcport->d_id = e->u.new_sess.id;
5471 if (pla) {
5472 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
5473 memcpy(fcport->node_name,
5474 pla->iocb.u.isp24.u.plogi.node_name,
5475 WWN_SIZE);
5476 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
5477 /* we took an extra ref_count to prevent PLOGI ACK when
5478 * fcport/sess has not been created.
5479 */
5480 pla->ref_count--;
5481 }
5482 } else {
5483 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5484 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
5485 if (fcport) {
5486 fcport->d_id = e->u.new_sess.id;
5487 fcport->flags |= FCF_FABRIC_DEVICE;
5488 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
5489 fcport->tgt_short_link_down_cnt = 0;
5490
5491 memcpy(fcport->port_name, e->u.new_sess.port_name,
5492 WWN_SIZE);
5493
5494 fcport->fc4_type = e->u.new_sess.fc4_type;
5495 if (NVME_PRIORITY(vha->hw, fcport))
5496 fcport->do_prli_nvme = 1;
5497 else
5498 fcport->do_prli_nvme = 0;
5499
5500 if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) {
5501 fcport->dm_login_expire = jiffies +
5502 QLA_N2N_WAIT_TIME * HZ;
5503 fcport->fc4_type = FS_FC4TYPE_FCP;
5504 fcport->n2n_flag = 1;
5505 if (vha->flags.nvme_enabled)
5506 fcport->fc4_type |= FS_FC4TYPE_NVME;
5507 }
5508
5509 } else {
5510 ql_dbg(ql_dbg_disc, vha, 0xffff,
5511 "%s %8phC mem alloc fail.\n",
5512 __func__, e->u.new_sess.port_name);
5513
5514 if (pla) {
5515 list_del(&pla->list);
5516 kmem_cache_free(qla_tgt_plogi_cachep, pla);
5517 }
5518 return;
5519 }
5520
5521 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5522 /* search again to make sure no one else got ahead */
5523 tfcp = qla2x00_find_fcport_by_wwpn(vha,
5524 e->u.new_sess.port_name, 1);
5525 if (tfcp) {
5526 /* should rarily happen */
5527 ql_dbg(ql_dbg_disc, vha, 0xffff,
5528 "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
5529 __func__, tfcp->port_name, tfcp->disc_state,
5530 tfcp->fw_login_state);
5531
5532 free_fcport = 1;
5533 } else {
5534 list_add_tail(&fcport->list, &vha->vp_fcports);
5535
5536 }
5537 if (pla) {
5538 qlt_plogi_ack_link(vha, pla, fcport,
5539 QLT_PLOGI_LINK_SAME_WWN);
5540 pla->ref_count--;
5541 }
5542 }
5543 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5544
5545 if (fcport) {
5546 fcport->id_changed = 1;
5547 fcport->scan_state = QLA_FCPORT_FOUND;
5548 fcport->chip_reset = vha->hw->base_qpair->chip_reset;
5549 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE);
5550
5551 if (pla) {
5552 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) {
5553 u16 wd3_lo;
5554
5555 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5556 fcport->local = 0;
5557 fcport->loop_id =
5558 le16_to_cpu(
5559 pla->iocb.u.isp24.nport_handle);
5560 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5561 wd3_lo =
5562 le16_to_cpu(
5563 pla->iocb.u.isp24.u.prli.wd3_lo);
5564
5565 if (wd3_lo & BIT_7)
5566 fcport->conf_compl_supported = 1;
5567
5568 if ((wd3_lo & BIT_4) == 0)
5569 fcport->port_type = FCT_INITIATOR;
5570 else
5571 fcport->port_type = FCT_TARGET;
5572 }
5573 qlt_plogi_ack_unref(vha, pla);
5574 } else {
5575 fc_port_t *dfcp = NULL;
5576
5577 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5578 tfcp = qla2x00_find_fcport_by_nportid(vha,
5579 &e->u.new_sess.id, 1);
5580 if (tfcp && (tfcp != fcport)) {
5581 /*
5582 * We have a conflict fcport with same NportID.
5583 */
5584 ql_dbg(ql_dbg_disc, vha, 0xffff,
5585 "%s %8phC found conflict b4 add. DS %d LS %d\n",
5586 __func__, tfcp->port_name, tfcp->disc_state,
5587 tfcp->fw_login_state);
5588
5589 switch (tfcp->disc_state) {
5590 case DSC_DELETED:
5591 break;
5592 case DSC_DELETE_PEND:
5593 fcport->login_pause = 1;
5594 tfcp->conflict = fcport;
5595 break;
5596 default:
5597 fcport->login_pause = 1;
5598 tfcp->conflict = fcport;
5599 dfcp = tfcp;
5600 break;
5601 }
5602 }
5603 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5604 if (dfcp)
5605 qlt_schedule_sess_for_deletion(tfcp);
5606
5607 if (N2N_TOPO(vha->hw)) {
5608 fcport->flags &= ~FCF_FABRIC_DEVICE;
5609 fcport->keep_nport_handle = 1;
5610 if (vha->flags.nvme_enabled) {
5611 fcport->fc4_type =
5612 (FS_FC4TYPE_NVME | FS_FC4TYPE_FCP);
5613 fcport->n2n_flag = 1;
5614 }
5615 fcport->fw_login_state = 0;
5616
5617 schedule_delayed_work(&vha->scan.scan_work, 5);
5618 } else {
5619 qla24xx_fcport_handle_login(vha, fcport);
5620 }
5621 }
5622 }
5623
5624 if (free_fcport) {
5625 qla2x00_free_fcport(fcport);
5626 if (pla) {
5627 list_del(&pla->list);
5628 kmem_cache_free(qla_tgt_plogi_cachep, pla);
5629 }
5630 }
5631 }
5632
qla_sp_retry(struct scsi_qla_host * vha,struct qla_work_evt * e)5633 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e)
5634 {
5635 struct srb *sp = e->u.iosb.sp;
5636 int rval;
5637
5638 rval = qla2x00_start_sp(sp);
5639 if (rval != QLA_SUCCESS) {
5640 ql_dbg(ql_dbg_disc, vha, 0x2043,
5641 "%s: %s: Re-issue IOCB failed (%d).\n",
5642 __func__, sp->name, rval);
5643 qla24xx_sp_unmap(vha, sp);
5644 }
5645 }
5646
5647 void
qla2x00_do_work(struct scsi_qla_host * vha)5648 qla2x00_do_work(struct scsi_qla_host *vha)
5649 {
5650 struct qla_work_evt *e, *tmp;
5651 unsigned long flags;
5652 LIST_HEAD(work);
5653 int rc;
5654
5655 spin_lock_irqsave(&vha->work_lock, flags);
5656 list_splice_init(&vha->work_list, &work);
5657 spin_unlock_irqrestore(&vha->work_lock, flags);
5658
5659 list_for_each_entry_safe(e, tmp, &work, list) {
5660 rc = QLA_SUCCESS;
5661 switch (e->type) {
5662 case QLA_EVT_AEN:
5663 fc_host_post_event(vha->host, fc_get_event_number(),
5664 e->u.aen.code, e->u.aen.data);
5665 break;
5666 case QLA_EVT_IDC_ACK:
5667 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
5668 break;
5669 case QLA_EVT_ASYNC_LOGIN:
5670 qla2x00_async_login(vha, e->u.logio.fcport,
5671 e->u.logio.data);
5672 break;
5673 case QLA_EVT_ASYNC_LOGOUT:
5674 rc = qla2x00_async_logout(vha, e->u.logio.fcport);
5675 break;
5676 case QLA_EVT_ASYNC_ADISC:
5677 qla2x00_async_adisc(vha, e->u.logio.fcport,
5678 e->u.logio.data);
5679 break;
5680 case QLA_EVT_UEVENT:
5681 qla2x00_uevent_emit(vha, e->u.uevent.code);
5682 break;
5683 case QLA_EVT_AENFX:
5684 qlafx00_process_aen(vha, e);
5685 break;
5686 case QLA_EVT_UNMAP:
5687 qla24xx_sp_unmap(vha, e->u.iosb.sp);
5688 break;
5689 case QLA_EVT_RELOGIN:
5690 qla2x00_relogin(vha);
5691 break;
5692 case QLA_EVT_NEW_SESS:
5693 qla24xx_create_new_sess(vha, e);
5694 break;
5695 case QLA_EVT_GPDB:
5696 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
5697 e->u.fcport.opt);
5698 break;
5699 case QLA_EVT_PRLI:
5700 qla24xx_async_prli(vha, e->u.fcport.fcport);
5701 break;
5702 case QLA_EVT_GPSC:
5703 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
5704 break;
5705 case QLA_EVT_GNL:
5706 qla24xx_async_gnl(vha, e->u.fcport.fcport);
5707 break;
5708 case QLA_EVT_NACK:
5709 qla24xx_do_nack_work(vha, e);
5710 break;
5711 case QLA_EVT_ASYNC_PRLO:
5712 rc = qla2x00_async_prlo(vha, e->u.logio.fcport);
5713 break;
5714 case QLA_EVT_ASYNC_PRLO_DONE:
5715 qla2x00_async_prlo_done(vha, e->u.logio.fcport,
5716 e->u.logio.data);
5717 break;
5718 case QLA_EVT_SCAN_CMD:
5719 qla_fab_async_scan(vha, e->u.iosb.sp);
5720 break;
5721 case QLA_EVT_SCAN_FINISH:
5722 qla_fab_scan_finish(vha, e->u.iosb.sp);
5723 break;
5724 case QLA_EVT_GFPNID:
5725 qla24xx_async_gfpnid(vha, e->u.fcport.fcport);
5726 break;
5727 case QLA_EVT_SP_RETRY:
5728 qla_sp_retry(vha, e);
5729 break;
5730 case QLA_EVT_IIDMA:
5731 qla_do_iidma_work(vha, e->u.fcport.fcport);
5732 break;
5733 case QLA_EVT_ELS_PLOGI:
5734 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI,
5735 e->u.fcport.fcport);
5736 break;
5737 case QLA_EVT_SA_REPLACE:
5738 rc = qla24xx_issue_sa_replace_iocb(vha, e);
5739 break;
5740 }
5741
5742 if (rc == EAGAIN) {
5743 /* put 'work' at head of 'vha->work_list' */
5744 spin_lock_irqsave(&vha->work_lock, flags);
5745 list_splice(&work, &vha->work_list);
5746 spin_unlock_irqrestore(&vha->work_lock, flags);
5747 break;
5748 }
5749 list_del_init(&e->list);
5750 if (e->flags & QLA_EVT_FLAG_FREE)
5751 kfree(e);
5752
5753 /* For each work completed decrement vha ref count */
5754 QLA_VHA_MARK_NOT_BUSY(vha);
5755 }
5756 }
5757
qla24xx_post_relogin_work(struct scsi_qla_host * vha)5758 int qla24xx_post_relogin_work(struct scsi_qla_host *vha)
5759 {
5760 struct qla_work_evt *e;
5761
5762 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN);
5763
5764 if (!e) {
5765 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5766 return QLA_FUNCTION_FAILED;
5767 }
5768
5769 return qla2x00_post_work(vha, e);
5770 }
5771
5772 /* Relogins all the fcports of a vport
5773 * Context: dpc thread
5774 */
qla2x00_relogin(struct scsi_qla_host * vha)5775 void qla2x00_relogin(struct scsi_qla_host *vha)
5776 {
5777 fc_port_t *fcport;
5778 int status, relogin_needed = 0;
5779 struct event_arg ea;
5780
5781 list_for_each_entry(fcport, &vha->vp_fcports, list) {
5782 /*
5783 * If the port is not ONLINE then try to login
5784 * to it if we haven't run out of retries.
5785 */
5786 if (atomic_read(&fcport->state) != FCS_ONLINE &&
5787 fcport->login_retry) {
5788 if (fcport->scan_state != QLA_FCPORT_FOUND ||
5789 fcport->disc_state == DSC_LOGIN_AUTH_PEND ||
5790 fcport->disc_state == DSC_LOGIN_COMPLETE)
5791 continue;
5792
5793 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) ||
5794 fcport->disc_state == DSC_DELETE_PEND) {
5795 relogin_needed = 1;
5796 } else {
5797 if (vha->hw->current_topology != ISP_CFG_NL) {
5798 memset(&ea, 0, sizeof(ea));
5799 ea.fcport = fcport;
5800 qla24xx_handle_relogin_event(vha, &ea);
5801 } else if (vha->hw->current_topology ==
5802 ISP_CFG_NL &&
5803 IS_QLA2XXX_MIDTYPE(vha->hw)) {
5804 (void)qla24xx_fcport_handle_login(vha,
5805 fcport);
5806 } else if (vha->hw->current_topology ==
5807 ISP_CFG_NL) {
5808 fcport->login_retry--;
5809 status =
5810 qla2x00_local_device_login(vha,
5811 fcport);
5812 if (status == QLA_SUCCESS) {
5813 fcport->old_loop_id =
5814 fcport->loop_id;
5815 ql_dbg(ql_dbg_disc, vha, 0x2003,
5816 "Port login OK: logged in ID 0x%x.\n",
5817 fcport->loop_id);
5818 qla2x00_update_fcport
5819 (vha, fcport);
5820 } else if (status == 1) {
5821 set_bit(RELOGIN_NEEDED,
5822 &vha->dpc_flags);
5823 /* retry the login again */
5824 ql_dbg(ql_dbg_disc, vha, 0x2007,
5825 "Retrying %d login again loop_id 0x%x.\n",
5826 fcport->login_retry,
5827 fcport->loop_id);
5828 } else {
5829 fcport->login_retry = 0;
5830 }
5831
5832 if (fcport->login_retry == 0 &&
5833 status != QLA_SUCCESS)
5834 qla2x00_clear_loop_id(fcport);
5835 }
5836 }
5837 }
5838 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5839 break;
5840 }
5841
5842 if (relogin_needed)
5843 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5844
5845 ql_dbg(ql_dbg_disc, vha, 0x400e,
5846 "Relogin end.\n");
5847 }
5848
5849 /* Schedule work on any of the dpc-workqueues */
5850 void
qla83xx_schedule_work(scsi_qla_host_t * base_vha,int work_code)5851 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
5852 {
5853 struct qla_hw_data *ha = base_vha->hw;
5854
5855 switch (work_code) {
5856 case MBA_IDC_AEN: /* 0x8200 */
5857 if (ha->dpc_lp_wq)
5858 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
5859 break;
5860
5861 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
5862 if (!ha->flags.nic_core_reset_hdlr_active) {
5863 if (ha->dpc_hp_wq)
5864 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
5865 } else
5866 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
5867 "NIC Core reset is already active. Skip "
5868 "scheduling it again.\n");
5869 break;
5870 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
5871 if (ha->dpc_hp_wq)
5872 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
5873 break;
5874 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
5875 if (ha->dpc_hp_wq)
5876 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
5877 break;
5878 default:
5879 ql_log(ql_log_warn, base_vha, 0xb05f,
5880 "Unknown work-code=0x%x.\n", work_code);
5881 }
5882
5883 return;
5884 }
5885
5886 /* Work: Perform NIC Core Unrecoverable state handling */
5887 void
qla83xx_nic_core_unrecoverable_work(struct work_struct * work)5888 qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
5889 {
5890 struct qla_hw_data *ha =
5891 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
5892 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5893 uint32_t dev_state = 0;
5894
5895 qla83xx_idc_lock(base_vha, 0);
5896 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5897 qla83xx_reset_ownership(base_vha);
5898 if (ha->flags.nic_core_reset_owner) {
5899 ha->flags.nic_core_reset_owner = 0;
5900 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5901 QLA8XXX_DEV_FAILED);
5902 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
5903 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5904 }
5905 qla83xx_idc_unlock(base_vha, 0);
5906 }
5907
5908 /* Work: Execute IDC state handler */
5909 void
qla83xx_idc_state_handler_work(struct work_struct * work)5910 qla83xx_idc_state_handler_work(struct work_struct *work)
5911 {
5912 struct qla_hw_data *ha =
5913 container_of(work, struct qla_hw_data, idc_state_handler);
5914 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5915 uint32_t dev_state = 0;
5916
5917 qla83xx_idc_lock(base_vha, 0);
5918 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5919 if (dev_state == QLA8XXX_DEV_FAILED ||
5920 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
5921 qla83xx_idc_state_handler(base_vha);
5922 qla83xx_idc_unlock(base_vha, 0);
5923 }
5924
5925 static int
qla83xx_check_nic_core_fw_alive(scsi_qla_host_t * base_vha)5926 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
5927 {
5928 int rval = QLA_SUCCESS;
5929 unsigned long heart_beat_wait = jiffies + (1 * HZ);
5930 uint32_t heart_beat_counter1, heart_beat_counter2;
5931
5932 do {
5933 if (time_after(jiffies, heart_beat_wait)) {
5934 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
5935 "Nic Core f/w is not alive.\n");
5936 rval = QLA_FUNCTION_FAILED;
5937 break;
5938 }
5939
5940 qla83xx_idc_lock(base_vha, 0);
5941 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5942 &heart_beat_counter1);
5943 qla83xx_idc_unlock(base_vha, 0);
5944 msleep(100);
5945 qla83xx_idc_lock(base_vha, 0);
5946 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5947 &heart_beat_counter2);
5948 qla83xx_idc_unlock(base_vha, 0);
5949 } while (heart_beat_counter1 == heart_beat_counter2);
5950
5951 return rval;
5952 }
5953
5954 /* Work: Perform NIC Core Reset handling */
5955 void
qla83xx_nic_core_reset_work(struct work_struct * work)5956 qla83xx_nic_core_reset_work(struct work_struct *work)
5957 {
5958 struct qla_hw_data *ha =
5959 container_of(work, struct qla_hw_data, nic_core_reset);
5960 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5961 uint32_t dev_state = 0;
5962
5963 if (IS_QLA2031(ha)) {
5964 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
5965 ql_log(ql_log_warn, base_vha, 0xb081,
5966 "Failed to dump mctp\n");
5967 return;
5968 }
5969
5970 if (!ha->flags.nic_core_reset_hdlr_active) {
5971 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
5972 qla83xx_idc_lock(base_vha, 0);
5973 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5974 &dev_state);
5975 qla83xx_idc_unlock(base_vha, 0);
5976 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
5977 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
5978 "Nic Core f/w is alive.\n");
5979 return;
5980 }
5981 }
5982
5983 ha->flags.nic_core_reset_hdlr_active = 1;
5984 if (qla83xx_nic_core_reset(base_vha)) {
5985 /* NIC Core reset failed. */
5986 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5987 "NIC Core reset failed.\n");
5988 }
5989 ha->flags.nic_core_reset_hdlr_active = 0;
5990 }
5991 }
5992
5993 /* Work: Handle 8200 IDC aens */
5994 void
qla83xx_service_idc_aen(struct work_struct * work)5995 qla83xx_service_idc_aen(struct work_struct *work)
5996 {
5997 struct qla_hw_data *ha =
5998 container_of(work, struct qla_hw_data, idc_aen);
5999 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
6000 uint32_t dev_state, idc_control;
6001
6002 qla83xx_idc_lock(base_vha, 0);
6003 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
6004 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
6005 qla83xx_idc_unlock(base_vha, 0);
6006 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
6007 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
6008 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
6009 "Application requested NIC Core Reset.\n");
6010 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
6011 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
6012 QLA_SUCCESS) {
6013 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
6014 "Other protocol driver requested NIC Core Reset.\n");
6015 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
6016 }
6017 } else if (dev_state == QLA8XXX_DEV_FAILED ||
6018 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
6019 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
6020 }
6021 }
6022
6023 /*
6024 * Control the frequency of IDC lock retries
6025 */
6026 #define QLA83XX_WAIT_LOGIC_MS 100
6027
6028 static int
qla83xx_force_lock_recovery(scsi_qla_host_t * base_vha)6029 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
6030 {
6031 int rval;
6032 uint32_t data;
6033 uint32_t idc_lck_rcvry_stage_mask = 0x3;
6034 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
6035 struct qla_hw_data *ha = base_vha->hw;
6036
6037 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
6038 "Trying force recovery of the IDC lock.\n");
6039
6040 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
6041 if (rval)
6042 return rval;
6043
6044 if ((data & idc_lck_rcvry_stage_mask) > 0) {
6045 return QLA_SUCCESS;
6046 } else {
6047 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
6048 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
6049 data);
6050 if (rval)
6051 return rval;
6052
6053 msleep(200);
6054
6055 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
6056 &data);
6057 if (rval)
6058 return rval;
6059
6060 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
6061 data &= (IDC_LOCK_RECOVERY_STAGE2 |
6062 ~(idc_lck_rcvry_stage_mask));
6063 rval = qla83xx_wr_reg(base_vha,
6064 QLA83XX_IDC_LOCK_RECOVERY, data);
6065 if (rval)
6066 return rval;
6067
6068 /* Forcefully perform IDC UnLock */
6069 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
6070 &data);
6071 if (rval)
6072 return rval;
6073 /* Clear lock-id by setting 0xff */
6074 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
6075 0xff);
6076 if (rval)
6077 return rval;
6078 /* Clear lock-recovery by setting 0x0 */
6079 rval = qla83xx_wr_reg(base_vha,
6080 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
6081 if (rval)
6082 return rval;
6083 } else
6084 return QLA_SUCCESS;
6085 }
6086
6087 return rval;
6088 }
6089
6090 static int
qla83xx_idc_lock_recovery(scsi_qla_host_t * base_vha)6091 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
6092 {
6093 int rval = QLA_SUCCESS;
6094 uint32_t o_drv_lockid, n_drv_lockid;
6095 unsigned long lock_recovery_timeout;
6096
6097 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
6098 retry_lockid:
6099 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
6100 if (rval)
6101 goto exit;
6102
6103 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
6104 if (time_after_eq(jiffies, lock_recovery_timeout)) {
6105 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
6106 return QLA_SUCCESS;
6107 else
6108 return QLA_FUNCTION_FAILED;
6109 }
6110
6111 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
6112 if (rval)
6113 goto exit;
6114
6115 if (o_drv_lockid == n_drv_lockid) {
6116 msleep(QLA83XX_WAIT_LOGIC_MS);
6117 goto retry_lockid;
6118 } else
6119 return QLA_SUCCESS;
6120
6121 exit:
6122 return rval;
6123 }
6124
6125 /*
6126 * Context: task, can sleep
6127 */
6128 void
qla83xx_idc_lock(scsi_qla_host_t * base_vha,uint16_t requester_id)6129 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
6130 {
6131 uint32_t data;
6132 uint32_t lock_owner;
6133 struct qla_hw_data *ha = base_vha->hw;
6134
6135 might_sleep();
6136
6137 /* IDC-lock implementation using driver-lock/lock-id remote registers */
6138 retry_lock:
6139 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
6140 == QLA_SUCCESS) {
6141 if (data) {
6142 /* Setting lock-id to our function-number */
6143 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
6144 ha->portnum);
6145 } else {
6146 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
6147 &lock_owner);
6148 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6149 "Failed to acquire IDC lock, acquired by %d, "
6150 "retrying...\n", lock_owner);
6151
6152 /* Retry/Perform IDC-Lock recovery */
6153 if (qla83xx_idc_lock_recovery(base_vha)
6154 == QLA_SUCCESS) {
6155 msleep(QLA83XX_WAIT_LOGIC_MS);
6156 goto retry_lock;
6157 } else
6158 ql_log(ql_log_warn, base_vha, 0xb075,
6159 "IDC Lock recovery FAILED.\n");
6160 }
6161
6162 }
6163
6164 return;
6165 }
6166
6167 static bool
qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host * vha,void * pkt)6168 qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host *vha, void *pkt)
6169 {
6170 struct purex_entry_24xx *purex = pkt;
6171 char fwstr[16];
6172 u32 sid;
6173 struct port_database_24xx *pdb;
6174
6175 sid = purex->s_id[2] << 16 | purex->s_id[1] << 8 | purex->s_id[0];
6176
6177 /* Domain Controller is always logged-out. */
6178 /* if RDP request is not from Domain Controller: */
6179 if (sid != 0xfffc01)
6180 return false;
6181
6182 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: s_id=%#x\n", __func__, sid);
6183
6184 pdb = kzalloc_obj(*pdb);
6185 if (!pdb) {
6186 ql_dbg(ql_dbg_init, vha, 0x0181,
6187 "%s: Failed allocate pdb\n", __func__);
6188 } else if (qla24xx_get_port_database(vha,
6189 le16_to_cpu(purex->nport_handle), pdb)) {
6190 ql_dbg(ql_dbg_init, vha, 0x0181,
6191 "%s: Failed get pdb sid=%x\n", __func__, sid);
6192 } else if (pdb->current_login_state != PDS_PLOGI_COMPLETE &&
6193 pdb->current_login_state != PDS_PRLI_COMPLETE) {
6194 ql_dbg(ql_dbg_init, vha, 0x0181,
6195 "%s: Port not logged in sid=%#x\n", __func__, sid);
6196 } else {
6197 /* RDP request is from logged in port */
6198 kfree(pdb);
6199 return false;
6200 }
6201 kfree(pdb);
6202
6203 vha->hw->isp_ops->fw_version_str(vha, fwstr, sizeof(fwstr));
6204 fwstr[strcspn(fwstr, " ")] = 0;
6205 /* if FW version allows RDP response length upto 2048 bytes: */
6206 if (strcmp(fwstr, "8.09.00") > 0 || strcmp(fwstr, "8.05.65") == 0)
6207 return false;
6208
6209 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: fw=%s\n", __func__, fwstr);
6210
6211 /* RDP response length is to be reduced to maximum 256 bytes */
6212 return true;
6213 }
6214
6215 /*
6216 * Function Name: qla24xx_process_purex_iocb
6217 *
6218 * Description:
6219 * Prepare a RDP response and send to Fabric switch
6220 *
6221 * PARAMETERS:
6222 * vha: SCSI qla host
6223 * purex: RDP request received by HBA
6224 */
qla24xx_process_purex_rdp(struct scsi_qla_host * vha,struct purex_item * item)6225 void qla24xx_process_purex_rdp(struct scsi_qla_host *vha,
6226 struct purex_item *item)
6227 {
6228 struct qla_hw_data *ha = vha->hw;
6229 struct purex_entry_24xx *purex =
6230 (struct purex_entry_24xx *)&item->iocb;
6231 dma_addr_t rsp_els_dma;
6232 dma_addr_t rsp_payload_dma;
6233 dma_addr_t stat_dma;
6234 dma_addr_t sfp_dma;
6235 struct els_entry_24xx *rsp_els = NULL;
6236 struct rdp_rsp_payload *rsp_payload = NULL;
6237 struct link_statistics *stat = NULL;
6238 uint8_t *sfp = NULL;
6239 uint16_t sfp_flags = 0;
6240 uint rsp_payload_length = sizeof(*rsp_payload);
6241 u16 vp_idx;
6242 size_t purex_sz;
6243 size_t rsp_els_sz;
6244 void *rsp_els_pkt = NULL;
6245 int rval;
6246
6247 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0180,
6248 "%s: Enter\n", __func__);
6249
6250 if (IS_QLA29XX(ha)) {
6251 vp_idx = le16_to_cpu(
6252 ((struct purex_entry_24xx_ext *)purex)->vp_idx);
6253 purex_sz = sizeof(struct purex_entry_24xx_ext);
6254 } else {
6255 vp_idx = purex->vp_idx;
6256 purex_sz = sizeof(*purex);
6257 }
6258
6259 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0181,
6260 "-------- ELS REQ -------\n");
6261 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0182,
6262 purex, purex_sz);
6263
6264 if (qla25xx_rdp_rsp_reduce_size(vha, purex)) {
6265 rsp_payload_length =
6266 offsetof(typeof(*rsp_payload), optical_elmt_desc);
6267 ql_dbg(ql_dbg_init, vha, 0x0181,
6268 "Reducing RSP payload length to %u bytes...\n",
6269 rsp_payload_length);
6270 }
6271
6272 if (IS_QLA29XX(ha))
6273 rsp_els_sz = sizeof(struct els_entry_24xx_ext);
6274 else
6275 rsp_els_sz = sizeof(struct els_entry_24xx);
6276
6277 rsp_els_pkt = dma_alloc_coherent(&ha->pdev->dev, rsp_els_sz,
6278 &rsp_els_dma, GFP_KERNEL);
6279 if (!rsp_els_pkt) {
6280 ql_log(ql_log_warn, vha, 0x0183,
6281 "Failed to allocate dma buffer ELS RSP.\n");
6282 goto dealloc;
6283 }
6284 rsp_els = rsp_els_pkt;
6285
6286 rsp_payload = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_payload),
6287 &rsp_payload_dma, GFP_KERNEL);
6288 if (!rsp_payload) {
6289 ql_log(ql_log_warn, vha, 0x0184,
6290 "Failed allocate dma buffer ELS RSP payload.\n");
6291 goto dealloc;
6292 }
6293
6294 sfp = dma_alloc_coherent(&ha->pdev->dev, SFP_RTDI_LEN,
6295 &sfp_dma, GFP_KERNEL);
6296
6297 stat = dma_alloc_coherent(&ha->pdev->dev, sizeof(*stat),
6298 &stat_dma, GFP_KERNEL);
6299
6300 /* Prepare Response IOCB */
6301 rsp_els->entry_type = ELS_IOCB_TYPE;
6302 rsp_els->entry_count = 1;
6303 rsp_els->sys_define = 0;
6304 rsp_els->entry_status = 0;
6305 rsp_els->handle = 0;
6306 rsp_els->nport_handle = purex->nport_handle;
6307 rsp_els->tx_dsd_count = cpu_to_le16(1);
6308 rsp_els->rx_xchg_address = purex->rx_xchg_addr;
6309 rsp_els->rx_dsd_count = 0;
6310 rsp_els->opcode = purex->els_frame_payload[0];
6311
6312 qla_els_set_vp_sof(vha, rsp_els_pkt, vp_idx);
6313
6314 rsp_els->d_id[0] = purex->s_id[0];
6315 rsp_els->d_id[1] = purex->s_id[1];
6316 rsp_els->d_id[2] = purex->s_id[2];
6317
6318 rsp_els->control_flags = cpu_to_le16(EPD_ELS_ACC);
6319 rsp_els->rx_byte_count = 0;
6320 rsp_els->tx_byte_count = cpu_to_le32(rsp_payload_length);
6321
6322 put_unaligned_le64(rsp_payload_dma, &rsp_els->tx_address);
6323 rsp_els->tx_len = rsp_els->tx_byte_count;
6324
6325 rsp_els->rx_address = 0;
6326 rsp_els->rx_len = 0;
6327
6328 /* Prepare Response Payload */
6329 rsp_payload->hdr.cmd = cpu_to_be32(0x2 << 24); /* LS_ACC */
6330 rsp_payload->hdr.len = cpu_to_be32(le32_to_cpu(rsp_els->tx_byte_count) -
6331 sizeof(rsp_payload->hdr));
6332
6333 /* Link service Request Info Descriptor */
6334 rsp_payload->ls_req_info_desc.desc_tag = cpu_to_be32(0x1);
6335 rsp_payload->ls_req_info_desc.desc_len =
6336 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc));
6337 rsp_payload->ls_req_info_desc.req_payload_word_0 =
6338 cpu_to_be32p((uint32_t *)purex->els_frame_payload);
6339
6340 /* Link service Request Info Descriptor 2 */
6341 rsp_payload->ls_req_info_desc2.desc_tag = cpu_to_be32(0x1);
6342 rsp_payload->ls_req_info_desc2.desc_len =
6343 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc2));
6344 rsp_payload->ls_req_info_desc2.req_payload_word_0 =
6345 cpu_to_be32p((uint32_t *)purex->els_frame_payload);
6346
6347
6348 rsp_payload->sfp_diag_desc.desc_tag = cpu_to_be32(0x10000);
6349 rsp_payload->sfp_diag_desc.desc_len =
6350 cpu_to_be32(RDP_DESC_LEN(rsp_payload->sfp_diag_desc));
6351
6352 if (sfp) {
6353 /* SFP Flags */
6354 memset(sfp, 0, SFP_RTDI_LEN);
6355 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x7, 2, 0);
6356 if (!rval) {
6357 /* SFP Flags bits 3-0: Port Tx Laser Type */
6358 if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5))
6359 sfp_flags |= BIT_0; /* short wave */
6360 else if (sfp[0] & BIT_1)
6361 sfp_flags |= BIT_1; /* long wave 1310nm */
6362 else if (sfp[1] & BIT_4)
6363 sfp_flags |= BIT_1|BIT_0; /* long wave 1550nm */
6364 }
6365
6366 /* SFP Type */
6367 memset(sfp, 0, SFP_RTDI_LEN);
6368 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x0, 1, 0);
6369 if (!rval) {
6370 sfp_flags |= BIT_4; /* optical */
6371 if (sfp[0] == 0x3)
6372 sfp_flags |= BIT_6; /* sfp+ */
6373 }
6374
6375 rsp_payload->sfp_diag_desc.sfp_flags = cpu_to_be16(sfp_flags);
6376
6377 /* SFP Diagnostics */
6378 memset(sfp, 0, SFP_RTDI_LEN);
6379 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0x60, 10, 0);
6380 if (!rval) {
6381 __be16 *trx = (__force __be16 *)sfp; /* already be16 */
6382 rsp_payload->sfp_diag_desc.temperature = trx[0];
6383 rsp_payload->sfp_diag_desc.vcc = trx[1];
6384 rsp_payload->sfp_diag_desc.tx_bias = trx[2];
6385 rsp_payload->sfp_diag_desc.tx_power = trx[3];
6386 rsp_payload->sfp_diag_desc.rx_power = trx[4];
6387 }
6388 }
6389
6390 /* Port Speed Descriptor */
6391 rsp_payload->port_speed_desc.desc_tag = cpu_to_be32(0x10001);
6392 rsp_payload->port_speed_desc.desc_len =
6393 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_speed_desc));
6394 rsp_payload->port_speed_desc.speed_capab = cpu_to_be16(
6395 qla25xx_fdmi_port_speed_capability(ha));
6396 rsp_payload->port_speed_desc.operating_speed = cpu_to_be16(
6397 qla25xx_fdmi_port_speed_currently(ha));
6398
6399 /* Link Error Status Descriptor */
6400 rsp_payload->ls_err_desc.desc_tag = cpu_to_be32(0x10002);
6401 rsp_payload->ls_err_desc.desc_len =
6402 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_err_desc));
6403
6404 if (stat) {
6405 rval = qla24xx_get_isp_stats(vha, stat, stat_dma, 0);
6406 if (!rval) {
6407 rsp_payload->ls_err_desc.link_fail_cnt =
6408 cpu_to_be32(le32_to_cpu(stat->link_fail_cnt));
6409 rsp_payload->ls_err_desc.loss_sync_cnt =
6410 cpu_to_be32(le32_to_cpu(stat->loss_sync_cnt));
6411 rsp_payload->ls_err_desc.loss_sig_cnt =
6412 cpu_to_be32(le32_to_cpu(stat->loss_sig_cnt));
6413 rsp_payload->ls_err_desc.prim_seq_err_cnt =
6414 cpu_to_be32(le32_to_cpu(stat->prim_seq_err_cnt));
6415 rsp_payload->ls_err_desc.inval_xmit_word_cnt =
6416 cpu_to_be32(le32_to_cpu(stat->inval_xmit_word_cnt));
6417 rsp_payload->ls_err_desc.inval_crc_cnt =
6418 cpu_to_be32(le32_to_cpu(stat->inval_crc_cnt));
6419 rsp_payload->ls_err_desc.pn_port_phy_type |= BIT_6;
6420 }
6421 }
6422
6423 /* Portname Descriptor */
6424 rsp_payload->port_name_diag_desc.desc_tag = cpu_to_be32(0x10003);
6425 rsp_payload->port_name_diag_desc.desc_len =
6426 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_diag_desc));
6427 memcpy(rsp_payload->port_name_diag_desc.WWNN,
6428 vha->node_name,
6429 sizeof(rsp_payload->port_name_diag_desc.WWNN));
6430 memcpy(rsp_payload->port_name_diag_desc.WWPN,
6431 vha->port_name,
6432 sizeof(rsp_payload->port_name_diag_desc.WWPN));
6433
6434 /* F-Port Portname Descriptor */
6435 rsp_payload->port_name_direct_desc.desc_tag = cpu_to_be32(0x10003);
6436 rsp_payload->port_name_direct_desc.desc_len =
6437 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_direct_desc));
6438 memcpy(rsp_payload->port_name_direct_desc.WWNN,
6439 vha->fabric_node_name,
6440 sizeof(rsp_payload->port_name_direct_desc.WWNN));
6441 memcpy(rsp_payload->port_name_direct_desc.WWPN,
6442 vha->fabric_port_name,
6443 sizeof(rsp_payload->port_name_direct_desc.WWPN));
6444
6445 /* Bufer Credit Descriptor */
6446 rsp_payload->buffer_credit_desc.desc_tag = cpu_to_be32(0x10006);
6447 rsp_payload->buffer_credit_desc.desc_len =
6448 cpu_to_be32(RDP_DESC_LEN(rsp_payload->buffer_credit_desc));
6449 rsp_payload->buffer_credit_desc.fcport_b2b = 0;
6450 rsp_payload->buffer_credit_desc.attached_fcport_b2b = cpu_to_be32(0);
6451 rsp_payload->buffer_credit_desc.fcport_rtt = cpu_to_be32(0);
6452
6453 if (ha->flags.plogi_template_valid) {
6454 uint32_t tmp =
6455 be16_to_cpu(ha->plogi_els_payld.fl_csp.sp_bb_cred);
6456 rsp_payload->buffer_credit_desc.fcport_b2b = cpu_to_be32(tmp);
6457 }
6458
6459 if (rsp_payload_length < sizeof(*rsp_payload))
6460 goto send;
6461
6462 /* Optical Element Descriptor, Temperature */
6463 rsp_payload->optical_elmt_desc[0].desc_tag = cpu_to_be32(0x10007);
6464 rsp_payload->optical_elmt_desc[0].desc_len =
6465 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6466 /* Optical Element Descriptor, Voltage */
6467 rsp_payload->optical_elmt_desc[1].desc_tag = cpu_to_be32(0x10007);
6468 rsp_payload->optical_elmt_desc[1].desc_len =
6469 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6470 /* Optical Element Descriptor, Tx Bias Current */
6471 rsp_payload->optical_elmt_desc[2].desc_tag = cpu_to_be32(0x10007);
6472 rsp_payload->optical_elmt_desc[2].desc_len =
6473 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6474 /* Optical Element Descriptor, Tx Power */
6475 rsp_payload->optical_elmt_desc[3].desc_tag = cpu_to_be32(0x10007);
6476 rsp_payload->optical_elmt_desc[3].desc_len =
6477 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6478 /* Optical Element Descriptor, Rx Power */
6479 rsp_payload->optical_elmt_desc[4].desc_tag = cpu_to_be32(0x10007);
6480 rsp_payload->optical_elmt_desc[4].desc_len =
6481 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6482
6483 if (sfp) {
6484 memset(sfp, 0, SFP_RTDI_LEN);
6485 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0, 64, 0);
6486 if (!rval) {
6487 __be16 *trx = (__force __be16 *)sfp; /* already be16 */
6488
6489 /* Optical Element Descriptor, Temperature */
6490 rsp_payload->optical_elmt_desc[0].high_alarm = trx[0];
6491 rsp_payload->optical_elmt_desc[0].low_alarm = trx[1];
6492 rsp_payload->optical_elmt_desc[0].high_warn = trx[2];
6493 rsp_payload->optical_elmt_desc[0].low_warn = trx[3];
6494 rsp_payload->optical_elmt_desc[0].element_flags =
6495 cpu_to_be32(1 << 28);
6496
6497 /* Optical Element Descriptor, Voltage */
6498 rsp_payload->optical_elmt_desc[1].high_alarm = trx[4];
6499 rsp_payload->optical_elmt_desc[1].low_alarm = trx[5];
6500 rsp_payload->optical_elmt_desc[1].high_warn = trx[6];
6501 rsp_payload->optical_elmt_desc[1].low_warn = trx[7];
6502 rsp_payload->optical_elmt_desc[1].element_flags =
6503 cpu_to_be32(2 << 28);
6504
6505 /* Optical Element Descriptor, Tx Bias Current */
6506 rsp_payload->optical_elmt_desc[2].high_alarm = trx[8];
6507 rsp_payload->optical_elmt_desc[2].low_alarm = trx[9];
6508 rsp_payload->optical_elmt_desc[2].high_warn = trx[10];
6509 rsp_payload->optical_elmt_desc[2].low_warn = trx[11];
6510 rsp_payload->optical_elmt_desc[2].element_flags =
6511 cpu_to_be32(3 << 28);
6512
6513 /* Optical Element Descriptor, Tx Power */
6514 rsp_payload->optical_elmt_desc[3].high_alarm = trx[12];
6515 rsp_payload->optical_elmt_desc[3].low_alarm = trx[13];
6516 rsp_payload->optical_elmt_desc[3].high_warn = trx[14];
6517 rsp_payload->optical_elmt_desc[3].low_warn = trx[15];
6518 rsp_payload->optical_elmt_desc[3].element_flags =
6519 cpu_to_be32(4 << 28);
6520
6521 /* Optical Element Descriptor, Rx Power */
6522 rsp_payload->optical_elmt_desc[4].high_alarm = trx[16];
6523 rsp_payload->optical_elmt_desc[4].low_alarm = trx[17];
6524 rsp_payload->optical_elmt_desc[4].high_warn = trx[18];
6525 rsp_payload->optical_elmt_desc[4].low_warn = trx[19];
6526 rsp_payload->optical_elmt_desc[4].element_flags =
6527 cpu_to_be32(5 << 28);
6528 }
6529
6530 memset(sfp, 0, SFP_RTDI_LEN);
6531 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 112, 64, 0);
6532 if (!rval) {
6533 /* Temperature high/low alarm/warning */
6534 rsp_payload->optical_elmt_desc[0].element_flags |=
6535 cpu_to_be32(
6536 (sfp[0] >> 7 & 1) << 3 |
6537 (sfp[0] >> 6 & 1) << 2 |
6538 (sfp[4] >> 7 & 1) << 1 |
6539 (sfp[4] >> 6 & 1) << 0);
6540
6541 /* Voltage high/low alarm/warning */
6542 rsp_payload->optical_elmt_desc[1].element_flags |=
6543 cpu_to_be32(
6544 (sfp[0] >> 5 & 1) << 3 |
6545 (sfp[0] >> 4 & 1) << 2 |
6546 (sfp[4] >> 5 & 1) << 1 |
6547 (sfp[4] >> 4 & 1) << 0);
6548
6549 /* Tx Bias Current high/low alarm/warning */
6550 rsp_payload->optical_elmt_desc[2].element_flags |=
6551 cpu_to_be32(
6552 (sfp[0] >> 3 & 1) << 3 |
6553 (sfp[0] >> 2 & 1) << 2 |
6554 (sfp[4] >> 3 & 1) << 1 |
6555 (sfp[4] >> 2 & 1) << 0);
6556
6557 /* Tx Power high/low alarm/warning */
6558 rsp_payload->optical_elmt_desc[3].element_flags |=
6559 cpu_to_be32(
6560 (sfp[0] >> 1 & 1) << 3 |
6561 (sfp[0] >> 0 & 1) << 2 |
6562 (sfp[4] >> 1 & 1) << 1 |
6563 (sfp[4] >> 0 & 1) << 0);
6564
6565 /* Rx Power high/low alarm/warning */
6566 rsp_payload->optical_elmt_desc[4].element_flags |=
6567 cpu_to_be32(
6568 (sfp[1] >> 7 & 1) << 3 |
6569 (sfp[1] >> 6 & 1) << 2 |
6570 (sfp[5] >> 7 & 1) << 1 |
6571 (sfp[5] >> 6 & 1) << 0);
6572 }
6573 }
6574
6575 /* Optical Product Data Descriptor */
6576 rsp_payload->optical_prod_desc.desc_tag = cpu_to_be32(0x10008);
6577 rsp_payload->optical_prod_desc.desc_len =
6578 cpu_to_be32(RDP_DESC_LEN(rsp_payload->optical_prod_desc));
6579
6580 if (sfp) {
6581 memset(sfp, 0, SFP_RTDI_LEN);
6582 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 20, 64, 0);
6583 if (!rval) {
6584 memcpy(rsp_payload->optical_prod_desc.vendor_name,
6585 sfp + 0,
6586 sizeof(rsp_payload->optical_prod_desc.vendor_name));
6587 memcpy(rsp_payload->optical_prod_desc.part_number,
6588 sfp + 20,
6589 sizeof(rsp_payload->optical_prod_desc.part_number));
6590 memcpy(rsp_payload->optical_prod_desc.revision,
6591 sfp + 36,
6592 sizeof(rsp_payload->optical_prod_desc.revision));
6593 memcpy(rsp_payload->optical_prod_desc.serial_number,
6594 sfp + 48,
6595 sizeof(rsp_payload->optical_prod_desc.serial_number));
6596 }
6597
6598 memset(sfp, 0, SFP_RTDI_LEN);
6599 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 84, 8, 0);
6600 if (!rval) {
6601 memcpy(rsp_payload->optical_prod_desc.date,
6602 sfp + 0,
6603 sizeof(rsp_payload->optical_prod_desc.date));
6604 }
6605 }
6606
6607 send:
6608 ql_dbg(ql_dbg_init, vha, 0x0183,
6609 "Sending ELS Response to RDP Request...\n");
6610 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0184,
6611 "-------- ELS RSP -------\n");
6612 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0185,
6613 rsp_els_pkt, rsp_els_sz);
6614 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0186,
6615 "-------- ELS RSP PAYLOAD -------\n");
6616 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0187,
6617 rsp_payload, rsp_payload_length);
6618
6619 rval = qla2x00_issue_iocb(vha, rsp_els_pkt, rsp_els_dma, 0);
6620
6621 if (rval) {
6622 ql_log(ql_log_warn, vha, 0x0188,
6623 "%s: iocb failed to execute -> %x\n", __func__, rval);
6624 } else if (rsp_els->comp_status) {
6625 ql_log(ql_log_warn, vha, 0x0189,
6626 "%s: iocb failed to complete -> completion=%#x subcode=(%#x,%#x)\n",
6627 __func__, rsp_els->comp_status,
6628 rsp_els->error_subcode_1, rsp_els->error_subcode_2);
6629 } else {
6630 ql_dbg(ql_dbg_init, vha, 0x018a, "%s: done.\n", __func__);
6631 }
6632
6633 dealloc:
6634 if (stat)
6635 dma_free_coherent(&ha->pdev->dev, sizeof(*stat),
6636 stat, stat_dma);
6637 if (sfp)
6638 dma_free_coherent(&ha->pdev->dev, SFP_RTDI_LEN,
6639 sfp, sfp_dma);
6640 if (rsp_payload)
6641 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_payload),
6642 rsp_payload, rsp_payload_dma);
6643 if (rsp_els_pkt)
6644 dma_free_coherent(&ha->pdev->dev, rsp_els_sz,
6645 rsp_els_pkt, rsp_els_dma);
6646 }
6647
6648 void
qla24xx_free_purex_item(struct purex_item * item)6649 qla24xx_free_purex_item(struct purex_item *item)
6650 {
6651 if (item == &item->vha->default_item)
6652 memset(&item->vha->default_item, 0, sizeof(struct purex_item));
6653 else
6654 kfree(item);
6655 }
6656
qla24xx_process_purex_list(struct purex_list * list)6657 void qla24xx_process_purex_list(struct purex_list *list)
6658 {
6659 struct list_head head = LIST_HEAD_INIT(head);
6660 struct purex_item *item, *next;
6661 ulong flags;
6662
6663 spin_lock_irqsave(&list->lock, flags);
6664 list_splice_init(&list->head, &head);
6665 spin_unlock_irqrestore(&list->lock, flags);
6666
6667 list_for_each_entry_safe(item, next, &head, list) {
6668 list_del(&item->list);
6669 item->process_item(item->vha, item);
6670 qla24xx_free_purex_item(item);
6671 }
6672 }
6673
6674 /*
6675 * Context: task, can sleep
6676 */
6677 void
qla83xx_idc_unlock(scsi_qla_host_t * base_vha,uint16_t requester_id)6678 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
6679 {
6680 #if 0
6681 uint16_t options = (requester_id << 15) | BIT_7;
6682 #endif
6683 uint16_t retry;
6684 uint32_t data;
6685 struct qla_hw_data *ha = base_vha->hw;
6686
6687 might_sleep();
6688
6689 /* IDC-unlock implementation using driver-unlock/lock-id
6690 * remote registers
6691 */
6692 retry = 0;
6693 retry_unlock:
6694 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
6695 == QLA_SUCCESS) {
6696 if (data == ha->portnum) {
6697 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
6698 /* Clearing lock-id by setting 0xff */
6699 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
6700 } else if (retry < 10) {
6701 /* SV: XXX: IDC unlock retrying needed here? */
6702
6703 /* Retry for IDC-unlock */
6704 msleep(QLA83XX_WAIT_LOGIC_MS);
6705 retry++;
6706 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
6707 "Failed to release IDC lock, retrying=%d\n", retry);
6708 goto retry_unlock;
6709 }
6710 } else if (retry < 10) {
6711 /* Retry for IDC-unlock */
6712 msleep(QLA83XX_WAIT_LOGIC_MS);
6713 retry++;
6714 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
6715 "Failed to read drv-lockid, retrying=%d\n", retry);
6716 goto retry_unlock;
6717 }
6718
6719 return;
6720
6721 #if 0
6722 /* XXX: IDC-unlock implementation using access-control mbx */
6723 retry = 0;
6724 retry_unlock2:
6725 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
6726 if (retry < 10) {
6727 /* Retry for IDC-unlock */
6728 msleep(QLA83XX_WAIT_LOGIC_MS);
6729 retry++;
6730 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
6731 "Failed to release IDC lock, retrying=%d\n", retry);
6732 goto retry_unlock2;
6733 }
6734 }
6735
6736 return;
6737 #endif
6738 }
6739
6740 int
__qla83xx_set_drv_presence(scsi_qla_host_t * vha)6741 __qla83xx_set_drv_presence(scsi_qla_host_t *vha)
6742 {
6743 int rval = QLA_SUCCESS;
6744 struct qla_hw_data *ha = vha->hw;
6745 uint32_t drv_presence;
6746
6747 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6748 if (rval == QLA_SUCCESS) {
6749 drv_presence |= (1 << ha->portnum);
6750 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6751 drv_presence);
6752 }
6753
6754 return rval;
6755 }
6756
6757 int
qla83xx_set_drv_presence(scsi_qla_host_t * vha)6758 qla83xx_set_drv_presence(scsi_qla_host_t *vha)
6759 {
6760 int rval = QLA_SUCCESS;
6761
6762 qla83xx_idc_lock(vha, 0);
6763 rval = __qla83xx_set_drv_presence(vha);
6764 qla83xx_idc_unlock(vha, 0);
6765
6766 return rval;
6767 }
6768
6769 int
__qla83xx_clear_drv_presence(scsi_qla_host_t * vha)6770 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
6771 {
6772 int rval = QLA_SUCCESS;
6773 struct qla_hw_data *ha = vha->hw;
6774 uint32_t drv_presence;
6775
6776 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6777 if (rval == QLA_SUCCESS) {
6778 drv_presence &= ~(1 << ha->portnum);
6779 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6780 drv_presence);
6781 }
6782
6783 return rval;
6784 }
6785
6786 int
qla83xx_clear_drv_presence(scsi_qla_host_t * vha)6787 qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
6788 {
6789 int rval = QLA_SUCCESS;
6790
6791 qla83xx_idc_lock(vha, 0);
6792 rval = __qla83xx_clear_drv_presence(vha);
6793 qla83xx_idc_unlock(vha, 0);
6794
6795 return rval;
6796 }
6797
6798 static void
qla83xx_need_reset_handler(scsi_qla_host_t * vha)6799 qla83xx_need_reset_handler(scsi_qla_host_t *vha)
6800 {
6801 struct qla_hw_data *ha = vha->hw;
6802 uint32_t drv_ack, drv_presence;
6803 unsigned long ack_timeout;
6804
6805 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
6806 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
6807 while (1) {
6808 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
6809 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6810 if ((drv_ack & drv_presence) == drv_presence)
6811 break;
6812
6813 if (time_after_eq(jiffies, ack_timeout)) {
6814 ql_log(ql_log_warn, vha, 0xb067,
6815 "RESET ACK TIMEOUT! drv_presence=0x%x "
6816 "drv_ack=0x%x\n", drv_presence, drv_ack);
6817 /*
6818 * The function(s) which did not ack in time are forced
6819 * to withdraw any further participation in the IDC
6820 * reset.
6821 */
6822 if (drv_ack != drv_presence)
6823 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6824 drv_ack);
6825 break;
6826 }
6827
6828 qla83xx_idc_unlock(vha, 0);
6829 msleep(1000);
6830 qla83xx_idc_lock(vha, 0);
6831 }
6832
6833 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
6834 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
6835 }
6836
6837 static int
qla83xx_device_bootstrap(scsi_qla_host_t * vha)6838 qla83xx_device_bootstrap(scsi_qla_host_t *vha)
6839 {
6840 int rval = QLA_SUCCESS;
6841 uint32_t idc_control;
6842
6843 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
6844 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
6845
6846 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
6847 __qla83xx_get_idc_control(vha, &idc_control);
6848 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
6849 __qla83xx_set_idc_control(vha, 0);
6850
6851 qla83xx_idc_unlock(vha, 0);
6852 rval = qla83xx_restart_nic_firmware(vha);
6853 qla83xx_idc_lock(vha, 0);
6854
6855 if (rval != QLA_SUCCESS) {
6856 ql_log(ql_log_fatal, vha, 0xb06a,
6857 "Failed to restart NIC f/w.\n");
6858 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
6859 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
6860 } else {
6861 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
6862 "Success in restarting nic f/w.\n");
6863 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
6864 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
6865 }
6866
6867 return rval;
6868 }
6869
6870 /* Assumes idc_lock always held on entry */
6871 int
qla83xx_idc_state_handler(scsi_qla_host_t * base_vha)6872 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
6873 {
6874 struct qla_hw_data *ha = base_vha->hw;
6875 int rval = QLA_SUCCESS;
6876 unsigned long dev_init_timeout;
6877 uint32_t dev_state;
6878
6879 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
6880 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
6881
6882 while (1) {
6883
6884 if (time_after_eq(jiffies, dev_init_timeout)) {
6885 ql_log(ql_log_warn, base_vha, 0xb06e,
6886 "Initialization TIMEOUT!\n");
6887 /* Init timeout. Disable further NIC Core
6888 * communication.
6889 */
6890 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
6891 QLA8XXX_DEV_FAILED);
6892 ql_log(ql_log_info, base_vha, 0xb06f,
6893 "HW State: FAILED.\n");
6894 }
6895
6896 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
6897 switch (dev_state) {
6898 case QLA8XXX_DEV_READY:
6899 if (ha->flags.nic_core_reset_owner)
6900 qla83xx_idc_audit(base_vha,
6901 IDC_AUDIT_COMPLETION);
6902 ha->flags.nic_core_reset_owner = 0;
6903 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
6904 "Reset_owner reset by 0x%x.\n",
6905 ha->portnum);
6906 goto exit;
6907 case QLA8XXX_DEV_COLD:
6908 if (ha->flags.nic_core_reset_owner)
6909 rval = qla83xx_device_bootstrap(base_vha);
6910 else {
6911 /* Wait for AEN to change device-state */
6912 qla83xx_idc_unlock(base_vha, 0);
6913 msleep(1000);
6914 qla83xx_idc_lock(base_vha, 0);
6915 }
6916 break;
6917 case QLA8XXX_DEV_INITIALIZING:
6918 /* Wait for AEN to change device-state */
6919 qla83xx_idc_unlock(base_vha, 0);
6920 msleep(1000);
6921 qla83xx_idc_lock(base_vha, 0);
6922 break;
6923 case QLA8XXX_DEV_NEED_RESET:
6924 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
6925 qla83xx_need_reset_handler(base_vha);
6926 else {
6927 /* Wait for AEN to change device-state */
6928 qla83xx_idc_unlock(base_vha, 0);
6929 msleep(1000);
6930 qla83xx_idc_lock(base_vha, 0);
6931 }
6932 /* reset timeout value after need reset handler */
6933 dev_init_timeout = jiffies +
6934 (ha->fcoe_dev_init_timeout * HZ);
6935 break;
6936 case QLA8XXX_DEV_NEED_QUIESCENT:
6937 /* XXX: DEBUG for now */
6938 qla83xx_idc_unlock(base_vha, 0);
6939 msleep(1000);
6940 qla83xx_idc_lock(base_vha, 0);
6941 break;
6942 case QLA8XXX_DEV_QUIESCENT:
6943 /* XXX: DEBUG for now */
6944 if (ha->flags.quiesce_owner)
6945 goto exit;
6946
6947 qla83xx_idc_unlock(base_vha, 0);
6948 msleep(1000);
6949 qla83xx_idc_lock(base_vha, 0);
6950 dev_init_timeout = jiffies +
6951 (ha->fcoe_dev_init_timeout * HZ);
6952 break;
6953 case QLA8XXX_DEV_FAILED:
6954 if (ha->flags.nic_core_reset_owner)
6955 qla83xx_idc_audit(base_vha,
6956 IDC_AUDIT_COMPLETION);
6957 ha->flags.nic_core_reset_owner = 0;
6958 __qla83xx_clear_drv_presence(base_vha);
6959 qla83xx_idc_unlock(base_vha, 0);
6960 qla8xxx_dev_failed_handler(base_vha);
6961 rval = QLA_FUNCTION_FAILED;
6962 qla83xx_idc_lock(base_vha, 0);
6963 goto exit;
6964 case QLA8XXX_BAD_VALUE:
6965 qla83xx_idc_unlock(base_vha, 0);
6966 msleep(1000);
6967 qla83xx_idc_lock(base_vha, 0);
6968 break;
6969 default:
6970 ql_log(ql_log_warn, base_vha, 0xb071,
6971 "Unknown Device State: %x.\n", dev_state);
6972 qla83xx_idc_unlock(base_vha, 0);
6973 qla8xxx_dev_failed_handler(base_vha);
6974 rval = QLA_FUNCTION_FAILED;
6975 qla83xx_idc_lock(base_vha, 0);
6976 goto exit;
6977 }
6978 }
6979
6980 exit:
6981 return rval;
6982 }
6983
6984 void
qla2x00_disable_board_on_pci_error(struct work_struct * work)6985 qla2x00_disable_board_on_pci_error(struct work_struct *work)
6986 {
6987 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
6988 board_disable);
6989 struct pci_dev *pdev = ha->pdev;
6990 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
6991
6992 ql_log(ql_log_warn, base_vha, 0x015b,
6993 "Disabling adapter.\n");
6994
6995 if (!atomic_read(&pdev->enable_cnt)) {
6996 ql_log(ql_log_info, base_vha, 0xfffc,
6997 "PCI device disabled, no action req for PCI error=%lx\n",
6998 base_vha->pci_flags);
6999 return;
7000 }
7001
7002 /*
7003 * if UNLOADING flag is already set, then continue unload,
7004 * where it was set first.
7005 */
7006 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags))
7007 return;
7008
7009 qla2x00_wait_for_sess_deletion(base_vha);
7010
7011 qla2x00_delete_all_vps(ha, base_vha);
7012
7013 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
7014
7015 qla2x00_dfs_remove(base_vha);
7016
7017 if (base_vha->timer_active)
7018 qla2x00_stop_timer(base_vha);
7019
7020 base_vha->flags.online = 0;
7021
7022 qla2x00_destroy_deferred_work(ha);
7023
7024 /*
7025 * Do not try to stop beacon blink as it will issue a mailbox
7026 * command.
7027 */
7028 qla2x00_free_sysfs_attr(base_vha, false);
7029
7030 fc_remove_host(base_vha->host);
7031
7032 scsi_remove_host(base_vha->host);
7033
7034 qla84xx_put_chip(base_vha);
7035
7036 base_vha->flags.init_done = 0;
7037 qla25xx_delete_queues(base_vha);
7038 qla2x00_free_fcports(base_vha);
7039 qla2x00_free_irqs(base_vha);
7040 qla2x00_mem_free(ha);
7041 qla82xx_md_free(base_vha);
7042 qla2x00_free_queues(ha);
7043
7044 qla2x00_unmap_iobases(ha);
7045
7046 pci_release_selected_regions(ha->pdev, ha->bars);
7047 pci_disable_device(pdev);
7048
7049 /*
7050 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
7051 */
7052 }
7053
7054 /**************************************************************************
7055 * qla2x00_do_dpc
7056 * This kernel thread is a task that is schedule by the interrupt handler
7057 * to perform the background processing for interrupts.
7058 *
7059 * Notes:
7060 * This task always run in the context of a kernel thread. It
7061 * is kick-off by the driver's detect code and starts up
7062 * up one per adapter. It immediately goes to sleep and waits for
7063 * some fibre event. When either the interrupt handler or
7064 * the timer routine detects a event it will one of the task
7065 * bits then wake us up.
7066 **************************************************************************/
7067 static int
qla2x00_do_dpc(void * data)7068 qla2x00_do_dpc(void *data)
7069 {
7070 scsi_qla_host_t *base_vha;
7071 struct qla_hw_data *ha;
7072 uint32_t online;
7073 struct qla_qpair *qpair;
7074
7075 ha = (struct qla_hw_data *)data;
7076 base_vha = pci_get_drvdata(ha->pdev);
7077
7078 set_user_nice(current, MIN_NICE);
7079
7080 set_current_state(TASK_INTERRUPTIBLE);
7081 while (1) {
7082 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
7083 "DPC handler sleeping.\n");
7084
7085 schedule();
7086
7087 if (kthread_should_stop())
7088 break;
7089
7090 if (test_and_clear_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags))
7091 qla_pci_set_eeh_busy(base_vha);
7092
7093 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
7094 goto end_loop;
7095
7096 if (ha->flags.eeh_busy) {
7097 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
7098 "eeh_busy=%d.\n", ha->flags.eeh_busy);
7099 goto end_loop;
7100 }
7101
7102 if (test_bit(UNLOADING, &base_vha->dpc_flags))
7103 /* don't do any work. Wait to be terminated by kthread_stop */
7104 goto end_loop;
7105
7106 ha->dpc_active = 1;
7107
7108 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
7109 "DPC handler waking up, dpc_flags=0x%lx.\n",
7110 base_vha->dpc_flags);
7111
7112 if (IS_P3P_TYPE(ha)) {
7113 if (IS_QLA8044(ha)) {
7114 if (test_and_clear_bit(ISP_UNRECOVERABLE,
7115 &base_vha->dpc_flags)) {
7116 qla8044_idc_lock(ha);
7117 qla8044_wr_direct(base_vha,
7118 QLA8044_CRB_DEV_STATE_INDEX,
7119 QLA8XXX_DEV_FAILED);
7120 qla8044_idc_unlock(ha);
7121 ql_log(ql_log_info, base_vha, 0x4004,
7122 "HW State: FAILED.\n");
7123 qla8044_device_state_handler(base_vha);
7124 continue;
7125 }
7126
7127 } else {
7128 if (test_and_clear_bit(ISP_UNRECOVERABLE,
7129 &base_vha->dpc_flags)) {
7130 qla82xx_idc_lock(ha);
7131 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7132 QLA8XXX_DEV_FAILED);
7133 qla82xx_idc_unlock(ha);
7134 ql_log(ql_log_info, base_vha, 0x0151,
7135 "HW State: FAILED.\n");
7136 qla82xx_device_state_handler(base_vha);
7137 continue;
7138 }
7139 }
7140
7141 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
7142 &base_vha->dpc_flags)) {
7143
7144 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
7145 "FCoE context reset scheduled.\n");
7146 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
7147 &base_vha->dpc_flags))) {
7148 if (qla82xx_fcoe_ctx_reset(base_vha)) {
7149 /* FCoE-ctx reset failed.
7150 * Escalate to chip-reset
7151 */
7152 set_bit(ISP_ABORT_NEEDED,
7153 &base_vha->dpc_flags);
7154 }
7155 clear_bit(ABORT_ISP_ACTIVE,
7156 &base_vha->dpc_flags);
7157 }
7158
7159 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
7160 "FCoE context reset end.\n");
7161 }
7162 } else if (IS_QLAFX00(ha)) {
7163 if (test_and_clear_bit(ISP_UNRECOVERABLE,
7164 &base_vha->dpc_flags)) {
7165 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
7166 "Firmware Reset Recovery\n");
7167 if (qlafx00_reset_initialize(base_vha)) {
7168 /* Failed. Abort isp later. */
7169 if (!test_bit(UNLOADING,
7170 &base_vha->dpc_flags)) {
7171 set_bit(ISP_UNRECOVERABLE,
7172 &base_vha->dpc_flags);
7173 ql_dbg(ql_dbg_dpc, base_vha,
7174 0x4021,
7175 "Reset Recovery Failed\n");
7176 }
7177 }
7178 }
7179
7180 if (test_and_clear_bit(FX00_TARGET_SCAN,
7181 &base_vha->dpc_flags)) {
7182 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
7183 "ISPFx00 Target Scan scheduled\n");
7184 if (qlafx00_rescan_isp(base_vha)) {
7185 if (!test_bit(UNLOADING,
7186 &base_vha->dpc_flags))
7187 set_bit(ISP_UNRECOVERABLE,
7188 &base_vha->dpc_flags);
7189 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
7190 "ISPFx00 Target Scan Failed\n");
7191 }
7192 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
7193 "ISPFx00 Target Scan End\n");
7194 }
7195 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
7196 &base_vha->dpc_flags)) {
7197 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
7198 "ISPFx00 Host Info resend scheduled\n");
7199 qlafx00_fx_disc(base_vha,
7200 &base_vha->hw->mr.fcport,
7201 FXDISC_REG_HOST_INFO);
7202 }
7203 }
7204
7205 if (test_and_clear_bit(DETECT_SFP_CHANGE,
7206 &base_vha->dpc_flags)) {
7207 /* Semantic:
7208 * - NO-OP -- await next ISP-ABORT. Preferred method
7209 * to minimize disruptions that will occur
7210 * when a forced chip-reset occurs.
7211 * - Force -- ISP-ABORT scheduled.
7212 */
7213 /* set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); */
7214 }
7215
7216 if (test_and_clear_bit
7217 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
7218 !test_bit(UNLOADING, &base_vha->dpc_flags)) {
7219 bool do_reset = true;
7220
7221 switch (base_vha->qlini_mode) {
7222 case QLA2XXX_INI_MODE_ENABLED:
7223 break;
7224 case QLA2XXX_INI_MODE_DISABLED:
7225 if (!qla_tgt_mode_enabled(base_vha) &&
7226 !ha->flags.fw_started)
7227 do_reset = false;
7228 break;
7229 case QLA2XXX_INI_MODE_DUAL:
7230 if (!qla_dual_mode_enabled(base_vha) &&
7231 !ha->flags.fw_started)
7232 do_reset = false;
7233 break;
7234 default:
7235 break;
7236 }
7237
7238 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE,
7239 &base_vha->dpc_flags))) {
7240 base_vha->flags.online = 1;
7241 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
7242 "ISP abort scheduled.\n");
7243 if (ha->isp_ops->abort_isp(base_vha)) {
7244 /* failed. retry later */
7245 set_bit(ISP_ABORT_NEEDED,
7246 &base_vha->dpc_flags);
7247 }
7248 clear_bit(ABORT_ISP_ACTIVE,
7249 &base_vha->dpc_flags);
7250 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
7251 "ISP abort end.\n");
7252 }
7253 }
7254
7255 if (test_bit(PROCESS_PUREX_IOCB, &base_vha->dpc_flags)) {
7256 if (atomic_read(&base_vha->loop_state) == LOOP_READY) {
7257 qla24xx_process_purex_list
7258 (&base_vha->purex_list);
7259 clear_bit(PROCESS_PUREX_IOCB,
7260 &base_vha->dpc_flags);
7261 }
7262 }
7263
7264 if (IS_QLAFX00(ha))
7265 goto loop_resync_check;
7266
7267 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7268 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
7269 "Quiescence mode scheduled.\n");
7270 if (IS_P3P_TYPE(ha)) {
7271 if (IS_QLA82XX(ha))
7272 qla82xx_device_state_handler(base_vha);
7273 if (IS_QLA8044(ha))
7274 qla8044_device_state_handler(base_vha);
7275 clear_bit(ISP_QUIESCE_NEEDED,
7276 &base_vha->dpc_flags);
7277 if (!ha->flags.quiesce_owner) {
7278 qla2x00_perform_loop_resync(base_vha);
7279 if (IS_QLA82XX(ha)) {
7280 qla82xx_idc_lock(ha);
7281 qla82xx_clear_qsnt_ready(
7282 base_vha);
7283 qla82xx_idc_unlock(ha);
7284 } else if (IS_QLA8044(ha)) {
7285 qla8044_idc_lock(ha);
7286 qla8044_clear_qsnt_ready(
7287 base_vha);
7288 qla8044_idc_unlock(ha);
7289 }
7290 }
7291 } else {
7292 clear_bit(ISP_QUIESCE_NEEDED,
7293 &base_vha->dpc_flags);
7294 qla2x00_quiesce_io(base_vha);
7295 }
7296 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
7297 "Quiescence mode end.\n");
7298 }
7299
7300 if (test_and_clear_bit(RESET_MARKER_NEEDED,
7301 &base_vha->dpc_flags) &&
7302 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
7303
7304 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
7305 "Reset marker scheduled.\n");
7306 qla2x00_rst_aen(base_vha);
7307 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7308 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
7309 "Reset marker end.\n");
7310 }
7311
7312 /* Retry each device up to login retry count */
7313 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) &&
7314 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
7315 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
7316
7317 if (!base_vha->relogin_jif ||
7318 time_after_eq(jiffies, base_vha->relogin_jif)) {
7319 base_vha->relogin_jif = jiffies + HZ;
7320 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags);
7321
7322 ql_dbg(ql_dbg_disc, base_vha, 0x400d,
7323 "Relogin scheduled.\n");
7324 qla24xx_post_relogin_work(base_vha);
7325 }
7326 }
7327 loop_resync_check:
7328 if (!qla2x00_reset_active(base_vha) &&
7329 test_and_clear_bit(LOOP_RESYNC_NEEDED,
7330 &base_vha->dpc_flags)) {
7331 /*
7332 * Allow abort_isp to complete before moving on to scanning.
7333 */
7334 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
7335 "Loop resync scheduled.\n");
7336
7337 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
7338 &base_vha->dpc_flags))) {
7339
7340 qla2x00_loop_resync(base_vha);
7341
7342 clear_bit(LOOP_RESYNC_ACTIVE,
7343 &base_vha->dpc_flags);
7344 }
7345
7346 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
7347 "Loop resync end.\n");
7348 }
7349
7350 if (IS_QLAFX00(ha))
7351 goto intr_on_check;
7352
7353 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
7354 atomic_read(&base_vha->loop_state) == LOOP_READY) {
7355 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
7356 qla2xxx_flash_npiv_conf(base_vha);
7357 }
7358
7359 intr_on_check:
7360 if (!ha->interrupts_on)
7361 ha->isp_ops->enable_intrs(ha);
7362
7363 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
7364 &base_vha->dpc_flags)) {
7365 if (ha->beacon_blink_led == 1)
7366 ha->isp_ops->beacon_blink(base_vha);
7367 }
7368
7369 /* qpair online check */
7370 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
7371 &base_vha->dpc_flags)) {
7372 if (ha->flags.eeh_busy ||
7373 ha->flags.pci_channel_io_perm_failure)
7374 online = 0;
7375 else
7376 online = 1;
7377
7378 mutex_lock(&ha->mq_lock);
7379 list_for_each_entry(qpair, &base_vha->qp_list,
7380 qp_list_elem)
7381 qpair->online = online;
7382 mutex_unlock(&ha->mq_lock);
7383 }
7384
7385 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED,
7386 &base_vha->dpc_flags)) {
7387 u16 threshold = ha->nvme_last_rptd_aen + ha->last_zio_threshold;
7388
7389 if (threshold > ha->orig_fw_xcb_count)
7390 threshold = ha->orig_fw_xcb_count;
7391
7392 ql_log(ql_log_info, base_vha, 0xffffff,
7393 "SET ZIO Activity exchange threshold to %d.\n",
7394 threshold);
7395 if (qla27xx_set_zio_threshold(base_vha, threshold)) {
7396 ql_log(ql_log_info, base_vha, 0xffffff,
7397 "Unable to SET ZIO Activity exchange threshold to %d.\n",
7398 threshold);
7399 }
7400 }
7401
7402 if (!IS_QLAFX00(ha))
7403 qla2x00_do_dpc_all_vps(base_vha);
7404
7405 if (test_and_clear_bit(N2N_LINK_RESET,
7406 &base_vha->dpc_flags)) {
7407 qla2x00_lip_reset(base_vha);
7408 }
7409
7410 ha->dpc_active = 0;
7411 end_loop:
7412 set_current_state(TASK_INTERRUPTIBLE);
7413 } /* End of while(1) */
7414 __set_current_state(TASK_RUNNING);
7415
7416 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
7417 "DPC handler exiting.\n");
7418
7419 /*
7420 * Make sure that nobody tries to wake us up again.
7421 */
7422 ha->dpc_active = 0;
7423
7424 return 0;
7425 }
7426
7427 void
qla2xxx_wake_dpc(struct scsi_qla_host * vha)7428 qla2xxx_wake_dpc(struct scsi_qla_host *vha)
7429 {
7430 struct qla_hw_data *ha = vha->hw;
7431 struct task_struct *t = ha->dpc_thread;
7432
7433 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
7434 wake_up_process(t);
7435 }
7436 EXPORT_SYMBOL(qla2xxx_wake_dpc);
7437
7438 /*
7439 * qla2x00_rst_aen
7440 * Processes asynchronous reset.
7441 *
7442 * Input:
7443 * ha = adapter block pointer.
7444 */
7445 static void
qla2x00_rst_aen(scsi_qla_host_t * vha)7446 qla2x00_rst_aen(scsi_qla_host_t *vha)
7447 {
7448 if (vha->flags.online && !vha->flags.reset_active &&
7449 !atomic_read(&vha->loop_down_timer) &&
7450 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
7451 do {
7452 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
7453
7454 /*
7455 * Issue marker command only when we are going to start
7456 * the I/O.
7457 */
7458 vha->marker_needed = 1;
7459 } while (!atomic_read(&vha->loop_down_timer) &&
7460 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
7461 }
7462 }
7463
qla_do_heartbeat(struct scsi_qla_host * vha)7464 static bool qla_do_heartbeat(struct scsi_qla_host *vha)
7465 {
7466 struct qla_hw_data *ha = vha->hw;
7467 u32 cmpl_cnt;
7468 u16 i;
7469 bool do_heartbeat = false;
7470
7471 /*
7472 * Allow do_heartbeat only if we don’t have any active interrupts,
7473 * but there are still IOs outstanding with firmware.
7474 */
7475 cmpl_cnt = ha->base_qpair->cmd_completion_cnt;
7476 if (cmpl_cnt == ha->base_qpair->prev_completion_cnt &&
7477 cmpl_cnt != ha->base_qpair->cmd_cnt) {
7478 do_heartbeat = true;
7479 goto skip;
7480 }
7481 ha->base_qpair->prev_completion_cnt = cmpl_cnt;
7482
7483 for (i = 0; i < ha->max_qpairs; i++) {
7484 if (ha->queue_pair_map[i]) {
7485 cmpl_cnt = ha->queue_pair_map[i]->cmd_completion_cnt;
7486 if (cmpl_cnt == ha->queue_pair_map[i]->prev_completion_cnt &&
7487 cmpl_cnt != ha->queue_pair_map[i]->cmd_cnt) {
7488 do_heartbeat = true;
7489 break;
7490 }
7491 ha->queue_pair_map[i]->prev_completion_cnt = cmpl_cnt;
7492 }
7493 }
7494
7495 skip:
7496 return do_heartbeat;
7497 }
7498
qla_heart_beat(struct scsi_qla_host * vha,u16 dpc_started)7499 static void qla_heart_beat(struct scsi_qla_host *vha, u16 dpc_started)
7500 {
7501 struct qla_hw_data *ha = vha->hw;
7502
7503 if (vha->vp_idx)
7504 return;
7505
7506 if (vha->hw->flags.eeh_busy || qla2x00_chip_is_down(vha))
7507 return;
7508
7509 /*
7510 * dpc thread cannot run if heartbeat is running at the same time.
7511 * We also do not want to starve heartbeat task. Therefore, do
7512 * heartbeat task at least once every 5 seconds.
7513 */
7514 if (dpc_started &&
7515 time_before(jiffies, ha->last_heartbeat_run_jiffies + 5 * HZ))
7516 return;
7517
7518 if (qla_do_heartbeat(vha)) {
7519 ha->last_heartbeat_run_jiffies = jiffies;
7520 queue_work(ha->wq, &ha->heartbeat_work);
7521 }
7522 }
7523
qla_wind_down_chip(scsi_qla_host_t * vha)7524 static void qla_wind_down_chip(scsi_qla_host_t *vha)
7525 {
7526 struct qla_hw_data *ha = vha->hw;
7527
7528 if (!ha->flags.eeh_busy)
7529 return;
7530 if (ha->pci_error_state)
7531 /* system is trying to recover */
7532 return;
7533
7534 /*
7535 * Current system is not handling PCIE error. At this point, this is
7536 * best effort to wind down the adapter.
7537 */
7538 if (time_after_eq(jiffies, ha->eeh_jif + ql2xdelay_before_pci_error_handling * HZ) &&
7539 !ha->flags.eeh_flush) {
7540 ql_log(ql_log_info, vha, 0x9009,
7541 "PCI Error detected, attempting to reset hardware.\n");
7542
7543 ha->isp_ops->reset_chip(vha);
7544 ha->isp_ops->disable_intrs(ha);
7545
7546 ha->flags.eeh_flush = EEH_FLUSH_RDY;
7547 ha->eeh_jif = jiffies;
7548
7549 } else if (ha->flags.eeh_flush == EEH_FLUSH_RDY &&
7550 time_after_eq(jiffies, ha->eeh_jif + 5 * HZ)) {
7551 pci_clear_master(ha->pdev);
7552
7553 /* flush all command */
7554 qla2x00_abort_isp_cleanup(vha);
7555 ha->flags.eeh_flush = EEH_FLUSH_DONE;
7556
7557 ql_log(ql_log_info, vha, 0x900a,
7558 "PCI Error handling complete, all IOs aborted.\n");
7559 }
7560 }
7561
7562 /**************************************************************************
7563 * qla2x00_timer
7564 *
7565 * Description:
7566 * One second timer
7567 *
7568 * Context: Interrupt
7569 ***************************************************************************/
7570 void
qla2x00_timer(struct timer_list * t)7571 qla2x00_timer(struct timer_list *t)
7572 {
7573 scsi_qla_host_t *vha = timer_container_of(vha, t, timer);
7574 unsigned long cpu_flags = 0;
7575 int start_dpc = 0;
7576 int index;
7577 srb_t *sp;
7578 uint16_t w;
7579 struct qla_hw_data *ha = vha->hw;
7580 struct req_que *req;
7581 unsigned long flags;
7582 fc_port_t *fcport = NULL;
7583
7584 if (ha->flags.eeh_busy) {
7585 qla_wind_down_chip(vha);
7586
7587 ql_dbg(ql_dbg_timer, vha, 0x6000,
7588 "EEH = %d, restarting timer.\n",
7589 ha->flags.eeh_busy);
7590 qla2x00_restart_timer(vha, WATCH_INTERVAL);
7591 return;
7592 }
7593
7594 /*
7595 * Hardware read to raise pending EEH errors during mailbox waits. If
7596 * the read returns -1 then disable the board.
7597 */
7598 if (!pci_channel_offline(ha->pdev)) {
7599 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
7600 qla2x00_check_reg16_for_disconnect(vha, w);
7601 }
7602
7603 /* Make sure qla82xx_watchdog is run only for physical port */
7604 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
7605 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
7606 start_dpc++;
7607 if (IS_QLA82XX(ha))
7608 qla82xx_watchdog(vha);
7609 else if (IS_QLA8044(ha))
7610 qla8044_watchdog(vha);
7611 }
7612
7613 if (!vha->vp_idx && IS_QLAFX00(ha))
7614 qlafx00_timer_routine(vha);
7615
7616 if (vha->link_down_time < QLA2XX_MAX_LINK_DOWN_TIME)
7617 vha->link_down_time++;
7618
7619 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
7620 list_for_each_entry(fcport, &vha->vp_fcports, list) {
7621 if (fcport->tgt_link_down_time < QLA2XX_MAX_LINK_DOWN_TIME)
7622 fcport->tgt_link_down_time++;
7623 }
7624 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
7625
7626 /* Loop down handler. */
7627 if (atomic_read(&vha->loop_down_timer) > 0 &&
7628 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
7629 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
7630 && vha->flags.online) {
7631
7632 if (atomic_read(&vha->loop_down_timer) ==
7633 vha->loop_down_abort_time) {
7634
7635 ql_log(ql_log_info, vha, 0x6008,
7636 "Loop down - aborting the queues before time expires.\n");
7637
7638 if (!IS_QLA2100(ha) && vha->link_down_timeout)
7639 atomic_set(&vha->loop_state, LOOP_DEAD);
7640
7641 /*
7642 * Schedule an ISP abort to return any FCP2-device
7643 * commands.
7644 */
7645 /* NPIV - scan physical port only */
7646 if (!vha->vp_idx) {
7647 spin_lock_irqsave(&ha->hardware_lock,
7648 cpu_flags);
7649 req = ha->req_q_map[0];
7650 for (index = 1;
7651 index < req->num_outstanding_cmds;
7652 index++) {
7653 fc_port_t *sfcp;
7654
7655 sp = req->outstanding_cmds[index];
7656 if (!sp)
7657 continue;
7658 if (sp->cmd_type != TYPE_SRB)
7659 continue;
7660 if (sp->type != SRB_SCSI_CMD)
7661 continue;
7662 sfcp = sp->fcport;
7663 if (!(sfcp->flags & FCF_FCP2_DEVICE))
7664 continue;
7665
7666 if (IS_QLA82XX(ha))
7667 set_bit(FCOE_CTX_RESET_NEEDED,
7668 &vha->dpc_flags);
7669 else
7670 set_bit(ISP_ABORT_NEEDED,
7671 &vha->dpc_flags);
7672 break;
7673 }
7674 spin_unlock_irqrestore(&ha->hardware_lock,
7675 cpu_flags);
7676 }
7677 start_dpc++;
7678 }
7679
7680 /* if the loop has been down for 4 minutes, reinit adapter */
7681 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
7682 if (!(vha->device_flags & DFLG_NO_CABLE) && !vha->vp_idx) {
7683 ql_log(ql_log_warn, vha, 0x6009,
7684 "Loop down - aborting ISP.\n");
7685
7686 if (IS_QLA82XX(ha))
7687 set_bit(FCOE_CTX_RESET_NEEDED,
7688 &vha->dpc_flags);
7689 else
7690 set_bit(ISP_ABORT_NEEDED,
7691 &vha->dpc_flags);
7692 }
7693 }
7694 ql_dbg(ql_dbg_timer, vha, 0x600a,
7695 "Loop down - seconds remaining %d.\n",
7696 atomic_read(&vha->loop_down_timer));
7697 }
7698 /* Check if beacon LED needs to be blinked for physical host only */
7699 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
7700 /* There is no beacon_blink function for ISP82xx */
7701 if (!IS_P3P_TYPE(ha)) {
7702 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
7703 start_dpc++;
7704 }
7705 }
7706
7707 /* check if edif running */
7708 if (vha->hw->flags.edif_enabled)
7709 qla_edif_timer(vha);
7710
7711 /* Process any deferred work. */
7712 if (!list_empty(&vha->work_list)) {
7713 unsigned long flags;
7714 bool q = false;
7715
7716 spin_lock_irqsave(&vha->work_lock, flags);
7717 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
7718 q = true;
7719 spin_unlock_irqrestore(&vha->work_lock, flags);
7720 if (q)
7721 queue_work(vha->hw->wq, &vha->iocb_work);
7722 }
7723
7724 /*
7725 * FC-NVME
7726 * see if the active AEN count has changed from what was last reported.
7727 */
7728 index = atomic_read(&ha->nvme_active_aen_cnt);
7729 if (!vha->vp_idx &&
7730 (index != ha->nvme_last_rptd_aen) &&
7731 ha->zio_mode == QLA_ZIO_MODE_6 &&
7732 !ha->flags.host_shutting_down) {
7733 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
7734 ql_log(ql_log_info, vha, 0x3002,
7735 "nvme: Sched: Set ZIO exchange threshold to %d.\n",
7736 ha->nvme_last_rptd_aen);
7737 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
7738 start_dpc++;
7739 }
7740
7741 if (!vha->vp_idx &&
7742 atomic_read(&ha->zio_threshold) != ha->last_zio_threshold &&
7743 IS_ZIO_THRESHOLD_CAPABLE(ha)) {
7744 ql_log(ql_log_info, vha, 0x3002,
7745 "Sched: Set ZIO exchange threshold to %d.\n",
7746 ha->last_zio_threshold);
7747 ha->last_zio_threshold = atomic_read(&ha->zio_threshold);
7748 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
7749 start_dpc++;
7750 }
7751 qla_adjust_buf(vha);
7752
7753 /* borrowing w to signify dpc will run */
7754 w = 0;
7755 /* Schedule the DPC routine if needed */
7756 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
7757 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
7758 start_dpc ||
7759 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
7760 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
7761 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
7762 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
7763 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
7764 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) ||
7765 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags))) {
7766 ql_dbg(ql_dbg_timer, vha, 0x600b,
7767 "isp_abort_needed=%d loop_resync_needed=%d "
7768 "start_dpc=%d reset_marker_needed=%d",
7769 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
7770 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
7771 start_dpc, test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
7772 ql_dbg(ql_dbg_timer, vha, 0x600c,
7773 "beacon_blink_needed=%d isp_unrecoverable=%d "
7774 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
7775 "relogin_needed=%d, Process_purex_iocb=%d.\n",
7776 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
7777 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
7778 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
7779 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
7780 test_bit(RELOGIN_NEEDED, &vha->dpc_flags),
7781 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags));
7782 qla2xxx_wake_dpc(vha);
7783 w = 1;
7784 }
7785
7786 qla_heart_beat(vha, w);
7787
7788 qla2x00_restart_timer(vha, WATCH_INTERVAL);
7789 }
7790
7791 /* Firmware interface routines. */
7792
7793 #define FW_ISP21XX 0
7794 #define FW_ISP22XX 1
7795 #define FW_ISP2300 2
7796 #define FW_ISP2322 3
7797 #define FW_ISP24XX 4
7798 #define FW_ISP25XX 5
7799 #define FW_ISP81XX 6
7800 #define FW_ISP82XX 7
7801 #define FW_ISP2031 8
7802 #define FW_ISP8031 9
7803 #define FW_ISP27XX 10
7804 #define FW_ISP28XX 11
7805 #define FW_ISP29XX 12
7806
7807 #define FW_FILE_ISP21XX "ql2100_fw.bin"
7808 #define FW_FILE_ISP22XX "ql2200_fw.bin"
7809 #define FW_FILE_ISP2300 "ql2300_fw.bin"
7810 #define FW_FILE_ISP2322 "ql2322_fw.bin"
7811 #define FW_FILE_ISP24XX "ql2400_fw.bin"
7812 #define FW_FILE_ISP25XX "ql2500_fw.bin"
7813 #define FW_FILE_ISP81XX "ql8100_fw.bin"
7814 #define FW_FILE_ISP82XX "ql8200_fw.bin"
7815 #define FW_FILE_ISP2031 "ql2600_fw.bin"
7816 #define FW_FILE_ISP8031 "ql8300_fw.bin"
7817 #define FW_FILE_ISP27XX "ql2700_fw.bin"
7818 #define FW_FILE_ISP28XX "ql2800_fw.bin"
7819 #define FW_FILE_ISP29XX "ql2900_fw.bin"
7820
7821
7822 static DEFINE_MUTEX(qla_fw_lock);
7823
7824 static struct fw_blob qla_fw_blobs[] = {
7825 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
7826 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
7827 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
7828 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
7829 { .name = FW_FILE_ISP24XX, },
7830 { .name = FW_FILE_ISP25XX, },
7831 { .name = FW_FILE_ISP81XX, },
7832 { .name = FW_FILE_ISP82XX, },
7833 { .name = FW_FILE_ISP2031, },
7834 { .name = FW_FILE_ISP8031, },
7835 { .name = FW_FILE_ISP27XX, },
7836 { .name = FW_FILE_ISP28XX, },
7837 { .name = FW_FILE_ISP29XX, },
7838 { .name = NULL, },
7839 };
7840
7841 struct fw_blob *
qla2x00_request_firmware(scsi_qla_host_t * vha)7842 qla2x00_request_firmware(scsi_qla_host_t *vha)
7843 {
7844 struct qla_hw_data *ha = vha->hw;
7845 struct fw_blob *blob;
7846
7847 if (IS_QLA2100(ha)) {
7848 blob = &qla_fw_blobs[FW_ISP21XX];
7849 } else if (IS_QLA2200(ha)) {
7850 blob = &qla_fw_blobs[FW_ISP22XX];
7851 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
7852 blob = &qla_fw_blobs[FW_ISP2300];
7853 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
7854 blob = &qla_fw_blobs[FW_ISP2322];
7855 } else if (IS_QLA24XX_TYPE(ha)) {
7856 blob = &qla_fw_blobs[FW_ISP24XX];
7857 } else if (IS_QLA25XX(ha)) {
7858 blob = &qla_fw_blobs[FW_ISP25XX];
7859 } else if (IS_QLA81XX(ha)) {
7860 blob = &qla_fw_blobs[FW_ISP81XX];
7861 } else if (IS_QLA82XX(ha)) {
7862 blob = &qla_fw_blobs[FW_ISP82XX];
7863 } else if (IS_QLA2031(ha)) {
7864 blob = &qla_fw_blobs[FW_ISP2031];
7865 } else if (IS_QLA8031(ha)) {
7866 blob = &qla_fw_blobs[FW_ISP8031];
7867 } else if (IS_QLA27XX(ha)) {
7868 blob = &qla_fw_blobs[FW_ISP27XX];
7869 } else if (IS_QLA28XX(ha)) {
7870 blob = &qla_fw_blobs[FW_ISP28XX];
7871 } else if (IS_QLA29XX(ha)) {
7872 blob = &qla_fw_blobs[FW_ISP29XX];
7873 } else {
7874 return NULL;
7875 }
7876
7877 if (!blob->name)
7878 return NULL;
7879
7880 mutex_lock(&qla_fw_lock);
7881 if (blob->fw)
7882 goto out;
7883
7884 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7885 ql_log(ql_log_warn, vha, 0x0063,
7886 "Failed to load firmware image (%s).\n", blob->name);
7887 blob->fw = NULL;
7888 blob = NULL;
7889 }
7890
7891 out:
7892 mutex_unlock(&qla_fw_lock);
7893 return blob;
7894 }
7895
7896 static void
qla2x00_release_firmware(void)7897 qla2x00_release_firmware(void)
7898 {
7899 struct fw_blob *blob;
7900
7901 mutex_lock(&qla_fw_lock);
7902 for (blob = qla_fw_blobs; blob->name; blob++)
7903 release_firmware(blob->fw);
7904 mutex_unlock(&qla_fw_lock);
7905 }
7906
qla_pci_error_cleanup(scsi_qla_host_t * vha)7907 static void qla_pci_error_cleanup(scsi_qla_host_t *vha)
7908 {
7909 struct qla_hw_data *ha = vha->hw;
7910 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
7911 struct qla_qpair *qpair = NULL;
7912 struct scsi_qla_host *vp, *tvp;
7913 fc_port_t *fcport;
7914 int i;
7915 unsigned long flags;
7916
7917 ql_dbg(ql_dbg_aer, vha, 0x9000,
7918 "%s\n", __func__);
7919 ha->chip_reset++;
7920
7921 ha->base_qpair->chip_reset = ha->chip_reset;
7922 for (i = 0; i < ha->max_qpairs; i++) {
7923 if (ha->queue_pair_map[i])
7924 ha->queue_pair_map[i]->chip_reset =
7925 ha->base_qpair->chip_reset;
7926 }
7927
7928 /*
7929 * purge mailbox might take a while. Slot Reset/chip reset
7930 * will take care of the purge
7931 */
7932
7933 mutex_lock(&ha->mq_lock);
7934 ha->base_qpair->online = 0;
7935 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7936 qpair->online = 0;
7937 wmb();
7938 mutex_unlock(&ha->mq_lock);
7939
7940 qla2x00_mark_all_devices_lost(vha);
7941
7942 spin_lock_irqsave(&ha->vport_slock, flags);
7943 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
7944 atomic_inc(&vp->vref_count);
7945 spin_unlock_irqrestore(&ha->vport_slock, flags);
7946 qla2x00_mark_all_devices_lost(vp);
7947 spin_lock_irqsave(&ha->vport_slock, flags);
7948 atomic_dec(&vp->vref_count);
7949 }
7950 spin_unlock_irqrestore(&ha->vport_slock, flags);
7951
7952 /* Clear all async request states across all VPs. */
7953 list_for_each_entry(fcport, &vha->vp_fcports, list)
7954 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
7955
7956 spin_lock_irqsave(&ha->vport_slock, flags);
7957 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
7958 atomic_inc(&vp->vref_count);
7959 spin_unlock_irqrestore(&ha->vport_slock, flags);
7960 list_for_each_entry(fcport, &vp->vp_fcports, list)
7961 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
7962 spin_lock_irqsave(&ha->vport_slock, flags);
7963 atomic_dec(&vp->vref_count);
7964 }
7965 spin_unlock_irqrestore(&ha->vport_slock, flags);
7966 }
7967
7968
7969 /**
7970 * qla2xxx_set_affinity_nobalance
7971 * @pdev: pci_dev struct for a qla2xxx device
7972 * @flag: bool
7973 * true: enable "IRQ_NO_BALANCING" bit for msix interrupt
7974 * false: disable "IRQ_NO_BALANCING" bit for msix interrupt
7975 * Description: This function will be called to disable/enable
7976 * "IRQ_NO_BALANCING" to avoid irqbalance daemon
7977 * kicking in during adapter reset.
7978 **/
7979
qla2xxx_set_affinity_nobalance(struct pci_dev * pdev,bool flag)7980 static void qla2xxx_set_affinity_nobalance(struct pci_dev *pdev, bool flag)
7981 {
7982 int irq, i;
7983
7984 for (i = 0; i < QLA_BASE_VECTORS; i++) {
7985 irq = pci_irq_vector(pdev, i);
7986
7987 if (flag)
7988 irq_set_status_flags(irq, IRQ_NO_BALANCING);
7989 else
7990 irq_clear_status_flags(irq, IRQ_NO_BALANCING);
7991 }
7992 }
7993
7994 static pci_ers_result_t
qla2xxx_pci_error_detected(struct pci_dev * pdev,pci_channel_state_t state)7995 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
7996 {
7997 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
7998 struct qla_hw_data *ha = vha->hw;
7999 pci_ers_result_t ret = PCI_ERS_RESULT_NEED_RESET;
8000
8001 ql_log(ql_log_warn, vha, 0x9000,
8002 "PCI error detected, state %x.\n", state);
8003 ha->pci_error_state = QLA_PCI_ERR_DETECTED;
8004
8005 if (!atomic_read(&pdev->enable_cnt)) {
8006 ql_log(ql_log_info, vha, 0xffff,
8007 "PCI device is disabled,state %x\n", state);
8008 ret = PCI_ERS_RESULT_NEED_RESET;
8009 goto out;
8010 }
8011
8012 qla2xxx_set_affinity_nobalance(pdev, false);
8013
8014 switch (state) {
8015 case pci_channel_io_normal:
8016 qla_pci_set_eeh_busy(vha);
8017 if (ql2xmqsupport || ql2xnvmeenable) {
8018 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
8019 qla2xxx_wake_dpc(vha);
8020 }
8021 ret = PCI_ERS_RESULT_CAN_RECOVER;
8022 break;
8023 case pci_channel_io_frozen:
8024 qla_pci_set_eeh_busy(vha);
8025 ret = PCI_ERS_RESULT_NEED_RESET;
8026 break;
8027 case pci_channel_io_perm_failure:
8028 ha->flags.pci_channel_io_perm_failure = 1;
8029 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
8030 if (ql2xmqsupport || ql2xnvmeenable) {
8031 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
8032 qla2xxx_wake_dpc(vha);
8033 }
8034 ret = PCI_ERS_RESULT_DISCONNECT;
8035 }
8036 out:
8037 ql_dbg(ql_dbg_aer, vha, 0x600d,
8038 "PCI error detected returning [%x].\n", ret);
8039 return ret;
8040 }
8041
8042 static pci_ers_result_t
qla2xxx_pci_mmio_enabled(struct pci_dev * pdev)8043 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
8044 {
8045 int risc_paused = 0;
8046 uint32_t stat;
8047 unsigned long flags;
8048 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
8049 struct qla_hw_data *ha = base_vha->hw;
8050 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
8051 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
8052
8053 ql_log(ql_log_warn, base_vha, 0x9000,
8054 "mmio enabled\n");
8055
8056 ha->pci_error_state = QLA_PCI_MMIO_ENABLED;
8057
8058 if (IS_QLA82XX(ha))
8059 return PCI_ERS_RESULT_RECOVERED;
8060
8061 if (qla2x00_isp_reg_stat(ha)) {
8062 ql_log(ql_log_info, base_vha, 0x803f,
8063 "During mmio enabled, PCI/Register disconnect still detected.\n");
8064 goto out;
8065 }
8066
8067 spin_lock_irqsave(&ha->hardware_lock, flags);
8068 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
8069 stat = rd_reg_word(®->hccr);
8070 if (stat & HCCR_RISC_PAUSE)
8071 risc_paused = 1;
8072 } else if (IS_QLA23XX(ha)) {
8073 stat = rd_reg_dword(®->u.isp2300.host_status);
8074 if (stat & HSR_RISC_PAUSED)
8075 risc_paused = 1;
8076 } else if (IS_FWI2_CAPABLE(ha)) {
8077 stat = rd_reg_dword(®24->host_status);
8078 if (stat & HSRX_RISC_PAUSED)
8079 risc_paused = 1;
8080 }
8081 spin_unlock_irqrestore(&ha->hardware_lock, flags);
8082
8083 if (risc_paused) {
8084 ql_log(ql_log_info, base_vha, 0x9003,
8085 "RISC paused -- mmio_enabled, Dumping firmware.\n");
8086 qla2xxx_dump_fw(base_vha);
8087 }
8088 out:
8089 /* set PCI_ERS_RESULT_NEED_RESET to trigger call to qla2xxx_pci_slot_reset */
8090 ql_dbg(ql_dbg_aer, base_vha, 0x600d,
8091 "mmio enabled returning.\n");
8092 return PCI_ERS_RESULT_NEED_RESET;
8093 }
8094
8095 static pci_ers_result_t
qla2xxx_pci_slot_reset(struct pci_dev * pdev)8096 qla2xxx_pci_slot_reset(struct pci_dev *pdev)
8097 {
8098 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
8099 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
8100 struct qla_hw_data *ha = base_vha->hw;
8101 int rc;
8102 struct qla_qpair *qpair = NULL;
8103
8104 ql_log(ql_log_warn, base_vha, 0x9004,
8105 "Slot Reset.\n");
8106
8107 ha->pci_error_state = QLA_PCI_SLOT_RESET;
8108
8109 pci_restore_state(pdev);
8110
8111 if (ha->mem_only)
8112 rc = pci_enable_device_mem(pdev);
8113 else
8114 rc = pci_enable_device(pdev);
8115
8116 if (rc) {
8117 ql_log(ql_log_warn, base_vha, 0x9005,
8118 "Can't re-enable PCI device after reset.\n");
8119 goto exit_slot_reset;
8120 }
8121
8122
8123 if (ha->isp_ops->pci_config(base_vha))
8124 goto exit_slot_reset;
8125
8126 mutex_lock(&ha->mq_lock);
8127 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
8128 qpair->online = 1;
8129 mutex_unlock(&ha->mq_lock);
8130
8131 ha->flags.eeh_busy = 0;
8132 base_vha->flags.online = 1;
8133 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
8134 ha->isp_ops->abort_isp(base_vha);
8135 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
8136
8137 if (qla2x00_isp_reg_stat(ha)) {
8138 ha->flags.eeh_busy = 1;
8139 qla_pci_error_cleanup(base_vha);
8140 ql_log(ql_log_warn, base_vha, 0x9005,
8141 "Device unable to recover from PCI error.\n");
8142 } else {
8143 ret = PCI_ERS_RESULT_RECOVERED;
8144 }
8145
8146 exit_slot_reset:
8147 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
8148 "Slot Reset returning %x.\n", ret);
8149
8150 qla2xxx_set_affinity_nobalance(pdev, true);
8151
8152 return ret;
8153 }
8154
8155 static void
qla2xxx_pci_resume(struct pci_dev * pdev)8156 qla2xxx_pci_resume(struct pci_dev *pdev)
8157 {
8158 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
8159 struct qla_hw_data *ha = base_vha->hw;
8160 int ret;
8161
8162 ql_log(ql_log_warn, base_vha, 0x900f,
8163 "Pci Resume.\n");
8164
8165
8166 ret = qla2x00_wait_for_hba_online(base_vha);
8167 if (ret != QLA_SUCCESS) {
8168 ql_log(ql_log_fatal, base_vha, 0x9002,
8169 "The device failed to resume I/O from slot/link_reset.\n");
8170 }
8171 ha->pci_error_state = QLA_PCI_RESUME;
8172 ql_dbg(ql_dbg_aer, base_vha, 0x600d,
8173 "Pci Resume returning.\n");
8174 }
8175
qla_pci_set_eeh_busy(struct scsi_qla_host * vha)8176 void qla_pci_set_eeh_busy(struct scsi_qla_host *vha)
8177 {
8178 struct qla_hw_data *ha = vha->hw;
8179 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
8180 bool do_cleanup = false;
8181 unsigned long flags;
8182
8183 if (ha->flags.eeh_busy)
8184 return;
8185
8186 spin_lock_irqsave(&base_vha->work_lock, flags);
8187 if (!ha->flags.eeh_busy) {
8188 ha->eeh_jif = jiffies;
8189 ha->flags.eeh_flush = 0;
8190
8191 ha->flags.eeh_busy = 1;
8192 do_cleanup = true;
8193 }
8194 spin_unlock_irqrestore(&base_vha->work_lock, flags);
8195
8196 if (do_cleanup)
8197 qla_pci_error_cleanup(base_vha);
8198 }
8199
8200 /*
8201 * this routine will schedule a task to pause IO from interrupt context
8202 * if caller sees a PCIE error event (register read = 0xf's)
8203 */
qla_schedule_eeh_work(struct scsi_qla_host * vha)8204 void qla_schedule_eeh_work(struct scsi_qla_host *vha)
8205 {
8206 struct qla_hw_data *ha = vha->hw;
8207 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
8208
8209 if (ha->flags.eeh_busy)
8210 return;
8211
8212 set_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags);
8213 qla2xxx_wake_dpc(base_vha);
8214 }
8215
8216 static void
qla_pci_reset_prepare(struct pci_dev * pdev)8217 qla_pci_reset_prepare(struct pci_dev *pdev)
8218 {
8219 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
8220 struct qla_hw_data *ha = base_vha->hw;
8221 struct qla_qpair *qpair;
8222
8223 ql_log(ql_log_warn, base_vha, 0xffff,
8224 "%s.\n", __func__);
8225
8226 /*
8227 * PCI FLR/function reset is about to reset the
8228 * slot. Stop the chip to stop all DMA access.
8229 * It is assumed that pci_reset_done will be called
8230 * after FLR to resume Chip operation.
8231 */
8232 ha->flags.eeh_busy = 1;
8233 mutex_lock(&ha->mq_lock);
8234 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
8235 qpair->online = 0;
8236 mutex_unlock(&ha->mq_lock);
8237
8238 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
8239 qla2x00_abort_isp_cleanup(base_vha);
8240 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16);
8241 }
8242
8243 static void
qla_pci_reset_done(struct pci_dev * pdev)8244 qla_pci_reset_done(struct pci_dev *pdev)
8245 {
8246 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
8247 struct qla_hw_data *ha = base_vha->hw;
8248 struct qla_qpair *qpair;
8249
8250 ql_log(ql_log_warn, base_vha, 0xffff,
8251 "%s.\n", __func__);
8252
8253 /*
8254 * FLR just completed by PCI layer. Resume adapter
8255 */
8256 ha->flags.eeh_busy = 0;
8257 mutex_lock(&ha->mq_lock);
8258 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
8259 qpair->online = 1;
8260 mutex_unlock(&ha->mq_lock);
8261
8262 base_vha->flags.online = 1;
8263 ha->isp_ops->abort_isp(base_vha);
8264 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
8265 }
8266
qla2xxx_map_queues(struct Scsi_Host * shost)8267 static void qla2xxx_map_queues(struct Scsi_Host *shost)
8268 {
8269 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
8270 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
8271
8272 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase)
8273 blk_mq_map_queues(qmap);
8274 else
8275 blk_mq_map_hw_queues(qmap, &vha->hw->pdev->dev,
8276 vha->irq_offset);
8277 }
8278
8279 struct scsi_host_template qla2xxx_driver_template = {
8280 .module = THIS_MODULE,
8281 .name = QLA2XXX_DRIVER_NAME,
8282 .queuecommand = qla2xxx_queuecommand,
8283
8284 .eh_timed_out = fc_eh_timed_out,
8285 .eh_abort_handler = qla2xxx_eh_abort,
8286 .eh_should_retry_cmd = fc_eh_should_retry_cmd,
8287 .eh_device_reset_handler = qla2xxx_eh_device_reset,
8288 .eh_target_reset_handler = qla2xxx_eh_target_reset,
8289 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
8290 .eh_host_reset_handler = qla2xxx_eh_host_reset,
8291
8292 .sdev_configure = qla2xxx_sdev_configure,
8293
8294 .sdev_init = qla2xxx_sdev_init,
8295 .sdev_destroy = qla2xxx_sdev_destroy,
8296 .scan_finished = qla2xxx_scan_finished,
8297 .scan_start = qla2xxx_scan_start,
8298 .change_queue_depth = scsi_change_queue_depth,
8299 .map_queues = qla2xxx_map_queues,
8300 .this_id = -1,
8301 .cmd_per_lun = 3,
8302 .sg_tablesize = SG_ALL,
8303
8304 .max_sectors = 0xFFFF,
8305 .shost_groups = qla2x00_host_groups,
8306
8307 .supported_mode = MODE_INITIATOR,
8308 .track_queue_depth = 1,
8309 .cmd_size = sizeof(srb_t),
8310 };
8311
8312 static const struct pci_error_handlers qla2xxx_err_handler = {
8313 .error_detected = qla2xxx_pci_error_detected,
8314 .mmio_enabled = qla2xxx_pci_mmio_enabled,
8315 .slot_reset = qla2xxx_pci_slot_reset,
8316 .resume = qla2xxx_pci_resume,
8317 .reset_prepare = qla_pci_reset_prepare,
8318 .reset_done = qla_pci_reset_done,
8319 };
8320
8321 static const struct pci_device_id qla2xxx_pci_tbl[] = {
8322 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
8323 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
8324 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
8325 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
8326 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
8327 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
8328 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
8329 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
8330 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
8331 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
8332 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
8333 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
8334 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
8335 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
8336 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
8337 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
8338 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8339 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
8340 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
8341 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
8342 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
8343 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
8344 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) },
8345 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) },
8346 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) },
8347 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) },
8348 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) },
8349 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2099) },
8350 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2299) },
8351 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2091) },
8352 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2291) },
8353 { 0 },
8354 };
8355 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
8356
8357 static struct pci_driver qla2xxx_pci_driver = {
8358 .name = QLA2XXX_DRIVER_NAME,
8359 .id_table = qla2xxx_pci_tbl,
8360 .probe = qla2x00_probe_one,
8361 .remove = qla2x00_remove_one,
8362 .shutdown = qla2x00_shutdown,
8363 .err_handler = &qla2xxx_err_handler,
8364 };
8365
8366 static const struct file_operations apidev_fops = {
8367 .owner = THIS_MODULE,
8368 .llseek = noop_llseek,
8369 };
8370
8371 /**
8372 * qla2x00_module_init - Module initialization.
8373 **/
8374 static int __init
qla2x00_module_init(void)8375 qla2x00_module_init(void)
8376 {
8377 int ret = 0;
8378
8379 BUILD_BUG_ON(sizeof(cmd_a64_entry_t) != 64);
8380 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64);
8381 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64);
8382 BUILD_BUG_ON(sizeof(cont_entry_t) != 64);
8383 BUILD_BUG_ON(sizeof(init_cb_t) != 96);
8384 BUILD_BUG_ON(sizeof(mrk_entry_t) != 64);
8385 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64);
8386 BUILD_BUG_ON(sizeof(request_t) != 64);
8387 BUILD_BUG_ON(sizeof(struct abort_entry_24xx) != 64);
8388 BUILD_BUG_ON(sizeof(struct abort_entry_24xx_ext) != 128);
8389 BUILD_BUG_ON(sizeof(struct abort_iocb_entry_fx00) != 64);
8390 BUILD_BUG_ON(sizeof(struct abts_entry_24xx) != 64);
8391 BUILD_BUG_ON(sizeof(struct abts_entry_24xx_ext) != 128);
8392 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64);
8393 BUILD_BUG_ON(sizeof(struct access_chip_rsp_84xx) != 64);
8394 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64);
8395 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64);
8396 BUILD_BUG_ON(sizeof(struct cmd_nvme_ext) != 128);
8397 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64);
8398 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64);
8399 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64);
8400 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64);
8401 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64);
8402 BUILD_BUG_ON(sizeof(struct ct_entry_24xx_ext) != 128);
8403 BUILD_BUG_ON(sizeof(struct ct_fdmi1_hba_attributes) != 2604);
8404 BUILD_BUG_ON(sizeof(struct ct_fdmi2_hba_attributes) != 4424);
8405 BUILD_BUG_ON(sizeof(struct ct_fdmi2_port_attributes) != 4164);
8406 BUILD_BUG_ON(sizeof(struct ct_fdmi_hba_attr) != 260);
8407 BUILD_BUG_ON(sizeof(struct ct_fdmi_port_attr) != 260);
8408 BUILD_BUG_ON(sizeof(struct ct_rsp_hdr) != 16);
8409 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64);
8410 BUILD_BUG_ON(sizeof(struct device_reg_24xx) != 256);
8411 BUILD_BUG_ON(sizeof(struct device_reg_25xxmq) != 24);
8412 BUILD_BUG_ON(sizeof(struct device_reg_2xxx) != 256);
8413 BUILD_BUG_ON(sizeof(struct device_reg_82xx) != 1288);
8414 BUILD_BUG_ON(sizeof(struct device_reg_fx00) != 216);
8415 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64);
8416 BUILD_BUG_ON(sizeof(struct els_entry_24xx_ext) != 128);
8417 BUILD_BUG_ON(sizeof(struct els_sts_entry_24xx) != 64);
8418 BUILD_BUG_ON(sizeof(struct els_sts_entry_24xx_ext) != 128);
8419 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64);
8420 BUILD_BUG_ON(sizeof(struct imm_ntfy_from_isp) != 64);
8421 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128);
8422 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128);
8423 BUILD_BUG_ON(sizeof(struct logio_entry_24xx) != 64);
8424 BUILD_BUG_ON(sizeof(struct logio_entry_24xx_ext) != 128);
8425 BUILD_BUG_ON(sizeof(struct mbx_entry) != 64);
8426 BUILD_BUG_ON(sizeof(struct mid_init_cb_24xx) != 5252);
8427 BUILD_BUG_ON(sizeof(struct mrk_entry_24xx) != 64);
8428 BUILD_BUG_ON(sizeof(struct mrk_entry_24xx_ext) != 128);
8429 BUILD_BUG_ON(sizeof(struct nvram_24xx) != 512);
8430 BUILD_BUG_ON(sizeof(struct nvram_81xx) != 512);
8431 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64);
8432 BUILD_BUG_ON(sizeof(struct pt_ls4_request_ext) != 128);
8433 BUILD_BUG_ON(sizeof(struct pt_ls4_rx_unsol) != 64);
8434 BUILD_BUG_ON(sizeof(struct purex_entry_24xx) != 64);
8435 BUILD_BUG_ON(sizeof(struct purex_entry_24xx_ext) != 128);
8436 BUILD_BUG_ON(sizeof(struct qla2100_fw_dump) != 123634);
8437 BUILD_BUG_ON(sizeof(struct qla2300_fw_dump) != 136100);
8438 BUILD_BUG_ON(sizeof(struct qla24xx_fw_dump) != 37976);
8439 BUILD_BUG_ON(sizeof(struct qla25xx_fw_dump) != 39228);
8440 BUILD_BUG_ON(sizeof(struct qla2xxx_fce_chain) != 52);
8441 BUILD_BUG_ON(sizeof(struct qla2xxx_fw_dump) != 136172);
8442 BUILD_BUG_ON(sizeof(struct qla2xxx_mq_chain) != 524);
8443 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_chain) != 8);
8444 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_header) != 12);
8445 BUILD_BUG_ON(sizeof(struct qla2xxx_offld_chain) != 24);
8446 BUILD_BUG_ON(sizeof(struct qla81xx_fw_dump) != 39420);
8447 BUILD_BUG_ON(sizeof(struct qla82xx_uri_data_desc) != 28);
8448 BUILD_BUG_ON(sizeof(struct qla82xx_uri_table_desc) != 32);
8449 BUILD_BUG_ON(sizeof(struct qla83xx_fw_dump) != 51196);
8450 BUILD_BUG_ON(sizeof(struct qla_fcp_prio_cfg) != FCP_PRIO_CFG_SIZE);
8451 BUILD_BUG_ON(sizeof(struct qla_fdt_layout) != 128);
8452 BUILD_BUG_ON(sizeof(struct qla_flt_header) != 8);
8453 BUILD_BUG_ON(sizeof(struct qla_flt_region) != 16);
8454 BUILD_BUG_ON(sizeof(struct qla_npiv_entry) != 24);
8455 BUILD_BUG_ON(sizeof(struct qla_npiv_header) != 16);
8456 BUILD_BUG_ON(sizeof(struct rdp_rsp_payload) != 336);
8457 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064);
8458 BUILD_BUG_ON(sizeof(struct sts_entry_24xx) != 64);
8459 BUILD_BUG_ON(sizeof(struct sts_entry_24xx_ext) != 128);
8460 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry) != 64);
8461 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry_ext) != 128);
8462 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry_fx00) != 64);
8463 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64);
8464 BUILD_BUG_ON(sizeof(struct verify_chip_rsp_84xx) != 52);
8465 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56);
8466 BUILD_BUG_ON(sizeof(struct vp_config_entry_24xx) != 64);
8467 BUILD_BUG_ON(sizeof(struct vp_config_entry_24xx_ext) != 128);
8468 BUILD_BUG_ON(sizeof(struct vp_ctrl_entry_24xx) != 64);
8469 BUILD_BUG_ON(sizeof(struct vp_ctrl_entry_24xx_ext) != 128);
8470 BUILD_BUG_ON(sizeof(struct vp_rpt_id_entry_24xx) != 64);
8471 BUILD_BUG_ON(sizeof(struct vp_rpt_id_entry_24xx_ext) != 128);
8472 BUILD_BUG_ON(sizeof(sts21_entry_t) != 64);
8473 BUILD_BUG_ON(sizeof(sts22_entry_t) != 64);
8474 BUILD_BUG_ON(sizeof(sts_cont_entry_t) != 64);
8475 BUILD_BUG_ON(sizeof(struct sts_cont_entry_ext) != 128);
8476 BUILD_BUG_ON(sizeof(sts_entry_t) != 64);
8477 BUILD_BUG_ON(sizeof(sw_info_t) != 32);
8478 BUILD_BUG_ON(sizeof(target_id_t) != 2);
8479
8480 qla_trace_init();
8481
8482 /* Allocate cache for SRBs. */
8483 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
8484 SLAB_HWCACHE_ALIGN, NULL);
8485 if (srb_cachep == NULL) {
8486 ql_log(ql_log_fatal, NULL, 0x0001,
8487 "Unable to allocate SRB cache...Failing load!.\n");
8488 return -ENOMEM;
8489 }
8490
8491 /* Initialize target kmem_cache and mem_pools */
8492 ret = qlt_init();
8493 if (ret < 0) {
8494 goto destroy_cache;
8495 } else if (ret > 0) {
8496 /*
8497 * If initiator mode is explictly disabled by qlt_init(),
8498 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
8499 * performing scsi_scan_target() during LOOP UP event.
8500 */
8501 qla2xxx_transport_functions.disable_target_scan = 1;
8502 qla2xxx_transport_vport_functions.disable_target_scan = 1;
8503 }
8504
8505 /* Derive version string. */
8506 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
8507 if (ql2xextended_error_logging)
8508 strcat(qla2x00_version_str, "-debug");
8509 if (ql2xextended_error_logging == 1)
8510 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
8511
8512 qla2xxx_transport_template =
8513 fc_attach_transport(&qla2xxx_transport_functions);
8514 if (!qla2xxx_transport_template) {
8515 ql_log(ql_log_fatal, NULL, 0x0002,
8516 "fc_attach_transport failed...Failing load!.\n");
8517 ret = -ENODEV;
8518 goto qlt_exit;
8519 }
8520
8521 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
8522 if (apidev_major < 0) {
8523 ql_log(ql_log_fatal, NULL, 0x0003,
8524 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
8525 }
8526
8527 qla2xxx_transport_vport_template =
8528 fc_attach_transport(&qla2xxx_transport_vport_functions);
8529 if (!qla2xxx_transport_vport_template) {
8530 ql_log(ql_log_fatal, NULL, 0x0004,
8531 "fc_attach_transport vport failed...Failing load!.\n");
8532 ret = -ENODEV;
8533 goto unreg_chrdev;
8534 }
8535 ql_log(ql_log_info, NULL, 0x0005,
8536 "QLogic Fibre Channel HBA Driver: %s.\n",
8537 qla2x00_version_str);
8538 ret = pci_register_driver(&qla2xxx_pci_driver);
8539 if (ret) {
8540 ql_log(ql_log_fatal, NULL, 0x0006,
8541 "pci_register_driver failed...ret=%d Failing load!.\n",
8542 ret);
8543 goto release_vport_transport;
8544 }
8545 return ret;
8546
8547 release_vport_transport:
8548 fc_release_transport(qla2xxx_transport_vport_template);
8549
8550 unreg_chrdev:
8551 if (apidev_major >= 0)
8552 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
8553 fc_release_transport(qla2xxx_transport_template);
8554
8555 qlt_exit:
8556 qlt_exit();
8557
8558 destroy_cache:
8559 kmem_cache_destroy(srb_cachep);
8560
8561 qla_trace_uninit();
8562 return ret;
8563 }
8564
8565 /**
8566 * qla2x00_module_exit - Module cleanup.
8567 **/
8568 static void __exit
qla2x00_module_exit(void)8569 qla2x00_module_exit(void)
8570 {
8571 pci_unregister_driver(&qla2xxx_pci_driver);
8572 qla2x00_release_firmware();
8573 kmem_cache_destroy(ctx_cachep);
8574 fc_release_transport(qla2xxx_transport_vport_template);
8575 if (apidev_major >= 0)
8576 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
8577 fc_release_transport(qla2xxx_transport_template);
8578 qlt_exit();
8579 kmem_cache_destroy(srb_cachep);
8580 qla_trace_uninit();
8581 }
8582
8583 module_init(qla2x00_module_init);
8584 module_exit(qla2x00_module_exit);
8585
8586 MODULE_AUTHOR("QLogic Corporation");
8587 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
8588 MODULE_LICENSE("GPL");
8589 MODULE_FIRMWARE(FW_FILE_ISP21XX);
8590 MODULE_FIRMWARE(FW_FILE_ISP22XX);
8591 MODULE_FIRMWARE(FW_FILE_ISP2300);
8592 MODULE_FIRMWARE(FW_FILE_ISP2322);
8593 MODULE_FIRMWARE(FW_FILE_ISP24XX);
8594 MODULE_FIRMWARE(FW_FILE_ISP25XX);
8595 MODULE_FIRMWARE(FW_FILE_ISP29XX);
8596